Chap 2 Threshold Voltage

CMOS VLSI Design

THRESHOLD VOLTAGE

Threshold voltage Slide 1

The threshold voltage of a MOSFET is usually defined as the gate voltage where an inversion layer forms at the interface between the insulating layer (oxide) and the substrate (body) of the transistor.

It is the voltage at which there are sufficient electrons in the inversion layer to make a low resistance conducting path between the MOSFET source and drain.

What affects the threshold voltage? substrate doping, oxide thickness, source-to-substrate voltage bias, gate material, and surface charge density

CMOS VLSI Design

THRESHOLD VOLTAGE

When VGS > VTHN (nMOSFET), the semiconductor/oxide interface is inverted, i.e., the inversion layer is formed. The associated depletion region (beneath the inversion layer) thickness is described by


s Surface potential

F bulk potential= difference between Fermi energy level of doped semiconductor andFermi energy level intrinsic semiconductor. It is midway between valence band edge and conduction band edge.

CMOS VLSI DesignThreshold voltage Slide 3

si cmFX /1006.1 12permittivity of Si

NA= carrier density in doped semiconductor substrate

ni= carrier density in intrinsic silicon (undoped)= KcmX 300/1045.1 310

KJX /1038.1 23

K

CX 1910602.1

KVq

kT [email protected]

k= Boltzmann constant=

T= temperature (

q= electronic charge=

THRESHOLD VOLTAGE


THRESHOLD VOLTAGE


THRESHOLD VOLTAGE

VFB= Flat band voltage

FBtmosTHN VVV 0

Qss’= fixed charge due to surface states that arrive due to imperfections in silicon – oxide

interface and doping

Where Vtmos is the ideal threshold voltage of an ideal MOS capacitor where there is no work function difference between the gate and substrate materials. It is positive for n-transistors and negative for p- transistors.


THRESHOLD VOLTAGEms work function difference between gate material and silicon substrate

CMOS VLSI Design

THRESHOLD VOLTAGE


The threshold voltage dependence on the doping density is illustrated with the figure below for both ntype and p-type MOS structures with an aluminum gate metal.

Threshold voltage of n-type (upper curve) and p-type (lower curve) MOSFETs versussubstrate doping density

The threshold of both types of devices is slightly negative at low doping densities and differs by 4 times the absolute value of the bulk potential. The threshold of nMOS capacitors increases with doping while the threshold of pMOS structures decreases with doping in the same way. A variation of the flatband voltage due to oxide charge will cause both curves to move down if the charge is positive and up if the charge is negative.

CMOS VLSI Design

BODY EFFECT


The threshold voltage is not constant wrt the voltage difference between the substrate and the source of the MOS transistor. This is known as substrate bias effect or body effect.

The threshold voltage of a MOSFET is affected by the voltage which is applied to the back contact. The voltage difference between the source and the bulk, VSB changes the width of the depletion layer and therefore also the voltage across the oxide due to the change of the charge in the depletion region. This results in a difference in threshold voltage which equals the difference in charge in the depletion region divided by the oxide capacitance

CMOS VLSI Design

BODY EFFECT


VSB= Substrate bias voltage

VTH0=threshold voltage for VSB=0

= constant that describes substrate bias effectγ

CMOS VLSI Design

BODY EFFECT When MOS device are made on a common

substrate, the substrate voltage of all devices is normally equal.

When the devices are in series, VSB increases as we proceed along the series chain (VSB1=0, VSB2 0)

When VGS>Vt, the depletion layer width remains constant and charge carriers are pulled into the channel from the source.

As the substrate bias VSB=Vsource - Vsubstrate is increased, the width of the channel – substrate depletion region also increases.


CMOS VLSI Design

BODY EFFECT This results in an increased density of trapped

carriers in the depletion region. For charge neutrality to hold, the channel charge must decrease.

Thus, the substrate voltage VSB adds to the channel – substrate junction potential. This increases the gate channel voltage drop.

Overall effect is the increase in the threshold voltage.


CMOS VLSI Design

CHANNEL LENGTH MODULATION

The behaviour of the MOS device is describe assuming that carrier mobility is constant.

Variations in channel length due to changes in VDS are not taken into account.

For long channel lengths, influence of channel variation can be neglected but as the devices are scaled down, this variation should be taken into account.

Channel length modulation (CLM) occurs due to the increase of depletion layer width as VDS increases


CMOS VLSI Design


When the MOS device is in saturation, the effective channel length is actually decreased.

This increases (W/L) ratio, thereby increasing β as the drain voltage increases

Thus rather than appearing as a constant current source with infinite output impedance, it has a finite output impedance.


CMOS VLSI Design



cDnDS

dl

effDn

DS

efftgs

effDS

Dn

tgseff

tgsDn

IdV

dX

LI

dV

dLVV

L

kW

dV

dI

VVL

kWVVI

)1

()(2

)(2

)(2

22

22

CMOS VLSI Design


Typical values for lc range from approximately

0.1 V-1 (short channel devices) to 0.01 (long channel devices).

Including CLM in our first-order drain current equation,


)](1[)(2

2DSsatDSctgs

effDn VVVV

L

kWI

CMOS VLSI Design

DRAIN PUNCH THROUGH


For minimum gate length devices, max VDS is limited by punchthrough when the drain-substrate depletion region extends from drain to source thus causing current to flow irrespective of the gate voltage. The resultant high current can destroy the device.

CMOS VLSI Design

MOBILITY VARIATION Mobility describes the ease with which carriers drift

in the substrate material It is defined as μ=average carrier drift velocity

(V)/electric field (E) Mobility varies according to the type of charge carriers:

electrons in silicon have a much higher mobility than that of holes. Thus n-devices have higher current producing capability

Mobility decreases with increase in doping concentration and increasing temperature


CMOS VLSI Design

FOWLER-NORDHEIM TUNNELING

When the gate oxide is very thin, a current can flow from gate to source or drain by electron tunneling through gate oxide. This current is proportional to the area of the gate of the transistor.

This effect limits the thickness of gate oxide as processes are scaled.


CMOS VLSI Design

IMPACT IONIZATION As the length of the gate of a MOS transistor is

reduced, the electric field at the drain of a transistor in saturation increases (for fixed VDS).

For submicron gate lengths, the field can become so high that electrons are imparted with enough energy to become ‘hot’ which impact the drain, dislodging holes that are then swept towards negatively charged substrate and appear as substrate current.



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Chap 2 Threshold Voltage