Subtractive effect of charge integration on dual-gate CID readout with correlated double sampling

254 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 2, FEBRUARY 1986

Subtractive Effect of Charge Integration on Dual-Gate CID Readout with Correlated Double Sampling

Abstmct-In this paper we describe the physical mechanisms of the “subtractive effect” on the dual-gate charge-injection device (C [ED) readout due to on-going charge integration during the time the viljeo waveform is processed with correlated double sampling. Performa see degradation of the CID area array caused by the subtractive effect :.nd two correction schemes for eliminating the problems under differsnt irradiation conditions are discussed.

I. INTRODUCTION

D UAL-GATE charge-injection devices are solid-state self-scanned focal plane mosaics that employ surface

charge transferlinjection to achieve full X-Y address capability for area arrays. Sensor arrays of this design ofkr great flexibility because of the inherently simple structure, and facilitate on-site noise-free signal integration and :.If noise suppression via correlated double samplibg (CUS) 111. In addition, they are capable of conventional sequential scan as well as random access readout. Recent prog- ress in InSb MIS processing and CID readout technology has led to the successful demonstration of 128 X 128 i p -

frared sensor arrays with focal plane Si MOS scanned preamplifiers 121.

The success of the visible Si CID sensor array [3] is undoubtedly due to the mature Si MIS technology; for other semiconductors such as InSb, however, the dielectric process is not yet well developed. Dual-gate CID area arrays require good charge transfer between row and colurr: 11 gates during the entire integration period. The existence of interface states or traps severely inhibits rapid charge transfer. As a consequence, the major technical difficulty in the implementation of large infrared CID area arraJs has been the charge transfer inefficiency. To achieve better charge transfer, the arrays are often operated with a bias charge in the potential well similar to the fat-zero ita charge-coupled devices. The bias charge in this readoct scheme, known as the charge sharing mode (CSM), serves to keep the interface states or traps filled [2]. Unfortu- nately, the signal charge in the CSM is shared by the duad- potential wells of the coupled gates and consequently ca.3 not be read out completely. This uniform loss in signal has been reported in 141 as a degradation in readout efficienc) I Furthermore, the continuous charge integration that takes place in the sites interferes with the CID readout process,

Manuscript received January 25, 1985; revised September 4, 1985. The author is with the Electronics Laboratory, General Electric C o r -

IEEE Log Number 8406500. pany, Syracuse, NY, 13221.

resulting in a subtractive effect. This effect reduces the signal on an intra-column basis in addition to causing other intriguing phenomena. The purpose of this paper is to in- vestigate the physical mechanisms of the subtractive effect associated with the CSM readout and to examine possible video processing schemes to correct the effect under different irradiation conditions.

11. PHYSICAL MECHANISMS The X-Y addressing capability of a CID area array is

accomplished by sloshing the charge in the dual potential wells back and forth between the row and column gates during the integration period. To maintain unique addressing, good charge transfer is a necessary condition especially for the conventional charge sharing or ideal mode readout in which for an N X N array at least N charge transfers are required before the signal charge from each pixel is read out [2]. Repeated sloshing back and forth of charge between the two gates of each pixel during the integration period would degrade a moderate efficiency for a single charge transfer to an unacceptably low efficiency for an array with large N . Recognizing the stringent re- quirement of good charge transfer in the dual-gate CID array readout, we have developed a new readout scheme named sequential row inject (SRI) [ 5 ] . The success of SRI lies in the fact that only one charge transfer/injection is needed for each sensing site in one complete charge integration and readout cycle, thereby providing much greater tolerance of charge transfer inefficiency in a large array. A detailed analysis of the dual-gate CID readout schemes such as the SRI and ideal mode has been reported in [4]. Here we will briefly review the readout mechanisms per- tinent to the subtractive effect.

A . Readout Schemes A comparison of the potential wells during the elemen-

tal readout cycle for the ideal mode and SRI is illustrated in Fig. 1 (a) and (b) , In the ideal mode readout, the signal charge is stored in the row potential well during the entire integration period until it is ready to be read out. The basic readout sequence is to first “half-select” a row, causing the row potential wells to collapse completely and the signal charge to transfer to the column sites, and then inject on the “selected” column. The injection pulse col- lapses the column potential wells thereby injecting the charge from the cell at the intersection of the selected row

001S-9383/S6/0200-0254$01.00 0 1986 IEEE

WANG: SUBTRACTIVE EFFECT OF CHARGE INTEGRATION 255

IDEAL MODE

C R

11

INTEGRATION

REFERENCE COLUMN

7 r-

COLUMN INJECT

SEQUENTIAL ROW INJECTION (SRI)

t

C R

REFERENCE COLUMN

COLUMN m READ

COLUMN

(a) (b) Fig. 1. CJD potential wells of the ideal mode and SRJ readout. The CDS

readout consists of first referencing the column (first sample or dc restore) and later reading it (second sample).

and column. The desired signal is the change in column voltage caused by the injected charge, and is measured by correlated double sampling the column voltage before and after the injection pulse.

The SRI readout is achieved by placing the injection pulses on the rows, one row at a time, and sensing the injected charge in the column. In contrast to the ideal mode, the dual gates of each pixel are coupled at all times in SRI. A bias charge is always maintained in the common potential wells of both row and column, and the signal charge is shared by the dual gates on top of the bias charge as shown in Fig. l(b). Therefore, the SRI is actually a special form of the CSM. Since no drive signal is applied to the columns and the injection pulse is applied to one row at a time, as shown in Fig. 4 of [4], charge transfer1 injection occurs only once in the selected cell of each column. The other cells are left undisturbed, thus eliminating the possibility of charge contributions from them and providing greater tolerance of charge transfer inefficiency. One can use a single preamp that is switched from column to column. In this case, only the signal from the column connected to the preamp is sensed and those from all other columns are discarded. This “serial” SRI reads an array with a line time of integration ( I I ) and a frame time of NtI, and is a low duty-cycle (11N) readout. In more demanding applications, a parallel SRI readout with N preamps, each

0 010 0

Fig. 2. Charge generation in the CJD potential wells and the induced current i during readout. The current causes a voltage change on the floating input node of the readout circuit. VcB and C,, are column bias voltage and sensing line shunt capacitance, respectively. S, is the parallel reset switch while S, is the select switch.

servicing one column, is required. The pixel integration time is still a line time but the whole array is also read out in a line time, thus permitting multiple frame integration during the normally longer system frame time.

B. Subtractive Effect Although the bias charge greatly improves the charge

transfer efficiency in the CSM, it is not without undesir- able side effects. As discussed in [4], sharing the signal charge between the dual gates results in a reduced readout efficiency. Moreover, the on-going charge integration in the column potential wells causes a voltage change on the floating input node of the readout circuitry. Fig. 2 illus- trates the charge flow in the MIS device and the induced displacement current in the readout circuit. The voltage change on the input node is

Av = iAtIC, (1)

where i is the induced current due to charge generation in the potential wells, At the time interval required to read out one pixel, and C, the total shunt capacitance on the input node. Since the signal charge is obtained by sensing the input node voltage, the charge integration inevitably interferes with the readout process, resulting in a subtractive or the so-called “photocurrent” effect [2]. It should be noted that the term “photocurrent” is a mis- nomer, for the effect is caused by the column voltage shift due to charge generation of any form, i.e., dark current, leakage, background, and signal irradiation. In a good sensor system, of course, the photogenerated charge should dominate. For simplicity, Fig. 2 depicts only one MIS site. In reality, an N X N CID array has N MIS sites connected in parallel to the common column metal run. The subtractive effect is thus due to the cumulative charge generation from all contributing sites. Note that the effect from any individual site ceases to exist if saturation is reached since the charge in the potential well of that par- ticular site no longer increases. Note also that in the ideal mode the charge is stored in the row potential wells during the integration period as shown in Fig. l(a). All of the column potential wells except the site with a half-selected row are empty and hence do not contribute to the subtrac-

256 IEEE TRAYSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 2, FEBRUARY 1986

u s I , EMPTY WELL

’-4 CHARGED WELL COLUMN /PREAMP

RESET

t-i

(a>

t----- tp ------I + f S -----I

+++-f5 RESET ;j - --4

. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . ---- --.

I S T 2N D SAMPLE

(b) Fig. 3. Raw video waveforms at the input of the preamp for dual-gate CI =I

readout (a) without and (b) with the subtractive effect. fp, fs, and 7, a x pixel readout time, time interval between the two samples of CDS, a,r d injection pulse width, respectively. Arrows 1st. and 2nd indicate the ill-

stant of completion of the first sample (dc restore, Fig. 7) and second sample of the CDS. The time between the completion of first sample and the onset of injection is deliberately kept at a minimum (say 20 nS). Charge integration during this brief moment is negligible and is ignored in (2).

tive effect. As far as readout is concerned, the ideal mode dual-gate CID is the same as the single-gate CID [ 6 ] , [?I.

The physical mechanisms of the subtractive effect can be demonstrated by the raw video waveforms at the input of the readout preamp, from which the signal is extract :d using correlated double sampling. Fig. 3(a) and (b) depicts the video waveforms without and with the subtractive cf- fect, respectively. In the idealized situation where the C:ID pixels, after completing one charge integration period, z.re “frozen” for readout, the signal voltage from each pixel in the selected column is the amplitude difference at the leading and trailing edge of the coupled injection pu.se [4], as shown in Fig. 3(a). If, however, charge integration continues during the course of readout, the column voltage increases with time according to (1) except during rc- set. The positive slope in the waveform of Fig. 3(b) is p : ~ - portional to the charge generation rate at all pixels in :he selected column; the net voltage increases between the two samples of the CDS (t,) serves to counter the signal vo:Lt- age. The loss in signal is also proportional to t,. In prac- tice, the readout preamp may be too slow to follow the ‘all of the injection pulse. To ensure amplifier recovery befxe a valid signal voltage is measured, appreciable time naay be allowed to elapse between injection and second samq,Re. The preamp circuit response time, therefore, defines the minimum t, for proper readout.

The subtractive effect is essentially caused by the: in- valid dc restore in the CID readout process. The error is

first sample reference. Quantitatively, the error voltage uej for the readout of pixel j depends on the number of pixels on the column ( N ) , integration time (tl>, time interval between the two samples of CDS (t,), and injection pulse duration (T~) as shown in Fig. 3. That is

N

urj = C mij(ts/tI) usi + [(ts - rl)/tI] u j (2) i = 1 i t j

where

uSi = 7 Hsi tlAdlC, ( 3 )

is the signal voltage from pixel i ( i = 1, 2, - * , N ) in the absence of the subtractive effect, assuming that the irradiance HJi on pixel i does not change appreciably during the integration time. 7 and Ad are the detector quantum efficiency and pixel detecting area, respectively. The pa- rameter mij reflects the status of the subtractive effect from contributing pixels and can be expressed as

1, if pixel i is not saturated during the readout of m.. = { pixel j ,

0 , if pixel i has reached saturation.

The first summation term in (2) accounts for the effect from pixels in the column other than the one undergoing readout. The last term represents the effect from the pixel being read right after the injection pulse, which is similar to the case of single-gate CID or dual-gate ideal mode readout as discussed in [7] . Of course, (3) defines the would-be signal voltage if it is not limited by the detector charge storage capacity. The apparent signal from pixel j can then be expressed as

u . = u . - u . aJ SJ eJ (4)

provided usj, as given by (3), is not greater than the detector saturation signal us$, which is determined by the storage capacity (defined by the pixel gate oxide capacitance and the injection voltage). In the case of a saturated pixel j , the apparent signal is given by

uaj = us, - U,j. (5)

C. Flooding Illumination versus Finite Focal Spot The sensor array is usually evaluated by flooding the

whole array with a uniform known irradiation. Assuming that the illumination is within the dynamic range of the detector and ignoring the responsivity variation over the array we have

and (2) becomes

where us is the uniform signal for each pixel in the absence of the subtractive effect. The fractional signal loss can then be calculated as

the difference between the true voltage reference and the UejlUsj = U e / U , = (Nt, - 71)Itl. (8)


Fig. 4 displays the sample-and-hold signal, responding to a flooding chopped flux, of one column of a 32 x 32 array operating in SRI with tl = 102 $3, ts = 1.3 pS, and Tt = 0.4 pS. Note that there are two blanking cycles (each of duration tp) preceding the sequential readout of 32 pixels in the column, during which the CDS is executed as usual except no injection pulse is applied to the row gate. As a consequence, the readout of the blanking cycle effec- tively registers the uniform subtractive effect for each column. As shown in Fig. 4, the apparent signal (u,) of the 32 pixels responding to chopped irradiation is “positive- going” whereas the error signal (u,) during the blanking cycles is “negative-going”, and the fractional signal loss is measured to be U , / U , ~ = u,/(u, +-u,) = 41 percent, in agreement with the predicted 40 percent using (8) and the above operating parameters.

If the flooding irradiation exceeds the saturation level, (2) reduces to

uej == [(t, - 71)/tr] us, (9) and the readout behavior is the same as that of the single- gate CID. Equation (9) also explains the drop commonly observed in the output chargehnput photon detector transfer function curves when the detector is heavily saturated.

When the array is operated in the imaging condition, the subtractive effect is in general less in quantity but more intriguing than that in the flooding mode. Fig. 5 shows an X-Y monitor display of a circular focal spot imaged on a 32 X 32 array. The dc offset of the nonilluminated pixels in the focal spot columns is suppressed by an amount proportional to the number of illuminated pixels in the cor- responding column, as given by the general formula of (2).

To illustrate further the subtractive effect in the imaging condition the sample-and-hold video signal of a column is shown in Fig. 6(a)-(d) with the chopped irradiation level approaching saturation. In Fig. 6(a), a circular focal spot of an intensity within the dynamic range and about 3.5- pixel size is centered at pixels 14 and 15. The nonilluminated pixels show the same negative signal (u,) as the blanking cycles. It is interesting to note that in Fig. 6(b)- (d) the subtractive effect begins to subside when the illu-

minated pixels are becoming saturated as then the charge integration process stops.

111. CORRECTION SCHEMES The last term of (2) due to post-inject charge integra-

tion in the pixel undergoing readout is usually negligible unless the irradiance is several times the saturation level [7]. The first summation term in (2), however, is a severe signal loss,, especially in a large array (i.e., large N ) , and should be corrected. Depending on the state of the potential wells (saturated or not), the required correction schemes are different.

A. Irradiance within Detector Dynamic Range As demonstrated in Fig. 6(a) in which no pixels are sat-

urated, the readout error signal (negative) is uniform over the nonilluminated pixels as well as the blanking cycles. In other words, the slope of the video waveform in Fig. 3(b) remains constant during the readout of all pixels in the column. The error reference voltage can, therefore, be sensed by reading the column without injecting any row (blanking cycle) prior to the normal read, and used to correct all pixels in the column. Fig. 7 shows a simplified video processor schematic diagram with the operation timing sequence to implement such a correction. The switch So resets the column and preamp bias. In addition to the usual switched capacitors C,/ SI and C3/S3 for correlated double sampling, the processor includes another switched capacitor C,/S2. The subtractive effect correction (SEC) is achieved by activating S, once in a line time at the begining of the column read cycle. The error mes- sage is therefore trapped in capacitor C,, and is added to each readout sample by capacitor C,. This simple correction scheme maintains the same timing sequence as in the normal CID readout.

B. Saturation When the target irradiance is high enough to cause sat-

uration in some (but not all) of the pixels, the error signal varies with time, as discussed in Section 11-C. In this case, the subtractive effect is rather dynamic as illustrated by the changing error signals in Fig. 6(c) and (d), and should

258 IEEE TRPdiSACTIQNS ON ELECTRON DEVICES, VQL. ED-33, NO. 2, FEBRUARY 1986

(b) ( 4 Fig. 6. Video signal of one column of a 32 X 32 array with first row open and two blanking cycles. (a) The array (and column) is illuminated by an

image spot centered at pixels 14 and 15, which covers roughly 3.5 pixels. (b), (c), and (d) display the video signal with increasing irradiance. In (b), pixel 14 suffers less subtractive effect than pixel 15, indicating the o ~ ~ s e t of saturation for both 14 and 15. By the time 15 is read out, 14 has just been read out and started a new integration cycle, and therefore contribut2s to the subtractive effect. (c) shows the change of ue,, (2), with time as a result of charge integration, saturation, and readout of pixels under irradiation. In (d) the irradiance is so high that the illuminated pixels (14 and 15) begin to saturate about 8 pixel times after readout, i.e., by the time pixel 26 is being read out. Note that for any pixel in the array integration starts at the trailing edge of the injection pulse and stops at the leading edge of the following injection pulse, if not limited by the storage capacity.

S o : RESET u - u 5,: DC RESTORE , fl n ra n n

+ SEC 4 - P l P2---&---P3 ----r(c-PPq

S 2 : SEC (LINE) I INJECT (LINE]

c- S3: S / H [L INE] L L

S E C i P l -+ SECiP2 T”’ S 2 : SEC (ELEMENT) 4 1 4 INJECT (ELEMEN

I L,

S ~ : S / H ELEMENT)^ I7 n Fig. 7. Readout video processor with subtractive effect correction In addition to the normal CID reset (So), inject, and correlated double sampling (SI

and &), the timing sequences S,:SEC(line) and S,:SEC(elemenc) are for the once-per-line and the element-by-element subtractive effect correction, respectively. P1, P 2 , etc., identify the pixels being read ont. Tne downward arrows indicate the completion of sampling transitions for switches SI, Sz, and Sz. Clock waveforms are merely illustrative and may nor be accurate with regard to relative timing of specific events.


be corrected on an element-by-element basis. The Same [2] M. D. Gibbons and S . C. H. Wang, “Status of CID InSb detector tech-

video processor (Fig* 7, can be used to imp1ement this ’ [3] H. K. Burke and G. J. Michon, “Charge-injection device imaging: Op- nology,” SPIE Proc., vol. 443, pp. 151-166, 1983.

correction. but with a different driving sequence for S7. erating techniaues and Derformance characteristics.” IEEE Trans.

a-double read cycle and for the sequential readout the line *ug. 1985.

increased bv a factor of & due to the operation of the Swab). time is In both the tempora1 noise is of CID imagers,” issued to the General Electric Company, 1982 (.I. M.

[5] U.S. Patent 4 316 221, “Apparatus for sequential row injection readout

switched capacitor C,/S2 [SI.

JV. CONCLUSIONS We have discussed the physical mechanisms of the read-

out subtractive effect associated with the charge sharing mode dual-gate CID. For a target irradiance within the dynamic range, the effect causes a uniform signal loss on an intra-column basis, which manifests itself as dark blooming. Severe signal distortion can occur due to the changing subtractive effect as the integrating pixels reach saturation. Based on the different physical phenomena, correction schemes are prescribed using an additional switched capacitor in the readout v‘ldeo processor. The once-per-line correction is valid for imaging with no saturation, and preserves essentially the same timing sequence as the normal CID readout. Element-by-element correction is appropriate if saturation is anticipated, which requires twice as much time to read one line. In both cases, the temporal noise is degraded by a factor of h.

ACKNOWLEDGMENT The author would like to thank G. H. Danielson, M. L.

Winn, and M. D. Gibbons for valuable discussions, and R. W. Aldrich for advice on paper preparation.

REFERENCES [ l ] M. A. White, D. R. Lampe, F. C. Blaha, and I. A. Mack, “Charac-

terization of surface channel CCD imaging arrays at low light levels,“ IEEEJ. Solid-state Circuits, vol. SC-9, pp. 1-13, 1974.

[6] S. C:H. Wang and M. L. Winn, “Single-gate charge-injection device readout modeling and analysis,” IEEE Trans. Electron Devices, vol. ED-32, pp. 55-60, Jan. 1985.

[7] D. L. Weinberg a@ A. F. Milton, “Output properties of charge-injection devices: Part I-Read on injection,” IEEE Trans. Electron De- vices., vol. ED-19, pp. 1483-1490, 1982.

[8] R. J. Kansy, “Response of a correlated double sampling circuit to 1if noise,” IEEE J . Solid-state Circuits, vol. SC-15, pp. 373-375, 1980.

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Subtractive effect of charge integration on dual-gate CID readout with correlated double sampling