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Stress in Flip-Chip Solder Bumps due to Package Warpage Matt Pharr ES-240 Project 12/9/08

Stress in Flip-Chip Solder Bumps due to Package Warpage

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Stress in Flip-Chip Solder Bumps due to Package Warpage. Matt Pharr ES-240 Project 12/9/08. Flip Chip. Circuit Board. MTTF = 183 hrs. Si. W. e. e. e. e. e. e. Circuit Board. Si. MTTF = 880 hrs. Applied Load. Si – rigid, Small CTE. Solder in Molten State. Cooling. - PowerPoint PPT Presentation

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Page 1: Stress in Flip-Chip Solder Bumps due to Package Warpage

Stress in Flip-Chip Solder Bumps due to Package

Warpage

Matt PharrES-240 Project

12/9/08

Page 2: Stress in Flip-Chip Solder Bumps due to Package Warpage

Flip Chip

Page 3: Stress in Flip-Chip Solder Bumps due to Package Warpage

Applied Load

Circuit Board

e e eSi

Circuit Board

e e eSi

W

MTTF = 183 hrs

MTTF = 880 hrs

Page 4: Stress in Flip-Chip Solder Bumps due to Package Warpage

Origin of Applied LoadSi – rigid,

Small CTE

Solder in Molten State

Substrate, large CTE

Cooling

Page 5: Stress in Flip-Chip Solder Bumps due to Package Warpage

Finite Element Model

200

400

400

5000

Silicon

Bismaleimide Triazene (BT) Substrate

200200

150

Underfill Solder

Page 6: Stress in Flip-Chip Solder Bumps due to Package Warpage

Material Properties

Material Young’s Modulus, E

(GPa)

Poisson’s Ratio ()

Thermal Exp. Coefficient (10-6/K)

Sn-3.5Ag Solder 50 0.3 23

Underfill 6 0.35 30

Silicon chip 131 0.3 2.8

Bismaleimide Triazene (BT)

26 0.39 15

Page 7: Stress in Flip-Chip Solder Bumps due to Package Warpage

Mesh

4-node linear coupled temperature-displacement quadrilateral

Fairly fine – why not? Refined near regions of interest

Edges and solder

Page 8: Stress in Flip-Chip Solder Bumps due to Package Warpage

Loading Conditions Step 1: 221°C – melting point of solder Step 2: 23°C

Coupled temp-disp steady state x-Symmetry Condition on Right End

Step 3 (Attempted): 1A current through solder Coupled thermal-electric Inputted thermal properties of materials Did not converge

Not sure why

Page 9: Stress in Flip-Chip Solder Bumps due to Package Warpage

Loading Conditions (cont.) Step 3: Solder and underfill at 100°C;

linear variation in substrate and Si to ambient temp of 70°C Used subroutine to define this temp field

Study 2: Ran same procedure except that it was assumed that the Si was very rigid and hence could not deform in the vertical direction

Page 10: Stress in Flip-Chip Solder Bumps due to Package Warpage

Mises Stress

Curvature agrees with intuition Slight variation (few MPa)

Page 11: Stress in Flip-Chip Solder Bumps due to Package Warpage

σ22

Stress is ~20 MPa in Solder Bumps Slight variation (~5 MPa)

Page 12: Stress in Flip-Chip Solder Bumps due to Package Warpage

Mises Stress Rigid Si

More variation in stress among solders

Page 13: Stress in Flip-Chip Solder Bumps due to Package Warpage

σ22 Rigid Si

Variation in stress in solders: ~20 MPa on right-side to ~35-40 MPa near left-side

Page 14: Stress in Flip-Chip Solder Bumps due to Package Warpage

Discussion Curvature seems physically intuitive Variation in solder location seems to have

minimal effect on stress Only ~5 MPa for σ22

I guessed it would be larger but that was assuming Si is perfectly rigid

If we make Si completely rigid, we get larger variation in stress among solders

Page 15: Stress in Flip-Chip Solder Bumps due to Package Warpage

Lessons Learned about FEA

FEA has advantages (over experiments): Relatively easy Easy to change material parameters

Do not assume FEA can handle everything Model could be wrong Solution may not converge