BGA User's Guide - Data Device Corporation · BGA package also contains multiple, silicon on a printed circuit board with hard dies pot epoxy encapsulation but uses solder bumps in,

BGA User's Guide

Application Note

© 2009 Data Device Corporation. All trademarks are the property of their respective owners.

AN/B-49

For more information: www.ddc-web.com

This application note will assist the PCB design engineer in integrating DDC's BGA Multi-Chip modules (Hybrids) into a design.

B G A U S E R ’ S G U I D E

Data Device Corporation 1 AN/B-49 www.ddc-web.com 5/13-0

1 DIE-UP OR FLIP CHIP MULTI-CHIP MODULE (MCM) BGA PACKAGE

BGA packaging technology utilizes a symmetrical array of solder balls at the bottom of the package making electrical and mechanical contact with the system circuit board. The solder ball array reduces the package size considerably when compared to DDCs ceramic quad flat-pack leaded products.

DDC BGA packages have a full or partial matrix of solder balls utilizing either 1.0mm or 0.8mm ball pitch (depending on series) shown in Figure 1. The PCB substrate consists of a multilayer, Hi TG-FR4 epoxy material that closely matches the coefficient of thermal expansion (CTE) of most system circuit boards. Signal, power, and ground balls are interspersed throughout the matrix for routing ease.

Figure 1. Bottom View of BGA Packages Note: These images are not to scale

http://www.ddc-web.com/



Chip and Wire Package Construction is shown in the cross section of Figure 2. The Die-Up BGA package contains multiple, wire bonded dies on a printed circuit board with a hard pot epoxy encapsulation. Beneath the die are the thermal vias which conduct and help to dissipate the heat through a portion of the solder ball array and finally into the thermal/ground plane of the system circuit board.

Figure 2. Solder Ball Matrix

Flip Chip package construction is shown in the cross section of Figure 3. A flip chip BGA package also contains multiple, silicon dies on a printed circuit board with hard pot epoxy encapsulation, but uses solder bumps instead of wire bonds to connect signals from the die to the substrate.

In order to attach the die within the BGA, solder balls are first attached to the signal pads on the top side of the die, then it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the substrate. The BGA is then heated to reflow the solder and complete the interconnect.

Heat transfer in the finished system is achieved through two paths: from the backside of the silicon dies into the encapsulant and then into the surrounding air, optionally through a heat sink and through ground signal pads and solder balls into the groundplane of the substrate, and from there through the identified thermal ground balls to the PCB ground plane.




Figure 3. Solder Ball Matrix (Flip Chip construction)

1.1 Daisy Chain Mechanical Samples

Daisy chain mechanical samples of BGA components are available for purchase through DDC (see Table 1). These are used to verify both the electrical and mechanical integrity of the solder joints during board environmental evaluations (such as shock/vibration and temperature cycling) to see how well the solder balls withstand varying mechanical stress conditions.

Alternating ball pairs are internally wired (connected; A1-A2, A3-A4, etc.) so that the user can test for electrical continuity between balls and board. Internal daisy chain interconnections are made by copper PWB traces.

Although these test units are inert, they are fully populated with silicon die (and isolation transformers in Total-ACE version) so that they closely match the thermal and mechanical characteristics of standard production units.

Table 1. Daisy Chain Mechanical Sample

Package Type Description Ball Pitch Series Daisy Chain

Mechanical Sample Part Number

312-Ball BGA 24 x 13 Full-Matrix 1.0mm Total-ACE BU-64843T8-600

324-Ball BGA 18 x 18 Full-Matrix 1.0mm Micro-ACE-TE BU-64863B8-600

128-Ball BGA 18 x 18 Partial-Matrix 1.0mm Micro-ACE BU-61860B3-601




2 THERMAL CONSIDERATIONS 2.1 Thermal Specifications

Table 2 indicates thermal resistance data obtained via simulation for the active transceiver (hottest die). The data includes junction-to-ambient “θJA” in still air (Per JESD 51-2 standard at 25°C), junction-to-case “θJC” at differing air flows (Per JESD 51-6 standard at 25°C), and junction-to-board “θJB” (Per JESD 51-8).

Table 2. Thermal Specifications

Package Type Description Ball Pitch Series θJB

(°C/W) θJC

(°C/W)

θJA (°C/W) in Still

Air

θJA (°C/W)

@ 1M/S

θJA (°C/W)

@ 2M/S

θJA (°C/W)

@ 3M/S

324-Ball BGA 18 x 18 Full-Matrix 0.8mm Total-AceXtreme 46.9 24.5 68.8 52.9 47.1 43.6 312-Ball BGA 24 x 13 Full-Matrix 1.0mm Total-ACE 26.5 26.2 37.8 31.4 29.8 29

2.2 Power Management Strategy

The user’s specific operational environment and conditions makes it difficult for DDC to apply a standard thermal solution other than to recommend that all package thermal connections (balls) performing the dual function of transceiver circuit ground and thermal heat sink be utilized to the maximum extent possible.

It is strongly recommended that these thermal balls (not applicable to all package options) be directly soldered to a circuit ground/thermal plane (a circuit trace is insufficient). Operation without an adequate ground/thermal plane is not recommended and extended exposure to these conditions may affect device reliability.

2.3 System Level Heat Sinking Solutions

Heat sinking of DDC BGA components via custom or off-the-shelf external devices is best left to the system engineer who can modify the design and develop a custom solution within the constraints of the specific application.

2.4 Thermal Management Options

The system board on which the BGA is mounted has a significant impact on thermal performance, as a high percentage of the generated heat will flow through the thermal BGA balls (not applicable to all package options) and into the board when properly designed. Table 2 listed the thermal resistance data (via simulation) for the active transceiver (hottest die) for selected BGA devices. Users should be aware that the




heat path from the hottest die (transceiver) to the board is bi-directional, thus an improperly cooled system board could actually heat the active transceiver.

Under certain conditions it may be advantageous to attach passive heat sinks and heat spreaders to the top of the BGA with thermally conductive double-sided tapes or mechanical retainers. The mass of the heat sink might cause stress cracking of the BGA balls or package under high shock & vibration conditions. It is advisable when using larger, high mass heat sinks that they be mechanically fastened to the PCB in order to prevent component damage.

3 RECOMMENDED PCB DESIGN RULES FOR BGA PACKAGES 3.1 Surface Land Pad

The surface land pad is the area on the printed circuit board (PCB) to which the BGA solder ball adheres. Pad size affects the space available for vias and for escape routing. Surface land pads are typically available in two basic designs; non-solder mask defined (NSMD), aka “copper defined” and solder mask defined (SMD) (See Figure 4). The major differences between the two types are the resulting size of the signal trace and available routing space, the type of vias one can use, and the final shape of the solder ball after solder reflow (see Figure 5 and Figure 6).

• With NSMD pads, the solder mask opening is larger than the copper pad (pad is fully exposed) resulting in a greater surface area for the BGA solder ball to adhere to.

• With SMD pads, the solder mask partially covers the copper pad surface. This provides better adhesion between the copper pad and the PCB but reduces the amount of copper surface area for the BGA solder ball to adhere to.

Figure 4. Surface Land Pads




Figure 5. Surface Land Solder Joints

Figure 6. BGA Pad Dimensions

DDC recommends that for BGA packages, non-solder mask defined (NSMD) pads be utilized for the board land pad as this allows for clearance between the land metal (diameter SL) and the solder mask opening (diameter SM) as shown in Figure 7 and Table 3. This design prevents creation of a stress point in the solder connection by pulling the soldermask away from the pads. The opening between the NSMD pad, solder mask, and signal trace width is dependent upon the manufacturing capabilities




of the PCB vendor. The cost of a PCB typically increases as trace line widths and spaces decrease.

DDC has determined that the best solder joint reliability and fatigue life is obtained when the PCB land pad design provides a balanced stress on the solder joint. BGA pads on most DDC components are solder mask defined. However, DDC recommends the use of NSMD pads on the PCB, with dimensions as specified in Table 3 below to achieve a balanced stress on solder joints. Any overlapping of the solder mask on pad metal by design or mis-registration is strongly discouraged. If solder mask defined pads (SMD) must be used then the surface land pads should be the same size as the BGA pad to provide a balanced stress upon solder joints.

The diameter of the BGA solder mask defined (SMD) component land pad is provided by DDC. This information is necessary before the start of board layout so that board pads are designed to match BGA side land geometry. Typical values of DDC BGA component land pads and the recommended board pad are listed and identified in Table 4.

*4 x 4 Matrix shown for illustration “One land pad shown with via connection”.

Figure 7. BGA Pad Outline Drawing




Table 3. PCB BGA Design

Recommended PCB Design Rules (Dimensions in mm)

324-Ball BGA 312-Ball BGA 324-Ball BGA 128-Ball BGA

18 x 18 Full-Matrix

24 x 13 Full-Matrix

18 x 18 Full-Matrix

18 x 18 Partial-Matrix

Total-AceXtreme Total-ACE Micro-ACE-TE Micro-ACE

Component land pad diameter (CL) (1) 0.46 (SMD) 0.56 (SMD) 0.56 (SMD) 0.5 (NSMD)

Component solder ball (SB) diameter 0.53 0.71 0.71 0.71

Solder land (SL) diameter 0.45 0.5 0.5 0.5

Opening in solder mask (SM) diameter 0.57 0.57 0.57 0.57

Solder (ball) land pitch (lp) 0.80 1.00 1.00 1.00

Line width between via and land (LW) 0.10 0.13 0.13 0.13

Distance between via and land (VLD) 0.56 0.70 0.70 0.70

Via land (VD) diameter 0.45 0.61 0.61 0.61

Through hole (TH) diameter 0.245 0.300 0.300 0.300 Note (1): For SMD pads, the component land pad diameter refers to the size of the opening in the solder mask on the

component. For the NSMD pads on the Micro-Ace component, the number provided is the size of the copper land.

3.2 Board Level Signal Routing

DDC’s BGA packages are a mixture of full matrix and partial matrix of solder balls (Figure 1). These packages are made of multilayer Hi TG-FR4 laminate substrates. Signal, power, and ground balls are interspersed throughout the matrix for routing ease. The number of layers required for routing of BGA packages is dictated by the layout of pins on each package. Figures 10 - 15 provide a visual representation of Package Ball Assignments.

Available via and routing space for 1.00mm & 0.8mm ball pitch BGA NSMD PCB Land Pads is shown in Figure 8 and Figure 9 respectively.




Figure 8. Available Via & Routing Space for 1.00-mm BGA NSMD PCB Land Pads

Figure 9. Available Via & Routing Space for 0.8-mm BGA NSMD PCB Land Pads




A B C D E F G H J K L M N P R T U V

18 NC NC NCCHA_15

53_LCHA_15

53_LCHA_15

53CHA_15

53NC NC NC NC NC

CHB_1553

CHB_1553

CHB_1553_L

CHB_1553_L

NC NC 18

17 NC NC NCCHA_15

53_LCHA_15

53_LCHA_15

53CHA_15

53NC NC NC NC NC

CHB_1553

CHB_1553

CHB_1553_L

CHB_1553_L

NC NC 17

16 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 16

15GND_LOGIC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NCGND_LOGIC

15

14GND_LOGIC

GND_LOGIC

DISAB_BC

DISAB_MULT

_RT

GND_LOGIC

GND_LOGIC

RTAD0

RTAD4

GND_LOGIC

GND_LOGIC

DISCIO (6)

DISCIO (0)

IRIG_DIG_IN

TX_INH_B

nSSFLAG NC

GND_LOGIC

GND_LOGIC

14

13 NCGND_LOGIC

DISAB_BIST

nRTBOOT

TEMP_DIODE

GND_LOGIC

RTAD1

RTADP

DISCIO (4)

DISCIO (1)

DISCIO (3)

TAG_CLK

TAG_ENABLE

TX_INH_A

nSNGEND

USER_OUT_1

USER_OUT_2 NC 13

12GND_LOGIC

GND_LOGIC

+3.3VLOGIC

NCGND_XCVR

GND_XCVR

RTAD3

DISCIO (7)

DISCIO (5)

DISCIO (2)

nMCRST/nINCMD

TAG_LOAD NC

GND_XCVR

GND_XCVR

NC NC NC 12

11GND_LOGIC

GND_LOGIC

PCI_nCPU

GND_LOGIC

GND_XCVR

GND_XCVR

RT_AD_LAT

TXINH_IN_A

TXDATA_OUT_A_

L

TXDATA_IN_A_L

TXINH_OUT_B

TXINH_IN_B NC

GND_XCVR

GND_XCVR

EXT_TRIG NC NC 11

10 JTAGTMS

JTAGTDI

+3.3VLOGIC

+3.3VLOGIC

GND_LOGIC

GND_LOGIC

RTAD2

TXINH_OUT_A

TXDATA_OUT_A

TXDATA_IN_A

TXDATA_OUT_B

TXDATA_IN_B NC NC NC NC

+3.3VXCVR

GND_XCVR

10

9 PCI_INTA#

JTAGnTRST

+3.3VLOGIC

GND_LOGIC

GND_LOGIC

GND_LOGIC

GND_LOGIC

+3.3VLOGIC

RXDATA_IN_A_L

RXDATA_OUT_A_L

TXDATA_OUT_B_

L

TXDATA_IN_B_L

+3.3VXCVR

GND_XCVR

GND_XCVR

+3.3VXCVR

NC NC 9

8 CLOCK_IN

JTAGTDO

+3.3VLOGIC

GND_LOGIC

1.8VPLL

1.8VCORE

GND_LOGIC

+3.3VLOGIC

RXDATA_IN_A

RXDATA_OUT_A

TRIG_SEL NC

+3.3VXCVR

GND_XCVR

GND_XCVR

+3.3VXCVR

NC NC 8

7 JTAGTCK

PCIREQ#/CPU_ADD

R(12)

+3.3VLOGIC

GND_LOGIC

1.8VCORE

1.8VCORE

GND_LOGIC

+3.3VLOGIC

CPU_ASYNC_nS

YNC

POL_SEL

CPU_AD_

MULTI

+3.3VLOGIC

+3.3VXCVR

GND_XCVR

GND_XCVR

+3.3VXCVR

RXDATA_IN_B_L

RXDATA_OUT_B_L 7

6PCI_GNT#/CPU_ADDR (13)

RST#/nMSTCLR

+3.3VLOGIC

GND_LOGIC

1.8VCORE

1.8VCORE

GND_LOGIC

+3.3VLOGIC

RD_nWR

DATA32_n16

MSW_nLSW

nDATA_STRB

+3.3VXCVR

GND_XCVR

GND_XCVR

+3.3VXCVR

RXDATA_IN_B

RXDATA_OUT_B 6

5 PCI_AD31/DATA31

PCI_AD29/DATA29

+3.3VLOGIC

GND_LOGIC

1.8VCORE

1.8VCORE

GND_LOGIC

+3.3VLOGIC

PCI_AD17/DATA17

C/BE1#/CPU_ADDR

(1)

PCI_AD0/DATA0

PCI_AD3/DATA3

+3.3VXCVR

GND_XCVR

GND_XCVR

+3.3VXCVR

NC NC 5

4 PCI_AD30/DATA30

PCI_AD28/DATA28

+3.3VLOGIC

GND_LOGIC

GND_LOGIC

GND_LOGIC

GND_LOGIC

+3.3VLOGIC

C/BE2#/CPU_ADDR

(2)

PCI_AD1/DATA1

PCI_AD2/DATA2

PCI_AD5/DATA5

PCI_AD6/DATA6

CPU_WDEN1

CPU_nBLAST

CPU_ADDR15 NC NC 4

3 NC PCI_AD27/DATA27

PCI_IRDY#/CPU_AD

DR(7)

PCI_AD24/DATA24

PCI_AD21/DATA21

PCI_AD20/DATA20

PCI_AD18/DATA18

PCI_FRAME#/CPU_ADDR(5)

PCI_TRDY#/CPU_AD

DR(6)

PCI_AD4/DATA4

PCI_AD11/DATA11

C/BE0#/CPU_ADDR(0)

PCI_AD7/DATA7

CPU_WDEN0

ADDR_LAT

CPU_ADDR14 NC NC 3

2 NC NC PCI_AD25/DATA25

PCI_IDSEL/CPU_AD

DR(10)

PCI_AD22/DATA22

HOST_CLK

PCI_PERR#/CPU_AD

DR(11)

PCI_STOP#/CPU_AD

DR(8)

PCI_SERR#

PCI_AD10/DATA10

PCI_PAR/CPU_ADD

R(4)

PCI_AD14/DATA14

PCI_AD8/DATA8 nINT MEM_

nREGnSELEC

T NC NC 2

1 NC NC NC PCI_AD26/DATA26

C/BE3#/CPU_ADDR

(3)

PCI_AD23/DATA23

PCI_AD19/DATA19

PCI_AD16/DATA16

DEVSEL#/CPU_ADD

R(9)

PCI_AD15/DATA15

PCI_AD13/DATA13

PCI_AD9/DATA9

PCI_AD12/DATA12

CPU_nSTOP

nDATA_RDY NC NC NC 1


MCM BALL LAYOUT LOOKING TOP DOWN THRU MCM

PCI BUS 1553 MISC TEST / PROGRAM PAD XCVR MISCCPU BUS MISC CONFIG PAD (STATIC)

Figure 10. Total-AceXtreme (0.8mm Ball Pitch) BGA Pin Assignments




Figure 11. Total-ACE (1.0mm Ball Pitch) BGA Pin Assignments

CHA_15 53-DIR*

CHA_15 53-DIR*

CHA_15 53-DIR* CHB_15

53-DIR* CHB_15 53-DIR*

CHB_15 53-DIR*

CHA_15 53-DIR CHA_15

53-DIR CHB_15 53-DIR CHB_15

53-DIR CHB_15 53-DIR CHA_15

53-DIR

A B C D E F G H J K L M N 24 LOGIC_

GND LOGIC_ GND LOGIC_

GND INT* D14 D10 D04 D00 (LSB) RTAD3 RT_AD_

_LAT LOGIC_ GND LOGIC_

GND LOGIC_ GND 24

23 LOGIC_ GND LOGIC_

GND LOGIC_ GND TAG_CL

K D12 D08 D06 D02 RTADP RTAD1 LOGIC_ GND LOGIC_

GND LOGIC_ GND 23

22 LOGIC_ GND LOGIC_

GND LOGIC_ GND TRANS/

BUFF* D13 D09 D05 D01 RTAD2 RSTBIT EN LOGIC_


GND 22

21 SNGL_E ND* BC_DIS

ABLE READY D* D15

(MSB) D11 D07 D03 INCMD* RTAD4 (MSB)

RTAD0 (LSB) NC NC NC 21

20 TX_INH_ A LOGIC_

GND IOEN* TX_INH_ B NC NC NC LOGIC_

GND LOGIC_ GND NC NC TXINH_I

N_B +3.3v_L OGIC 20

19 UPADD REN/LO

GIC 1 NC NC MCRST *

LOGIC_ GND LOGIC_


GND LOGIC_ GND

TXDATA _OUT_B

* NC TXINH_ OUT_B +3.3v_L

OGIC 19

18 STRBD* SELEC T* MEM/R

EG* MSTCL R*

LOGIC_ GND LOGIC_


GND LOGIC_ GND TXDATA

_IN_B* NC TRIG_S EL/ME

MENA_I CLOCK

_IN 18

17 RD/WR* +3.3v_L OGIC

+3.3v_L OGIC

A15/ CLK_S EL_1

LOGIC_ GND LOGIC_


GND LOGIC_ GND NC 16/8*/D

TREQ* +3.3v_L OGIC

POL_S EL/DTA

CK* 17

16 A14/CLK _SEL_0 +3.3v_L

OGIC +3.3v_L

OGIC A13/LO GIC "1" NC A00

(LSB) NC NC TXDATA _IN_B

TXDATA _OUT_B

ADDR_ LAT/ME MOE*

+3.3v_L OGIC

ZERWA IT*/ME MWR* 16

15 A10 A12/RT BOOT* A11

(MSB) A06 A04 A02 NC NC NC NC LOGIC_ GND LOGIC_

GND NC 15

14 A09 TXDATA _IN_A*

TXDATA _OUT_A

* A08 A01 +3.3v_L OGIC

+3.3v_L OGIC NC

MSB/LS B/DTGR

T* SSFLAG */EXT_T

RIG LOGIC_

GND LOGIC_ GND NC 14

13 TXINH_ OUT_A NC NC NC A05 +3.3v_L

OGIC +3.3v_L

OGIC NC NC NC NC RXDAT A_IN_B* RXDAT

A_IN_B 13

12 TXINH_I N_A A07 +3.3V_X

CVR +3.3V_X

CVR A03 RXDAT A_OUT_

A* RXDAT

A_IN_A* NC NC +3.3V_X CVR

+3.3V_X CVR

RXDAT A_OUT_

B* RXDAT

A_OUT_ B 12

11 NC XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

RXDATA _OUT_A RXDATA

_IN_A NC XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND NC 11

10 TXDATA _OUT_A

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND NC NC SLEEPI

N XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND NC 10

9 TXDATA _IN_A

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND NC +3.3V_X

CVR NC XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

+3.3V_X CVR 9

8 NC +3.3V_X CVR

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND NC NC +3.3V_X

CVR NC NC XCVR_T HERMA L_GND

XCVR_T HERMA L_GND NC NC 8

7 NC +3.3V_X CVR

+3.3V_X CVR NC NC NC +3.3V_X

CVR NC NC NC +3.3V_X CVR

+3.3V_X CVR NC 7

6 NC +3.3V_X CVR

+3.3V_X CVR NC NC NC +3.3V_X

CVR NC NC NC +3.3V_X CVR

+3.3V_X CVR NC 6

5 NC NC NC NC NC NC NC NC NC NC NC NC NC 5

4 NC NC NC NC NC NC NC 4

3 XCVR_ GND XCVR_

GND NC CHA_15 53 CHA_15

53* NC CHB_15 53 CHB_15

53* NC XCVR_ GND XCVR_

GND 3

2 XCVR_ GND XCVR_


53* NC CHB_15 53 CHB_15


GND 2

1 XCVR_ GND XCVR_


53* NC CHB_15 53 CHB_15


GND 1 A B C D E F G H J K L M N

GND No Connect +3.3V Power CPU INTERFACE

1553 MISC

XCVR MISC MCM BALL LAYOUT LOOKING TOP DOWN THRU MCM




A B C D E F G H J K L M N

24 GND GND GND AD11 SERR# AD14 AD19 AD16 AD23 AD24 GND GND GND 24

23 GND GND GND TAG_CLK PERR# TRDY# AD21 C/BE(2)

# AD18 AD17 GND GND GND 23

22 GND GND GND AD13 STOP# PAR IRDY# AD20 INTA# CLK_SEL_0 GND GND GND 22

21 SNGL_END*

CLK_SEL_1 AD12 AD15 C/BE{1}

#DEVSE

L# FRAME3 AD28 AD22 IDSEL# NC NC NC 21

20 AD9 BC_DISABLE AD10 AD8 NC NC NC GND GND NC NC TXINH_I

N_B

+3.3v_LOGIC

20

19 RTBOOT* NC NC NC GND GND GND GND GND TXDATA

_OUT_B* NC TXINH_OUT_B

+3.3v_LOGIC

19

18 AD7 C/BE(0)#

RTAD0 (LSB)

MSTCLR/RST# GND GND GND GND GND TXDATA

_IN_B* NC AD26 PCI_CLK 18

17 AD6

+3.3v_LOGIC

+3.3v_LOGIC

AD4 GND GND GND GND GND NC AD29

+3.3v_LOGIC

AD25 17

16 RTAD4 (MSB)

+3.3v_LOGIC

+3.3v_LOGIC

AD0 NC TX_INH_A/B NC NC TXDAT

A_IN_BTXDATA_OUT_B

SSFLAG*/EXT_TRIG

+3.3v_LOGIC

AD30 16

15 RTAD2 AD1 RTAD1 AD31 1553_CLK

INCMD*/MCRST

*NC NC NC NC GND GND NC 15

14 AD2 TXDATA_IN_A*

TXDATA_OUT_

A*RTAD3 AD27

+3.3v_LOGIC

+3.3v_LOGIC

NC AD5 C/BE{3}# GND GND NC 14

13 TXINH_OUT_A NC NC NC AD3

+3.3v_LOGIC

+3.3v_LOGIC

NC NC NC NC RXDATA_IN_B*

RXDATA_IN_B 13

12 TXINH_IN_A

RT_AD_LAT

+3.3V_X

CVR

+3.3V_X

CVRRTADP

RXDATA_OUT_

A*

RXDATA_IN_A* NC NC

+3.3V_X

CVR

+3.3V_X

CVR

RXDATA_OUT_

B*

RXDATA_OUT_

B12

11 NCXCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

RXDATA_OUT_A

RXDATA_IN_A NC

XCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

NC 11

10 TXDATA_OUT_A

XCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

NC NC GNDXCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

NC 10

9 TXDATA_IN_A

XCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

NC

+3.3V_XCVR

NCXCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

XCVR_THERMAL_GN

+3.3V_X

CVR9

8 NC

+3.3V_XCVR

XCVR_THERMAL_GN

XCVR_THERMAL_GN

NC NC

+3.3V_XCVR

NC NCXCVR_THERMAL_GN

XCVR_THERMAL_GN

NC NC 8

7 NC

+3.3V_XCVR

+3.3V_X

CVRNC NC NC

+3.3V_X

CVRNC NC NC

+3.3V_X

CVR

+3.3V_X

CVRNC 7

6 NC

+3.3V_XCVR

+3.3V_X

CVRNC NC NC

+3.3V_X

CVRNC NC NC

+3.3V_X

CVR

+3.3V_X

CVRNC 6

5 NC NC NC NC NC NC NC NC NC NC NC NC NC 5

4 NC NC NC CHA_1553-DIR

CHA_1553-DIR

CHA_1553-DIR NC CHA_15

53-DIRCHA_1553-DIR

CHA_1553-DIR NC NC NC 4

3 GND GND NC CHA_1553

CHA_1553-DIR*

CHA_1553* NC CHB_15

53CHA_1553-DIR*

CHB_1553* NC GND GND 3


CHA_1553-DIR*

CHA_1553* NC CHB_15

53CHA_1553-DIR*



CHA_1553-DIR*

CHA_1553* NC CHB_15

53CHA_1553-DIR*


A B C D E F G H J K L M N

GNDNo Connect +3.3V Power


XCVR MISC PCI INTERFACE1553 MISC

Figure 12. PCI-Total-ACE (1.0mm Ball Pitch) BGA Pin Assignments




Figure 13. Micro-ACE-TE (1.0mm Ball Pitch) ( with +5.0V transceivers) BGA Pin Assignments


18 NC NC NCTAG_CL

K D12 D08 D06 D02 RTADP RTAD1RT_AD_

LATRSTBIT

EN NC NC NC NC NC NC 18

17 NC NC NC INT* D14 D07 D04D00

(LSB) D01 RTAD3 RTAD2 NC NC NC NC NC NC NC 17

16 NC NC NCTRANS/BUFF* D13 D10 D05 INCMD*

RTAD4 (MSB)

RTAD0 (LSB)

+3.3/+5V Logic NC NC NC NC NC NC NC 16

15 SNGL_END* NC

READYD*

D15 (MSB) D11 D09 D03 NC NC NC

+3.3/+5V Logic NC NC

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

Tx/Rx-B*

Tx/Rx-B* 15

14 TX_INH_A NC IOEN* NC GND GND GND GND NC NC NC

RXDATA_OUT_

B*

RXDATA_OUT_

B

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

Tx/Rx-B* 14

13 VDD_Low*

MCRST*

TX_INH_B NC GND GND GND GND NC NC NC

RXDATA_IN_B*

RXDATA_IN_B

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

+5V_XC

VR

+5V_XC

VR13

12 STRBD*SELEC

T*

UPADDREN/LO

GIC 1NC GND GND GND GND NC NC NC

TXDATA_OUT_B

*

TXDATA_IN_B*

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

Tx/Rx-B 12

11 RD/WR*MSTCL

R*MEM/R

EG* NC NC NC NC NC NC NCTRIG_SEL/ME

MENA_INC NC

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

Tx/Rx-B Tx/Rx-B 11

10A14/CLK_SEL_

0

A13/Vcc

A15/CLK_SEL_

1

RXDATA_IN_A*

RXDATA_OUT_

A*A00 NC NC NC NC

16/8*/DTREQ*

ZEROWAIT*/MEMWR*

NCTXDATA_OUT_B

TXDATA_IN_B NC NC NC 10

9 A12/RTBOOT* A11 A08 NC

RXDATA_IN_A

RXDATA_OUT_A NC NC NC NC

ADDR_LAT/MEMOE*

CLK_INPOL_SEL/DTA

CK*

+3.3/+5V Logic

+3.3/+5V Logic NC NC NC 9

8 A10TXDATA_OUT_A

TXDATA_IN_A A04 A02 NC NC NC

SSFLAG*EXT_

TRIGNC NC NC NC NC

TXINH_OUT_B

TXINH_IN_B NC

+3.3/+5V Logic 8

7 +3.3/+5V Logic A09 A07 A06 A01 NC NC NC

MSB/LSB/DTGR

T*NC NC NC NC

+3.3/+5V Logic NC NC NC NC 7

6 NC NC A05 A03 NC NC NC NC NC NC NC NC NC NC NC NC NC NC 6

5 TXINH_OUT_A NC

TXDATA_OUT_A

*

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

NC NC NC NC NC NC NC NC NC NC 5

4 TXINH_IN_A NC

TXDATA_IN_A*

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

NC NC NC NC NC

+5V_RAM

+5V_RA

MNC NC NC 4

3 NC NC NCXCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

XCVR_THERMAL_GND

NC NC NC+3.3/+5V Logic NC NC NC NC NC NC 3

2 NC NC NC Tx/Rx-AXCVR_THERMAL_GND

+5V_XC

VR

XCVR_THERMAL_GND

Tx/Rx-A* NC NC


1 NC NC NC Tx/Rx-A Tx/Rx-A

+5V_XCVR

Tx/Rx-A*

Tx/Rx-A* NC NC



CPU INTERFACE GNDNo Connect +3.3/+5V Power


XCVR MISC1553 MISC




Figure 14. Micro-ACE-TE (1.0mm Ball Pitch) (with +3.3V transceivers) BGA Pin Assignments

A B C D E F G H J K L M N P R T U V 18 NC NC NC INT* D10 D12 D08 D04 D06 RTADP RTAD1 RTAD3 RTAD0

(LSB) RT_AD_ LAT MSTCL

R* NC NC NC 18

17 NC NC NC TRANS/ BUFF* D11 D07 D03 D05 D02 D00

(LSB) +3.3v_L OGIC

+3.3v_L OGIC

TRIG_S EL/ME

MENA_I INCMD* 16/8*/D TREQ* NC NC NC 17

16 NC NC NC D15 (MSB) D13 D09 NC NC RTAD2 D01 +3.3v_L

OGIC +3.3v_L

OGIC NC NC NC NC NC NC 16

15 IOEN* READY D* A10 NC NC D14 NC NC RTAD4

(MSB) NC NC NC NC NC NC NC NC NC 15

14 TX_INH_ A TX_INH_

B NC SNGL_E ND* NC TAG_CL

K NC NC NC NC RSTBIT EN NC NC NC NC NC NC NC 14

13 NC NC NC NC NC NC NC NC NC NC NC NC +3.3v_L OGIC

+3.3v_L OGIC GND GND GND NC 13

12 STRBD* SELEC T* A05 NC GND GND GND GND NC NC NC NC +3.3v_L

OGIC +3.3v_L

OGIC GND GND GND NC 12

11 A15/CL K_SEL_

1 RD/WR* NC MCRST * GND GND GND GND NC NC NC NC NC NC GND GND GND NC 11

10 A12/RT BOOT* A13/Vc

c A09 A08 GND GND GND GND NC NC NC NC NC RXDAT A_IN_B* RXDAT

A_IN_B CLK_IN ADDR_ LAT/ME MOE* NC 10

9 +3.3v_L OGIC

+3.3v_L OGIC A02 A07 A03 NC NC NC NC NC NC NC NC RXDAT

A_OUT_ B*

RXDAT A_OUT_

B NC NC A06 9

8 +3.3v_L OGIC

+3.3v_L OGIC

TXDATA _OUT_A

TXDATA _OUT_A

* TXINH_ OUT_A A00 RXDAT

A_IN_A* RXDATA

_IN_A NC NC TXDATA _OUT_B

TXDATA _OUT_B

* TXINH_ OUT_B NC SSFLA

G*EXT_ TRIG

ZEROW AIT*/ME MWR* A01 POL_S

EL/DTA CK* 8

7 A14/CL K_SEL_

0 A04 TXDATA _IN_A TXDATA

_IN_A* TXINH_I

N_A UPADD REN/LO

GIC 1 RXDAT

A_OUT_ A*

RXDATA _OUT_A NC NC TXDATA

_IN_B TXDATA _IN_B* TXINH_I

N_B NC +3.3v_L OGIC

+3.3v_L OGIC

+3.3v_L OGIC

+3.3v_L OGIC 7

6 MEM/R EG*

MSB/LS B/DTGR

T* NC NC A11 NC NC NC NC NC NC NC NC NC +3.3v_L OGIC

+3.3v_L OGIC

+3.3v_L OGIC

+3.3v_L OGIC 6

5 +3.3V_X CVR

+3.3V_X CVR NC XCVR_T

HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND


CVR +3.3V_X

CVR XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND NC NC +3.3V_X

CVR +3.3V_X

CVR 5

4 +3.3V_X CVR

+3.3V_X CVR NC XCVR_T

HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND


CVR +3.3V_X


XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

SLEEPI N NC +3.3V_X

CVR +3.3V_X

CVR 4

3 NC NC NC XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND


CVR +3.3V_X


XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND NC NC NC NC 3

2 NC NC NC Tx/Rx-A Tx/Rx-A XCVR_T HERMA L_GND

Tx/Rx- A* Tx/Rx-

A* +3.3V_X CVR

+3.3V_X CVR Tx/Rx-B Tx/Rx-B XCVR_T

HERMA L_GND

Tx/Rx- B* Tx/Rx-

B* NC NC NC 2

1 NC NC NC Tx/Rx-A Tx/Rx-A XCVR_T HERMA L_GND

Tx/Rx- A* Tx/Rx-

A* +3.3V_X CVR

+3.3V_X CVR Tx/Rx-B Tx/Rx-B XCVR_T

HERMA L_GND

Tx/Rx- B* Tx/Rx-

B* NC NC NC 1 A B C D E F G H J K L M N P R T U V

CPU INTERFACE GND No Connect +3.3/+5V Power

MCM BALL LAYOUT LOOKING TOP DOWN THRU MCM XCVR MISC 1553 MISC




Figure 15. Micro-ACE (1.0mm Ball Pitch) BGA Pin Assignments

A B C D E F G H J K L M N P R T U V 18 INT* TAG_CL

K GND D14 D12 D8 D2 D0 (LSB) D6 GND +3.3/+5

V Logic D4 D9 RT_AD_ LAT NC RTADP RTAD3 RTAD1 18

17 IOEN* TRANS/ BUFF* GND D15

(MSB) D11 D7 D3 D5 D13 GND +3.3/+5 V Logic D1 D10 RSTBIT

EN NC RTAD4 (MSB) RTAD2 RTAD0

(LSB) 17

16 +3.3/+5 V Logic +3.3/+5

V Logic Tx/Rx- B* Tx/Rx-

B* 16

15 TX_INH_ B READY

D* XCVR_T HERMA L_GND

+5V_XC VR 15

14 TX_INH_ A STRBD* XCVR_T

HERMA L_GND

+5V_XC VR 14

13 MCRST * MEM/R

EG* XCVR_T HERMA L_GND

+5V_XC VR 13

12 RD/WR* SELEC T* Tx/Rx-B Tx/Rx-B 12

11 A15/CL K_SEL_

1 MSTCL

R* NC NC 11

10 A13/Vc c

A14/CL K_SEL_

0 NC NC 10

9 GND GND GND CLK 9

8 +3.3/+5 V Logic +3.3/+5

V Logic ZEROW AIT*/ME MWR*

ADDR_ LAT/ME MOE* 8

7 A12/RT BOOT* A11 POL_S

EL/DTA CK*

16/8*/D TREQ* 7

6 A10 A9 MSB/LS B/DTGR

T* TRIG_S EL/ME

MENA_I 6

5 A7 A8 NC NC 5

4 A6 A5 GND GND 4

3 A4 A3 +5V_RA M

+5V_RA M 3

2 A2 NC NC Tx/Rx-A XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

XCVR_T HERMA L_GND

Tx/Rx- A* NC NC +3.3/+5

V Logic NC UPADD REN/LO

GIC 1 NC NC SSFLA G*EXT_

TRIG NC Vdd_Lo w 2

1 A0 (LSB) A1 NC Tx/Rx-A +5V_XC

VR +5V_XC

VR +5V_XC

VR Tx/Rx-

A* NC NC +3.3/+5 V Logic INCMD* NC NC NC NC NC GND 1


XCVR MISC CPU INTERFACE GND 1553 MISC No Connect +3.3/+5V Power





4 REFLOW SOLDERING PROCESS 4.1 Solder Reflow Guidlines

The user’s specific equipment and board loading/layout makes it difficult for DDC to propose a standard reflow solution other than to recommend that the user reference the reflow profile detailed in IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.” This reflow profile is applicable to all of DDCs plastic BGA products in both leaded and lead-free versions. DDC recommends using Daisy Chain Mechanical Samples (Table 1) to qualify the PCB assembly processes in lieu of actual devices.

4.2 Package Peak Reflow Temperature

The maximum peak reflow temperature of the plastic BGA case must not exceed +245 °C under any circumstances. This limitation is applicable to all of DDCs plastic BGA products in both leaded and lead-free versions.

4.3 Underfill

Solder reflow of a BGA device using the previously stated recommendations will produce good mechanical and thermal properties. In some instances the strength of the BGA solder bonds can be compromised by external forces. In those cases underfill (Figure 16) can be used to increase the strength of the BGA bond by 5 to 10 times and improve the thermal performance as well.

Figure 16. BGA Device with Underfill

The underfill is drawn under the BGA by capillary action and the temperature is held until the product has cured. Fast-curing underfills can be ready in several minutes, while some can take up to 90 minutes before reaching optimal strength.




When selecting an underfill, the user should be aware that rework may prove difficult or impossible depending on the chosen material.

5 MOISTURE SENSITIVITY OF PLASTIC BGAS 5.1 Moisture-Induced Cracking and Popcorning during Solder Reflow

Surface mount reflow processing subjects plastic BGAs to large thermal excursions and harsh chemicals from solder fluxes and cleaning fluids during assembly. Although minimized through BGA design elements, additional stresses exist due to differences between the Thermal Coefficient of Expansion (TCE) of the encapsulant, the Hi TG-FR4 substrate and multiple silicon die.

Hard pot epoxy mold compounds used in encapsulating BGAs absorb moisture (hygroscopic) determined by the storage environment and other factors. This moisture can vaporize (steam) during the rapid heating inherent in the solder reflow process, creating high internal pressures. These pressures may be sufficient to cause delamination, internal / external cracking, and broken/lifted bond wires.

Moisture sensitivity testing, handling procedures, and standards are maintained by two national organizations. DDC recommends that end users obtain copies of the documents below (available from www.jedec.org) and incorporate the procedures and recommendations into their standard process.

IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.”

AND

IPC/JEDEC J-STD-033 “Standard for Handling, Packing, Shipping, and Use of Moisture/Reflow Sensitive Surface Mount Devices.”

5.2 Assigned Package Moisture Sensitivity Level (MSL)

Table 5 depicts the DDC assigned MSL level for various packages. Specific MSL information and the recommended bake-out procedure are printed on the dry pack shipping bag in which the components are shipped. The MSL level printed on the dry pack shipping bag takes precedence over the values listed in Table 5.




Table 4. Moisture Sensitivity Level

Package Type Description Ball Pitch Series MSL Rating

324-Ball BGA 18 x 18 Full-Matrix 0.8mm Total-AceXtreme MSL-3

312-Ball BGA 24 x 13 Full-Matrix 1.0mm Total-ACE MSL-3

324-Ball BGA 18 x 18 Full-Matrix 1.0mm Micro-ACE-TE MSL-3

128-Ball BGA 18 x 18 Partial-Matrix 1.0mm Micro-ACE MSL-3

5.3 Electrostatic Discharge Sensitivity (ESD)

TABLE 6 depicts the DDC assigned ESD class for various packages. These devices can be damaged by electrostatic discharges < 250 volts and should be handled appropriately.

Table 5. Electrostatic Discharge Sensitivity

Package Type Description Ball Pitch Series ESD Rating

324-Ball BGA 18 x 18 Full-Matrix 0.8mm Total-ACExtreme Class 0

312-Ball BGA 24 x 13 Full-Matrix 1.0mm Total-ACE Class 0

324-Ball BGA 18 x 18 Full-Matrix 1.0mm Micro-ACE-TE Class 0

128-Ball BGA 18 x 18 Partial-Matrix 1.0mm Micro-ACE Class 0

DDC's ESD testing, handling procedures, and standards are based on the United States Military Standards listed below. DDC recommends that end users obtain copies of the documents below (available from http://global.ihs.com) and incorporate the procedures and recommendations into their standard process.

MIL-STD-750D “Test Method Standard for Semiconductor Devices”

AND

MIL-STD-1686C “Electrostatic Discharge Control Program for Protection of Electrical and Electronic Parts, Assemblies and Equipment”

6 REWORKING OF PLASTIC BGAS It is extremely important that proper procedures be followed to ensure successful reworking of Plastic BGAs. The same caveats regarding bake-out due to the hygroscopic nature of the hard pot epoxy encapsulation apply during the rework process as well. The printed circuit board must always be pre-baked before any




rework operation. It is recommended that the specific instructions provided by the manufacturer of the rework system be followed.

Specialized equipment and tools allowing for localized plastic BGA removal are commercially available. Hot gas rework systems with vacuum suction are recommended as these ensure that the component and the PCB board are not warped or overheated and that all balls are reflowed.

6.1 BGA Reballing

DDC does not recommend reballing of BGA components due to cost and durability concerns. A maximum of three reflow cycles are allowed.

6.2 Conformal Coating

DDC plastic (HardPot Epoxy) BGA components are compatible with both Urethane & Polyurethane conformal coating.

7 BGA PACKAGE LABELS 7.1 Package Marking (Symbolization)

All DDC BGA devices have package marking similar to the example shown in Figures 17 - 19. Marking can be laser inscribed or be in the form of a permanent Mylar label.

Figure 17. Total-AceXtreme Package Markings




Figure 18. Total-ACE Package Markings

Figure 19. Micro-ACE-TE Package Markings




Figure 20. Micro-ACE Package Markings


AN/B-49 5/13-0

The information in this Application Note is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice.

Outside the U.S. - Call 1-631-567-5700

United Kingdom: DDC U.K., LTD Mill Reef House, 9-14 Cheap Street, Newbury, Berkshire RG14 5DD, England Tel: +44 1635 811140 Fax: +44 1635 32264

France: DDC Electronique 10 Rue Carle-Herbert 92400 Courbevoie France Tel: +33-1-41-16-3424 Fax: +33-1-41-16-3425

Germany: DDC Elektronik GmbH Triebstrasse 3, D-80993 München, Germany Tel: +49 (0) 89-15 00 12-11 Fax: +49 (0) 89-15 00 12-22

Japan: DDC Electronics K.K. Dai-ichi Magami Bldg, 8F, 1-5, Koraku 1-chome, Bunkyo-ku, Tokyo 112-0004, Japan Tel: 81-3-3814-7688 Fax: 81-3-3814-7689 Web site: www.ddcjapan.co.jp

Asia: Data Device Corporation - RO Registered in Singapore Blk-327 Hougang Ave 5 #05-164 Singapore 530327 Tel: +65 6489 4801

Inside the U.S. - Call Toll-Free 1-800-DDC-5757

Headquarters and Main Plant 105 Wilbur Place, Bohemia, NY 11716-2426 Tel: (631) 567-5600 Fax: (631) 567-7358 Toll-Free, Customer Service: 1-800-DDC-5757

Web site: www.ddc-web.com

DATA DEVICE CORPORATIONREGISTERED TO:

ISO 9001:2008, AS9100C:2009-01EN9100:2009, JIS Q9100:2009

FILE NO. 10001296 ASH09

RE

GIS T E R E D F

IRM

®U

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Documents

BGA User's Guide - Data Device Corporation · BGA package also contains multiple, silicon on a printed circuit board with hard dies pot epoxy encapsulation but uses solder bumps in,