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SPI-07 – May 14, 2007 Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Motivation SPICE-based design space explorations are not viable due to system complexity Physical gap Hell of nano-scale physics 500M Transistor Platform Design-Productivity Gap Degradation of RC propagation delay across on-chip interconnects Low-swing signaling and coding for low-power Increased sensitivity to on-chip noise sources Development of accurate physical models and their abstraction into accurate compact models are mandatory for designing complex circuits
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[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Alessandro BoglioloUniversity of Urbino
Nicola Terrassan and Davide BertozziUniversity of Ferrara
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Outline1. Motivation2. Physical channel design3. Analytical model
• Design• Validation against HSPICE
4. Macromodel integration in SystemC• Accuracy assessment
5. Applications and conclusions
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
MotivationSPICE-based design space explorations are not viable due to system complexity
Physical gap
Hell of nano-scale physics
500M Transistor Platform
Design-Productivity GapIP coremasterIF
IFIP coreslave
switch
IP coremasterIF
IP coremaster IF
IFIP coreslave
IF IP coreslave
switch
switch
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Network on Chip
IP coremasterIF IP coremasterIF
IFIP coreslave IFIP coreslave
switch
IP coremasterIF IP coremasterIF
IP coremaster IFIP coremaster IF
IFIP coreslave IFIP coreslave
IF IP coreslaveIF IP coreslave
switch
switch
switch
Network on Chip
• Degradation of RC propagation delay across on-chip interconnects• Low-swing signaling and coding for low-power• Increased sensitivity to on-chip noise sources
Development of accurate physical models
and their abstraction into accurate compact models are mandatory for designing
complex circuits
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Objective of the workData out
FF in FF out
Data in
Driver
RC line
Receiver
Communication channel driver, interconnect, receiver, sampling stages Target: 1 GHz operating frequency, low-power, high throughput links
Scalability analysis From 130 to 90 nm, Berkeley Predictive Technology Models
Analytical model capturing the effects of on-chip noise sources on the channel sub-systems based on the noise sensitive area concept
Paramet. bit-level model of noisy on-chip communication channelsMacromodel integration in SystemC for system-level simulation
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Outline1. Motivation2. Physical channel design3. Analytical model
• Design• Validation against HSPICE
4. Macromodel integration in SystemC• Accuracy assessment
5. Applications and conclusions
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication ChannelsPseudo-differential
interconnect
Driver
RC Line
PDIFF receiver
Clocked sense amplifier
Static FF
• Makes use of a single wire per bit while still retaining most advantages of differential signaling: low swing, low sensitivity to supply noise
• Sources of reliability degradation: mismatches of input pair TNs or REFs
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Delay breakdown130nm technology node
Transistor sizing with Hspice optimization engineVdd=1.2V, Swing=0.2V
Interconnect length=2mm (intermediate metal layer)
Maximum Frequency: 1.35Ghz SAFF Flip Flop and PDIFF receiver are the delay bottlenecks
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Delay scalability130 nm technology node
• Vdd = 1,2 V• Swing = 0,2 V• Interconnect length = 2 mm• Intermediate metal layer• FMAX (130 nm)= 1,35 GHz
90 nm technology node• Vdd = 1 V• Swing = 0,2 V (to preserve noise margins)• Interconnect length = 2 mm• Intermediate metal layer• FMAX (90 nm)= 1,45 GHz
Propagation delay. Logic 1-to-0 transition
Scaling of gate delay Interconnect delay does not scale (51% degradation)
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Power breakdown130nm 90nm
Total Power: 98,968 µW 38,532 µW
Scaling factor of power ranges from 0.24x (SAFF) to 0.52x (NOR Latch) Interconnect power increases by 1.1x FF, driver and receiver are the most power-hungry components Interconnect power relevant only in 90nm Overall channel power reduces by 60%
30%
30%
7%
26%
7%
SAFFDriverRC linePDIFFLatch NOR
19%
27%
20%
24%
10%
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Outline1. Motivation2. Physical channel design3. Analytical model
• Design• Validation against HSPICE
4. Macromodel integration in SystemC• Accuracy assessment
5. Applications and conclusions
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Modelling approachsplitting the communication channel in two parts:
a driving section and a driven section
Data in
Driver
RC line
ReceiverFF in FF out
Data out
Splitting pointDriving section Driven section
Provides a signal waveformPoses conditions to its shapeto guarantee correct sampling
Error probability evaluatedby comparing the signal provided by the driving section
with the requirements posed by the driven section
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Noise sensitive areasReceiver requirements modelled through noise sensitive areas:
Vin
Hold Timet0
Vswing=0.2
Receiv. FFVin
clock
Triggering condition: a requirement on the input voltage at sampling timeSA-based receiver imposes holding requirements on the input signal:
the stronger the signal the shorter the hold time
regions in the signal-time plane which are forbidden to the signal waveform
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Experimental NSA
130 nm technology
node –
10% positive injected noise
on Vdd
A positive Vdd variation at the receiver shrinks the NSAThe receiver takes less time to sample input signals
Triggering condition reduces to: Vin higher than 0.140V (for sampling a logic 1) Vin lower than 0.065V (for sampling a logic 0)
nominal
Vin [V]
Thold [ps]
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Parametric NSA modelMeasured parameters are manipulated in order to use linear regressions to fit experimental data with a minimum number of fitting coefficients
1.01.11.2 cVddcGndcc
)Vc(VT
1LTin2
hold
LTeffin1.01.11.2hold VVcVddcGndc
1T
2VV
2VV
VV mgnd_ref_noref_nomgnd_refrefLTLTeff
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Model accuracy• Analytical models of Thold evaluated for different
random combinations of noise sources and Vin values
• HSPICE sweep simulations conducted with injected noise sources to determine the minimum hold time
• Results:– Average error: 3.5% in 130 nm (4.95% in 90nm)– Maximum error: 17.53% in 130 nm (23.5% in 90nm)
for concurrent common-mode noise on Vref and Vgnd
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Driving subcircuit modelData in
DriverRC line
FF in
Vin
Time (ps)
Far-E
nd V
olta
ge (m
V)
Far-end signal waveform approximated by a delay
followed by an exponential transient
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Exponential transient model t0)c(t
refin exp1GndVGndV
t0)c(trefrefin exp1V-GndVV
dd_nom
dd
012
2 VV
clclc1c
dd_nom
dd
0r0t0
rt
r0w0w0t0
rwwt12
w0w0
ww2 V
VcCR
CRl)CRCRCRCR(clCR
CRc1c
Logic 0 to 1 transition
Logic 1 to 0 transition
c is the slope parameter, experimentally approximated by:
Almost insensitive to Vref variationsDepends on interconnect length (l)
Further refined to account for wire parameters:
Rw,Cw: resistance and capacitance per unit lengthRt: driver output resistanceCr: receiver input capacitance
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Delay model
0ww1dd
2 cCRcGnd)(V1cd
Inversely proportional to Vdd - Gnd
Directly proportional to Resistance and Capacitance per unit length
We did not derive fitting models of the delay measured from HSPICE simulations, but of those delay values that minimize the MSE of the fitting exponential
transients
We therefore aim at achieving maximum accuracyin predicting the far-end voltage Vin at sampling time
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
AccuracyValidation against HSPICE for different noise scenarios
0%2%4%6%8%
10%12%14%16%18%20%
Min Avg(logic 1)
Avg(logic 0)
Max
130nm90nm
MSE for exp. transient
In practice, the error on Vin is much smaller than MSE
at sampling time
Time (ps)
Far-E
nd V
olta
ge (m
V)
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Outline1. Motivation2. Physical channel design3. Analytical model
• Design• Validation against HSPICE
4. Macromodel integration in SystemC• Accuracy assessment
5. Applications and conclusions
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication ChannelsMacromodel integration in
SystemCNeed: expose the analytical models to a
high-level modelling and simulation environment Interconnect analysis with SPICE accuracy in complex systems Traditional macromodels integrated in VHDL/Verilog SystemC is emerging as the ref. backbone for system-level design C-language programming facilitates HW-SW codesign
Analytical macromodel integration in SystemC
We exploited theAdvanced and Flexible Communication Abstractions in SystemC Ports: gateways to communication functions Interfaces: declaration of communication functions Channels: actual implementation of communication functions
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication ChannelsSystemC communication
abstractions
sc_signal withIntegratedAnalytical
model
HWModule
Predefined sc_signal channel
(read/write implementation)
HWModule
Plug-'n'-Play
Output port Input port
Interface InterfacePlug-and-play channels in the link communication model
Predefined channel augmented with analytical model
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Spic
eSy
stem C
SystemC vs SPICE accuracy
Technology node 130nm 130nm 90nm 90nmSampled logic value 1 0 1 0
Max Error 1,23% 5,87% 1,46% 6,26%Avg Error 0,46% 1,76% 0,38% 1,48%Min Error 0,02% 0,08% 0,00% 0,18%
Accuracy results for 30 different mixes of noise sources
Average error at sampling time never worse than 2%, max. error less than 7% Risk of logic value misprediction if sampled voltage close to decision threshold
a warning is generated by the SystemC channel Accounting for Inter-Symbol Interference Simulation time improvements with SystemC by 10x
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Outline1. Motivation2. Physical channel design3. Analytical model
• Design• Validation against HSPICE
4. Macromodel integration in SystemC• Accuracy assessment
5. Applications and conclusions
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Communication channel explorationFirst application
Injection of noise in the transmitter until a logic error is produced at the receiver
FF TXPower supply
noise
Power SupplyNoise Type SystemC HSPICE Error SystemC HSPICE ErrorDifferential 0,04 0,048 0,67% 0,056 0,063 0,70%
Common Mode 0,051 0,058 0,58% 0,063 0,074 1,10%
130nm 90nm
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Communication channel explorationSecond application: Exploration of different clocking schemes
ClockTX
ClockRX
1000 ps = 1 GHz
Native dual clocking schemes with phase shift
Which is the min. shiftfor correct sampling
at 1 GHz?SystemC35psHSPICE35ps(exact matching)
[email protected] – May 14, 2007
Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels
Conclusions Design of a communication channel for high-performance on-chip links
targeting 1 GHz operating frequency at 130nm and 90nm techn. nodes low power, low swing signaling
Analytical modelling of channel behavior in presence of noise Noise sensitive area concept, delay and signal slope models
Macromodel integration into SystemC Powerful communication abstractions Plug-and-play backannotated channel Very high accuracy in predicting far-end voltage at sampling time
Average error below 2%, max error below 7% Improvement of simulation time by 10x Accounting for Inter-Symbol Interference
Macromodels at work for fast assessment of channel robustness against noise sources physical channel design space exploration
Future work: crosstalk analytical macromodelling