05 Systemc Tutorial

7/28/2019 05 Systemc Tutorial

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Copyright 2005 by Ando Ki

SystemC Quick Tutorial

Ando Ki

[email protected] Systems

SystemC quick tutorial: 2 Copyright 2005 by Ando Ki

Agenda and objectives

SystemC design process

Design in hardware point of view

Design in SystemC point of view

Design organization

SystemC module, port, constructor,process

SystemC module instantiation

SystemC signal tracing

SystemC top-level

Compilation and running of SystemCprogram

Viewing VCD waveform

Compilation using make

This session presents a quicktutorial of SystemC to grasp how tomodel hardware and how tosimulate it.


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Standard C++developmentenvironment

SystemC design process

Design source filesin SystemC

C++ Compiler

Loader

Debugger

SystemC

SystemC classlibrary and

simulation kernel

header

library

Make

a.out(run.x)

wave data(VCD)

Running the executable (a.out)means simulation.


Design in hardware point of view

Hierarchy

memory, decode, and ram

Signal lines

directions, type of driving, width

Control and data

Concurrency or parallelism Reactivity

More such as clock, delay, and so on.

memory

decoder

ram

enable

address[31:0]

rdwr

data[15:0]

selected

enable

address[]

rdwr

we

data[]

READ WRITE

we


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Design in SystemC point of view

Hierarchy of blocks

module

Signal lines

port

signal

Control and data

abstraction level

Concurrency or parallelism

process

Reactivity

sensitivity list of process

wait()

more clock

memorymemory

enable

address

rdwr

data

selected

decoderdecoder

ramram

module

process

port

signal

we


Design organization

Design source code

Interface files: .h

Implementation files: .cpp

Interface file (.h) describes Port and data members of a module

prototypes of member functions of amodule

Implementation file contains

The code for the member functions

In1

In2Out

#include ..SC_MODULE .

{

};

void and::do_and() {

}

and.h and.cpp


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SystemC module

Basic building blocks in SystemC

Modules are declared with the SystemC keyword SC_MODULE, which is actually aC macro equivalent to defining the module as a C++ class.

Ports pass data to/from module Ports represent physical pins on a hardware block

In1

In2

Out

#include systemc.h

SC_MODULE(AND){

sc_inIn1;sc_inIn2;sc_outOut;

SC_CTOR(AND){

}

};

C macro

C++ constructor

ports

SystemC header

Interface file,e.g., and.h


SystemC port of module

Ports allow a module to access an interface

SystemC port is a means by which a module can call the method implemented by aSystemC channel.

#include systemc.h

SC_MODULE(AND){

sc_portIn1;sc_portIn2;sc_portOut;

};

ports

SystemCinterface

In1

In2 Out

sc_signal_in_if

channel


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SystemC constructor of module

Constructor registers process within the SystemC simulation kernel and also todefine the sensitivity list of the process

#include systemc.h

SC_MODULE(AND){


void do_and();

SC_CTOR(AND){

SC_METHOD(do_and);sensitive


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SystemC module in C++

#include systemc.h

SC_MODULE(AND){


void do_and();

SC_CTOR(AND){

SC_METHOD(do_and);

sensitive


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SystemC module instantiation

// half_adder.h#include and.h#include xor.h

SC_MODULE(half_adder){sc_inIn1, In2;sc_outSum, Carry;

AND Uand;XOR Uxor;

void do_half_adder();

SC_CTOR( half_adder): Uand(Uand), Uxor(Uxor)

{Uand.In1(In1); Uand.In2(In2);Uand.Out(Carry);Uxor.In1(In1); Uxor.In2(In2);Uxor.Out(Sum);

}};

In1

In2

Sum

Carry

Module instances

C++ initializers

Port connections

Note that there are no processes.


SystemC module: test stimulus

// stimulus.h

#include systemc.h

SC_MODULE(stimulus){sc_inclk;sc_outOut1, Out2;

void do_stimulus();

SC_CTOR( stimulus){

SC_METHOD(do_stimulus);

sensitive


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Tracing signal or data member of module

Step 1: create a trace file

Step 2: register signals variables to be traced

Step 3: close the trace file before returning from sc_main().

sc_trace_file* vcd_tf=sc_create_vcd_trace_file(wave);

sc_trace(vcd_tf, signal_object, string);sc_trace(vcd_tf, some_module.signal_object, string);sc_start();sc_close_vcd_trace_file(vcd_tf);

Create a trace file named wave.vcd.

Trace a signal object

Trace a signal object in asub-module

Close the trace file


SystemC top-level: sc_main (1/2)

Every SystemC program must include sc_main() function

sc_main() is called once by the SystemC simulation kernel.

Two major phases of execution of a SystemC program

Elaboration: module hierarchy is created, processes are registered

Simulation

sc_start() marks the end of elaboration and the start of simulation

Every process starts to execute at the start of simulation.

clockSig_sum

Sig_carrySig_A

Sig_B


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SystemC top-level: sc_main (2/2)

// main.cpp#include "half_adder.h"#include "stimulus.h"

int sc_main(int argc, char* argv[]) {

sc_clock clock("clock", 10, SC_NS);

sc_signal Sig_A, Sig_B;sc_signal Sig_sum, Sig_carry;

half_adder Uhalf_adder("Uhalf_adder");Uhalf_adder.In1(Sig_A);Uhalf_adder.In2(Sig_B);Uhalf_adder.Sum(Sig_sum);Uhalf_adder.Carry(Sig_carry);

stimulus Ustimulus("Ustimulus");Ustimulus.clk(clock);Ustimulus.Out1(Sig_A);Ustimulus.Out2(Sig_B);

sc_trace_file* vcd_tf =sc_create_vcd_trace_file("wave");

sc_trace(vcd_tf, clock, "clock");sc_trace(vcd_tf, Sig_A, "Sig_A");sc_trace(vcd_tf, Sig_B, "Sig_B");sc_trace(vcd_tf, Sig_sum, "Sig_sum");sc_trace(vcd_tf, Sig_carry, "Sig_carry");

sc_start(100, SC_NS);

sc_close_vcd_trace_file(vcd_tf);return(0);}

Clock creation: 10 nano second period

Connecting signals

Sub-module instantiation and port connection

Trace file creation and trace registration

Start simulation up to 100 nano second


Compilation of SystemC program

void and::do_and() {

}

and.hand.cpp

void xor::do_xor() {

}

xor.hxor.cpp half_adder.h

void stimulus::do_stimulus() {

}

stimulus.hstimulus.cpp

main.cpp

g++ -I/usr/local/SystemC/include -c and.cppg++ -I/usr/local/SystemC/include -c xor.cpp

g++ -I/usr/local/SystemC/include -c stimulus.cppg++ -I/usr/local/SystemC/include -c main.cpp

g++ -L/usr/local/SystemC/lib-linux-o run.x and.o xor.o stimulus.o main.o -lsystemc

Compiling eachimplementation files

GNU C++ compiler Where SystemC header files reside

Final executable, i.e., SystemC simulator

Where SystemC libraries reside


{

};


{

};

#include ..#include ..SC_MODULE .

{

};


{

};

#include ..#include ..

int sc_main(..)

}


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Running SystemC simulation

The executable object is a complete SystemC simulator.

Running the executable object means simulation.

g++ -I/usr/local/SystemC/include -c and.cppg++ -I/usr/local/SystemC/include -c xor.cppg++ -I/usr/local/SystemC/include -c stimulus.cppg++ -I/usr/local/SystemC/include -c main.cppg++ -L/usr/local/SystemC/lib-linux-o run.xand.o xor.o stimulus.o main.o lsystemc

./run.x Executable object

Simulation


Viewing VCD waveform

Run any VCD display utilities, such as GTKWave.


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Compilation using make

Use UNIX make command to determineautomatically which pieces of a largeprogram need to be recompiled, andissue the commands to recompile them.

#A sample Makefile for SystemC exampleTARGET_ARCH = linuxSYSTEMC = /usr/local/SystemCINCDIR = -I$(SYSTEMC)/includeLIBDIR = -L$(SYSTEMC)/lib-$(TARGET_ARCH)LIBS = -lsystemc

CC = g++CFLAGS = -c

SRCS = and.cppxor.cpp stimulus.cpp main.cppOBJ S = $(SRCS:.cpp=.o)EXE = run.x

.SUFFIXES: .cpp .o

.cpp.o:$(CC) $(CFLAGS) $(INCDIR) $&1 | c++filt[adki@garden] lsMakefile adder.cpp adder.h adder.o main.cpp main.o run.x*testbench.cpp testbench.h testbench.o[adki@garden]

[adki@garden] lsMakefile adder.cpp adder.h main.cpp testbench.cpp testbench.h[adki@garden] cat MakefileTARGET_ARCH = gccsparcOS5

CC = g++OPT = -O3

DEBUG = -gOTHER = -WallCFLAGS = $(OPT) $(OTHER) $(DEBUG)

MODULE = runSRCS = main.cpp testbench.cpp adder.cppOBJS = $(SRCS:.cpp=.o)

include ../../../Makefile.defs[adki@garden] makeg++ -O3 -Wall -g -I/usr/local/SystemC/include -c main.cppg++ -O3 -Wall -g -I/usr/local/SystemC/include -c testbench.cppg++ -O3 -Wall -g -I/usr/local/SystemC/include -c adder.cppg++ -O3 -Wall -g -I/usr/local/SystemC/include -L/usr/local/SystemC/lib-gccsparcOS5 -o run.x main.otestbench.o adder.o -lsystemc -lm 2>&1 | c++filt

[adki@garden] lsMakefile adder.cpp adder.h adder.o main.cpp main.o run.x*testbench.cpp testbench.h testbench.o[adki@garden]

Ex1: Simple adder CompilationCompilation


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Ex1: Simple adder Running

[adki@garden] lsMakefile* adder.cpp adder.h adder.o main.cpp main.o run.x*testbench.cpp testbench.h testbench.o[adki@garden] run.x

SystemC 2.0 --- Oct 22 2001 09:50:16Copyright (c) 1996-2001 by all Contributors

ALL RIGHTS RESERVEDWARNING: Default time step is used for VCD tracing.0+100=1003+117=1206+134=1409+151=16012+168=180[adki@garden] lsMakefile adder.cpp adder.h adder.o main.cpp main.o run.x*testbench.cpp testbench.h testbench.o wave.vcd[adki@garden] winwave wave.vcd &

[adki@garden]

[adki@garden] lsMakefile* adder.cpp adder.h adder.o main.cpp main.o run.x*testbench.cpp testbench.h testbench.o[adki@garden] run.x

SystemC 2.0 --- Oct 22 2001 09:50:16Copyright (c) 1996-2001 by all Contributors

ALL RIGHTS RESERVEDWARNING: Default time step is used for VCD tracing.0+100=1003+117=1206+134=1409+151=16012+168=180[adki@garden] lsMakefile adder.cpp adder.h adder.o main.cpp main.o run.x*testbench.cpp testbench.h testbench.o wave.vcd[adki@garden] winwave wave.vcd &[adki@garden]

Running & Checking waveform


Ex1: Simple adder WaveformInitial window


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Ex1: Simple adder WaveformSelecting signals to view


Ex1: Simple adder WaveformSimulated waveform


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Ex1: Simple adder WaveformExiting GTKwave


Ex2: Count example

This example shows how to compile a SystemC program and how to see theresults in waveform fashion.

Step 1: Go to your directory.

[user@host] cd codes/sc_tutorial/examples/count

[user@host] ls

Step 2: See the codes.

Step 3: Compile.

Step 4: Run.

Step 5: View the waveform.


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Ex2: Count example

test

CLK

count

reset

go

value

clk


Ex2: count module

1 // count.h2 #include "systemc.h"34 SC_MODULE(count) {5 sc_in clk, reset, go;6 sc_out value;78 void do_count();9 unsigned char local_value;1011 SC_CTOR(count) {12 SC_METHOD(do_count);13 sensitive


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Ex2: test module

1 // test.h2 #include "systemc.h"34 SC_MODULE(test) {5 sc_in clock;6 sc_out reset, go;7 sc_in value;8

9 void do_test();1011 SC_CTOR(test) {12 SC_CTHREAD(do_test, clock.neg());13 reset.initialize(1);14 go.initialize(0);15 }16 };

1 // test.cpp2 #include "test.h"34 void test::do_test() {5 wait();

6 reset.write(0);7 wait();8 while (true) {9 go.write(1);10 wait(5);11 go.write(0);12 wait(2);13 }14 }

testtest reset

godo_testdo_test value

clkInfinite

loop

go

clk


Ex2: Top-level1 // main.cc2 #include "count.h"3 #include "test.h"45 int sc_main(int argc, char** argv) {6 sc_signal value;7 sc_signal reset, go;8

9 sc_clockCLK("clock", 10, SC_NS);1011 count CNT("CNT");12 CNT.clk(CLK); CNT.reset(reset); CNT.go(go); CNT.value(value);1314 test TST("TST");15 TST(CLK, reset, go, value);1617 sc_trace_file *tf = sc_create_vcd_trace_file("wave");18 ((vcd_trace_file*)tf)->sc_set_vcd_time_unit(-9);19 sc_trace(tf, CLK, "clock"); sc_trace(tf, reset, "reset");20 sc_trace(tf, go, "go"); sc_trace(tf, value, "value");21 sc_trace(tf, CNT.local_value, "CNT.local_value");2223 sc_start(200, SC_NS);24 sc_close_vcd_trace_file(tf);25 return(0);26 }

Signals to connectports of modules

Make clock make countmodule with

namedconnection

make test module withpositional connection

Trace file creation:VCD format in

wave.vcd file

Include module headerfiles

Specify signals to bemonitored

Run simulation

Close trace file


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# MakefileCC = g++OPT = -O3DEBUG = -gOTHER = -Wall -Wno-deprecatedCFLAGS = $(OPT) $(OTHER) $(DEBUG)

MODULE = runSRCS = main.cpp count.cpp test.cppOBJS = $(SRCS:.cpp=.o)

include ./Makefile.defs

Ex2: Makefile

## Makefile.defsTARGET_ARCH = cygwin # linux gccsparcOS5SYSTEMC = /usr/local/SystemCINCDIR = -I$(SYSTEMC)/includeLIBDIR = -L$(SYSTEMC)/lib-$(TARGET_ARCH)LIBS = -lsystemc -lm $(EXTRA_LIBS)EXE = $(MODULE).x.SUFFIXES: .cc .cpp .o .x

$(EXE): $(OBJS)$(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@

$(OBJS)$(LIBS) 2>&1 | c++filt.cpp.o:

$(CC) $(CFLAGS) $(INCDIR) -c $enable(selected);RAM->rdwr(rdwr);RAM->we(we);RAM->data(data);

#include "systemc.h"#include "ram.h"

SC_MODULE(memory) {

sc_in address;sc_in enable, rdwr, we;sc_inout_rv data;

ram* RAM;

sc_signal selected;

void do_decoder();

SC_CTOR(memory) {RAM = new ram("R");

RAM->address(address);RAM->enable(selected);RAM->rdwr(rdwr);RAM->we(we);RAM->data(data);

#include "memory.h

void memory::do_decoder() {

if (enable) {int tmp = address.read();if (0


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Ex3: Simple memory sc_main

#include "memory.h"#include "testbench.h"

int sc_main(int argc, char *argv[]) {sc_signal add;sc_signal en;sc_signal rw;sc_signal we;sc_signal_rv data;

sc_set_time_resolution(1, SC_NS);sc_set_default_time_unit(1, SC_NS);sc_clock CLOCK("clock", 10, 0.5, 5, true);

// make MEMORY module with named

// connectionmemory MEMORY("memory");MEMORY.address(add);MEMORY.enable(en);MEMORY.rdwr(rw);MEMORY.we(we);MEMORY.data(data);

#include "memory.h"#include "testbench.h"

int sc_main(int argc, char *argv[]) {

sc_signal add;sc_signal en;sc_signal rw;sc_signal we;sc_signal_rv data;

sc_set_time_resolution(1, SC_NS);sc_set_default_time_unit(1, SC_NS);sc_clock CLOCK("clock", 10, 0.5, 5, true);

// make MEMORY module with named// connectionmemory MEMORY("memory");MEMORY.address(add);MEMORY.enable(en);MEMORY.rdwr(rw);MEMORY.we(we);MEMORY.data(data);

// make TESTBENCH module with// positional connectiontestbench TESTER("tester");

TESTER(add, en, rw, we, data, CLOCK);

// trace file creationsc_trace_file *tf =

sc_create_vcd_trace_file("wave");

sc_trace(tf, CLOCK, "clock");sc_trace(tf, add, "AD");sc_trace(tf, en, "EN");sc_trace(tf, rw, "RW");sc_trace(tf, we, "WE");sc_trace(tf, data, "DA");

sc_trace(tf, MEMORY.selected, "SEL");

sc_start(600, SC_NS);sc_close_vcd_trace_file(tf);return(0);

}

// make TESTBENCH module with// positional connectiontestbench TESTER("tester");TESTER(add, en, rw, we, data, CLOCK);


sc_create_vcd_trace_file("wave");

sc_trace(tf, CLOCK, "clock");sc_trace(tf, add, "AD");sc_trace(tf, en, "EN");sc_trace(tf, rw, "RW");sc_trace(tf, we, "WE");sc_trace(tf, data, "DA");sc_trace(tf, MEMORY.selected, "SEL");

sc_start(600, SC_NS);sc_close_vcd_trace_file(tf);return(0);

}

main.cpp

Note how toselect signals inthe sub-module.


Ex3: Simple memory testbench

#include testbench.hvoid testbench::do_test() {int i, j, flag, tmpA, tmpDW, tmpDR;

for (j=0; 1; j++) {flag = 0;

wait(2);tmpA = 1; tmpDW = 123;for (i=0; i


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Ex3: Simple memory testbench

int testbench::read_cycle(int iadd) {

int tmp;add.write(iadd);en.write(1);rw.write(1);we.write(0);wait(2);tmp = data.read().to_int();wait(1);add.write(0);en.write(0);wait(1);return tmp;

}

int testbench::read_cycle(int iadd) {int tmp;add.write(iadd);

en.write(1);rw.write(1);we.write(0);wait(2);tmp = data.read().to_int();wait(1);add.write(0);en.write(0);wait(1);return tmp;

}

void testbench::write_cycle(int iadd, int idata) {

add.write(iadd);en.write(1);rw.write(0);we.write(0);data.write(idata);wait(1);we.write(1);wait(1);add.write(0);en.write(0);rw.write(1);data.write("ZZZZZZZZZZZZZZZZ");wait(1);

}

void testbench::write_cycle(int iadd, int idata) {

add.write(iadd);en.write(1);

rw.write(0);we.write(0);data.write(idata);wait(1);we.write(1);wait(1);add.write(0);en.write(0);rw.write(1);data.write("ZZZZZZZZZZZZZZZZ");wait(1);

}

enable

address[]

rdwr

we

data[]

READ WRITE

testbench.cpp


Ex3: Simple memory compilation

# MakefileCC = g++OPT = -O3DEBUG = -gOTHER = -Wall

CFLAGS = $(OPT) $(OTHER) $(DEBUG)

MODULE = runSRCS = main.cpp memory.cpp

ram.cpp testbench.cppOBJS = $(SRCS:.cpp=.o)

include ../../../Makefile.defs

# MakefileCC = g++OPT = -O3DEBUG = -gOTHER = -WallCFLAGS = $(OPT) $(OTHER) $(DEBUG)

MODULE = runSRCS = main.cpp memory.cpp

ram.cpp testbench.cppOBJS = $(SRCS:.cpp=.o)

include ../../../Makefile.defs

[adki@oarchard] cd ~/Lecture/codes/SC_tutorial/examples/memory[adki@orchard] lsGNUmakefile main.cpp memory.cpp memory.h ram.cpp ram.htestbench.cpp testbench.h[adki@orchard] makeg++ -O3 -Wall -g -I/usr/local/SystemC/include -c main.cppg++ -O3 -Wall -g -I/usr/local/SystemC/include -c memory.cppg++ -O3 -Wall -g -I/usr/local/SystemC/include -c ram.cpp

g++ -O3 -Wall -g -I/usr/local/SystemC/include -L/usr/local/SystemC/lib-gccsparcOS5 -o run.x main.o memory.o ram.o -lsystemc -lm 2>&1 |c++filt[adki@orchard] lsGNUmakefile main.cpp main.o memory.cpp memory.hmemory.o ram.cpp ram.hram.o run.x* testbench.cpp testbench.h[adki@orchard] run.x

SystemC 2.0 --- Feb 5 2002 19:32:52Copyright (c) 1996-2001 by all Contributors

ALL RIGHTS RESERVEDWARNING: Default time step is used for VCD tracing.

Test passed ...

[adki@orchard] lsGNUmakefile main.cpp main.o memory.cpp memory.hmemory.o ram.cpp ram.h ram.o run.x*testbench.cpp testbench.h wave.vcd[adki@orchard] gtkwave wave.vcd &[3] 12311[adki@orchard]

[adki@oarchard] cd ~/Lecture/codes/SC_tutorial/examples/memory[adki@orchard] lsGNUmakefile main.cpp memory.cpp memory.h ram.cpp ram.htestbench.cpp testbench.h[adki@orchard] makeg++ -O3 -Wall -g -I/usr/local/SystemC/include -c main.cppg++ -O3 -Wall -g -I/usr/local/SystemC/include -c memory.cppg++ -O3 -Wall -g -I/usr/local/SystemC/include -c ram.cpp

g++ -O3 -Wall -g -I/usr/local/SystemC/include -L/usr/local/SystemC/lib-gccsparcOS5 -o run.x main.o memory.o ram.o -lsystemc -lm 2>&1 |c++filt[adki@orchard] lsGNUmakefile main.cpp main.o memory.cpp memory.hmemory.o ram.cpp ram.hram.o run.x* testbench.cpp testbench.h[adki@orchard] run.x

SystemC 2.0 --- Feb 5 2002 19:32:52Copyright (c) 1996-2001 by all Contributors

ALL RIGHTS RESERVEDWARNING: Default time step is used for VCD tracing.

Test passed ...

[adki@orchard] ls

GNUmakefile main.cpp main.o memory.cpp memory.hmemory.o ram.cpp ram.h ram.o run.x*testbench.cpp testbench.h wave.vcd[adki@orchard] gtkwave wave.vcd &[3] 12311[adki@orchard]

Makefile Compilation & running

Before running make, TARGET_ARCH

macro in ../../Makefile.defs must beappropriate one. For example, cygwin forCygwin on top of Windows.


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Lab 1: Simple calculator - Structure

Engine performs binary operation cmdon op1and op2.

cmdincludes addition (+), subtraction (-), multiplication (x), division (/).

Testbnech: stimulus & monitor & checking

testbenchtestbenchengineengine

op1op2

resultop1op2

result

clockclock

CLOCK

cmdcmd

main.cppmain.cpp

MakefileMakefile

engine.cppengine.cpp

engine.hengine.h

testbench.cpptestbench.cpp

testbench.htestbench.h

systemc.hsystemc.h

Block diagram File hierarchy


Lab 1: Simple calculator Design Steps

This lab introduces the process of making a module of the simple calculatorexample.

Follow the following steps:

Make an engine module consisting of engine.h and engine.cpp. Make it

Run it

Invoke waveform viewer

[user@host] cd ~/codes/SC_tutorial/labs[user@host] cd calculator

[user@host] vi engine.h[user@host] vi engine.cpp[user@host] make[user@host] run.x[user@host] gtkwave wave.vcd &

[user@host] cd ~/codes/SC_tutorial/labs[user@host] cd calculator[user@host] vi engine.h

[user@host] vi engine.cpp[user@host] make[user@host] run.x[user@host] gtkwave wave.vcd &


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Lab 1: Simple calculator sc_main

// main.cpp#include "engine.h"#include "testbench.h"

int sc_main(int argc, char *argv[]) {sc_signal cmd;sc_signal op1, op2, result;

sc_set_time_resolution(1, SC_NS); // V2.0sc_set_default_time_unit(1, SC_NS);sc_clock CLOCK("clock", 20, 0.5, 25, true);

// make ENGINE moduleengine ENGINE("engine");ENGINE(cmd, op1, op2, result);

// make TESTBENCH moduletestbench TEST("test");TEST(CLOCK, cmd, op1, op2, result);

// main.cpp#include "engine.h"#include "testbench.h"

int sc_main(int argc, char *argv[]) {sc_signal cmd;sc_signal op1, op2, result;

sc_set_time_resolution(1, SC_NS); // V2.0sc_set_default_time_unit(1, SC_NS);sc_clock CLOCK("clock", 20, 0.5, 25, true);

// make ENGINE moduleengine ENGINE("engine");ENGINE(cmd, op1, op2, result);

// make TESTBENCH moduletestbench TEST("test");TEST(CLOCK, cmd, op1, op2, result);


sc_create_vcd_trace_file("wave");sc_trace(tf, CLOCK, "clock");sc_trace(tf, cmd, "cmd");sc_trace(tf, op1, "op1");sc_trace(tf, op2, "op2");sc_trace(tf, result, "result");

sc_start(200, SC_NS);return(0);

}

main.cpp


Lab 1: Simple calculator (4/6)

#include "testbench.h"

void testbench::do_test() {float A, B, C;A = 15.0; B = 5.0;while (1) {

wait();cmd.write(ADD); operand1.write(A); operand2.write(B);wait();C = result.read();if (C!=(A+B)) printf("Error: %f+%f=%f(?)n", A, B, C);else printf("Addition: %f+%f=%fn", A, B, C);//---------cmd.write(SUB); operand1.write(A); operand2.write(B);wait();C = result.read();if (C!=(A-B)) printf("Error: %f-%f=%f(?)n", A, B, C);else printf("Subtraction: %f+%f=%f

n", A, B, C);

::

#include "testbench.h"

void testbench::do_test() {float A, B, C;A = 15.0; B = 5.0;while (1) {

wait();cmd.write(ADD); operand1.write(A); operand2.write(B);wait();C = result.read();if (C!=(A+B)) printf("Error: %f+%f=%f(?)n", A, B, C);else printf("Addition: %f+%f=%fn", A, B, C);//---------cmd.write(SUB); operand1.write(A); operand2.write(B);wait();C = result.read();if (C!=(A-B)) printf("Error: %f-%f=%f(?)n", A, B, C);else printf("Subtraction: %f+%f=%fn", A, B, C);

::

// header for testbench//#ifndef TESTBENCH_H# define TESTBENCH_H#include "systemc.h"#include "engine.h"

SC_MODULE(testbench) {sc_in clock;sc_out cmd;sc_out operand1;sc_out operand2;sc_in result;

void do_test();

SC_CTOR(testbench) {

SC_CTHREAD(do_test,clock.neg());}

};#endif



void do_test();

SC_CTOR(testbench) {SC_CTHREAD(do_test,

clock.neg());}

};#endif

testbench.h testbench.cpp


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::

//---------cmd.write(MUL); operand1.write(A); operand2.write(B);wait();C = result.read();if (C!=(A*B)) printf("Error: %f*%f=%f(?)n", A, B, C);else printf("Multiplication: %f*%f=%fn", A, B, C);//---------cmd.write(DIV); operand1.write(A); operand2.write(B);wait();C = result.read();if (C!=(A/B)) printf("Error: %f/%f=%f(?)n", A, B, C);else printf("Division: %f/%f=%fn", A, B, C);

}}

::

//---------cmd.write(MUL); operand1.write(A); operand2.write(B);wait();C = result.read();if (C!=(A*B)) printf("Error: %f*%f=%f(?)n", A, B, C);else printf("Multiplication: %f*%f=%fn", A, B, C);//---------

cmd.write(DIV); operand1.write(A); operand2.write(B);wait();C = result.read();if (C!=(A/B)) printf("Error: %f/%f=%f(?)n", A, B, C);else printf("Division: %f/%f=%fn", A, B, C);

}}



void do_test();


clock.neg());}

};#endif

// header for testbench//#ifndef TESTBENCH_H# define TESTBENCH_H

#include "systemc.h"#include "engine.h"


void do_test();


clock.neg());}

};#endif

testbench.h testbench.cpp



Tips for engine.h

Input ports: cmd, op1, op2 and clock

Note: cmd is int, op1 and op2 are float.

Output ports: result

The process should be SC_METHOD.

Note: sensitive with cmd, op1, op2.


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Lab 2: Simplex data protocol

The simplex data protocol is a simple data protocol used to transfer data fromone device to another in a single direction.

Refer to SystemC Users Guide Version 2.0 Chapter 2.

Primary objectives Understanding a SystemC system.

Understanding the processor SystemC modeling and simulation.

What to do:

Coding

Compilation

Simulation


Lab 2: Simplex data protocol - Structure

transmittransmit

clock

timertimer

clock

channelchannel

clock

receivereceive

clock

displaydisplay

clock

clockclock

Block diagram


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Session summary

SystemC module creation


SystemC program compilation


Note


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Note

Note

Documents

05 Systemc Tutorial