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Source/Drain Engineering for In0.7Ga0.3As N-Channel Metal–Oxide–Semiconductor Field-

Effect Transistors: Raised Source/Drain with In situ Doping for Series Resistance Reduction

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2011 Jpn. J. Appl. Phys. 50 04DF01

(http://iopscience.iop.org/1347-4065/50/4S/04DF01)

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Source/Drain Engineering for In0:7Ga0:3As N-Channel Metal–Oxide–Semiconductor

Field-Effect Transistors: Raised Source/Drain with In situ Doping

for Series Resistance Reduction

Xiao Gong1;2, Hock-Chun Chin1, Shao-Ming Koh1, Lanxiang Wang1;2, Ivana1;2, Zhu Zhu1,

Benzhong Wang3, Ching Kean Chia3, and Yee-Chia Yeo1;2�

1Department of Electrical and Computer Engineering, National University of Singapore, Singapore 1175762NUS Graduate School of Integrative Sciences and Engineering, National University of Singapore, Singapore 1174563Institute of Materials Research and Engineering, Agency for Science Technology and Research, Singapore 117602

Received September 16, 2010; revised October 7, 2010; accepted October 23, 2010; published online April 20, 2011

In this paper, we report N-channel metal–oxide–semiconductor field-effect transistors (N-MOSFETs) featuring in situ doped raised In0:53Ga0:47As

source/drain (S/D) regions. This is the first demonstration of such regrowth on an In0:7Ga0:3As channel. After SiON spacer formation, the raised

In0:53Ga0:47As S/D structure was formed by selective epitaxy of In0:53Ga0:47As in the S/D regions by metal-organic chemical-vapor deposition

(MOCVD). In situ silane SiH4 doping was also introduced to boost the N-type doping concentration in the S/D regions for series resistance RSD

reduction. The raised S/D structure contributes to IDsat enhancement for the In0:7Ga0:3As N-MOSFETs.

# 2011 The Japan Society of Applied Physics

1. Introduction

New materials and novel device architectures are needed toextend the performance limits of complementary metal–oxide–semiconductor (CMOS) technology. III–V compoundsemiconductors such as indium gallium arsenide (InGaAs)have very high electron mobility and are attractivecandidates to replace strained Si channel for next generationlogic applications.1–5) Recent research on III–V metal–oxide–semiconductor field-effect transistors (MOSFETs) hasfocused on gate stack and interface engineering, with verypromising results obtained.6–22) To harness the full potentialof III–V MOSFETs, source–drain (S/D) engineering is alsoan important direction.

Parasitic S/D series resistance RSD can be a performance-limiting factor in CMOS devices with sub-30-nm gate lengthsLG. In MOSFETs with aggressively scaled LG and highchannel mobility, the channel resistance RChannel would besmall so that RSD is an important component of the totalresistance between source and drain. Doping InGaAs S/Dregions by Si implantation and anneal does not achievesufficiently high doping concentration, leading to high S/Dseries resistance and compromised drive current performance.

InGaAs MOSFETs with raised S/D formed by regrowthby molecular beam epitaxy (MBE) were reported.23–27) InP/InGaAs composite channel MOSFETs with selectivelyregrown Nþ S/D regions by metal organic vapor-phaseepitaxy (MOVPE) were also demonstrated,28,29) where agate-last process was adopted. Active Si doping concentra-tion as high as �5� 1019 cm�3 was achieved by epitaxialgrowth with in situ doping. In refs. 23–29, the Indiumcomposition x in the InxGa1�xAs channel is below 0.7.

In this paper, we report the demonstration of RSD

reduction in In0:7Ga0:3As N-channel MOSFETs (N-MOSFETs) by in situ SiH4 doping during the selectiveepitaxy growth of In0:53Ga0:47As to form the heavily dopedraised S/D regions. Si doping of �4� 1019 cm�3 wasachieved. In addition, a raised S/D drain structure wasrealized. A self-aligned gate-first process was utilized tofabricate the InGaAs MOSFETs. By integrating the raised

S/D structure into an In0:7Ga0:3As N-MOSFET, significantseries resistance reduction and drive current improvementwere demonstrated. Current–voltage characteristics, trans-conductance, S/D series resistance and on- and off-statecurrents of In0:7Ga0:3As N-MOSFETs were studied in detail.

2. Process Development and Device Fabrication

2.1 Selective epitaxy of in situ doped raised S/D

The key process in device fabrication is the selective growthof in situ doped InGaAs by MOCVD. Indium and galliumcompositions were controlled by the flow rates of trimethyl-indium (TMIn) and trimethylgallium (TMGa), respectively.Temperature is an important factor affecting the selectivegrowth. Too low a growth temperature would lead to poorselectivity over SiO2 and SiON regions due to insufficientdesorption of nucleated seeds on the gate lines and spacers,whereas too high a growth temperature would degradethe quality of high-k HfAlO/In0:7Ga0:3As interface. Afterprocess optimization, the MOCVD selective growth waschosen to be conducted at 635 �C and at a chamber pressureof 75 Torr. TMGa, TMIn and tertiarybutylarsine (TBA) wereemployed as precursors. Flow rates for TMGa, TMIn, andTBA were 16, 130, and 60 sccm, respectively, for the growthof In0:53Ga0:47As on In0:7Ga0:3As. SiH4 was used to achievein situ N-type doping of �4� 1019 cm�3, as confirmed byHall measurement. This is significantly higher than the N-type doping concentration obtained using Si implant andanneal, which saturates at �1� 1019 cm�3.30)

2.2 Process flow and device fabrication

The process flow for device fabrication is illustrated inFig. 1. The cross-sectional transmission electron microscopy(TEM) image of a completed In0:7Ga0:3As channel N-MOSFET with raised In0:53Ga0:47As S/D structure isshown in Fig. 2(a). High-resolution TEM image of theIn0:53Ga0:47As/In0:7Ga0:3As heterostructure in Fig. 2(b) con-firms the pseudomorphic epitaxial growth of In0:53Ga0:47Ason In0:7Ga0:3As. Fast Fourier transform (FFT) diffractogram[inset in Fig. 2(b)] reveals the good crystalline quality ofIn0:53Ga0:47As epitaxial layer.

A first 500 nm thick In0:55Ga0:45As well layer with aP-type doping concentration NA of 5� 1017 cm�3 and a�E-mail address: eleyeoyc@nus.edu.sg

Japanese Journal of Applied Physics 50 (2011) 04DF01

04DF01-1 # 2011 The Japan Society of Applied Physics

REGULAR PAPERDOI: 10.1143/JJAP.50.04DF01

second 20 nm thick In0:7Ga0:3As channel layer with a lowerNA of 1� 1016 cm�3 were sequentially grown on InPsubstrates. High resolution X-ray diffraction (HRXRD)performed on a blanket sample confirms the compositionand high crystal quality of the InGaAs epitaxial layers(Fig. 3).

Pre-gate cleaning was performed on the In0:7Ga0:3Assurface. The pre-gate clean comprises HCl for removal ofnative oxide, NH4OH for removal of excess elementalarsenic, and (NH4)2S for ex situ passivation. Right after this,the samples were quickly loaded into a multiple-chamberMOCVD gate cluster system for interface engineering andHfAlO high-k dielectric deposition.15–19) Post-gate dielectricdeposition anneal (PDA) at 500 �C for 60 s was performedprior reactive sputter deposition of TaN.

70 nm of PECVD SiO2 was also deposited to cover the topsurface of TaN gate electrode for selective epitaxy. Aftergate lithography and dry etch with Cl2-based plasmachemistry, S/D regions were formed by Siþ implant at30 keV with dose of 1� 1014 cm�2, activated at 600 �C for60 s. This was followed by silicon oxynitride (SiON) spacerformation to cover the side wall of the gate stack forsubsequent selective InGaAs MOCVD epitaxy process toform the raised S/D structures. The SiON spacers preventthe raised S/D from electrically contacting the gatesidewalls. The MOCVD process was skipped for the control

devices. Finally, PdGe ohmic contacts were integrated tocomplete the device fabrication.

3. Device Characterization and Analysis

Identical equivalent oxide thickness (EOT) of �7:4 nm wasobtained for both control devices as well as devices withraised S/D, as shown in inversion capacitance–voltage(C–V ) characteristics at a frequency of 100 kHz in Fig. 4(a).Further inversion C–V measurement was performed at thefrequencies of 10 kHz, 100 kHz, and 1MHz for the devicewith raised S/D, as shown in Fig. 4(b).

Figure 5(a) plots the ID–VG curves of a controlIn0:7Ga0:3As MOSFET as well as an In0:7Ga0:3As MOSFETwith raised S/D. The LG of the two devices is 700 nm.ID–VD characteristics of the same pair of devices with goodsaturation and pinch-off characteristics are shown inFig. 5(b). Substantial drive current enhancement wasobserved at a gate overdrive VG � VT of 2.5V and VDS of2.5V for In0:7Ga0:3As device with the raised S/D structure.The performance of the devices is reasonably goodconsidering that equivalent oxide thickness EOT of �7:4 nmgate dielectric was used. Further improvement in perfor-mance can be achieved by reducing the gate dielectricthickness as well as the gate length.

Figure 6 shows the extrinsic transconductance Gm,ext

versus VG for both N-MOSFETs. For this pair of devices,

Pre-Gate CleanInterface Engineering andMOCVD HfAlO Deposition

Gate Definition

SiON Spacer Formation

Splits:

Selective Epitaxy of In-situ Doped In 0.53Ga0.47As

- In-situ Doped Raised S/D

- Control

S/D Implantation

Dopant Activation

PdGe Contact Formation

Dopant Activation

TaN and SiO2 Hardmask Deposition

Fig. 1. Process sequence employed in the fabrication of In0:7Ga0:3As

channel N-MOSFETs with in situ doped raised In0:53Ga0:47As S/D.

In0.7Ga0.3As Channel

100nm

TaN

In-situ Doped Raised In0.53Ga0.47As S/D

In0.55Ga0.45As

SiON Spacer

(a)

In0.7Ga0.3As

In0.53Ga0.47As

2nm

(b)

Fig. 2. (Color online) (a) TEM image of a completed In0:7Ga0:3As

channel N-MOSFET with selectively grown in situ doped raised

In0:53Ga0:47As S/D. The interface between two different materials is

indicated by dashed lines. The Nþ–P junction that separates the S/D regions

from the transistor channel or body is represented by dotted lines. (b) High

resolution TEM and FFT diffractogram, revealing the excellent crystalline

quality of the In0:53Ga0:47As epitaxial layer.

30.5 31.0 31.5

In0.7

Ga0.3

As

In0.55

Ga0.45

As InP

Inte

nsit

y (a

.u.)

Bragg Angle (°)

Fig. 3. HRXRD shows well-defined In0:7Ga0:3As and In0:55Ga0:45As

peaks, indicating high crystalline quality of the epitaxial layers.

-1 0 1 20

1

2

3

4

5

6

EOT = ~7.4 nmf = 100 kHz

Raised S/DControl

Gate Voltage VG (V)

Cap

acit

ance

C (

fF/μ

m2 )

(a)

0

1

2

3

4

5

6

(b)Gate Voltage V

G (V)

Cap

acit

ance

C (

fF/μ

m2 )

f = 10 kHzf = 100 kHzf = 1 MHz

-1 0 1 2

Fig. 4. (a) Inversion C–V curves measured at the frequency of 100 kHz

show comparable equivalent oxide thickness EOT for control devices and

devices with raised S/D. (b) C–V characteristics of the device with raised

S/D measured from 10 kHz to 1MHz.

X. Gong et al.Jpn. J. Appl. Phys. 50 (2011) 04DF01

04DF01-2 # 2011 The Japan Society of Applied Physics

the raised S/D architecture with in situ doping gives rise to�25% enhancement in saturation Gm,ext. The total resistanceRTotal between S/D measured at low VDS of 0.1V decreaseswith increasing VG, as shown in Fig. 7, and approaches theS/D series resistance RSD at high gate overdrive. RSD is thesum of source resistance RS and drain resistance RD. Usingthe extraction method in ref. 31, the RSD of in situ dopedraised S/D device and the control were extracted to be 3.1and 3.9 k���m, respectively. Reduced series resistance isa result of combined contributions from the higher S/Ddoping concentration as well as the structural improvementin the raised S/D that leads to more current spreading in thesource and drain regions.

The spacer separates the edge of the gate and the edge ofthe epitaxial InGaAs by 80 nm (Fig. 2). The S/D regionunderneath the spacer has a sheet resistance of �63�/�,as extracted from transmission line measurement (TLM)structure. Therefore, the series resistances contributed bysource and drain regions under the spacers add up to be�10:1���m, which is much smaller than the extracted RSD

of �3:1 k���m. In this work, the gate to contact spacing is�6 �m, and a major component of the RSD is the S/D

resistance between the spacers and the PdGe contacts. Theresistance of the S/D regions under the spacers may bedominant if a self-aligned contact metallization process isused, and can be reduced by thinning the spacers.

Further electrical characterization was performed on asample size of about 15 devices per split. Figure 8 shows thecumulative distribution of the extracted S/D series resis-tance. The statistical result shows a �30% reduction in themedian RSD. This contributes to drive current enhancement.Figure 9 plots the off-state leakage current IOFF and IDsat forthe two sets of device. Best fit trend lines for the controldevices and devices with raised S/D are shown in dashedand solid lines, respectively. IDsat enhancement of �20% at afixed IOFF of 10�6 A/�m was achieved.

Figure 10 benchmarks the normalized peak Gm ofIn0:7Ga0:3As devices with in situ doped raised S/D structurein this work with our previous work.32,33) The physicalHfAlO high-k thickness of In0:7Ga0:3As MOSFETs in thiswork and In0:53Ga0:47As MOSFETs with S/D stressors32,33)

is �19 and �15 nm, respectively. Peak Gm was normalizedwith Cox to account for the difference in EOT. Highernormalized peak Gm was achieved here due to higher indiumcomposition of 70% in the channel for improved electronmobility.

-1 0 1 20

50

100

150

200

~25%

VDS

= 0.1 V

VDS

= 1.2 V

Tra

nsco

nduc

tanc

e G

m,e

xt (

μS/μ

m)

Gate Voltage VG (V)

Raised S/DControl

LG = 700 nm

Fig. 6. Gm,ext–VG curves of the same pair of devices in Fig. 5. In situ

doped raised S/D gives rise to a �25% enhancement in saturation Gm,ext

due to source and drain series resistance reduction.

-1 0 1 20

50

100

150

200

250

(a)

VDS

= 0.1 V

VDS

= 1.2 V

LG = 700 nm

Raised S/DControl

Dra

in C

urre

n I D

(μA

/μm

)

Gate Voltage VG (V)

0 1 20

100

200

300

400

(b)

Step = 0.5 V

VG - V

T = 0 to 2.5 V

Drain Voltage VD (V)

Dra

in C

urre

n I D

(μA

/μm

)

Raised S/DControl

LG = 700 nm

Fig. 5. (a) ID–VG plot in the linear (VDS ¼ 0:1V) and saturation

(VDS ¼ 1:2V) regions. (b) ID–VD curves of the same pair of devices,

showing good saturation and pinch-off characteristics. Drive current is

higher for the In0:7Ga0:3As N-MOSFET with raised S/D as compared with

the In0:7Ga0:3As N-MOSFET control.

0 1 2 30

5

10

15

20 Raised S/DControl

Gate Voltage VG (V)

RTo

tal =

VD

S /ID

,lin (

kΩ·μ

m)

LG = 700 nm

VDS

= 0.1 V

Fig. 7. Total resistance in linear regime (VDS ¼ 0:1) at large VG indicates

smaller series resistance of the device with raised S/D than that of control.

0 2 4 6 80

20

40

60

80

100

Series Resistance (kΩ·μm)

Cum

ulat

ive

Pro

babi

lity

(%)

Raised S/DControl

~30%

Fig. 8. In situ doped raised S/D leads to �30% reduction of the median

series resistance. 15 devices for each split were measured. The gate lengths

of the devices measured range from 350 to 1000 nm.

X. Gong et al.Jpn. J. Appl. Phys. 50 (2011) 04DF01

04DF01-3 # 2011 The Japan Society of Applied Physics

4. Conclusions

Raised S/D structure with in situ doping process wasdemonstrated in InGaAs channel MOSFETs with indiumcomposition as high as 70%. Significant RSD reduction wasachieved, leading to very substantial IDsat enhancement. ThisS/D engineering approach is promising for RSD reduction inIII–V MOSFETs.

Acknowledgements

This work is supported by the Singapore National ResearchFoundation (NRF; Award Number NRF-RF2008-09), andthe Singapore Defence Science and Technology Agency(DSTA; Project Number POD0814040).

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50 100 150 200 25010-8

10-7

10-6

10-5

Raised S/D

ION

(μA/μm) at VGS

- VT = 2 V

I OF

F (

A/μ

m)

at V

GS -

VT =

-0.

2 V

Control

Fig. 9. In situ doped raised S/D gives a �20% IDsat enhancement at a

fixed IOFF of 10�6 A/�m. Devices measured have gate lengths ranging from

350 to 1000 nm. The best fit lines for control devices and devices with raised

S/D are plotted in dashed and solid lines, respectively. VT is the mean

threshold voltage for each group of devices. Threshold voltage was

extracted at VDS ¼ 1:2V by extrapolation of the ID–VG curve at the VG

which maximizes the transconductance.

400 600 800 1000

15

20

25

30

35

40

45 In0.7

Ga0.3

As channel with

raised S/DIn

0.53Ga

0.47As channel with

S/D stressor

Pea

k G

m/C

OX (

μS·μ

m/f

F)

Gate Length LG

(nm)

Fig. 10. Normalized peak Gm (measured at VDS ¼ 1:2V) versus LG.

In0:7Ga0:3As channel devices with raised S/D show higher normalized peak

Gm due to higher indium composition of 70% in the channel for improved

electron mobility.

X. Gong et al.Jpn. J. Appl. Phys. 50 (2011) 04DF01

04DF01-4 # 2011 The Japan Society of Applied Physics