SOC Encounter

INDEX

CHAPTER NAME

1 NCLAUNCH

2 RC COMPILER

3 SOC ENCOUNTER

CHAPTER 1 NCLAUNCH

Chapter 1

Cadence NClaunch NCLaunch is a graphical user interface that helps to manage large design projects and lets you configure and launch your Cadence simulation tools. NCLaunch here is used simulate Verilog, designs using the NCLaunch tool. This tutorial explains the functionality of the tool and gives example of simulating a Verilog module with NCLaunch.

In this tutorial we use one step method which automates design steps from compiling to simulation in one step. This feature is available for verilog only. Problem Statement The complete design flow is shown for the following design problem.

Verilog code of 8-bit fulladder

`timescale 1ns/1ps

module fa8(sum,c_out,a,b,c_in);

input [7:0]a,b;

input c_in;

output c_out;

output [7:0]sum;

wire c1,c2,c3,c4,c5,c6,c7;

fulladder a0(.sum(sum[0]),.c_out(c1),.a(a[0]),.b(b[0]),.c_in(c_in));

fulladder a1(.sum(sum[1]),.c_out(c2),.a(a[1]),.b(b[1]),.c_in(c1));






fulladder a7(.sum(sum[7]),.c_out(c_out),.a(a[7]),.b(b[7]),.c_in(c7));

endmodule

//fulladder module

`timescale 1ns/1ps

module fulladder(sum,c_out,a,b,c_in);

input a,b,c_in;

output sum,c_out;

wire s1,c1,c2,c3,c4;

xor (s1,a,b);

xor (sum,s1,c_in);

and (c1,a,b);

and (c2,b,c_in);

and (c3,a,c_in);

or (c4,c1,c2);

or (c_out,c4,c3);

endmodule

Directory Structure Create a new directory under your home directory to store all your vhdl/verilog designs. Path for Manual /edatools/cadence_new/ius62/doc/iustutorial/iustutorial.pdf other relevant manuals can also be found in /edatools/cadence_new/ius62/doc Invoking NClaunch Source File /edatools/scripts/cadence/ius.csh //solaris

/linuxeda/scripts/cadence/ius.csh //linux

and then to invoke the tool type

nclaunch &

NCLaunch Window The main NCLaunch window is divided into the following components: 1. Menu Bar and Tool Bar--Provide the commands and fast action buttons that

let you manipulate design elements and start the various tools. 2. File Browser--The pane on the left side of the window displays the files in the file system. 3. Design Browser--The pane on the right side of the window displays objects in design to be compiled and simulated. 4. Console Window--Displays output from tools, and allows you to input commands. Choose Single Step Mode When you run IUS for the first time, a window as shown below appears, Single step mode must be selected in the window.

Single step mode can also be selected later. Do as shown below to switch from multistep mode to single step mode.

Goto File -> Single Step Mode

Setting up work directory Every new project you are starting should have its own working directory. That is a directory that holds all the files produced after compiling your design or when you are trying to simulate your design. To create a new working directory got to menu File _ Set Design Directory

From file browser find your design files and move them to design, place tick on file if it is a library file else for normal verilog files donot place tick. If you have multiple files use the arrows on right hand side to set proper order of compilation (bottom hierarchy to top hierarchy). Press compile button in tools as indicated in figure below. Design is compiled, elaborated and then a simulation window opens.

Waveforms before synthesizing

Block diagram before synthesizing

Waveforms after synthesizing

Block diagram after synthesizing

Refer to this page after SOC-ENCOUNTER

Waveforms after Back annotation

Block diagram after Back annotation

CHAPTER 2

RC COMPILER

Chapter 2

Cadence RTL Compiler Introduction Cadence RTL compiler is a synthesis tool used to synthesize the Verilog code to physical cells as per the required technology, in this case UMC 90nm.It also allows us to apply constraints on the circuit like timing constraints, power constraints etc. The following steps will allow you to synthesize your Verilog code which was simulated in Cadence NCLaunch. Note : It should be kept in mind that RTL compiler does not check the functionality The Cadence RTL Compiler does the following things: Generate fast, area-efficient ASIC designs by employing user-specified standard cell Explore design tradeoffs involving design constraints such as timing, area, and

power under various loading, temperature, and voltage conditions. Synthesize and optimize finite state machines, synchronous and asynchronous

designs. Manage complexity by creating and partitioning hierarchical designs automatically, optimizes designs faster and utilize higher capacity with Automated Chip Synthesis. Benefit from the easy-to-use, customizable UNIX style user interface, TCL, and

intuitive visual interface. Enjoy support for industry standard languages. Design using hundreds of libraries offered by over 60 semiconductor and library

vendors

The figure depicts the flowchart for entire synthesis process.

The figure depicts the synthesis procedure from reading the HDL source to translation to mapping to the particular technology.

The broad steps of synthesis are: Hierarchical Compile Compile strategy Top level only compilation Incremental compile

Design Optimization High-level optimization -Arithmetic expressions optimization Full compile -Flattening and structuring -Mapping: -Delay optimization -Design rule fixing -Area specific optimization Sequential optimization for complex flip-flops and latches Finite State Machine (FSM) optimization Time borrowing for latch-based designs Timing Analysis Features Timing exceptions Case analysis to set constant paths Incremental timing update Support for synchronous and asynchronous designs Intuitive User Interface/Ease-of-Use Report generation Command log files Scripting Budgeting Automated Chip Synthesis Steps to run the tool Path to Manual

/edatools/cadence_new/rc72/doc/rc_user/rc_user.pdf /edatools/cadence_new/rc72/doc/rc_ta/rc_ta.pdf

Pre-requisites Before invoing the tool user has to make sure that following folders are created: Create the following folder in your home folder: >mkdir rc_compiler >cd rc_compiler Inside rc_compiler folder : >mkdir rtl scripts com_files results (four different folders) rtl: Stores the verilog code. e.g fsm.v com_files: Stores the technology library files scripts: Store the script file with the set of commands e.g fsm.g results: Stores the synthesised netlists,reports and log files. copy the following files in com_files folder CORE: /edatools/dk/umc90nm/faraday90nm/LLLowK1p9m/core/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/fsd0k_a/2007Q2v1.3/GENERIC_CORE_1D0V/FrontEnd/synopsys/fsd0k_a_generic_core_21.lib This library contains the standard cell definitions i.e. the definition of the various combinational andsequential elements to used during mapping. I/O: /edatools/dk/umc90nm/faraday90nm/LLLowK1p9m/IO/FOD0K_B25_T25_GENERIC_IO_DP_2008Q3v2.0/fod0k_b25/2008Q3v2.0/T25_GENERIC_IO/FrontEnd/synopsys/fod0k_b25_t25_generic_io_21.lib This library contains the information regarding the input output pads to be used in the design. To invoke the tool use the following commands in csh window: >cd rc_compiler >source /edatools/scripts/cadencerc62.csh ---for Solaris systems >source /linuxeda/scripta/caence/rc.csh ----for linux systems

Adding the I/O Pads The Following pads are added: UYNRLA(.O(),.I()); //input pads VYA28SRLA(.O(),.I()); //output pads Steps:

1. Define a module fa8(); 2. Declare all the signals as wire. (Remove previous module and declare its

input and outputs as wire.) 3. Call the final module of the design in the module 4. Define the pads. b5. Save the file with I/O pads in rc_compiler/rtl/fa8pads.v

`timescale 1ns/1ps

module fa8(sum,c_out,a,b,c_in);

input [7:0] a,b;

input c_in;

output c_out;

output [7:0]sum;

wire c1,c2,c3,c4,c5,c6,c7;

wire [7:0] a1,b1,sum1;

wire c_in1,c_out1;

UYNRLA U_A0 (.O(a1[0]), .I(a[0]), .IE(1'b1), .PU(1'b0), .PD(1'b0),

.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));

UYNRLA U_B0 (.O(b1[0]), .I(b[0]), .IE(1'b1), .PU(1'b0), .PD(1'b0),

.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));


.SMT(1'b0));

UYNRLA U_CIN (.O(c_in1), .I(c_in), .IE(1'b1), .PU(1'b0), .PD(1'b0),

.SMT(1'b0));

VYA28SRLA U_SUM0 (.O(sum[0]),.I(sum1[0]), .E(1'b1), .E2(1'b1), .E4(1'b1),

.SR(1'b1));


.SR(1'b1));


.SR(1'b1));


.SR(1'b1));


.SR(1'b1));


.SR(1'b1));


.SR(1'b1));


.SR(1'b1));

VYA28SRLA U_COUT (.O(c_out),.I(c_out1), .E(1'b1), .E2(1'b1), .E4(1'b1),

.SR(1'b1));

fulladder a_0(.sum(sum1[0]),.c_out(c1),.a(a1[0]),.b(b1[0]),.c_in(c_in1));

fulladder a_1(.sum(sum1[1]),.c_out(c2),.a(a1[1]),.b(b1[1]),.c_in(c1));






fulladder a_7(.sum(sum1[7]),.c_out(c_out1),.a(a1[7]),.b(b1[7]),.c_in(c7));

endmodule

Note: Corner,VDD and GND pads will be added after the code is synthesized. Editing the Script file The script file is used to save the commands required to synthesize the Verilog code. This file needs to be edited according to the design files. Steps:

1. Change the name of the verilog file to fa8.v . 2. Change the name of the top module to fa8_top . 3. Include the Library files for core and io cells . 4. Change the name of the report files 5. Save the script file in /rc_compiler/scripts/fa8.g .

Following is the script file: # is used for commenting a line. #******************Script file for RC compiler ***************************************

#Script file: top01_golden.g to be used as reference by the user. #Do not change any part of this script. This lab session will familiarize the user through the #navigation procedure in the design hierarchy that will be created by RTL compiler during a #synthesis session. #************************************************************************** #--------------------------------------------------------------------------------------------------------------- #Step 1: The following command lines set up the design environment & the library #--------------------------------------------------------------------------------------------------------------- set_attribute information_level 7 #----------------------------------------------------------------------------------------------------------------------- #The information level 7 specifies that you are going to supply the maximum amount of #information #to the compiler through the script file. #----------------------------------------------------------------------------------------------------------------------- set root_dir /assignments//rc_compiler #--------------------------------------------------------------------------------------------------------------- #The "set root_dir" command specifies the root directory or the absolute path from where you #are going to source the RC compiler. The path must be appropriately set. #--------------------------------------------------------------------------------------------------------------- set synth_dir /assignments//rc_compiler/results #----------------------------------------------------------------------------------------------------------------------- #The "set synth_dir" command specifies the synthesis directory. This is the directory where #the reports generated by the RC compiler will be stored. The path must be appropriately set.

#----------------------------------------------------------------------------------------------------------------------- set rtl_path /assignments//rc_compiler/rtl #----------------------------------------------------------------------------------------------------------------------- #The set rtl_path" command tells the RC compiler to look for the RTL (verilog file) in the #"rtl" folder inside "rc_compiler". The "rtl" folder is supposed to contain the RTL code file. #----------------------------------------------------------------------------------------------------------------------- set lib_path /assignments//rc_compiler/com_files #----------------------------------------------------------------------------------------------------------------------- #The RC compiler needs library files for synthesizing the RTL code #and generating the #synthesized netlist. The "set lib_path" command tells the RC compiler to look for the #library files in the folder named "com_files" inside "rc_compiler". #----------------------------------------------------------------------------------------------------------------------- set com_fl_path /assignments//rc_compiler/com_files #----------------------------------------------------------------------------------------------------------------------- #The set com_fl_path" command sets the library files path to the above directory. #----------------------------------------------------------------------------------------------------------------------- set file_list {fa8.v fulladder.v} #----------------------------------------------------------------------------------------------------------------------- #The "set file_list" command lists the files to be synthesized. There may be more than one #verilog files you may want to synthesize at a time with each one containing a module which #calls another module in a different file. Specify the name of all the files #inside the #parenthesis with space between them. An example is given below: #set file_list {fulladder.v half_adder.v} The fulladder module in the "fulladder.v" file uses #the halfadder module in the "half_adder.v" file. #----------------------------------------------------------------------------------------------------------------------- set top_module {fa8} #--------------------------------------------------------------------------------------------------------------- #Even though you may specify more than one files in the file list in the above command, the #top module must a single one. You cannot have more than one top module in your design. #The top module is supposed to be the one which calls or instantiates all other modules. #--------------------------------------------------------------------------------------------------------------- set_attribute gen_module_prefix G2C_DP_COMP set_attr hdl_search_path $rtl_path #----------------------------------------------------------------------------------------------------------------------- #The command "set_attr hdl_search_path $rtl_path" sets the rtl search path to the value of #the variable rtl_path which has been previously set. #----------------------------------------------------------------------------------------------------------------------- set_attr lib_search_path $lib_path #-----------------------------------------------------------------------------------------------------------------------

#The command "set_attr lib_search_path $lib_path" sets the library search path to the value #of the variable lib_path which has been previously set. #----------------------------------------------------------------------------------------------------------------------- set library {fsd0k_a_generic_core_21.lib fod0k_b25_t25_generic_io_21.lib} #----------------------------------------------------------------------------------------------------------------------- #The command "set library" sets the library to the following library file mentioned in the #parenthesis. The library file must be present in the com_files folder already. #----------------------------------------------------------------------------------------------------------------------- set_attribute library $library #----------------------------------------------------------------------------------------------------------------------- #The "set_attribute library $library" sets the library path to the value of the variable library #which has been set previously. #----------------------------------------------------------------------------------------------------------------------- include $com_fl_path/ae_utils.tcl load $file_list #----------------------------------------------------------------------------------------------------------------------- #Step 2: The following command lines loads or reads the source files for the design #including the top level module. #----------------------------------------------------------------------------------------------------------------------- elaborate $top_module #--------------------------------------------------------------------------------------------------------------- #The elaboration step flattens the netlist that is it breaks the top modules into various sub #modules until it reaches the leaf cells in the bottom of the hierarchy. #--------------------------------------------------------------------------------------------------------------- define_clock -domain clkdomain1 -name clock -period 3000 [find / -port clk] external_delay -input 1500 -clock clock [all_ins] external_delay -output 1200 -clock clock [all_outs] #--------------------------------------------------------------------------------------------------------------- #Step 3: Once the top level module is elaborated some basic constraints need to be set up, #which include the clock definition and external input delay on signals that are inputs, with #respect to the clock and similarly external output delays with respect to the subsequent clock #edge when the outputs from the design will be read by external circuits from this design #block. The clock period is to be 3000 ps (but can vary from design to design) and the #external input and output delays are to be 1500 and 1200 ps respectively. #Note: An external clock does not directly drive any points within the design, but is only #used as a reference for external delays. Combinational designs dont have any clocks but #still the above constraint must be defined for such designs because it is used as reference

#for Slack calculation. The name of the clock port in the above constraint must be same as #that of the clock port name in the top module of the design. In any other case the RC #compiler gives a error as UNCONSTRAINED Slack. #----------------------------------------------------------------------------------------------------------------------- #set_attribute preserve size_ok [find / -instance g1] #set_attribute preserve true [find / -subdesign del] #set_attribute preserve true $top_module.n2 #----------------------------------------------------------------------------------------------------------------------- #Prevent RC compiler from performing optimizations on specific objects in the design using #the "preserve" attribute. By default the RC compiler will perform optimizations that can #cause logic changes to any object in the design. The instances specified in the #parenthesis #can be in various formats. #For example the first preserve attribute preserves the instance named "g1".If the instance #"g1" has instances "g2" and "g3" in the #hierarchy, these instances would also be preserved. #Sub-modules can also be preserved by specifying the preserve attribute in the #second #format. #Note: An important thing to be remembered is that the compiler only preserves mapped #instances only. The "size_ok" part allows the instances to be optimized by resizing them but #while preserving them. #**The attributes have been commented and are to be used only if required. #----------------------------------------------------------------------------------------------------------------------- #----------------------------------------------------------------------------------------------------------------------- #Note: The RC compiler gives priority to the default design rule constraints imposed by the #technology library over the constraints set by the user for the design. In this case, the #compiler applies the user defined constraints to the design only if it doesnt violate the #default constraints. #----------------------------------------------------------------------------------------------------------------------- set_attribute max_dynamic_power 0.0 $top_module set_attribute max_leakage_power 0.0 $top_module #----------------------------------------------------------------------------------------------------------------------- #There are mainly two kinds of power dissipations in a design which the RC compiler reports #i.e. dynamic power (switching power) and leakage power (due to leakage currents). Both #the powers can be optimized for by setting the above two attributes. Setting the two powers #to 0.0 doesn't mean it minimizes the dissipation to zero. It just optimizes the design for

#minimum power. #----------------------------------------------------------------------------------------------------------------------- set_attribute ignore_library_drc true $top_module #----------------------------------------------------------------------------------------------------------------------- #Design rule constraints are imposed on synthesis by the physical limitations of the #technology library chosen for the synthesis. Design rules include # 1.Maximum capacitance per net # 2.Maximum fanout per gate # 3.Maximum transition time of a signal #The three constraints are used together to ensure that the library limits are not exceeded. ##Note:-However you can set looser design constraints than the ones specified in the #technology library. To force the RC compiler to #ignore the DRC specified in the library #you have set the "ignore_library_drc" attribute along with the max_capacitance, max_fanout #and max_transition attribute. #----------------------------------------------------------------------------------------------------------------------- set_attribute max_fanout 17 $top_module #----------------------------------------------------------------------------------------------------------------------- #Specify the maximum fanout design rule limit for all the nets in a design or port using the #max_fanout attribute. Setting the maximum fanout limit on a design sets the default the #maximum fanout for that design. Setting a maximum fanout limit on a port specifies that #the net connected to that port to have a total fanout load less than the value you specify. #----------------------------------------------------------------------------------------------------------------------- set_attribute max_capacitance 10 $top_module #----------------------------------------------------------------------------------------------------------------------- #The load on a net is composed of fanout and interconnect capacitances. Setting a maximum #capacitance limit on a port specifies that the net connected to that port to have a maximum #capacitance less than the value you specify. Setting a maximum capacitance limit on a #design sets the default maximum capacitance for that design. #----------------------------------------------------------------------------------------------------------------------- set_attribute max_transition 37 $top_module #--------------------------------------------------------------------------------------------------------------- #The transition time is the amount of time it takes for a signal to change logic states and is a #product of the signal-line capacitance and resistance on the wire. The wireload model details #the capacitance and resistance characteristics. The max_transition attribute sets the #maximum transition limit for nets attached to that port or design. Setting a maximum #transition limit on a design sets the default transition time to that value. #---------------------------------------------------------------------------------------------------------------

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#----------------------------------------------------------------------------------------------------------------------- ##Note: You cannot arbitrarily set a value for these attributes. Setting it to any value may #adversely affect the design. #----------------------------------------------------------------------------------------------------------------------- set_attribute delete_unloaded_seqs false $top_module #----------------------------------------------------------------------------------------------------------------------- #By default, RC compiler removes flip flops and logic if they do not transitively fan in out to #output ports. To prevent this, use the delete_unloaded_seqs attribute. #----------------------------------------------------------------------------------------------------------------------- #----------------------------------------------------------------------------------------------------------------------- #Step 4: Start synthesis and report the summary , timing of the slowest path , write out the #gate level netlist . #----------------------------------------------------------------------------------------------------------------------- #----------------------------------------------------------------------------------------------------------------------- #During RTL optimization, RTL compiler performs optimizations like data path synthesis, #resource sharing, speculation, mux optimization and CSA (carry save arithmetic) #optimizations. After this step RC compiler performs logic optimizations like restructuring #and redundancy removal. #Next the compiler performs synthesis remapping. During this phase the compiler only #performs global sizing of cells. During remapping some optimizations are targeted at area #and some at timing optimizations. #The final optimization step is incremental optimization (IOPT). Optimizations performed #during IOPT will improve timing and area and fix DRC violations. #----------------------------------------------------------------------------------------------------------------------- set_attribute drc_first true #----------------------------------------------------------------------------------------------------------------------- ##Note: By default, timing has the highest priority and the compiler will not fix DRC #violations if doing so causes timing violations. However the priority can be overridden by #setting the drc_first attribute to true. In this case all violations will be fixed. #----------------------------------------------------------------------------------------------------------------------- synthesize -to_mapped #----------------------------------------------------------------------------------------------------------------------- #During synthesis the compiler maps the combinational and sequential instances used in the #design to the technology mapped instances. The mapping or optimization effort defines the #level of effort the compiler puts in during synthesis. That is the higher the effort the higher #the optimization done by the compiler. By default, the effort is set to "low". The "synthesize #-to_mapped" command is used for this purpose. #-----------------------------------------------------------------------------------------------------------------------

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set MAP_EFF high synthesize -to_mapped -effort $MAP_EFF -no_incr #----------------------------------------------------------------------------------------------------------------------- #However, you can set the optimization effort to high by the #following command. #----------------------------------------------------------------------------------------------------------------------- synthesize -to_generic #----------------------------------------------------------------------------------------------------------------------- #Instead of doing mapped synthesis you could also do generic synthesis. In this case the #compiler doesn't map the instances used in your design to the technology but instead uses #generic gates. That is it uses the normal gates you use in your design-and, or, not, etc. ##Note: The difference between synthesize -to_mapped and synthesize -to_generic can be #noted from the netlist files generated by the RC compiler. #----------------------------------------------------------------------------------------------------------------------- #----------------------------------------------------------------------------------------------------------------------- ##Note:-Do not set all attributes specified in the script file at #the same time. It is advised to #use only those attributes that are required for the particular design. #----------------------------------------------------------------------------------------------------------------------- #predict_qos #synthesize -incremental #----------------------------------------------------------------------------------------------------------------------- #The following commands are used to generate various reports by the compiler. The #synthesize_incremental command is used to perform synthesis with incremental #optimization. #----------------------------------------------------------------------------------------------------------------------- report area > $synth_dir/fa8_area.rep report summary > $synth_dir/fa8_sum.rep #----------------------------------------------------------------------------------------------------------------------- #The above reports are self-explanatory. #----------------------------------------------------------------------------------------------------------------------- report timing -num_paths 4 > $synth_dir/fa8 _slack.rep #------------------------------------------------------------------- #The previous command reports the 4 paths with the worst slack. You can specify any no. of #paths. If you don't specify the "-num_paths 4" the compiler specifies the path with worst #slack. #----------------------------------------------------------------------------------------------------------------------- report gates > $synth_dir/fa8 _gates.rep #----------------------------------------------------------------------------------------------------------------------- #The gates report gives the information about the mapped gates used by the compiler for #mapping you design to the particular technology. However the no. doesn't exactly #correspond to the no. of gates you used in your design but no doubt it gives an approximate #idea. #-----------------------------------------------------------------------------------------------------------------------

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write -mapped > $synth_dir/fa8_NL.v #----------------------------------------------------------------------------------------------------------------------- #The "write -mapped" command generates the optimized netlist which you have to give as #input to the SOC Encounter for placement and routing. #----------------------------------------------------------------------------------------------------------------------- write_sdc > $synth_dir/fa8.sdc #----------------------------------------------------------------------------------------------------------------------- #The "write_sdc" command generates the sdc (synopsis design constraints) file which #contains the various design constraints the compiler applied to you design. This file is also #used as an input to the SOC encounter. #----------------------------------------------------------------------------------------------------------------------- #----------------------------------------------------------------------------------------------------------------------- #The following report commands could be typed in the rc prompt obtained after the compiler #completes synthesis. In addtion to these reports the following report commands could be #used: # 1.report power:- reports the dynamic and leakage power dissipation. # 2.report qor:- gives the qor report which gives fanout, power info. # 3.report design_rules:- Reports the design rule violations encountered during #synthesis. The maximum capacitance, fanout and transition time violations can be noted #using this command and modified accordingly. #There are many other reports which you could use. Just type the "report" command in the #"rc" prompt. #----------------------------------------------------------------------------------------------------------------------- #retime -min_delay -min_area #synthesize -to_mapped -incremental #report timing > $synth_dir/fa8_tim1.rep #report area > $synth_dir/fa8_area1.rep #----------------------------------------------------------------------------------------------------------------------- ##Note: The command "retime" doesn't work because of the absence of license for this #command. However this command could be used to improve the timing slack of the critical #paths in the design. The following report commands would generate the new reports. #----------------------------------------------------------------------------------------------------------------------- #----------------------------------------------------------------------------------------------------------------------- ########################################################################### #The script driven synthesis will complete at this stage and the g2c-rc shell will prompt with #the message "synthesis succeeded". Don't quit the shell. Instead from the command line in #the shell issue the following commands and check the tool response. These steps will make

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#the user conversant with the design hierarchy that is set up. ########################################################################### #Step 5 : - 'cd' to the top of the DH to identify the directory final/ at the top of the DH # - ls -l -a is used to list all characteristics of objects and contents of the current #directory - in this case . Familiarize yourself with the attributes that get attached #to a top level design in RC. #----------------------------------------------------------------------------------------------------------------------- #ls -l -a [find /des* -design ] #ls -l -a [find /des* -subdesign ] #ls -l -a [find /des* -instance ] #ls -l -a [find /des* -clock ] #ls -l -a [find /des* -port ] #ls -l -a [find /des* -pin ] #----------------------------------------------------------------------------------------------------------------------- #Step 6 : Open a new terminal and in it using a text editor write out a small Tcl script as #below and store it in the com_files directory (to list subdesigns: creating command #list_subdes # proc list_subdes { } { # foreach des [find / -subdes *] { # foreach inst [get_attr instances $des] { # echo "$des " # } # } # } # save this as "list_subdes.tcl" in the directory $root_dir/com_files/ # - Move back to the terminal that has the rc shell running # - source this tcl script file and use the command #----------------------------------------------------------------------------------------------------------------------- source $root_dir/com_files/list_subdes.tcl ########################################################################### # enter the command list_subdes and confirm the subdesign names. ########################################################################### list_subdes #Step 7: Quit the rc shell with the quit command and using a text editor to view the netlist file #created in Step 5. ###################################################################

To Synthesise the code use the following command: > rc -f ./scripts/fsm.g |tee ./results/fa8.log

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The command tells the RC compiler to look for the script file fa8.g inside the scripts folder in your root directory and create a log file named fa8.log in the results folder also in your root directory. To Synthesize from the rc prompt use the following command: rc:/>include ./scripts/fa8.g They include command does the same except that it creates a log file by the default name rc.log in your root directory. The log file saves all the data displayed in the csh window and can be use to review errors. The compilation may take some time depending on the complexity of the code. Analysis: report command is used to check the various attributes of the design After the sysnthesis the RTL Compiler returns to the following prompt rc:/> use the following command to check the Timing Slack of the worst path: rc:/> report timing if the slack is negative change the clock time in the script file as mentioned earlier. It is advised to keep the slack >500ps to allow for some margin for placement and routing in the SOC Encounter. Note: Do not exit from RTL Compiler before checking the reports. The synthesized netlist (fa8_NL.v) obtained from the compiler will look like:

`timescale 1ns/1ps

// Generated by Cadence Encounter(R) RTL Compiler v07.20-p004_1

`include "fsd0k_a_generic_core_21.lib"

`include "fod0k_b25_t25_generic_io_21.lib"

module fulladder(sum, c_out, a, b, c_in);

input a, b, c_in;

output sum, c_out;

wire a, b, c_in;

wire sum, c_out;

FA1RLX2 g40(.A (b), .B (a), .CI (c_in), .S (sum), .CO (c_out));

endmodule

module fulladder_1(sum, c_out, a, b, c_in);

input a, b, c_in;

output sum, c_out;

wire a, b, c_in;

wire sum, c_out;

wire n_0, n_1, n_2, n_3, n_4, n_10;

AO12RLXLP g40(.A1 (n_4), .B1 (n_2), .B2 (n_10), .O (sum));

ND2RLX4 g41(.I1 (n_3), .I2 (n_0), .O (c_out));

NR2RLXLP g42(.I1 (n_2), .I2 (n_10), .O (n_4));

ND2RLX3 g43(.I1 (c_in), .I2 (n_1), .O (n_3));

XNR2RLX1 g44(.I1 (b), .I2 (a), .O (n_2));

OR2RLX1 g45(.I1 (b), .I2 (a), .O (n_1));

ND2RLX1 g46(.I1 (b), .I2 (a), .O (n_0));

BUFRLXLP g47(.I (c_in), .O (n_10));

endmodule


input a, b, c_in;

output sum, c_out;

wire a, b, c_in;

wire sum, c_out;


endmodule


input a, b, c_in;

output sum, c_out;

wire a, b, c_in;

wire sum, c_out;

wire n_0, n_1, n_2, n_3, n_4, n_10;

AO12RLXLP g40(.A1 (n_4), .B1 (n_10), .B2 (n_2), .O (sum));

ND2RLX4 g41(.I1 (n_3), .I2 (n_0), .O (c_out));

NR2RLXLP g42(.I1 (n_2), .I2 (n_10), .O (n_4));

ND2RLX3 g43(.I1 (c_in), .I2 (n_1), .O (n_3));

XNR2RLX1 g44(.I1 (b), .I2 (a), .O (n_2));

OR2RLX1 g45(.I1 (b), .I2 (a), .O (n_1));

ND2RLX1 g46(.I1 (b), .I2 (a), .O (n_0));

BUFRLXLP g47(.I (c_in), .O (n_10));

endmodule


input a, b, c_in;

output sum, c_out;

wire a, b, c_in;

wire sum, c_out;

wire n_0, n_1, n_2, n_3, n_4;

AO12RLX1 g40(.A1 (n_4), .B1 (n_1), .B2 (n_3), .O (sum));

MOAI1RLX2 g41(.A1 (n_0), .A2 (n_2), .B1 (b), .B2 (a), .O (c_out));

NR2RLX1 g42(.I1 (n_3), .I2 (n_1), .O (n_4));

XNR2RLX1 g43(.I1 (b), .I2 (a), .O (n_3));

NR2RLX1 g44(.I1 (b), .I2 (a), .O (n_2));

INVRLXLP g45(.I (n_0), .O (n_1));

INVRLX4 g46(.I (c_in), .O (n_0));

endmodule


input a, b, c_in;

output sum, c_out;

wire a, b, c_in;

wire sum, c_out;

FA1RLX2 g40(.A (c_in), .B (a), .CI (b), .S (sum), .CO (c_out));

endmodule


input a, b, c_in;

output sum, c_out;

wire a, b, c_in;

wire sum, c_out;

wire n_0, n_1, n_2, n_3;

MUX2RLX2 g40(.S (n_3), .A (n_0), .B (n_1), .O (sum));

MOAI1RLX2 g41(.A1 (n_0), .A2 (n_2), .B1 (b), .B2 (a), .O (c_out));

XNR2RLX1 g42(.I1 (b), .I2 (a), .O (n_3));

NR2RLX1 g43(.I1 (b), .I2 (a), .O (n_2));

INVRLXLP g45(.I (n_0), .O (n_1));

INVRLX2 g46(.I (c_in), .O (n_0));

endmodule


input a, b, c_in;

output sum, c_out;

wire a, b, c_in;

wire sum, c_out;


endmodule

module fa8(sum, c_out, a, b, c_in);

input [7:0] a, b;

input c_in;

output [7:0] sum;

output c_out;

wire [7:0] a, b;

wire c_in;

wire [7:0] sum;

wire c_out;

wire \a1[0] , \a1[1] , \a1[2] , \a1[3] , \a1[4] , \a1[5] , \a1[6] ,

\a1[7] ;

wire \b1[0] , \b1[1] , \b1[2] , \b1[3] , \b1[4] , \b1[5] , \b1[6] ,

\b1[7] ;

wire c2, c4, c5, c6, c7, c_in1, c_out1, n_34;

wire n_35, \sum1[0] , \sum1[1] , \sum1[2] , \sum1[3] , \sum1[4] ,

\sum1[5] , \sum1[6] ;

wire \sum1[7] ;

fulladder a_0(.sum (\sum1[0] ), .c_out (n_34), .a (\a1[0] ), .b

(\b1[0] ), .c_in (c_in1));

fulladder_1 a_1(.sum (\sum1[1] ), .c_out (c2), .a (\a1[1] ), .b

(\b1[1] ), .c_in (n_34));

fulladder_2 a_2(.sum (\sum1[2] ), .c_out (n_35), .a (\a1[2] ), .b

(\b1[2] ), .c_in (c2));


(\b1[3] ), .c_in (n_35));


(\b1[4] ), .c_in (c4));


(\b1[5] ), .c_in (c5));


(\b1[6] ), .c_in (c6));

fulladder_7 a_7(.sum (\sum1[7] ), .c_out (c_out1), .a (\a1[7] ), .b

(\b1[7] ), .c_in (c7));

UYNRLA U_A0(.I (a[0]), .IE (1'b1), .PU (1'b0), .PD (1'b0), .SMT

(1'b0), .O (\a1[0] ));


(1'b0), .O (\a1[1] ));


(1'b0), .O (\a1[2] ));


(1'b0), .O (\a1[3] ));


(1'b0), .O (\a1[4] ));


(1'b0), .O (\a1[5] ));


(1'b0), .O (\a1[6] ));


(1'b0), .O (\a1[7] ));

UYNRLA U_B0(.I (b[0]), .IE (1'b1), .PU (1'b0), .PD (1'b0), .SMT

(1'b0), .O (\b1[0] ));


(1'b0), .O (\b1[1] ));


(1'b0), .O (\b1[2] ));


(1'b0), .O (\b1[3] ));


(1'b0), .O (\b1[4] ));


(1'b0), .O (\b1[5] ));


(1'b0), .O (\b1[6] ));


(1'b0), .O (\b1[7] ));

UYNRLA U_CIN(.I (c_in), .IE (1'b1), .PU (1'b0), .PD (1'b0), .SMT

(1'b0), .O (c_in1));

VYA28SRLA U_COUT(.I (c_out1), .E (1'b1), .E2 (1'b1), .E4 (1'b1), .SR

(1'b1), .O (c_out));

VYA28SRLA U_SUM0(.I (\sum1[0] ), .E (1'b1), .E2 (1'b1), .E4 (1'b1),

.SR (1'b1), .O (sum[0]));


.SR (1'b1), .O (sum[1]));


.SR (1'b1), .O (sum[2]));


.SR (1'b1), .O (sum[3]));


.SR (1'b1), .O (sum[4]));


.SR (1'b1), .O (sum[5]));


.SR (1'b1), .O (sum[6]));


.SR (1'b1), .O (sum[7]));

endmodule

Test bench `timescale 1ns/1ps

module fa8_tb;

reg c_in;

reg [7:0]a,b;

wire c_out;

wire [7:0]sum;

fa8 fa8_tb(.c_out(c_out),.sum(sum),.a(a),.b(b),.c_in(c_in));

initial

begin

a=8'b00000000;b=8'b00000000;c_in=1'b0;

#5 a=8'b11001111;b=8'b10101010;

#5 a=8'b11111111;b=8'b11111111;c_in=1'b1;

#10 $finish;

end

initial

begin

$recordfile("fa8.trn");

$recordvars;

end

endmodule

Back Annotation After the synthesis, it is required to check the functionality of the design so the fa8_NL.v needs to be simulated in NCLaunch Following Modifications are required:

1. Include the Verilog simulation files at the top of the fa8_NL.v

include "fsd0k_a_generic_core_21.lib" This file is available at Core : /edatools/dk/umc90nm/faraday90nm/LLLowK1p9m/core/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/fsd0k_a/2007Q2v1.3/GENERIC_CORE_1D0V/FrontEnd/verilog/fsd0k_a_generic_core_21.lib Copy this file in the folder where you are invoking NCLaunch Tool Renote: It is to be kept in mind the now the time scale has been changed to 10ps so the Verilog test bench needs to be edited accordingly. The rest of the procedure can be referred from Chapter-1 NCLaunch This is the end of synthesis process. Now feed the NETLIST file (fa8_NL.v) along the SDC file (fa8_chip.sdc) generated by the compiler to SOC encounter for Placement and Routing process.

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CHAPTER 3 SOC ENCOUNTER

Chapter-3

Physical Placement and Routing Cadence SOC Encounter

Introduction Up till now we have successfully defined our digital system in Verilog and synthesized the gate level netlist for UMC 90nm technology i.e. converted out system description to the physical technology parameters using the *.lib files from the technology library. Now we are in position to physically place the design on silicon i.e placement and routing. This decides where to place different modules in the design. One might ask why we need to do this when everything has to be placed on the silicon. As designers and the competition in the ASIC design companies try to make their design work as fast as possible. For E.g.: Consider a large system like a system on chip which has both processors, memory data converters etc. It is imperative to say that memory needs to be close to the processor for faster access of data as it will be a critical step for speed. Following Flow is used for placement and writing Physical Placements Basics:

The above flow chart explains the complete flow. We will discuss every step in detail

Following that a the complete flow will be shown step by step. 1. FLOORPLANNING

Floor planning of a design is the first step after import of the technology files and gate-level verilog netlist. In this step the floorplan needs to be prepared for power supplies, placement of IO-pads and standard cells. It is required to determine the die size by arrangement of the IOs on the pad frame and the pad-frame to core distance. 2. POWER PLANNING The task where the power supplies for the core rows and macros are specified is referred to as power planning. The designer needs to design the power supply rails around the core and blocks by choosing metal layers as well as physical location and width of the supply lines . 3. CELL PLACEMENT In this task the information in the gate-level netlist is used to place the standard cells on the floor plan. The standard cells may be arranged by providing timing information generated during RTL synthesis. 4. CLOCK TREE SYNTHESIS After cell placement the location of registers is known and the clock tree(s) can be synthesized. The clock buffers will be placed in the gaps of the floorplan. Furthermore, due to the nature of CTS the clock tree will be routed in this step ahead of any other signal. This guarantees that the clock tree will be routed in the most efficient way, and thereby clock skew will be reduced. 5. POWER ROUTING The power supplies specified during power planning need to be connected. Encounter will create connections between the core rows and core rings, and from the core rows to the core supply pads. 6. SIGNAL ROUTING In this task the signals in the netlist need to be routed to complete physical placement of the design. The tool will try to optimize timing by optimal routing, i.e., the signals will be assembled by wires that span over several layers. 7. VERIFICATION The final step is verify to that everything has been connected properly.

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Files Required: To run the designing process Encounter also requires many files to load the design and its properties specific to the desired technology in this case UMC 90nm. Technology and Design Files: Physical placement of a design requires the layout and timing information of the standard cells. Constraint driven placement may be utilized with constraints generated during RTL synthesis. Layout and timing information is provided from the technology vendors. The former is provided by the library exchange format (LEF) file. The information in the LEF file includes layer names, layer widths, layer usage, external dimensions, cell pin and port as well as blockage description. The latter, timing information, is provided by the technology libraries (.lib), which are available as worst- and best-corner cases to model process variations. The constraints set during synthesis may be transferred to Encounter by a Synopsys Design Constraints (SDC) file. The file is tool command language (Tcl) based and specifies the design intent, including the timing, power, and area constraints. The gate-level netlist of the design which was generated during RTL synthesis needs to be provided in verilog format. Library 1. Physical Library (LEF) : It contains Information of technology, standard cells, Hard Blocks, and APR 2. Timing Library (LIB) : It contains Timing information of the standard cells and Hard Blocks User Data 1.Gate-Level Netlist (Verilog) 2. SDC Constraint (*.sdc) 3. IO Constraint (*.ioc) IO Assignment File: The physical location as well as the orientation of the IOs need to be specified in a IO assignment file. Beside the IOs which are already inferred with the RTL model, IOs for core and pad power need to be specified. ESD pads are also placed which are beyond the scope of this manual. A template file *.io is saved after the design is loaded that specifies the pads for power supply,corner pads etc. location/orientation of the pads. Dependent on the location, the pads need to be oriented by specifying the direction of the pads The names of IO's were defined in the Verilog code before RTL synthesis in last chapter.The position of the pads may be top, left, bottom, right respectively. The core power supplies should remain as the center of top and bottom or right and left. Corner pads are placed in topright, topright, bottomleft, bottomright.

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User Guide Path

/edatools/cadence_new/soc71/doc/soceUG/soceUG.pdf

USING THE P&R TOOL Tool Used: Cadence SOC Encounter 7.1 Caution : Please be patient with the tool it has a very heavy binary. Invoking multiple tools is discouraged when using SOC Encounter. To import a new design we have to exit the tool and then invoke it again. Pre-requisites and invoking the tool: Note: Use of Tab key is encoraged for paths completion. Invoke the tool in a new csh window as it will prodece the enccounter> prompt and render the window useless for other purposes. Steps: 1. Make a folder soc_encounter in your home folder.

>mkdir soc_encounter

2. Change to this directory.

>cd soc_encounter/

3. Source the following file:

>source /edatools/scripts/cadence/soc71.csh --for Solaris Systems $ source /linuxeda/scripts/cadence/soc.csh --for Linux Systems

4. Invoking the tool:

>encounter xmode

Sometimes the tool may give an error in invoking the tool in 32 bit. Use the following command to invoke the tool in 64 bit. WRITE THE COMMAND AS IT IS BEFORE INVOKING THE TOOL.

>setenv CDS_AUTO_64BIT ALL

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The following window will appear:

Switches between Floorplan, Amoeba and Layout view Before importing the design in Encounter power pads, ground pads and corner pads need to be added to the fa8_NL.v file. Following steps must be followed. 1. Open the file rc_compiler/results/fa8_NL.v 2. Add the following instances at the end of fa8 CORNERRLA cor1(); //corner pad instances CORNERRLA cor2(); CORNERRLA cor3(); CORNERRLA cor4();

VCC2IORLA(); // power pad instance

VCCKRLA();// power pad instance

GND2IORLA(); //ground pad instance

GNDKRLA();//ground pad instance

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Following Steps explains how to work with Cadence SOC Encounter STEP 1: Technology and Design Import The technology and design files need to be read by Encounter to generate a database. The technology files that accommodate physical and timing information are accessed by selecting files with following extentions. .lef .lib The required .lib files model worst- (wc) and best (bc) process corners by max- and min-timing libraries, respectively. The design files consist of the gate-level netlist, timing constraint file, having the endings Following files are also required:

.v .sdc

We have generated these files after from RTL compiler and store were store in rc_compiler/results in your home directory. To import the design Design Import Design

The order of the files must be maintained otherwise the design will not load. Verilog netlist: rc_compiler/results/fa8_NL.v Precautions to be followed while importing a gate level netlist :

1.If designing a chip, IO PADs, power PADs, and Corner PADs should be added before the netlist is imported 2.Make sure that there is no assign statement and no *cell* cell name in the netlist

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Timing Libraries: Max.Timing Libraries: 1./edatools/dk/umc90nm/faraday90nm/LLLowK1p9m/core/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/fsd0k_a/2007Q2v1.3/GENERIC_CORE_1D0V/FrontEnd/synopsys/fsd0k_a_generic_core_0d9vwc.lib 2./edatools/dk/umc90nm/faraday90nm/LLLowK1p9m/IO/FOD0K_B25_T25_GENERIC_IO_DP_2008Q3v2.0/fod0k_b25/2008Q3v2.0/T25_GENERIC_IO/FrontEnd/synopsys/fod0k_b25_t25_generic_io_ss1p08v125c.lib Min.Timing Libraries: 1./edatools/dk/umc90nm/faraday90nm/LLLowK1p9m/core/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/fsd0k_a/2007Q2v1.3/GENERIC_CORE_1D0V/FrontEnd/synopsys/fsd0k_a_generic_core_1d1vbc.lib 2./edatools/dk/umc90nm/faraday90nm/LLLowK1p9m/IO/FOD0K_B25_T25_GENERIC_IO_DP_2008Q3v2.0/fod0k_b25/2008Q3v2.0/T25_GENERIC_IO/FrontEnd/synopsys/fod0k_b25_t25_generic_io_ff1p32vm40c.lib LEF Files: 1./edatools/dk/umc90nm/faraday90nm/LLLowK1p9m/core/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/fsd0k_a/2007Q2v1.3/GENERIC_CORE_1D0V/BackEnd/lef/header6m015_V55.lef 2./edatools/dk/umc90nm/faraday90nm/LLLowK1p9m/core/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/FSD0K_A_GENERIC_CORE_1D0V_DP_2007Q2v1.3/fsd0k_a/2007Q2v1.3/GENERIC_CORE_1D0V/BackEnd/lef/fsd0k_a_generic_core.lef 3./edatools/dk/umc90nm/faraday90nm/LLLowK1p9m/IO/FOD0K_B25_T25_GENERIC_IO_DP_2008Q3v2.0/fod0k_b25/2008Q3v2.0/T25_GENERIC_IO/BackEnd/lef/header6m015_V55.lef 4./edatools/dk/umc90nm/faraday90nm/LLLowK1p9m/IO/FOD0K_B25_T25_GENERIC_IO_DP_2008Q3v2.0/fod0k_b25/2008Q3v2.0/T25_GENERIC_IO/BackEnd/lef/fod0k_b25_t25_generic_io.6m015.lef SDC File: rc-compiler/results/fa8.sdc It is recommended to save these specifications in a config file, i.e., select Save and specify the name of the configuration file.

Load option can be used to load the *.conf file load a design.

The default folder where Encounter will save all the files is from the folder the tool is invoked. Finally, select OK to complete this task. If everything was properly declared the initial floorplan will be visible like the following.

As can be seen the Design has been loaded but the pads are not placed properly. Save the *.io file Design Save I/O file. Now open this *.io file and make the changes in it to make it look like the following: Before: (bottomleft (inst name="C1" ) (inst name="C2" ) (inst name="C3" ) (inst name="C4" ) )

After: (bottomleft (inst name="C1" ) ) (bottomright (inst name="C2" ) ) (topleft (inst name="C3" ) ) (topright (inst name="C4" ) ) Remove all the offsets from the design and let the tool choose the offsets. Then click the Reload Button

STEP 2: Floorplanning In this design step you need to specify the dimensions of the design core, distance between core and IOs, core utilization, Height/Width Ratio etc. Floorplan Specify Floorplan

Depending on the type of design H/W ratio are specified in this case we have left it as it is. These values are calculated during the design import by the tool. Set margins between Core and IO to 200. The core utilization should not be more than 0.8 (80%). The rest 20% is left for clock buffers and routing. Floorplan Connect Global Nets Select Pin and specify VCC under Pin name, and select Apply all. Specify VCC as Global net and click on Add to list, and the connection will appear on the left hand side of the pane. Select Tie High without changing the other settings and add it to the list. Repeat step two for GND (Tie Low). Click on Apply and check and if no warnings appear close the window. The list should look like exactly the same. Note : In addition to the above , also include the following things: vdd : NET : * VCC:Module() gnd : NET : * GND:Module() in the connection List else we get some connectivity errors

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Before you continue you should save the floorplan by choosing Design Save Floorplan Thereby, it is possible to retrieve the floorplan settings for an eventual redesign.

STEP 3: Power Planning The gates on the core rows and the blocks need to be connected to the IO supply pads. This connection is done by core and block rings that need to be setup during power planning. In this task the physical location and size of the power rings need to be specified. Furthermore, it is recommended to route power stripes above the core rows to assure a sufficient current propagation.

Power Power Planning Add Rings Following form will appear. Assure that the nets GND and VDD are prompted. Input the values shown in the figure.

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Click OK . Next part in Power Planning is to Add power Stripes which distribute power over the core. Power Power Planning Add Stripes Keep the values as in the following form:

Note : 1. Like the selection of horizontal stripes we can select the required number of vertical stripes depending on the design requirement. 2. Use the metal layers for horizontal and vertical stripes differently if not we get metal shorting errors. The following view should appear: Save the design as PP.enc.

STEP 4 : Cell Placement The layout is now ready for cell placement and this can be influenced by information in the constraint file. Place Standard Cells

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The physical location of the registers is known by the tool after cell placement and the clock tree can be synthesized.

Note : The placed cells can be moved from one place to another by using select option from menubar

STEP 5: Clock Tree Synthesis The physical location of the registers is known after cell placement and thus the clock tree can be synthesized. For clock tree synthesis following flow should be followed.

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Timing Design Clock Click on the Gen Spec to specification file.This option selects the gates introduced for clocks. The following window will appear.

Clock Clock Tree Browser Click OK. The cells to be selected are found in the fsm_NL.v i.e the file generated by RTL Compiler. We need to check for every cell listed. Missing even a single type will not generate proper clock. The following window will appear:

Click OK. in the above window. The following window shows the highlighted clock signal routing. Note : Since present design is combinational we dont have clock. But we do so inorder to get external delays . The following figure shows the state before special route.which means that routing to power and ground is not over.

STEP 6: Filler Cells The gaps on the core and IO rows need to be filled with dummy cells referred to as core and IO filler, respectively. Core filler cells ensure the continuity of power/ground rails and N+/P+ wells in the row. Since filler cells will close any gap it is important to perform CTS before filler cell placement. Select Place Filler Add Filler Select

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Note : Instead of using different kinds of filler cells, it is recommended to use few kinds of filler cells that do not match with the metal used in power rings and stripes to avoid metal shorting errors. The following window will appear. Select each type of filler.

STEP 7:Power Routing In this task all connections to VCC and GND will be routed. In particular all pins (block, pad,standard cell) will be connected through the stripes and core/block rings to the power pads. Route Special Route

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Deselect Pad rings & Block Pins since the used technology has already power rails on the IO cells, and start routing be clicking on OK.

This may take some time As can be seen in the following figure the power and gnd pads are connected to the core.

STEP 8: Signal Routing using WRoute After all block and cells are placed and the clock tree is routed the cells on the core rows need to be connected as specified in the netlist. This is accomplished by a routing tool Wroute, which is incorporated into SoCEncounter. Select Route WRoute

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Click OK This step takes time. As is tries to route the blocks without violations. Remember one thing if Wroute take very long them there may be something wrong in the netlist i.e. some nodes may be unconnected. Save the design as Placed.enc. The final view after running WRoute looks as shown below: The following figure shows routing to power and ground as well as routing to standard cells .

STEP 9: Verifcation After the routing job has completed it need to be tested if everything was properly connected in the layout during power- and signal routing. Furthermore, it is necessary to check got antenna violations, which could be due to a long metal wire on a single layer. If it is possible that a charge builds faster than it can be dissipated a large voltage can be developed. If a transistors gate is exposed to this large voltage then it can be destroyed. This is referred to as an antenna violation. On the drop-down menu select Verify Verify Geometry and keep the standard settings. If any geometry violations were discovered white x become visible on the layout. The verifiacation report is generated in csh window. Window below shows Verify Geometry window. Press OK in this window to run verification.

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Probable errors during verification after routing: 1. Spacing errors and overlap/shorting errors. These can be removed by deleting the metal which appears to be white cross marked or in a white block and perform WRoute again. The errors are rectified since the tool uses another metal in that particular place instead of the previous one. 2. Min-cut vioalations also occurs. They can be removed by clicking PowerPower planningedit viaselect the option fix min cut violations. 3. If cross marks appear on the standard cells itself then pick the standard cell using select option in menu and place it in vacant area in the core and WRoute again. If no violations are there the following thing appears in csh window: Verify Geometry report created on Sat Apr 9 14:43:07 2011 Begin Summary ... Cells : 0 SameNet : 0 Wiring : 0 Antenna : 0 Short : 0 Overlap : 0 End Summary

No DRC violations were found Its means DRC is completed. After the above step do metallization by selecting option metal filling from the menu bar. After clicking that option the following figure appears (it takes more time depending on the design)

The above figure shows the metal filling in the vacant spaces in the chip. After the above step is performed we should extract parasitic capacitances which is nothing but R C Extraction. For that do the following: Click Timing -> Analysis Condition -> Specify RC Extraction Mode. Set mode to Detail. Then Click OK. After that click Timing -> Extract RC. Unselect all options and click OK

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Click Timing -> Calculate Delay. Unselect Ideal Clock. Then click OK. SDF will be generated and it will be used in Post-layout simulation. (go to last page of NCVerilog part) By doing the above steps we have extracted the parasitics which is nothing but PEX. A .spef file is also created in our home folder Generate a .DEF file. The procedure is : DesignsaveDEF. Now we should generate .GDS file that contains all the information about the layout. To generate the GDS file: click Design->Save->GDS. Use filename.gds as the output stream file name, leave others as default and click OK. The window below shows the GDS Export window. GDS Filename and Map Filename are where you want to save the respective files.

The exported GDS can be opened with Virtuoso Layout Editor but previously requisite display.drf of target technology need to be placed in Virtuoso directory. Exported GDS looks as shown First create umc folder in your home folder. From there include the tech file of umc90nm create new library in it and select attach to the existing tech file and include 9onm tech file and then open CDS,log. In that open fileimportstream A new window opens Fill the library name ,topcellview name and design library (which you have created that contains umc90nm tech file) .click ok. Now a new dialogue box stating that the loading gds is successful would appear. Click ok. Close cds.log window and open it again. Click fileopen(the library name which u have given that contains umc90nm library tech files)click on the topcell view name

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from the list. You can see many metals and via names present in that list. Click the topcell view name and then the following window would open.

Back Annotation : The back annotation part is performed in the ncverilog by running the SOC generated .v extension file that is present in filename.enc.dat file in SOC folder. Copy that file inti NCVerilog and the test bench chould be appended with following command : $sdf_annotate (filename.v, instance_name of ur test bench, , , MAXIMUM) Declare the above statement in initial begin - end block in the test bench. Run the filename.v , testbench and fsd0k_a_generic_core_21.lib fod0k_b25_t25_generic_io_21.lib The paths are alredy given in page number 17. The corresponding waveforms are given in page number 12 With this step GDS is completed

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