The Electro-migration Modeling The proposed Electro …...Cadence SoC Encounter used as the place-and-route tool. Cadence SoC Encounter DataBase Access commands used for the extraction

The Electro-migration Modeling

The proposed Electro-migration flow

Application of the EM flow to a LEON3-based case study system

Experimental results and discussion

Conclusion and hints for future work

Reduction of interconnect width and thickness with technology scalingUsage of low-k dielectric materials for inter-metal capacitance reduction => high-performanceSaturation of the operating voltage around 1V in current deep sub-micron technologies.Current density of wires increases with scaling => Electro-migration becomes important in nanometer eraReduction of inter-metal spacing and voltage saturation => rise of electric field between wires of the same metal layer => emerging dielectric breakdown issuesNeed for methodologies and tools estimating the impact of Back-End-of-Line (BEOL) reliability mechanisms on system’s performance.

Electro-migration (EM), due to the massive transport of Cu atoms from the wire’s anode to the cathode by the free electrons , leading to the formation of voids => progressive resistance rise of interconnects.

Stress-migration (SM), existing because of possible abrupt changes on the operating temperature, thereby causing tensile stresses on interconnects => increased resistance and inter-metal capacitance.

Time-Dependent Dielectric Breakdown (TDDB), rising because of the enhanced electric field due to the shrinking of inter-metal spacing => gradual dielectric damage.

Introduction

The Electro-migration Modeling





std. cellFF

std. cell

std. cell std. cell FF

FF

Path 1

Path 2

clock period

Path 2 delay

Path 1 delay

slack1

slack2

Timing violation on Path 2 !

•30% increased resistance in the black-colored wire of Path 2 due to EM => Timing violation!

•Path 1 can tolerate more performance degradation due to reliability wear-out mechanisms (EM), compared to Path 2.

•Timing failures due to EM are depend on the operating conditions (Vdd, T) and functionality (current density of wires).

30%R

Introduction

Motivation





Progressive void formation on a copper wire over time due to EM

Current passes through the barrier as void grows progressively due to

migration of Cu atoms

Resistance change of a copper wire over time due to EM

Nor

mal

ized

R

Stress Time (H:M:S)

Past abrupt failures

Future gradual failures

•T = 275 °C •J = 20 mA/μm2

The wire’s void grows a critical value, Lvoid, where the wire’s resistance shows an abrupt step, determined by the equation:

The time (counted at years) at which this step occurs, namely t50, is given as follows:

The resistance slope after t=t50 is computed as follows:

In the above equations, j is the current density, T is the temperature, Ea is the activation energy, K is the Boltzmann constant and n is a constant dependent on the technology (usually n=2).

*( * *(2* )) ( * )

b Custep void

b b

R Lt W t H W H

ρ ρ⎛ ⎞= −⎜ ⎟+⎝ ⎠

50 , 50 ,1 1* * exp( * ( ))

n

stress aop stress

op op stress

j Et tj K T T

⎛ ⎞= −⎜ ⎟⎜ ⎟

⎝ ⎠

, ,1 1* * exp( * ( ))

n

stress aslope op slope stress

op op stress

j ER Rj K T T

⎛ ⎞= −⎜ ⎟⎜ ⎟

⎝ ⎠

Introduction

Motivation

The Electro-migration modeling




The generic reliability analysis flow for the estimation of interconnect reliability phenomenas’ impact on system’s performance over time.

The proposed design flow for the estimation of progressive EM impact on system performance over time.

A typical SoC with the LEON3 SPARC processor. In our case study, another LEON3 core is attached on the AMBA AHB bus.

The 3.5x4.8 mm2 floorplan of the MP-SoC case study with two LEON3 cores, implemented with the Synopsys SAED 90nm standard-cell library.

RTL (VHDL) code of the LEON3 case study system generated automatically by the Gaisler Research tools, in a parameterized style.

Mentor Graphics ModelSim used for the RTL functional simulation.

Synopsys Design Compiler used for synthesis and for the post-layout timing analysis.

Cadence SoC Encounter used as the place-and-route tool.

Cadence SoC Encounter DataBase Access commands used for the extraction of wires from the layout and the computation of the new resistances due to EM, through Tcl scripts.

Perl scipts written for the update of .SPEF files with the new resistances after the EM annotation impact.

Introduction

Motivation

The Electro-migration modeling




Timing constraint (clock period) : 4.5 nsSetup timing slack for the critical path: 0.03 nsThe four timing-critical register-to-register paths are selected (coming through the first processor’s (CPU0) pipeline). Common nets examined in the four selected paths.

Examined path

Initial Delay

Delay with EM annot.

Initial Slack

Slack with EM

Delay overhead

Delay ov. (%)

Critical path 4.32 4.86 0.03 -0.51 0.54 12.5

Path 2 4.26 5.31 0.09 -0.97 1.05 24.64

Path 3 4.21 4.57 0.13 -0.22 0.46 8.55

Path 4 4.15 4.97 0.19 -0.62 0.85 19.75

Table 1. Delay (in ns) of the timing-critical paths of the design, before and after the EM impact annotation.

The annotation of EM impact on the wires of the four paths does not affect their timing uniformly.

The delay overhead at each examined path due to EM is not correlated with their initial timing criticality.

In the presented case study, the initial critical path becomes the third more critical, after the annotation of the EM impact (updated .SPEF).

The difference in delay overhead is due to different wires affected by EM in each path.

The proposed work presents a design flow for the estimation of EM impact on the system’s performance over time.

The presented flow is fully compatible with industrial tool flows, built on automated scripts.

Based on the experiments, also sub-critical paths become timing-critical after the EM impact annotation.

Future work will mainly focus on:

The annotation of temperature variation across the different design units in the current flow.

The selection of paths with nets mostly affected by EM in MP-SoCplatforms.

The integration of vias in the current design flow, along with their corresponding EM model.

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The Electro-migration Modeling The proposed Electro …...Cadence SoC Encounter used as the place-and-route tool. Cadence SoC Encounter DataBase Access commands used for the extraction