Nanometer Design Technology - pudn.comread.pudn.com/downloads128/ebook/544864/CadenceSOCEncounter.pdfDesign SoC Encounter 2.2 SI sign off Analyze SI (CeltIC) Complete SI Solution SI-Aware

CADENCE CONFIDENTIALCADENCE CONFIDENTIAL

Nanometer Design Technology

October 2002

2 CADENCE CONFIDENTIAL

Cadence is the Market Leader

IEEE Corporate Innovation Award Recipient for 2002

1,322Electronic Arts101,430Cadence Design91,492Veritas Software81,504BMC Software72,010Compuware62,048Siebel Systems52,073Peoplesoft44,198Computer Assoc.310,860Oracle225,296Microsoft1

Rev. # Mil.CompanyRank

Market Leader2001 Total Revenue: $1.43B2001 Product Revenue: $830M

Global BusinessNorth America 59%Europe 21%Japan/Asia 20%>58 offices worldwide

Unmatched ResourcesTotal Employees: 5,600Engineers: >3,6002001 R&D investment: ~$300M


What’s Different About Nanometer Design?

Wires dominate digital design

Most ICs will be digital/mixed-signal

SoC verification includes digital, analog, & software

Design-in becoming a major bottleneck








Cadence strategy: deliver the best wires


SI solution: a case study


Delivering The Best WiresContinuous convergence methodology

Full-chip virtual prototypeFundamentally new approach

– No front-end

– No back-end

The prototype is the chip

– Prototype includes detailed wiring

– New full-chip iteration every day

– Always work on highest priority

– Predictable, systematic progress

Performance

Man

ufac

tura

bility

Silicon closure

Wires the first dayand every day


Wires Dominate Manufacturability

• New processes– Copper: 9+ layers and CMP– Subwavelength lithography– Manufacturing rules exploding

• Nanometer requirements– Routing: variable spacing– Routing: variable width– Routing: OPC & PSM

compliant

Copper distortions

Subwavelength distortions

9+ metal levels

Dishing Erosion

100xRC


Wires Dominate Performance

• Wires– 70%+ total delay– Coupling: 50%+ variation– IR drop: 50% variation

• Nanometer requirements– Routing: physics-aware– Delay: calculation w/SI & IR drop– Analysis: correlated to silicon

Wire length (mm)

2x

Grid spacing: 2x

Grid spacing: 1x

1x

Opposite direction

Same direction

1.5 2.5 3.50.5

-40%

0%

40%

80%

120%

Incr

e men

tal d

e lay

-80%

Neighbors switch concurrently

Total delayCu, low k

Gate delay

Total delayAl, SiO2

InterconnectAl, SiO2

Interconnect Cu, low k

0

0.5 0.35 0.25 0.18 0.13 0.10.65

5

10

15

20

25

30

35

Feature size generation, micron

Del

ay, p

s


Wires Dominate Predictability

• Optimization

– >0.18m: logic

– 0.18m – 0.13m: placement

– <0.13m: wires

• Nanometer requirements

– Methodology: wire-centric

– Minimize: time-to-wire

– Minimize: full-chip iteration time

Logic (gates)

Placement

Routing (wires)

≥ 0.25µ 0.18µ - 0.13µ ≤ 90nm


Traditional Linear MethodologyDoes not support nanometer wires

Nanometer wire gap!

Floor planning(Based on Cluster)

Logic synthesis

Physical synthesis(Based on placement)

Power planning

Routing

Physical analysis

Clock tree synthesis

Nm delay iscouplingdependent

Nm delay isroutedependent

Physicalsynthesis view of delay

Nm delay ismetal layerdependent

M8M6M5

Fron

t-end

Back

-end

Firstwires


Full-chip virtual prototype

Continuous ConvergenceThe wire-centric methodology

Fundamentally new approach

– No front-end

– No back-end

The prototype is the chip

– Prototype includes detailed wiring

– New full-chip iteration every day

– Always work on highest priority

– Predictable, systematic progress

Performance

Man

ufac

tura

bility

Silicon closure

Wires the first dayand every day


Cadence Encounter PlatformDelivering the best wires

Complete environment

– First Encounter

– NanoRoute

– Integrated signal integrity

– Complete power solution

Nanometer performance– 10M gates flat

– 50M+ gates hierarchical

Sign-off

“Tape out every day”

Power plan &IR-drop analysis

Partition/floorplan

Trial detailed route

Detailed nm route with signal integrity

Hierarchical clock tree synthesis

Physical synthesis/ placement optimization

150psskew

120ps skew50psskew

50psskew

100psskew

130ps skew

Timing & SI analysis

Otherengines

Logic design


First EncounterWires the first day and every day

Hierarchical partitioning

Full-chip physical prototype

Physicalsynthesis

CellPlace,CTS

TrialRoute

Extract.STA

Signalintegrity

First Encounter UltraTM

RTL / Gates

DVD IC3.5 million gates + 54 macros

Switch IC2.5 million gates + 194 macros

DSP Core700K gates + 25 macros

Network Processor9 million gates

MIPS Core500K gates + 26 macros

Design

6 – 8 weeks

in progress

2 weeks

2 months

1 week

Competitor

2 days

1 day

1 day

½ day

½ day

FE Time*

* Includes: placement, trial route, RC extraction, delay calculations, static timing analysis, timing optimization, and clock tree synthesis

Source: Top-10 semiconductor/ASIC company

Production proven with >250 tapeouts


NanoRouteCreating the best nanometer wires

Nanometer routing– On-the-fly signal integrity

prevention & correction

– Variable spacing routes

– Variable width routes

Nanometer performance

– 7x+ faster than grid-based

– Speed ~linear w/processors

Spee

d &

Cap

acity

Flexibility

80K wiresStructured customTop-level only

1M cellsBest suited for flat≥ 0.13μ

50M+ gatesHierarchical SoCs90nm variable pitch

NanoRoutegraph-basedrouting

Grid-basedrouting

Shape-basedrouting

Production proven with >25 tapeouts


Top View

Grid-based Routing

Variable Metal Pitches: 130nm => 90nm

• Graph-based Router– Dynamic and efficient representation

and searching of routing space

• Grid-based Router– Dense routing grids lead to long

search times or explosion of memory

Side View

M2

M3

M4

M6


Fire

& IC

E Q

XEx

tract

ion

Cadence Analysis SuiteThe most accurate wire analysis available

Nanometer accuracy

– Signoff SI and IR drop

– Delay calculation +/- 2% of SPICE

– Automatic library characterization

– Silicon calibrated accuracy

Nanometer performance– Fully hierarchical

– Multiprocessor support

CeltICSignoff signal integrity

PacifICTransistor-level signal integrity

SeismICHigh-capacity substrate analysis

VoltageStormSignoff IR drop & electromigration

SignalStormSignoff delay calculation w/SI

Production proven with 100s of tapeouts


Encounter Delivers Nanometer PerformanceExample: 1.25M-cell network design

Full-chip iteration with wires < 11hrs– Netlist import 00:12:42

– Full-chip flat placement 07:48:03

– Full-chip flat routing 01:09:56

– Full-chip RC extraction 00:02:11

– Full-chip timing analysis 00:30:43

– Partitioning 00:04:45

– Full-chip power analysis 00:30:00

– Peak memory used 2731.1M

– Workstation (32-bit) Solaris SPARC

Hours instead of days or weeks


Cadence Encounter PlatformIntegration roadmap

SoC Encounter 2002.1

Hierarchical 130nm

• Silicon virtual prototype

• Signal integrityanalysis / repair

• Silicon Ensemble5.4 support


Convergence

• Unified First Encounter UI

• CeltIC fully integrated

• Directly invoke PKS, NanoRoute, wroute, Fire/ICE

• 64-bit Solaris, HPUX


90nm & OpenAccess

• OpenAccess databaseread/write (beta)

• NanoRoute fully integrated

• 50M+ gate capacity

• Entire system on Linux

May 2002 September 2002 December 2002


5-10M gatesDelays basedon wire length

.35μ – .18μ

50M+ gatesDelays based on wire-to-wire couplingVariable metal pitch

Key EDA Technologies:- Hierarchical design - Virtual prototyping - Signal integrity - Power design- Graph-based routing

130nm – 90nm

20042002 2003 2005 2006

70 nm

90 nm

130 nm

180 nm

250 nmProc

ess

Tech

nolo

gy

50 nm

Cadence Encounter PlatformLong-term roadmap

Chips > 100M gatesDelays based on subwavelengthand inductive effects

Key EDA Technologies:- Subwavelength-aware P+R- Design for manufacturability

70nm and below

SiliconEnsembleFamily

EncounterPlatform

EncounterPlatform 70/50

Migration path







Cadence strategy: deliver the best wires


SI solution: a case study


Analyze SI (CeltIC)

Fix routes (NanoRoute)

SI Sign-off Analysis

Timing, SI-aware routingOptimize wires (NanoRoute)

Prevention

Analysis

Repairing

RTL / gates

Tape out

DesignSoC Encounter 2.2

SI sign off

Analyze SI (CeltIC)

Complete SI Solution

SI-Aware Implementation

Prototype Cells and WiresOptimize cells (FE)

Fix cells (FE)


Prevention: Congestion Optimization for CrosstalkReduction

Original placement New placement

CongOpt

Move cells/placementto reduce wire congestionand coupling


Prevention: Slew Balancing to Reduce Crosstalk Glitch & Delay Variations

Delta delay

Upsize!

Downsize!

Avoid too fast and too slow slew ratesSide benefits: Claim back space

Delta delay


Prevention - SI-aware Routing

SI-aware Routing

Increase spacing to reduce coupling capacitance

Soft spacing to reduceparallel wire lengths


SI-aware Routing

Layer switching to reduce coupling capacitance

Net reordering to reduce coupling



* From sign-off verification tools

0

200

400

600

800

# of

Net

s

0.00 0.05 0.10 0.15 0.20 0.25

With SI option

No SI option

Coupling Capacitance (pf)

With SI optionNo SI option

31212Noise Violations*

73428Delay Violations*

NanoRouteOther RoutersOn-the-fly extraction, timing andnoise analysis



SI Analysis - CeltIC

• Detects crosstalk induced failures

• Can prevent chip failures and poor yields

• Automatically creates noise repairs via ECOs to Place and Route – Integrated into SoC-Encounter

and SE-PKS

• Reports 10-100X fewer “false”glitch violations

• Outputs delay changes to STA

CeltIC’s Accuracy

CeltICSPICE


Propagated NoiseAttacker Failure?

clk

d qVictim

CeltIC – Accurate Failure Identification• CeltIC propagates glitches and determines if they will be

rejected by their receiving latches or flip-flops

1

10

100

1,000

10,000

100,000

115K nets.18µm

174K nets.15µm

1.4M nets.15µm

457K nets130nm

532K nets130nm

176

1 1

40 214

401

10,832 9,760 6,500

Competitor

CeltIC

Number of Reported Violations (log scale)


Strategy for Crosstalk Glitch Fixing

• Different possibilities to repair crosstalk victims

– Driver sizing

– Buffer Insertion

– Wide Space Routing

Insert Buffer

Widen Routing Space

Upsize Driver


SI Analysis:Click and Analyze in SoC Encounter

analyze and report browser forvictim/aggressor

highlight inFE window

highlight inFE window







Cadence strategy: deliver the best transistors



0%

10%

20%

30%

40%

50%

60%

70%

80%

1998 1999 2000 2001 2002 2003 2004 2005 2006

Most SoCs Will Be Digital/Mixed-Signal

Transistors Area Effort Re-spins

98%

2%

20%

80%

40%50/50

Digital Analog

Analog’s Impact on Overall DesignSoCs with Digital and Analog

60%


Nanometer Custom Design IssuesIntegrating sensitive circuits with massive digital

Mixed-signal design

– Digital-analog co-verification

– Chip-level integration

Mixed-signal productivity

– Top-down methodology

– Layout, migration, & reuse

Foundry interface– Silicon accurate modeling

– Process technology adoption

– Yield analysis


Delivering The Best TransistorsCadence Custom Design

Custom Block Design

Analog Design Environ.

Spectre & Spectre RF

Virtuoso XL

NeoCellRF FPGA

Analog Memory

I/O

Cells

ProcessDesign Kits

CircuitSurfer

80% of all custom designers use Cadence

Chip-Level Integration

Chip Assembly Router

AMS Designer

Assura DRC/LVS/RCX

OpenAccess Database

Technology Partners• Agilent Technologies• Numerical Technologies• PDF Solutions

FoundryTSMC Chartered UMC


The Cadence DifferenceCadence knows transistors

“Custom design at digital speed”

– 2x-3x faster circuit simulation

– 4x-10x layout productivity

– Most accurate extraction

– Industry standard environment

3.125 QUAD SERDES• Process 0.13μ CMOS• Digital gates 5k • Analog transistors 45k• Clock 1.56GHz• Hierarchy 9 levels• Top-level pins 4000

Who would you trust integrating this into your next SoC?


NetlistPhysical

Electrical SchematicLayout

More…

The Best Wires & The Best TransistorsOpenAccess Database

• Unified data model

• Extensible w/native speed

• Open API and source code

• High capacity & performance

• Independent coalition support

Customertool

Customertool

Customertool

3rd partytool

3rd partytool

3rd partytool Coalition Members

Agere, HP, IBM, Intel, LSI Logic, Mentor Graphics, Motorola, STMicroelectronics

Ope

nAcc

ess

User extensions

Unified database

CadenceEncounter Platform

CadenceCustom IC Environment







Cadence strategy: deliver complete SoC verification



SoC VerificationMassive digital & analog & software

SoCs with Digital and Analog

0

25M

50M

75M

100M

0.25μ 0.18μ 0.13μ 100nm0.35μ

Digital Gate Capacity

0%

20%

40%

60%

80%

1998 2000 2002 2004 2006

Over 70% of silicon re-spins contained functional errors

SoC HW and SW Cost

0%

20%

40%

60%

80%

0.35μ 0.25μ 0.18μ 0.13μ 90nm

HardwareSoftwareHardwareSoftware


Digitalverification

Analog circuitverification

HW-SWco-verification

Full systemverification

Mixed-signalverification

HW-SWmodeling

Algorithmmodeling

Delivering Complete SoC VerificationCadence Functional Verification

Cadence provides a complete, well-integrated solution

Algorithm Simulation(SPW & libraries)

System Simulation(NC-SystemC)

AMS Simulation(AMS Designer)

Circuit Simulation(Spectre & Spectre RF)

Acceleration(Palladium)

Logic Simulation(NC-Sim & VC)

Emulation & Prototyping(Palladium, PCB, & FPGA)


Cadence Functional VerificationNanometer design advancements

Massive digital logic• Transaction-level verification• High capacity and performance• Simulation acceleration support

HW/SW co-verification• >10K times faster than simulation• 128M gate capacity • Easy access: QuickCycles EX & IP cards

Digital/analog• Top-down methodology• Mixed-signal & -language in single kernel• Analog behavioral model abstraction

Acceleration in native simulation environment







Cadence strategy: deliver silicon-package-board co-design



Design-in Becoming a BottleneckEspecially across a design chain

Many nanometer packages will cost more than the silicon

1816

1210

6

201995 1997 1999 2001 2003 2005

8

4

20

14

Uni

ts (b

illion

s)

0.41501801.212002002

1.850901.86001999

1012302.52001996

543103.3661993

250155161990

Ztarget(mÙ)

Current(Amps)

Power(Watts)

Voltage(Volts)

Frequency (MHz)Year

Flip-chip Volume High-performance System Requirements


Silicon-Package-Board Co-design Cadence is the industry standard

Superior high-speed PCB design

– Constraint-driven environment

– Advanced signal analysis

Leading IC package design

– Co-design package with PCB

– Used by all major packaging houses

Industry first chip I/O planner (4Q02)– Co-design chip I/O with package

– Analyze silicon-package-board


Help Your Customers Get to VolumePCB Design Kits

SoCs design-in bottleneck

– 1000s of pins & critical timing

– PCB design takes many months

– Every day is lost volume & profit

PCB design kits

– Complete set of executable models

– Saves months in design

Leaders extending their lead

– Intel processor program

– Xilinx Virtex-II Pro program

Comprehensiveexecutable modelssave design-in time



Most SoCs will be digital/mixed-signal



The Cadence Nanometer Design Strategy

Deliver the best wires

Deliver the best transistors

Deliver complete SoC verification

Deliver silicon-package-board co-design


Documents

Nanometer Design Technology - pudn.comread.pudn.com/downloads128/ebook/544864/CadenceSOCEncounter.pdfDesign SoC Encounter 2.2 SI sign off Analyze SI (CeltIC) Complete SI Solution SI-Aware