Simulation Timing

8/9/2019 Simulation Timing

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Behavioral Simulation:

Step % !enerating the erilog CodeCop the code given in the appendi# into a te#t file and save the files as .v files.

The code includes four modules and a test bench.

Step * +mporting the erilog file to +CFBStart icfb. To start icfb" open a terminal console set the displa to our des$top

using the setenv command and enter icfb, as shown in the Figure *.

Figure * Starting icfb

nce ou boot up the icfb" in the C+ go File +mport erilog to get to the windowin Figure /. 0ighlight verilog file ou want to import in the 1file filter name2 which in

our case is m design.v and the name of the target librar which in this is 1new*2. 0it theadd button in the 1verilog files to import2 which will automaticall fill in the path to theverilog file ou highlighted. 3ow clic$ 4 to import the file.


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Figure / indow for the verilog file to import

5our log window will loo$ li$e this.


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Figure 6 7og File generated while importing the verilog file

Figure 8 9odule imported to icfb

Figure 8 shows the module after ou import the verilog files.

Step / Starting Sim isionnce ou have imported the verilog files to icfb ou are read to run the

simulation in erilog :7. For doing this" first of all" close icfb as well as all the other open windows.


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Then in the terminal console t pe in 1verilog ;gui m design.v2 as shown in theFigure < which would start up Sim ision where ou can simulate our verilog code

Figure < Starting Sim ision

Step 6 Setting up the SimulationThe Sim ision windows is shown in Figure =. &ouble clic$ on 1tb>design2" seen

on the left side in the window" to displa all the input and outputs of the design as shownin Figure =.

Figure = Sim ision indow


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Then in the Sim ision window go Select Signal and hit the waveform buttonwhich is the button inside the red circle on top right side of the window as shown inFigure ?.

Figure ? aveform !eneration

' new waveform window should appear as which should loo$ li$e Figure @.

Figure @ aveform generation in Sim ision

The ne#t step is to hit the button Simulation Aeinvo$e Simulation in thewaveform window. pon doing that ou should have some new buttons added to the

waveform window as shown in Figure % .

Figure % 3ew Buttons added to the aveform window


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3ow to simulate the circuit hit the 1pla 2 button which is circled in Figure % .5ou should get the behavioral simulation result of the circuit as shown in Figure %%.

Figure %% Behavioral Simulation of the &igital Circuit

This concludes the behavioral simulation of the circuit.

unction SimulationFunctional simulation li$e behavioral simulation also ignores timing but it

includes dela of the bloc$s included in the design" which can be set to fi#ed valuethrough the verilog code. e add a dela of % unit in the flip-flop as shown in Figure %*.

Figure %* 'dding dela in the Flip-Flop circuit


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Save the verilog file after adding the dela to it. 3ow simulate the code again the b following the Step / , 6 of the behavioral simulation. 5our output should loo$ li$eFigure %/.

Figure %/ Simulation with &ela added

's seen in Figure %/ the simulation fails if the dela is % time units because thedela is larger than the cloc$ period which is ? time units.

Static Time AnalysisStatic timing anal sis is the anal sis of logic in a static manner" computing the

dela times for each path. +t does not reDuire the creation of a set of test (or stimulus)vectors (an enormous Eob for a large circuits). Timing anal sis wor$s best withs nchronous s stems whose ma#imum operating freDuenc is determined b the longest

path dela between successive flip-flops. The path with the longest dela is the critical!ath .

e use build gates for the s nthesis of our design. Before loading the verilog filein the build gates be sure to delete the test bench module from the design as it cannot bes nthesi ed. e save the new verilog file without the test bench as m design%.v. 'lso toma$e things a little simpler we created a new folder 1s nthesis2 and placed the verilogfile in that director . From now on we ma$e 1s nthesis2 our wor$ing director . Thevarious steps involved in the s nthesis and timing anal sis are listed below.


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Step % Starting Build !atesTo start Build !ates t pe 1bg>shell Gp$s Ggui2 in the terminal console as shown

in the Figure %6.

Figure %6 Starting Build !ates

The ! + for build gates is shown in Figure %8.

Figure %8 Build !ates ! +


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Step * 7oading erilog Files and !enerating the Schematic 3ow ou can load the verilog file in build gates. To do this go File pen.

Choose verilog in the options appearing on the right side of the window which willdispla all the verilog files in the director as shown in Figure %


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'fter loading the verilog file ou can s nthesi e it b using Command Build !eneric.pon doing this ou should have a schematic as shown in the Figure %?.

Figure %? Schematic !enerated b Build !ates

Step / !enerating Timing AeportFor generating the timing report we use .tcl files. ' file timing.tcl is used to set

timing constraints on the design. 'nother file report.tcl generates the timing and areareport as well as the netlist for the schematic. Both the files are given in the appendi#.5ou should save both these files in our wor$ing director with our verilog code.

To source the timing.tcl file t pe 1source timing.tcl2 in the command window atthe bottom in the Build !ates ! +. Then run it using the command 1timing2. 'fter running the timing.tcl file source the report.tcl file and run it the same wa . 5our windowshould loo$ li$e Figure %@.


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Figure %@ Sourcing and Aunning tcl Files.

nce ou run the report.tcl file" ou should have two new folders (1netlist2 ,1report2) created automaticall in our wor$ing director . The report director containsthe timing" area and hierarch report. 5our timing report should loo$ similar to Figure * .

's seen from the Figure * the design fails the timing test. 5ou can improve thetiming performance of our circuit either b rela#ing the timing constraints (in case of this design simpl increasing the period of the cloc$) stated in our timing.tcl or boptimi ing the circuit using build gate to reduce the dela .


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Figure * Timing Aeport

Step 6 ptimi ing the &esign to +mprove the Timing HerformanceTo optimi e the circuit ou need to first set the target technolog . 5ou can do this

b going command set target technolog . 5ou will get a window as shown in Figure*%.


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'fter optimi ing the circuit generate the report again b running the timing.tcl fileand report.tcl file. The report should show a reduction in the dela of the critical path.ur timing report is shown in Figure */. 's can be seen in the report we increased thecloc$ period to 8 and also due to optimi ation there is some improvement in the dela

over the dela obtained in the unoptimi ed circuit. 5ou can improve optimi ation btr ing different target technologies and tr ing different setting for optimi ation.

Figure */ Timing Aeport for optimi ed circuit.

Logical or Gate Level Simulation7ogic simulation or gate-level simulation is used to chec$ the timing performance

of an 'S+C. 7ogic gate or logic cell (3'3&" 3 A" and so on) is treated as a blac$ bo#modeled b a function whose variables are the input signals. Setting all the dela s to unit

value is the eDuivalent of functional simulation.For logic simulation save the generated netlist for the s nthesi ed circuit as a

verilog file. +f the s nthesis is done correctl the circuit should be at the gate level. Thensimulate the verilog code b following the steps listed in the behavioral simulation at the

beginning of this tutorial. +f ou do not have correct libraries or the are not lin$edcorrectl ou will get an error that some modules could not be found.


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A!!endi"

#ydesign$v

II Stimulus form >design

module tb>m designJ II Test Bench 9odulereg b pass " b pass%" module>cloc$" rst" a" b" cin" selJwire out>sum"out>coutJ

m >design (b pass " b pass%" module>cloc$" rst" a" b" cin" sel" out>sum"out>cout)J II Calls m >design module

initial begin module>cloc$K J II initial settings rstK J aK J

bK J cinK J selK%J b pass K J b pass%K J

L? aK%J II test pattern L? bK%J L? cinK%J L? aK J L? rstK%J

L? b pass K%J L? b pass%K%J L? selK J L% MfinishJ

end

alwa s begin II cloc$ setupL6 module>cloc$KNmodule>cloc$J

end

endmodule


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alwa s R(posedge cl$) beginif(rst)D K Jelse

D K dJendendmodule

Timing$tcl

proc timing L &efining an ideal cloc$ L UUUUUUUUUUUUUUUUUUL -waveform leading>edge trailing>edge

L -period the value of the periodL Videal>cloc$V is the name of the cloc$ L -cloc$ specifies the name of the ideal cloc$ L -pos the positive edge of the ideal cloc$ L -neg the negative edge of the ideal cloc$ L UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUset>cloc$ ideal>cloc$ -waveform 6 -period %set>cloc$>root -cloc$ ideal>cloc$ -pos module>cloc$ L Source all>inputsL UUUUUUUUUUUUUU

proc all>inputs find -port -input -nocloc$s VUVL Source all>outputsL UUUUUUUUUUUUUUU

proc all>outputs find -port -output VUVL &efining the set-up and hold times for all input(s) with respect to ideal>cloc$ L -earl refers to a set-up time value for our input(s)L -late refers to a hold-time value for our input(s)L UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUset>input>dela -cloc$ ideal>cloc$ -earl .% Wall>inputsXset>input>dela -cloc$ ideal>cloc$ -late .* Wall>inputsXL &efining the set-up time for the ne#t moduleYs input portsset>e#ternal>dela . -cloc$ ideal>cloc$ Wall>outputsXL &efining the drive (output) resistance of our input(s)set>drive>resistance Wall>inputsXII Stimulus form >designmodule tb>m designJ II Test Bench 9odulereg b pass " b pass%" module>cloc$" rst" a" b" cin" selJwire out>sum"out>coutJ

m >design (b pass " b pass%" module>cloc$" rst" a" b" cin" sel" out>sum"


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%e!ort$tcl proc report m$dir reportm$dir netlistreport>timing Z reportItiming.rpt

report>area -hier -cell Z reportIarea.rptreport>hierarch Z reportIhierarch .rptwrite>verilog -hier netlistIm >design.net


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%e&erences

%) Bindal" 'hmed" 1S nthesis and Timing erification Tutorial2" Computer [ngineering&epartment" San \ose State niversithttp IIvlsicad.ucsd.eduIcoursesIece*< b-w 6I7ab%IB!Tutorial.pdf

*) http IIwww-ee.eng.hawaii.eduI]msmithI'S+CsI0T97IBoo$IC0%/IC0%/.htm
http://vlsicad.ucsd.edu/courses/ece260b-w04/Lab1/BGTutorial.pdfhttp://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH13/CH13.htmhttp://vlsicad.ucsd.edu/courses/ece260b-w04/Lab1/BGTutorial.pdfhttp://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH13/CH13.htm

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Simulation Timing