George Mason University ECE 545 – Introduction to VHDL Timing Event-driven simulation ECE 545 Lecture 8

ECE 545 – Introduction to VHDL George Mason University

TimingEvent-driven simulation

ECE 545Lecture 8

ECE 545 – Introduction to VHDL 2

Sources• A. Deway, Analysis and Design of Digital

Systems with VHDL,

Chapters 15, VHDL Technology• M. Abramovici, M. Breuer, A. Friedman

Chapter 3.10, Gate-Level Event Driven Simulation

• P. Ashenden, The Designer’s Guide to VHDL,

Chapter 5.3 Signal Attributes Delta Delays Transport and Inertial Delay Mechanisms


Timing of digital circuits


Timing Characteristics of Combinational Circuits

• Combinational Circuits Are Characterized by Propagation Delays• through logic components (gates, LUTs)• through interconnects (routing delays)

tp LUT tp routing

LUT LUT LUT

Total propagation delay through combinational logic


Timing Characteristics of Combinational Circuits (2)

• Total Propagation Delay of Logic Depends on the Number of Logic Levels and Delays of Logic Components• Number of logic levels is the number of

logic components (gates, LUTs) the signal propagates through

• Routing Delays Depend on:• Length of interconnects• Fanout



• Fanout – Number of Inputs Connected to One Output• Each inputs has its capacitance• Fast switching of outputs with high fanout

requires higher currents and strong drivers

LUT LUT

LUT

LUT



• In Current Technologies Routing Delays Make 50-70% of the Total Propagation Delays


Timing Characteristics of Sequential Circuits (1)

• Timing Features of Flip-flops• Setup time tS – minimum time the input has

to be stable before the rising edge of the clock

• Hold time tH – minimum time the input has to be stable after the rising edge of the clock

• Propagation delay tP – time to propagate input to output after the rising edge of the clock


Timing Characteristics of Sequential Circuits (2)

D Q

clk

clk

D

Q

tS tH

tP

Input D must remain

stable during

this interval

Input D can freely

change during

this interval


Critical Path (1)

• Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers

D Qin

clk

D Qout

tP logic

tCritical = tP FF + tP logic + tS FF


Critical Path (2)

• Min. Clock Period = Length of The Critical Path

• Max. Clock Frequency = 1 / Min. Clock Period


Clock Jitter

• Rising Edge of The Clock Does Not Occur Precisely Periodically• May cause faults in the circuit

clk


Clock Skew

• Rising Edge of the Clock Does Not Arrive at Clock Inputs of All Flip-flops at The Same Time

D Qin

clk

D Qout

delay

D Qin

clk

D Qout

delay


Dealing With Clock Problems

• Use Only Dedicated Clock Nets for Clock Signals

• Do Not Put Any Logic in Clock Nets


Specifying time in VHDL


Physical data types

Types representing physical quantities, such as time, voltage, capacitance, etc. are referred in VHDL as physical data types.

TIME is the only predefined physical data type.

Value of the physical data type is called a physical literal.


Time values (physical literals) - Examples

7 ns

1 min

min

10.65 us

10.65 fs

Unit of time

(dimension)

SpaceNumeric value


TIME values

Numeric value can be an integer or

a floating point number.

Numeric value is optional. If not given, 1 is

implied.

Numeric value and dimension MUST be

separated by a space.


Units of time

Unit Definition

Base Unit

fs femtoseconds (10-15 seconds)

Derived Units

ps picoseconds (10-12 seconds)

ns nanoseconds (10-9 seconds)

us microseconds (10-6 seconds)

ms miliseconds (10-3 seconds)

sec seconds

min minutes (60 seconds)

hr hours (3600 seconds)


Values of the type TIME

Value of a physical literal is defined in terms

of integral multiples of the base unit, e.g.

10.65 us = 10,650,000,000 fs

10.65 fs = 10 fs

Smallest available resolution in VHDL is 1 fs.

Smallest available resolution in simulation can be

set using a simulator command or parameter.


Arithmetic operations on values of the type TIME

Examples:

7 ns + 10 ns = 17 ns

1.2 ns – 12.6 ps = 1187400 fs

5 ns * 4.3 = 21.5 ns

20 ns / 5ns = 4


Propagation delay in VHDL


Propagation delay in VHDL - Example

entity MAJORITY isport (A_IN, B_IN, C_IN : in STD_LOGIC; Z_OUT : out STD_LOGIC);end MAJORITY;

architecture DATA_FLOW of MAJORITY isbeginZ_OUT <= (not A_IN and B_IN and C_IN) or

(A_IN and not B_IN and C_IN) or(A_IN and B_IN and not C_IN) or(A_IN and B_IN and C_IN) after 20 ns;

end DATA_FLOW;


Propagation delay - Example


MLU: Block Diagram

B

A

NEG_A

NEG_B

IN0

IN1

IN2

IN3 OUTPUT

SEL1

SEL0

MUX_4_1

L0L1

NEG_Y

Y

Y1

A1

B1

MUX_0

MUX_1

MUX_2

MUX_3


MLU - Architecture Body – Example 1begin

A1<= not A after 6 ns when (NEG_A='1') elseA after 5 ns;

B1<= not B after 6 ns when (NEG_B='1') else B after 5 ns;

Y <= not Y1 after 6 ns when (NEG_Y='1') elseY1 after 5 ns;

MUX_0 <= A1 and B1 after 3 ns;MUX_1 <= A1 or B1 after 3 ns;MUX_2 <= A1 xor B1 after 4 ns;MUX_3 <= A1 xnor B1 after 5 ns;

L<=L1 & L0;

with (L) select Y1 <= MUX_0 after 7 ns when "00",

MUX_1 after 6 ns when "01", MUX_2 after 8 ns when "10",

MUX_3 after 7 ns when others;

end MLU_DATAFLOW;


MLU - Architecture Body – Example 2begin

A1<= not A after MUX2_delay when (NEG_A='1') elseA after MUX_2_delay;

B1<= not B after MUX2_delay when (NEG_B='1') else B after MUX2_delay;

Y <= not Y1 after MUX2_delay when (NEG_Y='1') elseY1 after MUX2_delay;

MUX_0 <= A1 and B1 after GATE_delay;MUX_1 <= A1 or B1 after GATE_delay;MUX_2 <= A1 xor B1 after XOR_delay;MUX_3 <= A1 xnor B1 after XOR_delay;

L<=L1 & L0;

with (L) select Y1 <= MUX_0 after MUX4_delay when "00",

MUX_1 after MUX4_delay when "01", MUX_2 after MUX4_delay when "10",

MUX_3 after MUX4_delay when others;

end MLU_DATAFLOW;


Delay constants

constant MUX2_delay: time := 5 ns;

constant GATE_delay : time := 3 ns;

constant XOR_delay : time := 4 ns;

constant MUX4_delay: time := 7 ns;

Can be defined in the declarative portion

of the architecture or in the package


Inertial delay model


Inertial delay model

Short pulses (spikes) are not passed to the

outputs of logic gates due to the inertia of

physical systems.

Logic gates behave like low pass filters and

effectively filter out high frequency input

changes as if they never occurred.


Inertial delay model - Example

SIG_OUT <= not SIG_IN after 7 ns


VHDL-87 Inertial delay model

Any input signal change that does not persist

for at least a propagation delay of the device

is not reflected at the output.

inertial delay (pulse rejection limit) = propagation delay


VHDL-93 Enhanced inertial delay model

VHDL-93 allows the inertial delay model to be declaredexplicitly as well as implicitly.

Explicitly:Z_OUT <= inertial (not A_IN and B_IN and C_IN) or


Implicitly:Z_OUT <= (not A_IN and B_IN and C_IN) or



VHDL-93 Enhanced inertial delay model

VHDL-93 allows inertial delay, also called

a pulse rejection limit, to be different from the

propagation delay.

SIG_OUT <= reject 5 ns inertial not SIG_IN after 7 ns;


Transport delay model

With a transport delay model, all input signal

changes are reflected at the output, regardless of

how long the signal changes persist.

Transport delay model must be declared explicitly using the

keyword transport.

Inertial delay model is a default delay model because it

reflects better the actual behavior of logic components.

Transport delay model is used for high-level modeling.


Transport delay model - Example

SIG_OUT <= transport not SIG_IN after 7 ns


Other delay models

Rise and Fall delays

- a different delay for a transition 0→1

and a transition 1→0


Event-driven simulation


Event list as a linked list structure

time

signalnew value

List of events scheduled

to occur at time tq


Event list as an array – Timing wheel

time

signalnew value

List of events scheduled

to occur at time tc


Notation

(i, vi’) – an entry of the event list associated with the time t indicating that at the time t the value of signal i is scheduled to be set to vi’

v(i) – current value at the output of gate i

d(i) – nominal delay of gate i


Top-level algorithm

while (event list not empty)

begin

t = next time in list

process entries for time t

end


Process entries for time t - Basic version

Activated = Ø /* set of activated gates = empty set */

For every entry (i, vi’) pending at the current time t if vi’ ≠ v(i) then

begin /* it is indeed an event */v(i) = vi’ /* update value of signal i */for every j on the fanout list of i

beginupdate input values of jadd j to Activated

endend

For every j Activatedbegin

vj’ = evaluate(j)schedule (j, vj’) for time t+d(j)

end


Event-driven simulation - example

(z, 1)

8 10 12

(z, 0) (z, 0)

time


Notation

lsv(j) – last scheduled value of j

lst(j) – last scheduled time of j = time of the last event scheduled for signal j


Process entries for time t – True events only version – Two-pass algorithm

Activated = Ø /* set of activated gates = empty set */

For every entry (i, vi’) pending at the current time t if vi’ ≠ v(i) then

begin /* it is indeed an event */v(i) = vi’ /* update value of signal i */for every j on the fanout list of i

beginupdate input values of jadd j to Activated

endend

For every j Activatedbegin

vj’ = evaluate(j)if vj’ ≠ lsv(j) then

beginschedule (j, vj’) for time t+d(j)lsv(j) = vj’

end end


Process entries for time t – True events only version – One-pass algorithm

For every entry (i, vi’) pending at the current time t begin

for every j on the fanout list of ibegin

update input values of jvj’ = evaluate(j)if vj’ ≠ lsv(j) then

begint’ = t + d(j)if t’ = lst(j) then cancel event (j, lsv(j)) at time t’schedule (j, vj’) for time t’lsv(j) = vj’ lst(j) = t’

endend

end


Delta delay


Delta delay

A propagation delay of 0 time units is

equivalent to omitting the after clause and is

called a delta delay.

Used for functional simulation.


Two-dimensional aspect of time


Top-level algorithm

while (event list not empty)

begin

t = next time in list

process entries for time t

end

If next time in list

= previous time

then the previous

iteration of the

loop has advanced

time by one

delta delay


Transactions vs. Events


Transaction vs. Event

T5 = T1+20 ns

Z_OUT transactions

Z_OUT events

(‘0’, T1 + 20 ns) (‘1’, T2 + 20 ns) (‘0’, T3 + 20 ns)

(‘1’, T2 + 20 ns) (‘0’, T3 + 20 ns)


Properties of signals

Signals represent a time-ordered list of valuesdenoting past, present and future values.

This time history of a signal is called a waveform.

A value/time pair (v, t) is called a transaction.

If a transaction changes value of a signal, it iscalled an event.


Signal Attributes


Signal attributes (1)

S’transaction - a signal of type bit that changes value from ‘0’ to ‘1’ or vice versa each time there is a transaction on S.

S’event - True if there is an event on S in the current simulation cycle, false otherwise.

S’active – True if there is a transaction on S in a given simulation cycle, false otherwise.



S’last_event - The time interval since the last event on S.

S’last_active - The time interval since the last transaction on S.

S’last_value – The value of S just before the last event on S.



S’delayed(T) - A signal that takes on the same value as S, but is delayed by time T.

S’stable(T) - A Boolean signal that is true if there has been no event on S in the time interval T up to the current time, otherwise false.

S’quiet(T) – A Boolean signal that is true if there has been no transaction on S in the time interval T up to the current time, otherwise false.


Detecting setup time violation

if clk’event and clk=‘1’ then

assert d’last_event >= setup_time

report “Setup time violation”


Timing simulation after synthesis


Synthesis process

• Simulation before synthesis is used to verify circuit functionality and may differ from the one after synthesis

• Synthesis tool generates SDF (Standard Delay Format) as a standard delay file and the netlist for synthesized VHDL code with delays.• Generated netlist contains many

component instantiation statements with library references


SDF file

( DELAYFILE ( CELL( CELLTYPE “XOR”) ( INSTANCE U34.Z_VTX) ( DELAY( INCREMENT ( DEVICE 01 (0.385090:0.385090:0.3850900.385090:0.385090:0.385090)(0.235177: 0.235177: 0.235177) ) ) ) )

A part of the SDF file is shown below.It indicates XOR gate delays (low to high, high to low) of minimum, typical and worst case timing


Netlist from the synthesis tool

library IEEE;library TC200G;use IEEE.std_logic_1164.all;use TC200G.components.all;entity CONSYN is port( RSTn, CLK, D0, D1, D2, D3, D4, D5, D6, D7 : in std_logic; FF_OUT, COMB_OUT, FF_COMB_OUT : out std_logic);end CONSYN;architecture structural of CONSYN issignal XOR8, FF, n70, n71, n72, n73, n74, n75, n76, n67, n68, n69 : std_logic;begin FF_OUT <= FF; COMB_OUT <= XOR8;FF_reg : FD2 port map( Q => FF, QN => n75, D => XOR8, CP => CLK, CD => RSTn) ;

U30 : MUX21L port map( Z => n71, A => n67, B => n68, S => n69);

U31 : EN port map( Z => n67, A => D1, B => D0); U32 : IV port map( Z => n68, A => n67); U33 : EOP port map( Z => n69, A => D6, B => D7); U34 : EO3 port map( Z => n70, A => D3, B => D2,

C => D4); U35 : EO port map( Z => n72, A => D5, B => n70); U36 : EOP port map( Z => XOR8, A => n72,

B => n71); U37 : FA1A port map( S => n73, CO => n76, CI => D3,

A => D2, B => FF); U38 : EO3 port map( Z => n74, A => n68, B => n73,

C => D4); U39 : EOP port map( Z => FF_COMB_OUT, A => D5,

B => n74);end structural;

Documents

George Mason University ECE 545 – Introduction to VHDL Timing Event-driven simulation ECE 545 Lecture 8