Sachin ShindeXiaolai He

Simulation and Timing Analysis in Cadence Using Verilog XL and Build Gates

Aim:The aim of this tutorial is to demonstrate the procedure for using Cadence for

different level of simulation of a digital design starting from the top behavioral simulation going down to the gate level. The list of simulations shown below is ordered from high-level to low-level simulation (high-level being more abstract and low-level being more detailed).

• Behavioral simulation • Functional simulation • Static timing analysis • Gate-level simulation • Switch-level simulation • Transistor-level or circuit-level simulation

Starting from high-level to low-level simulation, the simulations become more accurate, but they also become progressively more complex and take longer to run.

Circuit:

Figure 1 The Digital Circuit used for SimulationNote: All the verilog modules associated with the design in Figure 1 as well as the test bench used for simulation are given in the appendix.

Behavioral Simulation:

Step 1: Generating the Verilog CodeCopy the code given in the appendix into a text file and save the files as .v files.

The code includes four modules and a test bench.

Step 2: Importing the Verilog file to ICFBStart icfb. To start icfb, open a terminal console set the display to your desktop

using the setenv command and enter icfb& as shown in the Figure 2.

Figure 2 Starting icfb

Once you boot up the icfb, in the CIW go File Import Verilog to get to the window in Figure 3. Highlight verilog file you want to import in the “file filter name” which in our case is mydesign.v and the name of the target library which in this is “new2”. Hit the add button in the “verilog files to import” which will automatically fill in the path to the verilog file you highlighted. Now click OK to import the file.

Figure 3 Window for the verilog file to import

Your log window will look like this.

Figure 4 Log File generated while importing the verilog file

Figure 5 Module imported to icfb

Figure 5 shows the module after you import the verilog files.

Step 3 Starting SimVisionOnce you have imported the verilog files to icfb you are ready to run the

simulation in Verilog XL. For doing this, first of all, close icfb as well as all the other open windows.

Then in the terminal console type in “verilog +gui mydesign.v” as shown in the Figure 6 which would start up SimVision where you can simulate your verilog code

Figure 6 Starting SimVision

Step 4 Setting up the SimulationThe SimVision windows is shown in Figure 7. Double click on “tb_design”, seen

on the left side in the window, to display all the input and outputs of the design as shown in Figure 7.

Figure 7 SimVision Window

Then in the SimVision window go Select Signal and hit the waveform button which is the button inside the red circle on top right side of the window as shown in Figure 8.

Figure 8 Waveform Generation

A new waveform window should appear as which should look like Figure 9.

Figure 9 Waveform generation in SimVision

The next step is to hit the button Simulation Reinvoke Simulation in the waveform window. Upon doing that you should have some new buttons added to the waveform window as shown in Figure 10.

Figure 10 New Buttons added to the Waveform window

Now to simulate the circuit hit the “play” button which is circled in Figure 10. You should get the behavioral simulation result of the circuit as shown in Figure 11.

Figure 11 Behavioral Simulation of the Digital Circuit

This concludes the behavioral simulation of the circuit.

Function SimulationFunctional simulation like behavioral simulation also ignores timing but it

includes delay of the blocks included in the design, which can be set to fixed value through the verilog code. We add a delay of 10 unit in the flip-flop as shown in Figure 12.

Figure 12 Adding delay in the Flip-Flop circuit

Save the verilog file after adding the delay to it. Now simulate the code again the by following the Step 3 & 4 of the behavioral simulation. Your output should look like Figure 13.

Figure 13 Simulation with Delay added

As seen in Figure 13 the simulation fails if the delay is 10 time units because the delay is larger than the clock period which is 8 time units.

Static Time Analysis Static timing analysis is the analysis of logic in a static manner, computing the

delay times for each path. It does not require the creation of a set of test (or stimulus) vectors (an enormous job for a large circuits). Timing analysis works best with synchronous systems whose maximum operating frequency is determined by the longest path delay between successive flip-flops. The path with the longest delay is the critical path.

We use build gates for the synthesis of our design. Before loading the verilog file in the build gates be sure to delete the test bench module from the design as it cannot be synthesized. We save the new verilog file without the test bench as mydesign1.v. Also to make things a little simpler we created a new folder “synthesis” and placed the verilog file in that directory. From now on we make “synthesis” our working directory. The various steps involved in the synthesis and timing analysis are listed below.

Step 1: Starting Build Gates To start Build Gates type “bg_shell –pks –gui” in the terminal console as shown

in the Figure 14.

Figure 14 Starting Build Gates

The GUI for build gates is shown in Figure 15.

Figure 15 Build Gates GUI

Step 2 Loading Verilog Files and Generating the Schematic Now you can load the verilog file in build gates. To do this go FileOpen.

Choose verilog in the options appearing on the right side of the window which will display all the verilog files in the directory as shown in Figure 16.

Figure 16 Loading the Verilog Files

On loading the file you will see a screen like shown in Figure 17.

Figure 17 Verilog File Loaded

After loading the verilog file you can synthesize it by using Command Build Generic. Upon doing this you should have a schematic as shown in the Figure 18.

Figure 18 Schematic Generated by Build Gates

Step 3 Generating Timing Report For generating the timing report we use .tcl files. A file timing.tcl is used to set

timing constraints on the design. Another file report.tcl generates the timing and area report as well as the netlist for the schematic. Both the files are given in the appendix. You should save both these files in your working directory with your verilog code.

To source the timing.tcl file type “source timing.tcl” in the command window at the bottom in the Build Gates GUI. Then run it using the command “timing”. After running the timing.tcl file source the report.tcl file and run it the same way. Your window should look like Figure 19.

Figure 19 Sourcing and Running tcl Files.

Once you run the report.tcl file, you should have two new folders (“netlist” & “report”) created automatically in your working directory. The report directory contains the timing, area and hierarchy report. Your timing report should look similar to Figure 20.

As seen from the Figure 20 the design fails the timing test. You can improve the timing performance of your circuit either by relaxing the timing constraints (in case of this design simply increasing the period of the clock) stated in your timing.tcl or by optimizing the circuit using build gate to reduce the delay.

Figure 20 Timing Report

Step 4 Optimizing the Design to Improve the Timing PerformanceTo optimize the circuit you need to first set the target technology. You can do this

by going command set target technology. You will get a window as shown in Figure 21.

Figure 21 Setting Target Technology

In this case we choose ambit_xatl. After choosing the technology file you optimize the circuit by going command

optimize. Our selection for the various parameters is shown in Figure 22.

Figure 22 Setting Optimization Parameters

After optimizing the circuit generate the report again by running the timing.tcl file and report.tcl file. The report should show a reduction in the delay of the critical path. Our timing report is shown in Figure 23. As can be seen in the report we increased the clock period to 50 and also due to optimization there is some improvement in the delay over the delay obtained in the unoptimized circuit. You can improve optimization by trying different target technologies and trying different setting for optimization.

Figure 23 Timing Report for optimized circuit.

Logical or Gate Level SimulationLogic simulation or gate-level simulation is used to check the timing performance

of an ASIC. Logic gate or logic cell (NAND, NOR, and so on) is treated as a black box modeled by a function whose variables are the input signals. Setting all the delays to unit value is the equivalent of functional simulation.

For logic simulation save the generated netlist for the synthesized circuit as a verilog file. If the synthesis is done correctly the circuit should be at the gate level. Then simulate the verilog code by following the steps listed in the behavioral simulation at the beginning of this tutorial. If you do not have correct libraries or they are not linked correctly you will get an error that some modules could not be found.

Appendix

Mydesign.v

// Stimulus formy_designmodule tb_mydesign; // Test Bench Modulereg bypass0, bypass1, module_clock, rst, a, b, cin, sel; wire out_sum,out_cout;

my_design (bypass0, bypass1, module_clock, rst, a, b, cin, sel, out_sum,out_cout); // Calls my_design module

initial begin module_clock=0; // initial settings rst=0; a=0; b=0; cin=0; sel=1; bypass0=0; bypass1=0;

#8 a=1; // test pattern #8 b=1; #8 cin=1; #8 a=0; #8 rst=1; #8 bypass0=1; #8 bypass1=1; #8 sel=0; #10 $finish; end always begin // clock setup

#4 module_clock=!module_clock; end endmodule

// Module my_design

module my_design (bypass0, bypass1, module_clock, rst, a, b, cin, sel, out_sum,out_cout);input bypass0, bypass1, module_clock, rst, a, b, cin, sel;output out_sum, out_cout;wire wbypass0, wbypass1, wa, wb, wcin, wsel, wout_sum, wout_cout;ff ff1 (.clk(module_clock), .rst(rst), .d(bypass0), .q(wbypass0));ff ff2 (.clk(module_clock), .rst(rst), .d(bypass1), .q(wbypass1));ff ff3 (.clk(module_clock), .rst(rst), .d(a), .q(wa));ff ff4 (.clk(module_clock), .rst(rst), .d(b), .q(wb));ff ff5 (.clk(module_clock), .rst(rst), .d(cin), .q(wcin));ff ff6 (.clk(module_clock), .rst(rst), .d(sel), .q(wsel));ff ff7 (.clk(module_clock), .rst(rst), .d(wout_sum), .q(out_sum));ff ff8 (.clk(module_clock), .rst(rst), .d(wout_cout), .q(out_cout));full_adder fa (.a(wa), .b(wb), .cin(wcin), .sum(wsum), .cout(wcout));mux mx0 ( .a(wbypass0), .b(wsum), .sel(wsel), .out(wout_sum));mux mx1 ( .a(wbypass1), .b(wcout), .sel(wsel), .out(wout_cout));endmodule

//Module mux.v

module mux ( a, b, sel, out);input a, b, sel;output out;wire out = sel ? a : b;endmodule

//Module Full_adder

module full_adder (a, b, cin, sum, cout);input a, b, cin;output sum, cout;wire cout = (a & b) | (cin & (a | b));wire sum = a ^ b ^ cin;endmodule

//Module Flip Flop

module ff (clk, rst, d, q);input clk, rst, d;output q;reg q;

always @(posedge clk)beginif(rst)q = 0;elseq = d;endendmodule

Timing.tcl

proc timing { } {# Defining an ideal clock# ******************# -waveform {leading_edge trailing_edge}# -period: the value of the period# "ideal_clock" is the name of the clock# -clock: specifies the name of the ideal clock# -pos: the positive edge of the ideal clock# -neg: the negative edge of the ideal clock# *********************************set_clock ideal_clock -waveform {0 4} -period 10set_clock_root -clock ideal_clock -pos module_clock# Source all_inputs# **************proc all_inputs {} {find -port -input -noclocks "*"}# Source all_outputs# ***************proc all_outputs {} {find -port -output "*"}# Defining the set-up and hold times for all input(s) with respect to ideal_clock# -early refers to a set-up time value for your input(s)# -late refers to a hold-time value for your input(s)# ***************************************set_input_delay -clock ideal_clock -early 0.1 [all_inputs]set_input_delay -clock ideal_clock -late 0.2 [all_inputs]# Defining the set-up time for the next module's input portsset_external_delay 0.0 -clock ideal_clock [all_outputs]# Defining the drive (output) resistance of your input(s)set_drive_resistance 0 [all_inputs]}// Stimulus formy_designmodule tb_mydesign; // Test Bench Modulereg bypass0, bypass1, module_clock, rst, a, b, cin, sel; wire out_sum,out_cout;

my_design (bypass0, bypass1, module_clock, rst, a, b, cin, sel, out_sum,

Report.tclproc report {} {mkdir reportmkdir netlistreport_timing > report/timing.rptreport_area -hier -cell > report/area.rptreport_hierarchy > report/hierarchy.rptwrite_verilog -hier netlist/my_design.net}

References

1) Bindal, Ahmed, “Synthesis and Timing Verification Tutorial”, Computer Engineering Department, San Jose State University http://vlsicad.ucsd.edu/courses/ece260b-w04/Lab1/BGTutorial.pdf

2) http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH13/CH13.htm