Major inflection points at logic, memory,

foundry and display customers are creating a

great future for Applied Materials, said CEO

Gary Dickerson, speaking at an analyst meet-

ing on Monday.

In opening remarks, Dickerson chose not

to mention the recently failed merger between

Applied Materials and TEL. Instead, he de-

scribed how key inflection points are being

enabled by new materials technologies. “Those

inflections are enabled by materials innova-

tion. New structures and new materials in

semiconductor and displays create great, great

opportunities for Applied,” he said.

He also pointed to new product launches

that target these opportunities. This week, Ap-

plied Materials launched a new ALD system,

as well as a new etch system. Both systems

represent completely new platforms.

Dickerson said the new transitions or inflec-

tion points are “the biggest that we’ve seen in

decades.” He also said the rate of change is

faster than he’s ever seen. “When you look at

what they need to do for higher performance,

longer battery life and better visual experience

at the right cost, the technologies to enable

those major inflections are bigger than we have

ever seen in this industry,” he said.

Great Future Ahead Says Applied Materials’ DickersonBY PETE SINGER

JULY 14, 2015

MOSCONE CENTER | SAN FRANCISCO, CALIFORNIA

TUESDAYSHOW DAILYSHOW DAILYSHOW DAILY9:00 am – 10:00 amOPENING KEYNOTE PANEL: Scaling the Walls of Sub-14nm ManufacturingPANEL MODERATOR: Jo de Boeck, Senior Vice President, Corporate Technology, imecKeynote Stage, Room 135, North Hall E

10:00 am – 12:35 pmSTS Session: Semiconductor Manufacturing: Current Challenges and Future Opportunities for the Semiconductor Supply ChainSESSION PARTNER: SEMATECHMoscone North, Hall E, Room 131

10:30 am – 12:30 pm What’s Next for MEMS?TechXPOT South, South Hall

11:10 am – 12:45 pmSILICON INNOVATION FORUM: Start-Up PitchesMODERATOR: Dr. Pradeep Haldar, Vice President of Entrepreneurship, Innovation and Clean Energy Programs at SUNY Polytechnic Institute, Interim Dean of SUNY Poly’s College of Nanoscale Engineering and Technology Innovation, Chief Operating and Technical Officer of the U.S. Photovoltaic Manufacturing Consortium (USPVMC) in partnership with SEMATECH

1:30 pm – 3:30 pmMATERIALS SESSION: Contamination Control in the Sub-20nm EraHOSTED BY SEMI CGMG CommitteeTechXPOT South, South Hallcontinued on p. 3

DON’T MISS

Presentations at the SEMI/Gartner Market

Symposium on Monday afternoon could be

summed up in two words: Uncertainties Ahead.

That was part of the title for the presenta-

tion by Bob Johnson, a research vice president

at Gartner. Currency volatility, with multiple

currencies contending with a strong dollar, is

expected to continue in the short term, he said.

“This affects everyone in the electronics

supply chain,” Johnson said.

Jim Walker, another Gartner research vice

president, earlier said China is in for a “hard

landing,” after a spectacular run-up in equities

traded on the Shanghai Stock Exchange in the

past year, followed by a crash last month.

“The U.S. economy is the bright spot,” he

said. “Businesses and households are spending

more.” Those U.S. expenditures are cautious,

he added.

The keynote address was by Ian Ferguson,

continued on p 3

Strong Dollar to Create Economic Uncertainties in Global Market

Gary Dickerson, CEO ofApplied Materials

BY PETE SINGER

We’ll be your unfair advantage.

Conceptualize

Design

Commercialize

Manufacture

Fulfill

Sustain

www.plexus.com+1 877 733 7260

When you work with Plexus for your semiconductor needs, you’re gaining

some serious firepower. From printed circuit board assemblies and advanced

mechatronics to system integration and functional testing — we have the expertise

to help you bring your most complex ideas into reality. We’ll work as an extension of

your own team, collaborating with you from concept and design to a commercially

viable product we can help you sustain in the market. And with locations across

the Americas, Europe and Asia, we can support all your global supply chain,

engineering, manufacturing and aftermarket service needs.

With Plexus on your team, you can realize greater value, faster time to market

and improved global competitiveness.

It’s almost not fair.

SHOW DAILY

TUESDAY | JULY 14, 2015

3SHOW DAILY

Applied Materials today unveiled the Applied

Olympia ALD system, using thermal sequen-

tial-ALD technology for the high-volume man-

ufacturing (HVM) of leading-edge 3D mem-

ory and logic chips. Strictly

speaking this is a mini-batch

tool, since four 300mm wa-

fers are loaded onto a turn-

table in the chamber that

continuously rotates through

four gas-isolated modular

processing zones. Each zone

can be configured to flow any

arbitrary ALD precursor or

to exposure the surface to

Rapid-Thermal-Processing

(RTP) illumination, so an

extraordinary combination

of ALD processes can be run

in the tool. “What are the

applications that will result

from this? We don’t know

yet because the world has

never before had a tool which could provide

these capabilities,” said David Chu, Strategic

Marketing, Applied’s Dielectric Systems and

Modules group.

Figure 1 shows that in addition to a high-

throughput simple ALD process such that wa-

fers would rotate through A-B-A-B precursors

in sequence, or zones configured in an A-B-C-

B sequence to produce a nano-laminate such as

Zirconia-Alumina-Zirconia (ZAZ), almost any

combination of pre- and post-treatments can

be used. The gas-panel and chemical source

sub-systems in the tool allow for the use up to

4 precursors. Consequently, Olympia opens

“When you think about mobility or au-

tomotive or IoT or wearables, the pace of

the technology changes are very, very fast,”

he said. He said hitting these narrow win-

dows was “life or death for our customers.”

About a year ago, Applied Materials

formed a Patterning Group, led by Prabu

Raja, group vice president. The group han-

dles etch, CVD, selective material removal

and ALD. “The growth there has been tre-

mendous,” Dickerson said.

Dickerson said they have moved $400

million of investment in the company into

these opportunities and into new products.

This week, Applied Materials launched

the Centris™ Sym3™ Etch system, featuring

an entirely new chamber for atomic-level

precision manufacturing. The Centris Sym3

etch chamber employs a unique True Sym-

metry™ technology with multiple tuning

controls for optimizing global process uni-

formity to the atomic level. Key to the design

is a focus on controlling and removing etch

byproducts, which are increasingly hamper-

ing within-chip patterning uniformity.

The company also launched a new

Olympia™ atomic layer deposition (ALD)

system that features a flexible and rapid

process sequence vital for controlling the

more complex chemistries needed to de-

velop the next generation of ALD films.

Further, the modular design creates com-

plete separation of chemistries, eliminating

the pump/purge steps of conventional ALD

technologies for improved productivity.

Great Future Ahead continued from p. 3

vice president of segment marketing at ARM

Holdings. “The semiconductor industry is con-

solidating,” he said. “A lot’s going on. The pace

is accelerating.”

Regarding the Internet of Things, Ferguson

said, “Just because it’s connected doesn’t make it

a good idea.” He divided the IoT market into con-

sumer, commercial, and industrial segments.

For the near future of the IoT, he predicted

there will be “a significant security scare,”

which will bring on more security precautions.

Second, “people will stop discussing things as

smart devices,” Ferguson said. Instead of smart

refrigerators and smart televisions, there will

be just refrigerators and televisions, he noted.

Finally, “new connected things will interface to

multiple subsystems,” he concluded.

Johnson said solid-state drives will be a sig-

nificant driver of growth, especially boosting

NAND flash memory devices.

The DRAM market is set for an oversupply

situation with the additional capacity coming

on line, which will be followed by price de-

clines, according to Johnson.

In contrast, NAND flash is “the bright

spot” in the semiconductor industry, “due to

SSDs gaining traction,” Johnson said.

Show Daily StaffPublished by Solid State Technology,

an Extension Media company.

EXTENSION MEDIAVince RidleyPublishervridley@extensionmedia.com

Pete SingerEditorpsinger@extensionmedia.com

Jeff DorschContributing Editorjdorsch@austin.rr.com

Ed KorczynskiContributing Editoredk@extensionmedia.com

Shannon DavisContributing Editorsdavis@extensionmedia.com

TRADESHOW MEDIA PARTNERSMark LarsonProduction and Printingmark@tsmpartners.com

Kevin ClarkeLayout and Designkevin@tsmpartners.com

Strong Dollar continued from p. 1

Fig.1: The four zones within the Olympia sequential-ALD chamber can be configured to use any combination of pre-cursors or treatments. (Source: Applied Materials)

Applied Materials’ Olympia ALD Spins Powerful New CapabilitiesRotating sequential-ALD chamber with four flexible zones provides unprecedented materials control

BY ED KORCZYNSKI

continued on p 10

MOSCONE CENTER | SF, CA

4

Rudolph Technologies, Inc. and DISCO Cor-

poration of Tokyo, Japan, announced a col-

laborative partnership to deliver leading-edge

hardware and software solutions to optimize

the wafer saw unit processes. These compre-

hensive solutions will enable their customers to

consistently improve the quality and productiv-

ity of their advanced packaging products. The

complete wafer saw solution includes: DISCO’s

fully automatic dicing saw for high-throughput,

dual-cut processing, DISCO’s ablation laser

saw and stealth dicing saw, Rudolph’s NSX®

inspection system for post-saw inspection, Ru-

dolph’s new Equipment Sentinel™ fault detec-

tion and classification (FDC) software for real

time monitoring and feedback of DISCO’s dic-

ing tools, and Rudolph’s Discover Enterprise™

yield management software for sophisticated

wafer-to-process tool correlations.

The evolution of semiconductor device ma-

terials for advanced packaging has resulted in

more stringent dicing process requirements.

Process deviations and excursions during

die singulation can result in

chips and cracks that impact

the long-term reliability of

devices. The agreement be-

tween DISCO and Rudolph,

which took effect June 1,

2015, will drive a new level

of innovation in saw pro-

cessing, including improved

kerf control, chipping mini-

mization and overall cost-

of-ownership enhancement

resulting in solutions that

will accelerate advanced packaging adoption.

“With the increasing use of complex materi-

als in today’s semiconductor devices, dicing is

an increasingly critical process step. DISCO

is committed to providing the highest quality

wafer saw solutions to address our customers’

most demanding challenges. We continue to in-

vest in our industry-leading wafer dicing equip-

ment, leveraging advanced sensors and data

acquisition technologies to provide even greater

insight into the performance of our equipment,”

explains Noboru Yoshinaga, executive oper-

ating officer, general manager, sales division

at DISCO. “Through our collaboration with

Rudolph we are able to turn data into valuable

knowledge for our customers, making DISCO

tools easier to ramp, monitor and control.”

“For the past year, our collaboration with

DISCO has allowed us to understand and ad-

dress the increasing challenges faced by our

mutual customers resulting in a close partner-

ship capable of providing comprehensive solu-

tions to improve device reliability and data re-

porting, while at the same time lowering their

costs and decreasing ramp times,” states Mike

Plisinski, Rudolph’s executive vice president

and chief operating officer. “Demand for turn-

key solutions is increasing and we are commit-

ted to continuing to develop and build on this

success to meet that growing demand.”

According to Thomas Sonderman, vice

president and general manager of Rudolph’s

Software Business Unit, “Our new, automat-

ed FDC software, Equipment Sentinel, offers

advanced packaging manufacturers signifi-

cant benefits that, to date, have not been fully

exploited by the industry. For example, the

bi-directional correlation of equipment sen-

sor data with diced product data gives users

a comprehensive, easy-to-understand view of

their process, allowing them to use predictive

analytics to take immediate action, thus re-

ducing product jeopardy and improving the

overall effectiveness of their manufacturing

operations. The savings that result from avoid-

ing a single failure at a critical process step can

easily justify the return on investment for this

type of process control solution.”

Equipment Sentinel™, which was an-

nounced today, combines key wafer-level data

with high-fidelity tool signal and event data

into a single framework, giving users a com-

prehensive, easy-to-understand view of their

processes and equipment. Currently installed

at multiple beta sites worldwide, fab personnel

will use Equipment Sentinel software to ex-

tract the maximum value from the voluminous

amounts of data generated in today’s semicon-

ductor operations.

“Many applications have been developed

over the years to address advanced tool moni-

toring and control for semiconductor manu-

facturing, but they are typically focused on

either wafer or equipment state information,

not both,” said Sonderman. “Equipment Sen-

tinel integrates these formerly independent

data streams into a powerful monitoring and

control engine to enable timely actionable in-

telligence, greatly enhancing optimization ca-

pabilities with predictive analytics in the fab.”

Rudolph’s new Equipment Sentinel soft-

ware can efficiently identify

and isolate the cause of ab-

normal operating conditions

and implement corrective

actions to reduce product

jeopardy and increase over-

all equipment effectiveness.

“The ability to quickly

detect, isolate and correct ac-

tual tool excursions provides

unparalleled value to a manu-

facturing operation. In many

cases, the detection of a single

critical incident more than offsets the total cost of

this type of system,” added Sonderman. “Equip-

ment Sentinel is capable of acquiring, process-

ing and analyzing the massive amounts of data

generated in today’s high-tech manufacturing

environments, providing a new avenue for cor-

rective actions to ensure the maximum return on

investment for semiconductor manufacturers.”

Stop by the Rudolph booth #5580 for more

information.

Rudolph Technologies and DISCO Corporation Partner to Improve Wafer Saw Process

A high speed saw blade cuts through silicon, separating the die.

Package it. Visit: aseglobal.com

Innovative IC, System-in-Package, and MEMS packaging portfolio for today’s

miniaturization, mobility, and IoT needs.

Wire Bond

FlipChip

WLP2.5D& 3D

Fanout SiP

Senseit.

Moveit.

Wearit.

MOSCONE CENTER | SF, CA

6

Plasma etching is a key step in wafer fabrica-

tion, from deposition to the patterning of pho-

tolithography to dry or wet etch. As such, it is a

crucial and hotly-contested area for vendors of

semiconductor manufacturing

equipment.

Lam Research holds about

half of the worldwide etch

equipment market and princi-

pally competes with Applied

Materials, Tokyo Electron, and

Hitachi High-Technologies.

In May, Lam introduced

the Kiyo F Series conductor etch system for

volume production of advanced DRAMs and

3D NAND flash memory devices. Lam says

the Kiyo F Series is employed for critical con-

ductor etch applications at “all major memory

manufacturers.”

A year ago, Lam brought out the 2300 Kiyo

F Series with the Hydra Uniformity System,

which corrects for critical-dimension non-uni-

formities on the incoming wafer. The company

also unveiled an

atomic layer etch

(ALE) capability

on the 2300 Kiyo

F Series conduc-

tor etch system,

which is paired

with Lam’s atom-

ic layer deposition

(ALD) systems,

the V EC TOR

ALD Oxide sys-

tem for dielectric

film ALD and the

ALTUS system

for tungsten met-

al film ALD.

Applied Ma-

terials and To-

kyo Electron set

plans in 2013

to merge their

companies. The

merged compa-

ny, to be called

Eter is, would

have commanded

about one-third

of the worldwide

etching equip-

ment market. The merger was called off in

April, however, as U.S. antitrust regulators

indicated that they would not approve the

transaction.

SEMI cheered a decision by the U.S. De-

partment of Commerce in February to remove

export controls on certain etch equipment,

concluding a four-month investigation. SEMI

had petitioned the federal government agency

in July 2014 to look at the foreign availability

of anisotropic plasma dry etching equipment.

“SEMI stands for free trade and open mar-

kets to support the development and success of

the global semiconductor manufacturing indus-

try supply chain,” Denny McGuirk, president

and CEO of SEMI, said in a statement. “We

applaud the decontrol of semiconductor etch

equipment as a rational response to current

technology, trade, and commercial realities.

This is a win for both equipment makers and

their customers operating in the global market.”

“The Commerce Department’s decision

to remove export control restrictions for etch

equipment is a big victory for the U.S. semi-

conductor equipment sector and our custom-

ers around the world,” said Randhir Thakur,

executive vice president and general manager

of the Silicon Systems Group at Applied Ma-

terials. “Recognizing the availability of these

tools will help fuel growth and promote the

success of the global industry supply chain.”

In May, imec and Tokyo Electron presented

a direct copper etch scheme for patterning cop-

per interconnections (see photo). This would

replace the usual copper damascene process,

according to imec and TEL. The Belgian re-

search organization worked with nine leading

chipmakers on developing the direct copper

etch technology.

Dry or wet, etching technology will be the

subject of discussions at the SEMICON West

2015 conference and exhibition.

Etching, a Crucial Step in Semiconductor ManufacturingBY JEFF DORSCH

TEM section of copper etched lines encapsulated by SiN cap layer.

SEMICON Daily Ad Layout-Plasma-Therm.indd 1 7/1/2015 11:36:14 AM

semi_show_1.indd 1 22/06/2015 15:03:54

MOSCONE CENTER | SF, CA

8

Each year at SEMICON West, the “Best of West” awards are presented by Solid State Technology and SEMI. The award was established to recognize new products moving the industry forward with technological developments in the microelectronics supply chain.

The Best of West 2015 Finalists will be displaying their tools on the show floor at Moscone Center from July 14-16:

The 2014 Best of West Finalists are:ClassOne TechnologySolstice S4Solstice S4 is the first automated plating tool

that delivers ad-

vanced perfor-

mance on smaller

substrates at affordable prices. Described as

“advanced plating for the rest of us,” Solstice is

designed specifically for the smaller-substrate

users in emerging technologies such as MEMs,

LEDs, Power Devices, RF Communications,

Interposers, Photonics and Microfluidics.

Solstice sets new standards for plating per-

formance and affordability.

South Hall, Booth #2521.

National Instruments NI Semiconductor Test Systems NI’s Semiconductor Test Systems (STS) fea-

ture PXI mod-

ular instru-

mentation and

open system design software for semiconduc-

tor test environments. Unlike traditional ATE

systems that incur costs as old generations of

equipment become obsolete, NI STS’ open

architecture allows engineers to retain their

investments and easily scale. Its compact de-

sign eliminates floor space, power, and main-

tenance costs, and is ideal for characterization

and production to decrease time to market.

North Hall, Booth #5472.

Nordson ASYMTEKProgrammable Tilt + Rotate 5-Axis Fluid DispenserWith requirements for precision, accuracy, and

speed more stringent

than ever and pushing

the limits of dispensing

equipment capabilities,

the new programmable Tilt + Rotate 5-Axis

Fluid Dispenser solves these problems, achiev-

ing unparalleled accuracy and precision in X,

Y, and Z axes for thin lines and small dots, to

make high-volume manufacturing possible for

today’s new products.

North Hall, Booth #5743.

SEMI and Solid State Technology Announce the 2015 “Best of West” Award Finalists

The Best of West Award winner will be announced during SEMICON West on Wednesday, July 15, 2015.

SHOW DAILY 9SHOW DAILY

Those interested in learning about develop-

ments in chemical mechanical planarization

(CMP) for hard drives and integrated circuits

would do well to attend the CMP Technical

and Market Trends session on Thursday, July

16, at 11 am in the TechXPOT North area of

Moscone Center’s North Hall. Representatives

of Intel, HGST, Entegris, TDK, and other com-

panies will be speaking.

While 450mm wafers haven’t been much

in the news this year, Thursday’s session will

include a presentation by the Global 450 Con-

sortium, with speakers from the College of

Nanoscale Science + Engineering (CNSE)

and SEMATECH.

CNSE is part of the SUNY Polytechnic In-

stitute in Albany, N.Y., which also contains the

Chemical Mechanical Planarization Center, a

joint program with SEMATECH. Mitsubishi

Chemical joined the program this spring.

While CMP is still used for its traditional

polishing applications for interlayer dielec-

trics, it’s also finding employment in more

advanced applications, such as bulk oxide pol-

ishing, shallow trench isolation, “stop on poly”

isolation, and polishing of various dielectrics

in advanced transistor designs.

Late last month, Applied Materials and Ca-

dence Design Systems announced that they are

collaborating on optimizing the CMP process

through silicon characterization and model-

ing for ICs with 14-nanometer features, and

beyond that process node. Cadence, one of

the leading vendors of electronic design auto-

mation software and services, will provide its

CMP Predictor and CMP Process Optimizer

tools. Applied will employ its Reflexion LK

Prime CMP system.

“From our collaboration, we expect to more

accurately predict gate height, dishing and ero-

sion on each step of the CMP process, which

could enable design and manufacturing teams

to achieve higher yield and deliver advanced-

node designs to market faster,” Derek Witty,

vice president and general manager of Applied’s

CMP Products Group, said in a statement.

Whatever your level of expertise in CMP,

SEMICON West 2015 will help you polish up

your knowledge of the field.

The Latest in CMP Tech Will Be on Offer at SEMICON WestBY JEFF DORSCH

The Applied Reflexion® LK Prime™ CMP system.

■ Scanning Probe Microscopy■ Selective Deposition as an Enabler of Self-Alignment■ Spectroscopic Ellipsometry■ Surface Modification of Materials by Plasmas for Medical Purposes■■ Tribology

FOCUS TOPICS & OTHER SESSIONS■ 2D Materials■ Accelerating Materials Discovery for Global Competitiveness■ Actinides & Rare Earths■ Additive Manufacturing/3D Printing■■ Atom Probe Tomography■ Energy Frontiers■ Exhibitor Technology Spotlight■ Helium Ion Microscopy■ In-Situ Spectroscopy & Microscopy■ IPF on Mesoscale Science and Technology of Materials and Metamaterials■■ Materials Characterization in the Semiconductor Industry■ Novel Trends in Synchrotron & FEL-Based Analysis

DIVISION/GROUP PROGRAMS■ Advanced Surface Engineering■ Applied Surface Science■ Biomaterial Interfaces & Biomaterials Plenary■ Electronic Materials & Processing■ Magnetic Interfaces & Nanostructures■■ Manufacturing Science & Technology■ MEMS and NEMS■ Nanometer-scale Science & Technology■ Plasma Science & Technology■ Surface Science■ Thin Films■ Vacuum Technology

Details available at www.avs.org

Housing Deadline: September 25, 2015Early Registration Deadline: September 28, 2015

Addressing cutting-edge issues associated with materials, processing, and interfaces in both the research and manufacturing communities. The weeklong Symposium fosters an environment that cuts across traditional boundaries between disciplines and features:

October 18-23, 2015 | San Jose Convention Center | San Jose, CA

AVS 62ND INTERNATIONALSYMPOSIUM & EXHIBITION

10

the way to depositing the widest spectrum of

next-generation atomic-scale conformal films

including advanced patterning films, higher-

and lower-k dielectrics, low-temperature films,

and nano-laminates.

“The Olympia system overcomes funda-

mental limitations chipmakers are experienc-

ing with conventional ALD technologies, such

as reduced chemistry control of single-wafer

solutions and long cycle times of furnaces,” Dr.

Mukund Srinivasan, vice president and gen-

eral manager of Applied’s Dielectric Systems

and Modules group. “Because of this, we’re

seeing strong market response, with Olympia

systems installed at multiple customers to sup-

port their move to 10nm and beyond.” Future

device structures will need more and more con-

formal ALD, as new materials will have to coat

new 3D features.

When engineering even-smaller struc-

tures using ALD, thermal budgets inherently

decrease to prevent atomic inter-diffusion.

Compared to thermal ALD, Plasma-En-

hanced ALD (PEALD) functions at reduced

temperatures but tend to induce impurities

in the film because of excess energy in the

chamber. The ability of Olympia to do RTP

for each sequentially deposited atomic-layer

leads to final film properties that are inherently

superior in defectivity levels to PEALD films

at the same thermal budget: alumina, silica,

silicon-nitride, titania, and titanium-nitride

depositions into high aspect-ratio structures

have been shown.

Purging (from the tool) pump-purgeFab engineers who have to deal with ALD tech-

nology—from process to facilities—should

be very happy working with Olympia because

the precursors flow through the chamber con-

tinuously instead of having to use the pump-

purge sequences typical of single-wafer and

mini-batch ALD tools used for IC fabrication.

Pump-purge sequences in ALD tools result in

the following wastes:

• Wasted chemistry since tools generally

shunt precursor-A past the chamber di-

rectly to the pump-line when precursor-B

is flowing and vice-versa,

• More wasted chemistry because the entire

chamber gets coated along with the wafer,

• Wasted cleaning chemistry during routine

chamber and pump preventative-mainte-

nance,

• Wasted downtime to clean the chamber and

pump, and

• Wasted device yield because precursors

flowing in the same space at different times

can accidentally overlap and create defects.

“Today there are chemistries that are more

or less compatible with tools,” reminded Chu.

“When you try to use less-compatible chemis-

tries, the purge times in single-wafer tools really

begin to reduce the productivity of the process.

There are chemistries out there today that would

be desirable to use that are not pursued due to

the limitations of pump-purge chambers.”

Olympia ALD continued from p. 3

Proven Technology, Trusted Partner™

SHOW DAILY 11SHOW DAILY

CEA-Leti announced its first results towards

the demonstration of CoolCube’s feasibility in

FinFET technology on its 300mm production

line, and new CoolCubeTM circuit designs

that improve the tradeoff between area, speed

and power.

Key process steps developed on 300mm wa-

fers show progress in closing the gap between

the demonstration of a single device and taking

the technology to fabrication.

CoolCubeTM is Leti’s sequential integra-

tion technology that enables the stacking of

active layers of transistors in the third dimen-

sion. Under development for eight years, it

aims at fully benefiting from the third di-

mension, and is enabled by cutting in half the

thermal budget in manufacturing transistors,

while maintaining their performance.

Mobile devices, where minimal power con-

sumption is key, are the primary mar-

ket for chips manufactured with the

technology. CoolCubeTM also allows

designers to include backside imag-

ers in the chips, and co-integration

of NEMS in a CMOS fabrication pro-

cess also is possible.

“CoolCubeTM enables local via

density that is 10,000 times higher

than ‘standard’ 3D integration, be-

cause the technology is designed to

connect stacked active layers at a

nanometric scale,” said Maud Vinet, Leti’s ad-

vanced CMOS laboratory manager. “In the digi-

tal area, we expect this 3D technique to allow

a gain of 50 percent in area and 30 percent in

speed compared to the same technology gener-

ation in classic 2D – gains comparable to those

expected in the next generation. In heteroge-

neous integration, we expect CoolCubeTM to

be an actual enabler of smart-sensor arrays by

allowing a close integration of sensors, detec-

tion electronics and digital signal processing.”

Leti’s team will be in the European Pavilion,

South Hall, Booth #2317, during SEMICON

West.

Leti Reports FinFET Feasibility and Circuit Design with CoolCube Tech

Leti’s CoolCube is made possible by sequential inte-gration.

Delivering Superior Quality, Quick Turn Around, Affordable Repair and an Excellent Warranty to the

Semiconductor Industry since 1992.

Innovator, Customizer, and Manufacturer of new and refurbished OEM lasers for the Semiconductor Industry.

Custom Engineered Designs / New Product PartneringWork directly with our customers designing lasers to their specifications and servicing needs.

Manufacturing & Refurbishing ExcellenceDirect source for high-quality gas and solid-state lasers meeting specifications of OEM’s worldwide.

WaferInspectionMaskInspectionIon Implant MonitoringConfocalDefect Review

Find us at Semicon West - Scan this QR Code

Contact: (801) 467-3391 or laser@nationallaser.com

Precision Light ~ Precision Servicewww.nationallaser.com

12

Solid State Technology is delighted to an-

nounce that Dr. Gary Patton has joined the

Advisory Board of The ConFab. Now in its

twelfth year, The ConFab is an invitation-only

event where executives from equipment and

materials suppliers meet with decision makers

from semiconductor manufacturers, packag-

ing houses and fabless companies. In 2016,

The ConFab will be back at The Encore at The

Wynn in Las Vegas, from June 12-15th.

Dr. Patton is the Chief Technology Officer

and head of worldwide Research and Develop-

ment at GLOBALFOUNDRIES. He is respon-

sible for the company’s semiconductor technol-

ogy R&D roadmap, operations, and execution.

Dr. Patton, who delivered a keynote talk at

The ConFab in 2014 and returned in 2015, was

previously Vice President of IBM’s Semicon-

ductor Research and Development Center in

East Fishkill, New York. He had responsibil-

ity for IBM’s semiconductor

R&D roadmap, operations,

and technology develop-

ment alliances, with pri-

mary locations in East Fish-

kill, New York, Burlington,

Vermont, and the Albany

Nanotech Research Center

in Albany, New York.

During his career at

IBM, Dr. Patton has held

various management and

executive positions in IBM’s

Microelectronics, Storage

Technology, and Research

Divisions, including posi-

tions in technology and

product development, manufacturing, and

business line management. Dr. Patton received

his B.S. degree in electrical engineering from

UCLA and his M.S. and

Ph.D. degrees in electrical

engineering from Stanford

University. He is also a Fel-

low of the IEEE.

“It’s a great honor to

have Gary on the Advisory

Board,” said Pete Singer,

Editor-in-Chief of Solid

State Technology, and

conference chair for The

ConFab. “Gary has tremen-

dous insights into the next

generation technology that

will be required to move

the semiconductor indus-

try forward. He’s also well

versed in the economics of semiconductor

manufacturing, which is the main focus of

The ConFab.”

Dr. Gary Patton, Chief Tech nology Officer and head of worldwide Research and Development at GLOBALFOUNDRIES.

The ConFab Welcomes Dr. Gary Patton to Advisory Board

June 12-15, 2016Encore at the WynnLas Vegas

Make Plans Now to Attend the Semiconductor Manufacturing Industry’s Premier Conference & Networking Event

www.theconfab.com

SHOW DAILY 13SHOW DAILY

Save Costs by Conserving Energy in the Sub-FabBY PETE SINGER

Opportunities for cost savings abound in

the “sub-fab” of semiconductor operations

where the vacuum pumps and gas abatement

systems reside. Typically, these systems are

running full tilt, no matter what’s going on in

the process tool.

In a case where the cobbler’s children may

finally be getting new shoes, work is underway

to improve the communication between sub-

fab equipment and process tools so that fuel

in gas abatements systems can be turned off if

there’s nothing to abate, and vacuum pumps

can be throttled back or slowed if there’s noth-

ing to pump.

“If you have equipment that is enabled with

this capability, you can access these savings by

essentially turning down the power or the fuel

gas consumption when they’re not actually

required for chip processing, said Dr. Michael

Czerniak, Environmental Solutions Business

Development Manager, at Edwards Ltd.

Czerniak will be giving a talk at 2:00pm

on Tuesday at SEMICON West as part of the

Sustainable Manufacturing Forum. The fo-

rum, which will be held on Tuesday in Moscone

North, Hall E, Room 132 from 10:00am to

5:00pm, allows experts to share the latest

information on the environmental and social

impacts of advanced technologies that are

likely to be introduced into semiconductor

manufacturing in the near future.

At SEMICON West in 2014, Czerniak was

honored with SEMI’s Merit Award, along with

Daniel Chlus (IBM) and Lance Rist (RistTex).

The trio, were part of the Energy Saving Equip-

ment Communication Task Force responsible for

developing new standards designed to help re-

duce energy consumption in production equip-

ment, specifically the SEMI E167 standard.

While production equipment and support

equipment are all capable of reduced utility

consumption, imple-

mentation has been

slow due to lack of a

standard.

SEMI’s E167

solved one piece of

the puzzle – enabling

the factory host to

tell the process too

that there are no wafers coming, for example

– another standard is needed for the tool to

communicate with sub-fab equipment that

it, too, can power down. That is where a new

standard, SEMI S23 comes in. “Once the tool

has decided it doesn’t need pumps and abate-

ment for the next 45 minutes or so — whatever

it decides — it can then cascade that message

down to the subfab where the energy savings

will actually take place,” Czerniak explained.

At SEMICON West, a working group of the

Dr. Michael Czerniak

continued on p. 17

Vacuum Solutions for the Entire Fab

1-800-USA-PUMP I www.buschusa.com

Go Green, Go Busch!

Save up to 40% on electrical energy usage by choosing Premium Efficiency Busch Pumps.

Visit us at Booth 2210 to learn more!

14

Immersion Lithography Remains the Industry’s Workhorse TechnologyBY JEFF DORSCH

While the lithography equipment market

sometimes seems like A Tale of Two Cities, it’s

more complicated than that. The basic fact is

that the semiconductor industry is soldiering

on with 193-nanometer immersion lithogra-

phy technology and multiple-patterning ex-

posures while extreme-ultraviolet lithography

continues its long-aborning development.

ASML Holding is the leading vendor in

the EUV lithography field, and it’s also a big

supplier of 193nm immersion lithography sys-

tems. The industry consensus now seems to

be that the near future will see the combined

use of EUV and immersion, possibly at the

10-nanometer process node and definitely at

the 7nm node. Beyond that, it’s anyone’s guess.

ASML had big news to reveal at the SPIE

Advanced Lithography Symposium in Febru-

ary. Taiwan Semiconductor Manufacturing

had successfully exposed 1,022 wafers within

24 hours on ASML’s NXE:3300B EUV system,

with sustained power of more than 90 watts

from the scanner’s power source.

In April, ASML reported that “one of its

major U.S. customers” had agreed to order at

least 15 EUV systems. Industry speculation on

the unidentified customer quickly centered on

Intel. The Dutch company has been relatively

quiet since then.

Hans Meiling, ASML’s vice president of ser-

vice and product marketing EUV, notes the

progress that the company has made in the

past year, but didn’t offer any new information

on its EUV program. ASML’s EUV scanners

will be “meeting production requirements

within a couple of years,” he says.

“We want to get to 75 percent availability

and 1,000 wafers per day,” Meiling says, and

not just in a one-day test at TSMC. The goal

is to provide that kind of productivity and

throughput for all EUV customers, he adds.

In 2016, ASML is aiming for a daily through-

put of 1,500 wafers, according to Meiling. “We

have a large program internally to support

that,” he says.

A six-inch full-area nanoimprinted wafer pro-cessed by EVG NIL solutions. Source: EVG.

www.Solid-State.com

Reach the largest, most qualified community of decision makers for semiconductor and electronics manufacturing through the magazine, email newsletters, website, webcasts and The ConFab Conference & Networking event. Topics include Advanced Packaging, MEMS, LEDs and Displays as well as current trends in the industry.

SemiconductorS

advanced packaging

memS

ledS

diSplayS

Request your free subscription today, and see why electronics manufacturing professionals worldwide trust Solid State Technology:

www.solid-state.com/subscribe

SHOW DAILY 15SHOW DAILY

To make its EUV scanners productive and

production-ready, ASML has developments

on several fronts, Meiling notes. “It’s a multi-

faceted introduction of not only the scanner,”

he says, taking in photomasks, photoresists,

and pellicles.

Progress has been made in detecting and

reducing defects in EUV mask blanks, Meil-

ing reports. It seems likely that Intel, Samsung

Electronics, and TSMC will each make their

own EUV masks, he says.

When it comes to resists, “we don’t control

the ecosystem,” Meiling says. “We’re moni-

toring this.” Resist suppliers are “continually

improving critical-dimension quality” and pro-

viding “faster resist without losing the imaging

capability,” he states.

Even “beautiful masks,” near-perfect pho-

tomasks, “have to have a pellicle to protect

them,” Meiling observes. “Light goes through

the pellicle twice,” he notes, and the pellicle’s

membrane must be very thin as a result. ASML

began work on a EUV pellicle two years ago and

has developed a removable pellicle. The com-

pany has achieved “full mask coverage” with

its pellicle and is going through an initialization

phase on producing them, according to Meiling.

The ASML executive ticks off the attributes

of EUV – single exposures of chips, reduction

of process complexity, and the capability to deal

with the complexity of chip layers. “Customers

are finding out with multipatterning, it’s becom-

ing more and more difficult,” Meiling says. “It’s

very difficult for certain layers in the chip stack.”

For all the publicity about EUV, ASML is

constantly improving its deep-ultraviolet lithog-

raphy scanners as well, he notes. “Immersion is

our workhorse,” Meiling says. “We’re tighten-

ing requirements brought to us by customers.”

Stefan Weichselbaum, ASML’s director of

product marketing DUV, says the company is

committed to “holistic lithography” – looking

beyond scanner performance and integrating

a metrology environment. Most of all, ASML

wants to keep DUV/immersion machines af-

fordable, and “the most simple thing we can

do is improving the output,” he says.

Currently capable of processing 250 wafers

per hour, the NXT:1980 scanner will be boosted

to 275 wafers per hour during the second half of

this year, according to Weichselbaum. Among

other improvements, ASML has debuted feed-

forward corrections, reticle cooling, and wafer-

by-wafer correction for higher-order reticle dis-

tortion in the NXT:1980. “If we can manage it

through software, we will,” he adds.

Weichselbaum says, “EUV is coming.

We’re pretty close to a world where DUV

wouldn’t exist.”

Donis Flagello, president, CEO, and chief

operating officer of Nikon Research Corpora-

tion of America, would likely beg to differ with

that statement.

“EUV is probably not going to go away,” he

says, while adding, “It’s not going to take over.”

Nikon does analysis on EUV technology

and the state of the art in immersion lithog-

raphy; the company is focused on 193nm and

continued on p. 16

GamechangersWe are fearless game changers, bringing first-of-kind design experience to the most complex facilities in the world.

Working with our clients, we drive the industry toward new tools and technology in a faster time to market at lower cost.

Learn more at ch2m.com.

John Frank, Vice President Electronics Group john.frank@ch2m.com

Consistently ranked at the top of ENR’s

semiconductor design firms.

SemiconWest.2015.HalfpageAd.IN0611151059PDX_final.indd 1 6/22/2015 9:32:11 AM

16

“pushing to get the costs down,” Flagello says.

“Demand is still strong” for 193nm ma-

chines, he reports. “The entire Internet runs

on semiconductors.” Still, “the semiconductor

industry is mature” and consolidating, Flagello

says. “We can see it in conferences.”

Immersion lithography presents its own

challenges in masks and resists, the Nikon

executive notes. “We can afford to pump more

power into the system,” Flagello says. “We

have to control the lenses better.”

While EUV has a long, well-known history

of delays and problems, the industry transition

to 193nm lithography wasn’t an easy one, ei-

ther, according to Flagello. “There was lots of

stuff we didn’t expect,” he says.

There are alternatives to 193nm and EUV

lithography, such as directed self-assembly,

direct-write electron-beam, and nanoimprint

lithography. DSA “would be complementary”

to the mainstream lithography technologies,

and the others have their disadvantages, Flag-

ello says.

An Steegen, imec’s senior vice president of

process technology, says, “Multipatterning is

the most cost-effective way.” With “cheaper

materials,” the costs of multipatterning can be

further reduced, and “there are lots of efforts

here at imec and our suppliers,” she adds.

Immersion lithography can be extended

to the 10nm and 7nm process nodes, Steegen

says. With EUV, “you can replace multipattern-

ing exposures with one exposure,” she notes.

The industry roadmap calls for EUV in-

sertion into production in 2017, Steegen says.

EUV source power is “almost everywhere run-

ning at 80 watts,” she adds, and uptime has

been improved. “The whole EUV ecosystem

is coming together,” Steegen notes, with prog-

ress in EUV photomasks and photoresists.

Directed self-assembly is “a complemen-

tary patterning technology,” the imec execu-

tive says. “We always keep an eye on all the

alternatives.” While imec has succeeded in im-

proving DSA, “we are not having huge activi-

ties around these areas,” such as multi-beam

E-beam and nanoimprint, Steegen says.

“We’re getting smarter, combining multi-

patterning and EUV,” she adds.

One issue that concerns her is the use of Fin-

FETs in current and future process nodes. “How

far can we push those? When will they break?”

she asks. “How tall can we make the FinFET?

Beyond 5 nanometers? The taller, the better.”

Another area where lithography is pro-

gressing is in the field of advanced packag-

ing. Doug Anberg, vice president of advanced

stepper technology at Ultratech, says wafer

bumping and other packaging technologies

are “still progressing forward. We’re seeing a

lot of activity in that area.”

Thomas Uhrmann, director of business

development for EV Group, says “there is a

lot of traction” in lithography for advanced

packaging. His company plans to exhibit a na-

noimprint platform tool at SEMICON West,

intended for making light-emitting diodes and

Internet of Things devices (see photo).

Immersion Lithography continued from p. 15

SHOW DAILYSHOW DAILY

SEMI S23 task force is preparing additions to the Related Information sec-

tion of SEMI S23 to provide for suggested utility-consumption test condi-

tions and report formats for some components and peripheral equipment

commonly used in semiconductor manufacturing equipment systems.

The components initially considered are dry vacuum pumps, refriger-

ated chillers and heat exchangers, although other components such as

process power equipment may be considered soon. Also under discussion

is the inclusion of Related Information for the application of efficiency

rating systems for components and peripheral equipment. The goal of

the working group is to produce suggested new Related Information in

SEMI S23 for consideration on a future SEMI Standards Ballot.

“We’re working pretty hard as part of a SEMI standards committee

– to get standardized signaling for that sort of information – so that all

pump and abatement suppliers can get access to signals that allow them

to do these energy savings,” Czerniak said.

Czerniak said this will work best in a new facility, once the tools have the

ability to communicate directly with the pumps and abatement systems. In

a retrofit scenario, it can be a challenge to get those signals. “We’re talking

about getting signals derived from loadlock pumps,” he said.

In practice, it may be impossible to actually turn off vacuum pumps

completely, particularly those that are pumping byproducts that tend to

condense inside the pump. “You generally don’t want to switch them

off due to the risk of not being able to restart them. In those cases, what

you do is typically reduce the frequency at which you spin them and save

maybe 10-15% of the running power. To get them back to full speed and

full operating temperature isn’t such a long period of time,” Czerniak said.

On the other hand, with gas abatement systems, particularly those

that burn fuel (i.e., natural gas) to destroy the byproducts, it’s possible to

shut them to near zero. “In our case, we usually just leave them running

on a pilot flame. They come back on line in tens of seconds, and you save

about 90% of your fuel gas. There are very significant savings,” Czerniak

said. “At the same time, you also save on your CO2 footprint. It gets to

be quite an important factor when people do CO2 audits of their manu-

facturing process so they can put green stickers on their end products.”

This has been the focus of one of the working groups in the European

EEM450PR project, which is focused on 450mm tool developed (similar

work is underway at the G450C Consortium in Albany).

In his talk on Tuesday Czerniak will describe those models that were

constructed as part of the EEM450PR project to simulate the impact of

green modes, at various levels of wafer inactivity, initially for 300mm,

and then extended for a hypothetical 450mm fab. It was also noted that

additional savings would be possible in the facility, e.g. reduced process

cooling water when the pump and abatement thermal load is reduced.

The model was then validated by looking at data from a HVM 300mm

fab, simulating the effect of green modes (without actually implementing

them), and also live green mode implementation on pumps and abate-

ment at imec’s R&D lab in Europe.

A live demonstration was also conducted in the G450C Albany fab

on some installed 450mm toolsets, as part of the complementary and

collaborative engagement between the regions on the 450mm topic..

TUESDAY | JULY 14, 2015

17

Sub Fab continued from p. 13

MOSCONE CENTER | SF, CA

18

The era of three-dimensional chips is upon us.

At the Design Automation Conference last

month in the Moscone Center, I saw a Hybrid

Memory Cube in the booth of Open-Silicon in

the South Hall. There before me was technol-

ogy I had read about for years, without witness-

ing it in person.

The Hybrid Memory Cube, High-Bandwidth

Memory technology, and logic parts such as

Intel’s Xeon Phi “Knights Landing” micropro-

cessor are leading examples of 3DIC technol-

ogy. Meanwhile, other advances in packaging

– chip-scale packages, copper pillar bumping,

fan-in wafer-level packaging, flip-chip ball

grid arrays, and wafer-level fan-out packages,

among others – are gaining in adoption.

The Semiconductor Technology Sympo-

sium during SEMICON West 2015 will include

two sessions devoted exclusively to advanced

packaging on Tuesday, July 14. Packaging: The

Very Big Picture is scheduled for 10 am, while

Packaging: Digital Health and Semiconductor

Technology will commence at 2 pm.

SEMI reported packaging materials rep-

resented $20.4 billion in worldwide sales dur-

ing 2014. That figure was essentially flat with

2013. SEMI noted that if bonding wire were

excluded from the segment, sales would have

been up more than 4 percent from the previous

year. “The continuing transition to copper-

based bonding wire from gold is negatively im-

pacting overall packaging materials revenues,”

SEMI stated.

McKinsey & Co. last year published a re-

port on advanced packaging technologies that

estimated the number of integrated circuits

containing 2.5DIC and 3DIC technologies will

increase from about 60 million units in 2012 to

more than 500 million units in 2016.

“There still is a lot of uncertainty in the

market about 2.5DIC and 3.0DIC technolo-

gies – for instance, when and how exactly to

adopt these newer packaging configurations,

who will dominated among the players, and

the role China will play,” the authors of the

report wrote.

Through-silicon vias figure in many 3DIC

schemes, while silicon interposers are often

regarded as a bridge to 3DIC technology and

called 2.5DIC packaging. Ed Korczynski, se-

nior technical editor of Solid State Technol-

ogy magazine, wrote last month about recent

developments in 3DIC technology.

The emergence of advanced packaging and

3DICs hasn’t escaped the attention of semicon-

ductor equipment vendors, of course. KLA-

Tencor in April introduced two systems – the

CIRCL-AP for characterization and model-

ing of wafer-level packaging processes and the

ICOS T830 for automated optical inspection of

IC packages with 2D and 3D measurements.

Both products are already installed in facilities

around the world.

“Advanced packaging technologies offer

device performance advantages, such as in-

creased bandwidth and improved energy ef-

ficiency,” Brian Trafas, KLA-Tencor’s chief

marketing officer, said in a statement. “The

packaging production methods, however, are

more complex – involving the implementa-

tion of typical front-end IC manufacturing

processes, such as chemical mechanical pla-

narization and high-aspect-ration etch, and

unique processes, such as temporary bonding

and wafer reconstitution.”

For 2014, Amkor Technology reported that

“advanced products” accounted for $1.553 bil-

lion in revenue, or 49.6 percent of the com-

pany’s total revenue. That figure has steadily

risen over the past three years.

Phil Garrou, a senior consultant for Yole

Developpement, speaking last December at

a symposium in Burlingame, Calif., took a

hardline position on the subject of 2.5D tech-

nology. “It’s 2D or 3D,” he said, with nothing

in between. “Interposers are packages,” he

added.

Wherever you stand on 2D, 2.5D, or 3D,

there will be much to discuss at SEMICON

West this week.

Advanced Packaging, 3DICs to Figure in SEMICON West DiscussionsBY JEFF DORSCH

The Hybrid Memory Cube combines high-speed logic and DRAM layers into one optimized 3D package that leverages through-silicon via (TSV) technology. Source: Micron.

It’s how we add value.

Enabling Technology Inflection Points Across Key Semiconductor Processes

As one of the industry’s largest and leading providers of process materials, materials handing and contamination control solutions, we have the breadth of application knowledge, materials expertise and solutions you need to help solve critical challenges and enable inflection points in your advanced process development.

Contact us and learn how Entegris can add value to your advanced manufacturing processes and development.

www.entegris.comEntegris®, the Entegris Rings Design® and Creating a Material Advantage® are registered trademarks of Entegris, Inc. ©2015 Entegris, Inc. All rights reserved.