SESSIONS RISC-V Summit · particularly important for embedded computing and IoT device. One obstacle to measuring code size and settling this issue has been the lack of an open benchmark

Registration

8:00am - 7:00pmRegistration

Welcome Address: Exponential Progressacross Industries and Around the World withRISC-V

9:00am - 9:20amKeynotes

Location: Grand Ballroom 220-A

Calista will discuss the progress spanning the globalRISC-V community in collaboration, innovation, andadoption of RISC-V across numerous industries andaround the world. The Foundation is uniquely poised todisrupt the business model, collaborate on sharedtechnical building blocks, and accelerate proliferationof the architecture. Across 2019 we've seentremendous progress across all stakeholders andwe're focused on driving the Foundation priorities andprograms for deep engagement and broadparticipation in the RISC-V revolution.

All Access, Conference or Keynote & Expo Passrequired to attend Keynote sessions.

Participants

Calista Redmond - CEO, RISC-V Foundation

State of the Union



Present the current status of RISC-V developments,including updates on the RISC-V ISA roadmap andrecent progress in the technical committees.


Participants

Krste Asanovic - Professor | Chief Architect, UCBerkeley | SiFive

Unshackling Memory!



Todays compute platforms have evolved fromdecades of existing architectures. While software hasbeen the focus for the last decade, RISC-V affords usthe opportunity to rethink hardware. For example, whydoes the CPU own main memory? Are homogeneousarchitectures really the best implementation? To buildoptimized architectures for today’s processingrequires collaboration and innovation. Open sourcehardware groups such as CHIPS Alliance, coupled withRISC-V will provide the platform for memory to befreed from a processor. Martin Fink’s keynote willshare the vision of how we can unshackle memory toaddress future compute requirements.


Participants

Speaker: Martin Fink , Western Digital

Open for Business: True Stories of How FarWe’ve Come With the RISC-V Ecosystem



There can be no doubt that RISC-V has moved out ofacademia and is well into its commercialization andbroad adoption phase. RISC-V has been makingheadlines around the world as startups to multibillion-dollar technology leaders have announcedarchitectures and product families enabled by the freeand open-source ISA. None of this would be possiblewithout the establishment of a robust RISC-Vecosystem that fosters collaboration, innovation, andenablement for the design community to buildinventive hardware with RISC-V as its core. In thisyear’s keynote address, Microchip fellow and foundingRISC-V board member Ted Speers will dive into“Collaborate, Innovate, Build it” by providing hisinsights on the exponential growth of the RISC-Vecosystem based on his own experiences in bringingabout RISC-V-based products.


Participants

Ted Speers - Head of Product Planning for FPGABusiness, Microchip Technology Inc.

Lightning Talks featuring Chronos Tech, SolidSands and Think Silicon



Lightning Talks give StartUps the opportunity to pitchtheir company to the entire General Session audience.Each company will have three minutes for theirpresentation. Come hear the latest ideas surroundingRISC-V!

You'll hear from Chronostech, Solid Sands, ThinkSilicon and one more surprise ...


Participants

Speaker: Marianne Damstra - CCO, Solid Sands

Speaker: Stefano Giaconi - Cofounder & CTO, ChronosTech

Speaker: Ulli Mueller - Senior Vice President Sales &Marketing, Think Silicon, Think Silicon

RISC-V of Samsung in the Age of 5G and AI



Compute requirements today are more diverse thanever. With the ramp up of 5G wireless networks, IoT’svarious workloads, mobile requirements andautomotive applications there is a need for broadprocessing solutions. RISC-V provides a clean slateapproach for organizations to tackle these variedcompute demands. We’ll discuss how Samsung isaddressing these challenges for 2020 and beyond.


Participants

Speaker: Junho Huh - VP, Next GenerationArchitecture, Samsung Electronics, SamsungElectronics

SESSIONSTUESDAY, DECEMBER 10 - 10/12/2019

RISC-V SummitDecember 10 - 12, 2019

San Jose Convention CenterSan Jose, California

+1 (888) 670-8200 tmt.knect365.com/risc-v-summit/ [email protected]

Ruby Sponsor SiFive presents: Taking RISC-Vinto New Markets



With RISC-V architecture going mainstream, SiFiveCore IP has seen production deployments rangingfrom tiny embedded controllers to mass-marketconsumer devices, all the way up to enterprisenetworks. To enable connected intelligence at scale, aCPU portfolio is required which supportsheterogeneous combinations of compute whilemaintaining a common programming model. SiFiveCore IP, built on RISC-V, is architected to enableheterogeneous compute and efficiency requirementsby providing a scalable portfolio of CPU IP which canbe customized according to domain-specificapplication requirements. In this talk, we will highlightrecent advancements around extending SiFive's 64-bitRISC-V processors with a special focus on a newcomputational dimension required to enable the visionof a world of a trillion connected devices.


Participants

Yunsup Lee - CTO, SiFive

Expo Hall

11:30am - 7:00pmExpo

Location: Executive Ballroom

Lunch Break

11:30am - 12:50pmNetworking


Poster Gallery on Expo Floor

11:30am - 7:00pmPoster Gallery

Open to All Pass Types: Poster Gallery located at theheart of the Expo Floor. New and different posterseach day!

Stop by the Gallery to view and discuss the work ofyour colleagues in this informal, relaxed setting.

Poster Gallery Schedule

11:30 a.m.-1:30 p.m. & 3:30-5:30 p.m.

Achieving Fault Tolerance For Persistent Memory

Building Mixed-Criticality Systems with RISC-V-basedSoC FPGAs

SHAKTI E-class SDK and IDE for IoT Applications

Experiments and AI Model Validations for Neo/TVMon RISC-V Architectures with SIMD

An Open and Coherent Memory Centric ArchitectureEnabled by RISC-V

Gaining the Upper Hand in the Escalating Cyberwar

1:30-3:30 p.m. & 5:30-7 p.m.

Designing RISC-V Custom instruction extensions withtiming driven profile and analysis

Open-source Validation Suite for RISC-V

RISC-V ISA Extensions for Efficient Acceleration of IoTapplications

Application Optimization and Status Update of RISC-VP extension

Architectural Overview of the European ProcessorInitiative

View all poster descriptions here >>

Participants

Chuan-Hua Chang - Managing Director, AndesTechnology Corporation

Huynh Tu Dang - Principal Engineer, Western DigitalCorperation

Alexander Kamkin - Leading Researcher, ISP RAS

Nick Kossifidis - Principal Research Engineer, ICS-FORTH

Paul Loewenstein - Senior Technologist, WesternDigital

Allen Lu - AI compiler manager, Peakhills GroupCorporation

Arjun Menon - Senior Project Officer, IIT Madras |Shakti Project

Sandro Pinto - Research Scientist and InvitedProfessor, Universidade do Minho

Jim Straus - Senior Consulting Engineer, ImperasSoftware

Greg Sullivan - Chief Scientist, Dover Microsystems

Weifeng Zhang - Chief Scientist of HeterogeneousComputing, Alibaba Group

Code Size of RISC-V versus ARM using theEmbench™ 0.5 Benchmark Suite: What is theCost of ISA Simplicity?

12:50pm - 1:10pmHardware/Architecture


Some wonder whether RISC-V can really be anindustrial strength instruction set given that it is somuch simpler than ISA alternatives, such as ARMv7and ARMv8. There is not only questions ofperformance but also of code size, which isparticularly important for embedded computing andIoT device. One obstacle to measuring code size andsettling this issue has been the lack of an openbenchmark for embedded computing that is widelyquoted and believed to be representative of realapplications.

At the RISC-V Summit in Zurich this year weannounced Embench™ (for Embedded Benchmark), abenchmark suite of 20 real programs for embeddedIoT devices created by experts from both academiaand industry.

This talk evaluates the code size impact of the simplerRISC-V ISA versus ARMv7 and ARMv8 using Embench0.5 and multiple compilers for each ISA, answering theseveral open questions, including:

• How much of an impact is the compiler versus theISA?

• What is the performance impact of optimizing forsmallest code size?

• What is the impact on code size if we addedregister spilling and restoring instructions onprocedure entry/exit to RISC-V?

In addition to answering interesting questions likethose above, these results demonstrate the benefit ofa realistic and open benchmark for embeddedcomputing, so that future publications of performancefor embedded computers will more likely includeEmbench along with the older, single, syntheticbenchmarks of Dhrystone and CoreMark.

Authors: David Patterson (UC Berkeley), JeremyBennett (Embecosm),Palmer Dabbelt (SiFive), Cesare Garlati (Hex FiveSecurity),and Ofer Shinaar (Western Digital)

All Access or Conference pass required to attendConference sessions.

Participants

David Patterson - Vice Chair, RISC-V Foundation





https://tmt.knect365.com/risc-v-summit/poster-sessions-december-10

Emerald Sponsor Microchip presents: Gettingstarted with PolarFire SoC

12:50pm - 1:10pmSecurity/Verification

Location: Grand Ballroom 220-B

In this session you will learn how to start your firstdesign on PolarFire SoC. You will learn how toconfigure PolarFire SoC’s Microprocessor Subsystemin the Libero SoC Design Suite, develop bare-metalembedded projects on SoftConsole DevelopmentEnvironment and debug them on a PolarFire SoCVirtual Machine (Renode).


Participants

Speaker: Hugh Breslin - Design Engineer, MicrochipTechnology

Speaker: Anton Krug - Development Engineer,Microchip Technology

Linux on RISC-V -- Fedora and Firmware StatusUpdate

12:50pm - 1:10pmSoftware

Location: Grand Ballroom 220-C

Summarize Fedora on RISC-V development includingthe little history, current status and some simple stepsdescribing how to run Fedora on QEMU,FPGA board orthe SiFive RV64 development board. Meanwhile,provide the status of current Specs andfirmware(OpenSBI/UEFI/uboot) for RISC-V and thekernel development statu


Participants

Speaker: Wei Fu - Software Engineer, Red Hat

Every CPU Cycle Counts



RISC-V is being used in complex real-timeheterogeneous systems. The software executing onsuch systems needs to be tuned to provide the bestperformance possible. In such cases every processorcycle counts. Developers will need as much non-intrusive insight as possible into the operation of thesoftware and its interaction with the underlyinghardware structures, including NoCs and of courseCPUs, to make it as efficient as possible. One keyelement of this system-level fine-tuning is the ability tohave cycle accurate processor trace which providesinformation on how many cycles the code is taking toexecute, whether there are stalls and dependenciesand how long they last. Armed with this information,designers of these critical systems can make furtheroptimizations and achieve substantial efficiency gains.

This presentation will outline a cycle accurateinstruction trace encoder algorithm which has beenimplemented using as the primary input the interfaceproposed in the Processor Trace working group. Thepresentation will illustrate how the encoder'scapabilities - including filtering, matching and SoC-wide cross-triggering - can be used to producesignificant improvements in overall systemperformance.


Participants

Speaker: Gajinder Panesar - CTO, UltraSoC

Speaker: Iain Robertson - VP Engineering, UltraSoC

Architectural Extensions for a RISC-VProcessor for Embedded Security



RISC-V is rapidly becoming a mainstream class ofprocessor, due to its simplicity and being freelyavailable without royalties. In the embedded space theRISC-V standard provides very little in terms ofsecurity, only simple memory protection. In this talk Iwill describe how we started from a standard RISC-Vprocessor and developed a world-class embeddedprocessor suitable for running security applications,such as iSim for embedded SIM cards.


Participants

Speaker: Tariq Kurd - CPU Architect, Huawei UK

Headline Sponsor Western Digital presents:GCC Compiler: Code Size Density



In this session we wish to present: why this challengerises on RISCV, the research we did with on this topic,and finally presenting one of the solutions wepromoted, along with future plans.


Participants

Speaker: Nidal Faour - Staff Engineer, R&D Engineering- Firmware & Toolchain, CTO Group, Western Digital

Speaker: Ofer Shinaar - Manager, R&D Engineering –Firmware & Toolchain, CTO Group, Western Digital

A RISC-V ISA Extension for Ultra-Low PowerIoT Wireless Signal Processing



This work presents an instruction-set extension to theopen-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoTtransceivers. The custom instructions are tailored tothe needs of 8/16/32-bit integer complex arithmetictypically required by quadrature modulations. Theproposed extension occupies only 3 major opcodesand most instructions are designed to come at a near-zero hardware and energy cost. Using Codasip Studio,an instruction accurate (IA) model of the newarchitecture is used to evaluate four IoT basebandprocessing test benches: FSK demodulation, LoRapreamble detection, 32-bit FFT and CORDIC algorithm.Results show an average energy efficiencyimprovement of more than 35% with up to 50%obtained for the LoRa preamble detection algorithm.


Participants

Speaker: Zdenek Prikryl - CTO, Codasip





System-Level Security Verification of RISC-VBased SoCs



RISC-V processors are being incorporated in a widevariety of systems for which security is critical. Thesesystems often contain a mixture of open-source andproprietary hardware IP, firmware, and applicationsoftware. System security depends on thecorrectness of all of these components andvulnerabilities can result from both errors duringsystem integration, and misconfiguration and misuseof hardware security features by firmware andsoftware. For example, hardware-enforced accesscontrol policies for memory regions and peripheralsare typically programmed by privileged firmwareduring boot instead of being fixed in the hardwareitself. Without analyzing the firmware and hardwaretogether, it is impossible to verify that platform-levelsecurity objectives hold. Our talk will review commonsystem-level security issues and provide amethodology to analyze both hardware and softwaretogether leveraging existing pre-silicon simulation andemulation verification flows. We will present a casestudy based on our experience winning the 2019Hack@DAC competition, which involved finding andreporting security bugs that the organizers inserted inboth the hardware and firmware of a RISC-V basedSoC.


Participants

Speaker: Nicole Fern - Senior Hardware SecurityEngineer, Tortuga Logic, Inc.

Open Source Compiler Tool Chains for RISC-V:Past, Present and Future



RISC-V has had a functional GNU compiler tool chainfor the last 6 years. However it is only in the last 2years that the GCC compiler was accepted upstream,the first LLVM tool chains have appeared, and seriouscommercial commitment to optimization has rampedup. This is perhaps not surprising - it is only as siliconimplementations become mainstream reality that onewould expect to see heavy investment in theassociated tools. In this talk we'll look at the newtechniques that are being developed for the GNU andLLVM tool chains. RISC-V is now gaining some of thefeatures and performance that have been standard inother architectures. We'll look at: - support for the bitmanipulation instruction set in the compiler, so thatstandard C and C++ can automatically take advantageof these instructions. - the use of GNU CGEN to allowautomatic generation of assembler, disassembler andISS for standard and custom extensions. - thechallenges of more complex instruction setextensions, such as the 'V' extension. Moreimportantly RISC-V is now starting to pioneertechniques that are not seen in other architecture'stool chains. We'll look at: - generic combinedelimination, a wrapper around GCC and LLVM toprovide iterative compilation and optimal selection ofindividual optimization passes. - LLDB for RISC-V anda generic debug server, the first port of LLDB tosupport bare metal debugging, including forheterogenous multicore systems, whether of differentRISC-V variants or RISC-V and other architectures. -Lockstep debugging, where GDB or LLDB can connectto different versions of a target, such as a simulationmodel and real hardware, running them in lockstep andtrapping any discrepancies. We'll conclude by lookingat the future for open source tool chains, and aroadmap for development that includes support formore instruction set extensions, next generationoptimizations, and research techniques such asinductive logic programming and superoptimization.


Participants

Speaker: Jeremy Bennett - Chief Executive,Embecosm

Software PPA Metrics: Results from Real-worldMCU Security Applications



From a semiconductor hardware perspective,tradeoffs between the three key metrics of Power,Performance and Area (PPA) are well known andcritically important in the optimization of a design. Inthis paper, results from a set of redefined softwarePPA metrics are examined. Based on porting multiplereal-world production microcontroller security andmachine learning applications from Arm Cortex-Mcores to PULPino RISC-V cores, these revisited metricswere studied. Two different security applications, bothfunctioning as independent black box securityenclaves, were analyzed. Using the redefineddefinitions, performance in terms of execution cyclecounts and dynamic instruction pathlength, power interms of silicon dissipation plus memory access typesand rates, and static code size as a proxy for area arepresented and compared.


Participants

Speaker: Joe Circello - Fellow, Chief MCU CorePlatform & Security Architect, NXP Semiconductors,N.V.





An Open and Coherent Memory CentricArchitecture Enabled by RISC-V



There is a dearth of interfaces for efficient attachmentof emerging non-volatile memory and purpose-builtcompute accelerators to processor pipelines. Earlyintegrated microprocessors exposed an off-chip front-side bus to which discrete memory and peripheralcontrollers could attach in a standardized fashion.With the advent of symmetric multiprocessing anddeep caches, this direct connection, together withmemory controllers, has been implemented primarilyusing proprietary on-die technology. Proprietaryinterconnects and protocols hinder architecturalinnovation and are at odds with the open nature of therapidly growing RISC-V movement. In this talk weintroduce OmniXtend, a fully open coherence protocolmeant to restore unrestricted interoperability ofheterogeneous compute engines with a wide variety ofmemory and storage technologies. OmniXtend wasmotivated by the desire to break out of the status quoof prevailing system design and fueled by the urgentneed of the RISC-V ecosystem for a common scale-outprotocol. Our proposed system supports a four-hopMESI protocol and is designed to take advantage of anew wave of Ethernet switches with stateful andprogrammable data planes to facilitate systemscalability. We briefly discuss the protocol operationand show performance measurements of the first everNUMA RISC-V system prototype.


Participants

Speaker: Dejan Vucinic - Director, NVM SystemsArchitecture, Western Digital

The RISC-V Open ISA’s shock Wave ofProcessor Innovation that's Causing a SeismicShift in SoC Verification Requirements



The open RISC-V ISA enables great flexibility ofimplementation with options and custom extensions.This flexibility has great advantages and possibilitiesfor the processor and SoC architects of tomorrowsdevices.

Single source ISA’s of the past addressed theprocessor verification and the general industryverification methods have addressed the rest of theSoC. But with an Open ISA all users and adopters willneed to review the verification flows of the processorand SoC.

This panel will look at the implications of the industryadopting the flexibility of an Open ISA and therequirements for verification and compliance for all.

The panellists’ background and experience cover theperspectives of:

Processor IP developers

SoC system architects

Test tool experts

Simulation experts

Verification experts


Participants

Moderator: Ann Mutschler - Executive Editor/EDA,Semiconductor Engineering

Panelist: Simon Davidmann - CEO, Imperas

Panelist: Richard Ho - Principal Hardware Engineer,Google

Panelist: Emerson Hsiao - Senior VP, AndesTechnology USA Corp.

Panelist: Dave Kelf - Chief Marketing Officer, BrekerVerification Systems

Panelist: Frank Schirrmeister - Senior Group Director,Product Management, System Development, System &Verification Group (SVG), Cadence Design Systems,Inc.

Panelist: Mike Thompson - Director of VerificationEngineering, OpenHW Group

Ruby Sponsor SiFive presents: The OpenSecure Platform Architecture of SiFive Shield

2:20pm - 2:40pmHardware/Architecture.


Modern SoC's require a scalable open platformarchitecture to implement security. SiFive Sheild is anopen, secure plaform architecture that enables whole-SoC security features and lifecycle management.SiFive WorldGuard is integral to flexible, scalablesolution and offers a hardware based multi-domainsecurity solution that encompasses both single andmulti-core applications, for both embedded andapplication processor uses. Integation of coresightcompatible trace and debug rounds out a solutionready to integrate into your next SoC design, includingthose targetted at mission critical uses.


Participants

Speaker: Dany Nativel - Security Director, SiFive

Software Flow for Complex SoC-FPGA



SoC-FPGA devices where both a processor subsystemand an FPGA are integrated into a single monolithicdevice have become popular in recent years.Developing embedded software for such an SoC-FPGArepresents a challenge when compared to developingembedded software for a traditional SoC. Theunderlying hardware platform, while flexible andextensible, is by nature inconstant. Fixed hardwaredescriptions do not apply to SoC-FPGA platformswhere the selection of SoC peripherals areconfigurable and additional functionalities can beadded to the FPGA area of the device. This talkdescribes the embedded software development flowfor a complex SoC-FPGA. The talk will describehardware level configuration, its generated artifactsand how these are integrated into a classic embeddedsoftware development flow.


Participants

Speaker: Cyril Jean - Director, Embedded SystemsSolutions, Microchip Technology





The RISC-V Journey Through Containers to theCloud



Open-source is all around us but there is still animportant part that is controlled behind closed doorsby big companies. Hardware. Risc-V is a free andopen-source architecture that opened one of the lastpieces of the puzzle. Together with software andcontainers, we can have a complete cloud-native stackready for the open-world to come. In this talk we willsee the journey the Risc-V open-source instruction setwent from having initial support for the Goprogramming language thru up-streaming supportlibraries to the requirements on building the softwarethat allowed containers to be ran in this newarchitecture and the roadmap for broad support as afirst class citizen on the cloud.


Participants

Speaker: Carlos Eduardo de Paula - Senior CloudArchitect, Red Hat

Networking Break

3:10pm - 3:40pmNetworking


Avoiding Amdahl's Law: RISC-V ArchitectureExploration for AI & ML Many-core ComputeArrays



Amdahl's Law is a guiding principle for computingarchitecture with regard to parallel computingefficiency for a target workload or application, but inmany AI (Artificial Intelligence) and ML (MachineLearning) applications the workload is not a fixed orstatic task but the fluid interpretation of events againsta baseline model that evolves overtime. RISC-V allowsprocessor architects far greater degrees of freedomwith fine-grained optimization at each node. Individualsingle core performance can be optimized for a giventask with including the use of the latest RISC-V Vectorextensions and/or with custom instructions. Computeclusters can be based on a hierarchical approach withsub-units based on multiple cores configured withinlarger arrays. The analysis and profiling of thesesystems depends on the target application which caninvolve the processing of many, many billions ofinstructions and exposure to real time events. VirtualPlatforms allow designers to run real-world data setscenarios to profile and optimize the computestructures. The reference platform helps define theRTL specifications and also becomes the reference forverification testing. The virtual platform forms thebasis for early software development and is anexcellent pre-silicon evaluation vehicle for prospectivecustomers, developers, and end users.


Participants

Speaker: Simon Davidmann - CEO, Imperas

Introducing Scalable New Core IP for MissionCritical Use



RISC-V Is well suited to the needs of moderncomputing challenges, including mission criticalapplications. The new SiFive mission critical Core IPproduct line is scalable and offers high-performance,incredibly efficient performance and features,including formal verification and secure operation.


Participants

Speaker: Aniket Saha - Director of Product Marketing,SiFive

Speaker: Murali Vijayaraghavan - Principal Engineer,SiFive

Developing with FreeRTOS and RISC-V



The open source (now MIT licensed) FreeRTOS kernelhas helped embedded developers manage thecomplexity of their microcontroller designs for 15years -- during which time FreeRTOS has gained areputation for reliability, ease of use, and responsivesupport. Under the stewardship of Amazon WebServices (AWS), the FreeRTOS project has expanded toinclude MIT-licensed security and connectivity librariesunder Amazon FreeRTOS. In February, AWS announcedofficial upstream support for RISC-V in the FreeRTOSkernel, enabling developers to create new or migrateexisting FreeRTOS-based applications on RISC-Vmicrocontrollers using fully-tested and supportedFreeRTOS kernel libraries. In this talk, Richard Barry,the founder of the FreeRTOS project, will demonstratehow the kernel's extensible architectures enableFreeRTOS to run on a range of RISC-Vimplementations, and how you can integrate securityand connectivity libraries to give your devices OTAcapabilities and connectivity over BLE and Wi-Fi.


Participants

Speaker: Richard Barry - Founder | Principal Engineer,FreeRTOS | Amazon Web Services

Scalable, Configurable Neural NetworkAccelerator Based on RISC-V Core



Neural Network and machine learning are becomingincreasingly popular for a wide variety of applicationsincluding handwriting recognition, object detection,object classification, image recognition, and naturallanguage processing. Recently hardware acceleratorIP for Neural Network applications from differentcompanies has demonstrated that custom hardwareaccelerators for neural network processing canoutperform software implementations in bothperformance and power consumption. However, thereis neither an agreed-upon interface to neural networkaccelerators nor a consensus on neural networkhardware implementations. Hence a scalable,configurable, high performance, hardware architecturefor efficient implementation of machine learningalgorithms on RISC-V is presented in this paper.


Participants

Speaker: Karthik Wali - Staff Digital Design Engineer,LG Electronics





Enabling the Full Power of a MultiprocessorSoC



The use of multicore SoCs in embedded designs is onthe increase and there are multiple incentives for thisdesign decision. In this session, we will review theavailable multicore architectures and show how theyare leveraged with a selection of softwareconfigurations. The use of multiple operating systemson heterogeneous multicore devices will be explored,and how this facilitates the design of systems withmultiple time domains- basically real-time and non-realtime components. Additionally, the concept of mixed-criticality will be introduced- a design approach forsystems where safety and certifiability are keyrequirements. Certification effort and cost can beminimized, while still meeting requirements for theworldwide authorities.


Participants

Speaker: Jeff Hancock - Senior Product Manager,Mentor (a Siemens Company)

Open Source Verification Platform for RISC-VProcessors



Since the initial release of SV/UVM based RISC-Vinstruction generator in RISC-V Summit 2018, we havebeen focusing on building an end-to-end open sourcesolution for RISC-V processor verification. In thissession, we will discuss our recent development onthis effort, including: - New enhancements in theinstruction generator. - A functional coverage modelused for verification signoff. - A highly extendable flowfor end-to-end verification. - A standard UVMtestbench to verify a variety of RISC-V processors. Theaim of this work is to build an ecosystem for RISC-Vprocessor verification, with a great flexibility to supportvarious processor implementations, ISS, RTLsimulator.


Participants

Speaker: Tao Liu - Senior Hardware Engineer, Google

Speaker: Richard Ho - Principal Hardware Engineer,Google

Next-generation IDE for your RISC-V Product in20 Minutes



The embedded market is overwhelmed with thenumber of integrated development environments (IDE)provided by the semiconductor industry. Mostly, theyare based on the same text editor but have ownbranded interface. Working with hardware fromvarious companies requires installing different IDEsand waste time when switching between projects.Developing and maintaining of own IDE needs strongexpertise and financial resources. This moment playsa key role for semiconductor companies who havegreat expertise in creating RISC-V Ñ ores but do notwant to lose time and valuable resources working onanother. PlatformIO is a unique, cross-platform andhardware-agnostic solution that provides developerswith a modern integrated development environmentthat includes advanced embedded instruments fordebugging, unit testing, and remote management.Thanks to its flexible architecture it can be easilycustomized to support any RISC-V core and platform-specific SDK reducing the time required to ship yourRISC-V solution to the market. This showcase willappeal to anyone interested in modern developmenttools for RISC-V products.


Participants

Speaker: Ivan Kravets - CEO, PlatformIO

RISC-V in Practical Education of ComputerArchitecture



RISC-V is the ideal ISA for computer scienceeducation. Beyond basic education of thefundamentals along the ISA, the large number of opensource processor cores allows for a practicaleducation based on those implementations. Anyhow,many computer science curricula do not coverhardware design. The transfer of knowledge likecomplex pipelining or branch predictors to theimplementations is therefore not intuitive. In this talk Ipresent the open source framework and tools thattrace microarchitectural state of complex processorcores like Rocket, Ariane or BOOM and representsthem in an intuitive form. It is a unified approach forhardware simulation and FPGA implementations. Thestudents can run programs and deepen theirunderstanding of the concepts with actualimplementations. The talk will close with an overviewof the Computer Architecture course at MunichUniversity of Applied Sciences and how it can beadopted in other universities or as educationalresource.


Participants

Speaker: Stefan Wallentowitz - Professor, MunichUniversity of Applied Sciences





Democratising Formal Verification of RISC-VProcessors



We present a new formal verification (FV)methodology for RISC-V processor verification usingour ISA formal proof kit developed using the non-proprietary fragment of SystemVerilog Assertionscurrently supporting the RV32IC instruction set. Ourmethodology exploits abstractions and problemreduction techniques to provide guarantees on proofconvergence with any formal verification tool - makingour solution both predictable and scalable.

Our methodology finds the following kinds of bugs:

• Functional• Low-power• X-propagation• Deadlocks• Security• Safety

We deployed our solution to verify a range of 32-bitprocessors from the PULP platform and found newbugs besides establishing end-to-end exhaustiveproofs of correctness. Some of these cores have beenpreviously verified and are running in silicon!

We caught corner-case bugs difficult, if not impossible,to catch in dynamic simulation, with a run time ofseconds. So far, we found 90+ bugs in zeroriscy, and65+ in ibex, indicating functional, safety, security, andpower issues. It takes less than 30 minutes to get 50%of the proofs proven exhaustively, 2 hours for 80%proofs, and the remaining 20% proofs finish in about24 hours depending upon the formal tool used.

For DV engineers, being able to find bugs (corner-case)and proofs using any formal tool without writing asingle line of verification code is a significantmilestone for RISC-V processor verification. Beingvendor-neutral, it has the potential to enable moredesigners and verification engineers to adopt FVproviding a way to democratize the formal verificationof RISC-V processors!


Participants

Speaker: Ashish Darbari - CEO, Axiomise Limited

SEGGER presents: Visualizing and Recordingthe true Runtime Behavior of a RISC-V basedApplication -- in real-time



What if you could take debugging your RISC-V basedembedded system far beyond the system insightsprovided by a regular debugger? What if you couldensure your system performs as designed, track downinefficiencies, and show unintended interactions andresource conflicts? And what if you could do all this inreal-time, and for free?

This 20-minute presentation shows attendees howthey can achieve all this, using SystemView.SystemView is a free real-time recording andvisualization tool for embedded systems that revealsthe true runtime behavior of an application. Untilrecently, SystemView had only been available for Arm-based systems. However, now that SEGGER addedRISC-V System Bus Access support, which in turnenabled the use of SEGGER’s unique Real-TimeTransfer (RTT) technology, SystemView has now finallyalso become available to RISC-V users. RTT enableshigh-speed data transfer for continuous extraction ofreal-time data, requiring no hardware other than a J-Link and the standard RISC-V debug interface.

SystemView offers cycle accurate tracing of interruptsand task start-stop as well as task activation and APIcalls when an RTOS is used. It visualizes and analyzesCPU load by task and interrupts and scheduler. Using aJ-Link debug probe with SystemView provides theultimate advantage of streaming data transfer:Recording and analysis in real-time, working as a livesoftware oscilloscope. This is a great means to gain adeep understanding of the runtime behavior of anapplication.

SystemView records the data retrieved from the targetand visualizes the result in different ways. Datarecordings can also be saved for later documentationand analysis. Evaluating a system this way isextremely helpful in finding and eliminating problemsor simply optimizing the system. It is an essential partof quality management in any professional softwaredevelopment.


Participants

Speaker: Axel Wolf - Sr. Staff Field ApplicationsEngineer, SEGGER Microcontroller LLC

The Next Generation of GAP8: An IoTApplication Processor for Inference at the VeryEdge



The talk will introduce the audience to GreenWavesTechnologies' next-generation IoT Applicationprocessor. It will explore the customer applicationsthat have driven the feature evolutions from GAP8 andlook at how the chip's new features drive the energylevels needed to do edge inference down to a newlevel. The talk will also look at how RISC-V hasenabled GreenWaves to tape out our next-generationchip in a state of the art process and look at how thatcontributes to our ability to drive power consumptiondown at the edge. We are unable to share furtherdetails at this point since the product will be launchedat the RISC-V Summit.


Participants

Speaker: Martin Croome - VP, Business Development,Greenwaves Technologies





RISC-V and a Meta-framework SecurityCertification Approach for a Secure ConnectedWorld



This talk will show the advances that have been madeon generating a unified certification for SecurityDevices, it will show the NXP plans for certifying RISC-V based devices. NXP along with industry partnerscreated a certification methodology called SESIP(Secure Evaluation of Security IoT Products). SESIP isan industry led initiative to generate an optimized user-friendly certification process for connected products.The aim is to create a worldwide testing andcertification approach to ensure that connecteddevices are tested and labelled, to make secure bydesign principals the core building block of theconnected IoT products, Industrial, Automotive, IoT,etc. The main asset of SESIP is that it can be used tobring the various security certification standardstogether and act as a physical manifestation of themeta-framework approach as detailed by ECSO. It isalso IP agnostic and therefore fits well with the RISC-Vambitions. This talk will show what SESIP is, how itcan link various standards and certificates togethere.g. CC (SOG-IS and iTC), UL 2700, ICA (China), IEC62443 etc. SESIP can also benefit industry ledinitiatives e.g. Charter of Trust, IoXT pledges etc,ENISA IoT requirements.


Participants

Speaker: John Boggie - Director, Head ofCybersecurity Certification, NXP Semiconductors

Code Density Improvements Beyond The CStandard Extension



The emergence of the RISC-V architecture has givenrise to a demand for widely differing microarchitecturalimplementations, ranging from deeply embeddedmicrocontrollers to DSPs to superscalar processors.Efficient code density is important in almost everyapplication domain; however, it is critical in deeplyembedded microcontroller and DSP applications asthe available address space is often quite limited.The RISC-V specification addresses code density viathe C extension, yet the ABI definition and currentimplementation of C extension lack certain usefulfeatures. Consequently, code size can be 20-50%higher than that of competing ISAs. The Codasipapproach to delivering RISC-V processor IP is toemploy the silicon-proven methodology of the high-level CodAL architecture description language and itssuite of tools called Codasip Studio to implementvarious RISC-V microarchitectures and optimize andextend instruction sets. Using Codasip Studio (anEclipse-based integrated processor developmentenvironment), the leading toolset for RISC-V ISA andABI customization, we have implemented severalimprovements to the C extension so that this codesize disadvantage has been eliminated. In thispresentation, we will demonstrate the work done todate to improve code density for our customers,including the addition of new instructions andimprovements to the ABI such as inclusion of moreregisters. Additionally, we have made optimizations tothe LLVM compiler such as the save-restoremechanism. We will compare results using severalbenchmarks and examine PPA. These findings willbenefit the entire RISC-V ecosystem.


Participants

Speaker: Zdenek Prikryl - CTO, Codasip

Welcome Happy Hour







TIME EXPO HARDWARE/ARCHI-TECTURE

HARDWARE/ARCHI-TECTURE.

KEYNOTES NETWORKING POSTER GALLERY REGISTRATION SECURITY/VERIFI-CATION

SOFTWARE

8:00AM 8:00am - Registra-tion

9:00AM 9:00am - WelcomeAddress: Exponen-tial Progressacross Industriesand Around theWorld with RISC-V

9:20am - State ofthe Union

10:00AM 10:00am - Un-shackling Memory!

10:20am - Open forBusiness: True Sto-ries of How FarWe’ve Come Withthe RISC-V Ecosys-tem

10:40am - Light-ning Talks featur-ing Chronos Tech,Solid Sands andThink Silicon

10:50am - RISC-Vof Samsung in theAge of 5G and AI

11:00AM 11:30am - ExpoHall

11:10am - RubySponsor SiFive pre-sents: Taking RISC-V into New Markets

11:30am - LunchBreak

11:30am - PosterGallery on ExpoFloor

SCHEDULETUESDAY, DECEMBER 10 - 10/12/2019







SOFTWARE

12:00PM 12:50pm - CodeSize of RISC-V ver-sus ARM using theEmbench™ 0.5Benchmark Suite:What is the Cost ofISA Simplicity?

12:50pm - EmeraldSponsor Microchippresents: Gettingstarted with Po-larFire SoC

12:50pm - Linux onRISC-V -- Fedoraand Firmware Sta-tus Update

1:00PM 1:20pm - EveryCPU Cycle Counts

1:50pm - A RISC-VISA Extension forUltra-Low PowerIoT Wireless SignalProcessing

1:20pm - Architec-tural Extensions fora RISC-V Processorfor Embedded Se-curity

1:50pm - System-Level Security Veri-fication of RISC-VBased SoCs

1:20pm - HeadlineSponsor WesternDigital presents:GCC Compiler:Code Size Density

1:50pm - OpenSource CompilerTool Chains forRISC-V: Past, Pre-sent and Future

2:00PM 2:00pm - SoftwarePPA Metrics: Re-sults from Real-world MCU SecurityApplications

2:20pm - An Openand CoherentMemory Centric Ar-chitecture Enabledby RISC-V

2:50pm - SoftwareFlow for ComplexSoC-FPGA

2:20pm - RubySponsor SiFive pre-sents: The OpenSecure Platform Ar-chitecture of SiFiveShield

2:20pm - The RISC-V Open ISA’s shockWave of ProcessorInnovation that'sCausing a SeismicShift in SoC Verifi-cation Require-ments

2:50pm - The RISC-V Journey ThroughContainers to theCloud








SOFTWARE

3:00PM 3:40pm - AvoidingAmdahl's Law:RISC-V ArchitectureExploration for AI &ML Many-coreCompute Arrays

3:50pm - Scalable,Configurable Neur-al Network Acceler-ator Based onRISC-V Core

3:10pm - Network-ing Break

3:40pm - Introduc-ing Scalable NewCore IP for MissionCritical Use

3:40pm - Develop-ing with FreeRTOSand RISC-V

4:00PM 4:10pm - Enablingthe Full Power of aMultiprocessorSoC

4:40pm - RISC-V inPractical Educationof Computer Archi-tecture

4:10pm - OpenSource VerificationPlatform for RISC-VProcessors

4:40pm - Democra-tising Formal Verifi-cation of RISC-VProcessors

4:10pm - Next-generation IDE foryour RISC-V Prod-uct in 20 Minutes

4:40pm - SEGGERpresents: Visualiz-ing and Recordingthe true RuntimeBehavior of a RISC-V based Applica-tion -- in real-time

5:00PM 5:10pm - The NextGeneration ofGAP8: An IoT Appli-cation Processorfor Inference at theVery Edge

5:30pm - WelcomeHappy Hour

5:10pm - RISC-Vand a Meta-framework SecurityCertification Ap-proach for a SecureConnected World

5:10pm - CodeDensity Improve-ments Beyond TheC Standard Exten-sion





Registration


Welcome




RISC-V and Chips Alliance Address newCompute Requirements



CHIPS (Common Hardware for Interfaces, Processorsand Systems) Alliance harnesses the energy of opensource collaboration to accelerate hardwaredevelopment. CHIPS Alliance develops open sourcehardware and software development tools relevant tosilicon devices and FPGAs. By creating this open andcollaborative environment, CHIPS Alliance sharesresources which lower the cost of development for it’smembers. Companies, universities and individuals canwork together to develop high quality open sourceCPUs, complex IP blocks and software developmenttools. The organization has several work groups andhas already delivered software contributions toFuseSoC, Verilator and Cocotb. CHIPS Alliance is opento all organizations who are interested in collaboratingon open source hardware or software tools toaccelerate the creation of chip designs. Leadingorganizations such as Google, Western Digital,Alibaba, SiFive, Antmicro, Esperanto, Codasip, Metricsand Imperas are part of CHIPS Alliance.


Participants

Speaker: Zvonimir Bandic - Sr. Director, Next GenPlatform Technologies | Chairman of the Board, CHIPSAlliance, Western Digital | CHIPS Alliance

Speaker: Dejan Vucinic - Director, NVM SystemsArchitecture, Western Digital

An Open Source Approach to System Security



RISC-V provides a relative "clean slate" when it comesto designing systems. However, while general securitymeasures can benefit from an open source approach,specific use cases may require proprietary securitymeasures to address the particular needs of thatsystem. It's common knowledge that sharingspecifications with peers can advance developmentand testing more effectively than most proprietarymethods. But where do you draw the line betweendeveloping your own security measures andcontributing to the common good? What are the risksof open source, especially in security? Whatframeworks are required to ensure that the mostsensitive parts of the system are protected whileleaving some security aspects more open? This talk byRambus Security Technologies Fellow, HelenaHandschuh, will discuss these issues and howRambus ensures appropriately secured cores.


Participants

Speaker: Helena Handschuh - Rambus Fellow & Chair,RISC-V Foundation Security Standing Committee,Rambus

How RISC-V made the Quick Jump fromAcademia to Industry and Why it will Changethe Entire Semiconductor Industry - a VentureCapital perspective



What convinced Sutter Hill Ventures to invest in SiFivebefore the RISC-V foundation or SiFive even existed ?Where are the opportunities for startups in the RISC-Veco-system going forward and what are VCs looking tofund ? How will open standards and automationchange the semiconductor business model of thefuture ? Stefan Dyckerhoff is a Managing Director atSutter Hill Ventures, the first investor in RISC-V and thecompany's founding CEO and current Chairman.


Participants

Speaker: Stefan Dyckerhoff - Managing Director,Sutter Hill Ventures

Open Source Processor IP for High VolumeProduction SoCs: CORE-V Family of RISC-VCores



This keynote session will describe the CORE-V familyof open-source cores that implement the RISC-V ISA.CORE-V (pronounced core-five) is a series of RISC-Vbased open-source processor cores with associatedprocessor subsystem IP, tools and software forelectronic system designers. The CORE-V familyprovides quality core IP in line with industry bestpractices in both silicon and FPGA optimizedimplementations. These cores can be used tofacilitate rapid design innovation and ensure effectivemanufacturability of production SoCs. RISC-V is anopen, free ISA enabling a new era of processorinnovation through open standard collaboration. Bornin academia and research, RISC-V ISA delivers a newlevel of extensible software and hardware freedompaving the way for the next 50 years of computingdesign and innovation.

The session will describe barriers to adoption of open-source IP and opportunities to overcome thesebarriers. The talk will also include a roadmap andcalendar 2020 goals for the CORE-V Family.


Participants

Speaker: Rick O' Connor - Founder, President & CEO,OpenHW Group

SESSIONSWEDNESDAY, DECEMBER 11 - 11/12/2019




Keynote Panel: Opportunity and Risks in OpenSource Hardware



Open-source hardware is the most disruptivemovement in the electronics industry since open-source software. It may also be the most influentialsince early observations of Moore’s Law.

While it has existed in various forms for decades,turbulence in the high-tech market has seen open-source hardware evolve from hobbyist components tomass-produced, mainstream technologies. As wereach the physical limitations of transistor scaling,open-source hardware is poised to upend the multi-trillion-dollar tech industry by providing a scalable,cost-effective, and application-optimized path forward.

But as experienced in the open-source softwarephenomenon, open source hardware is not without itschallenges. First, what is the definition of open-sourcehardware, and what classifies as such? Next, how doorganizations navigate the temptations of “Free” tocalculate the true costs of developing a system basedon open-source hardware? And once you’re finallydeveloping open-source hardware products, how doyou protect yourself from patent disputes.

For open source hardware, it’s still the Wild West. Thiskeynote panel addresses how leaders in open-sourcehardware are innovating today, and preparing forwidespread adoption tomorrow.


Participants

Panelist: Krste Asanovic - Professor | Chief Architect,UC Berkeley | SiFive

Panelist: Mendy Furmanek - IBM Director –OpenPOWER Processor Enablement; OpenPOWERPresident, IBM

Panelist: Joseph Jacks - Founder and CEO, OSSCapital

Moderator: Brandon Lewis - Editor-in-Chief, OpenSystems Media

Panelist: Tim Whitfield - VP Strategy Embedded andAutomotive, ARM

Qualcomm Diamond Sponsor Session: GlobalAmbitions for RISC-V




Participants

Moderator: Calista Redmond - CEO, RISC-V Foundation

Panelist: Travis Lanier - Senior Director, ProductManagement, Qualcomm

Panelist: Rob Oshana - VP Software Engineering, NXP

Panelis: Yu Pu - IoT SOC Lead, Alibaba

Expo Hall

11:30am - 4:00pmExpo


Lunch Break

11:30am - 12:50pmNetworking


Poster Gallery on Expo Floor

11:30am - 4:00pmPoster Gallery

Open to All Pass Types: Poster Gallery located at theheart of the Expo Floor. New and different posterseach day!

Stop by the Gallery to view and discuss the work ofyour colleagues in this informal, relaxed setting.

Poster Gallery Schedule

11:30 a.m.-1:45 p.m.

The RISC-V in Implantable Medical Devices

RISC-V Compliance suite: Ensuring maximum softwarereuse with device compatibility, the defining qualitytest for a RISC-V Processor

Integrating RISC-V Instruction Set Simulator (ISS) withSystemC

A Vehicle Security Surveillance System Based on aRISC-V Processor

Pre-silicon Detection of Hardware Trojans and SecurityVulnerabilities in RISC-V Cores

The RISC-V Orbital Space Lab Satellite Payload basedon a Fault-Tolerant Processor Core with HardwareThread Full/Weak Protection and Thread-ControlledWatch-Dog Timer

1:45-4 p.m.

Graphics Processing Extension RISC-V

JIT Superoptimization on RISC-V via SymbolicExecution

RISC-V Based Security Co-Processors for MissionAssurance Architecture

Trustworthy Systems: From The ISA On Up

On the seL4 Center of Excellence

View all poster descriptions here >>

Participants

Alfredo Arnaud - Dr.Eng, Professor, UniversidadCatólica del Uruguay

Sven Beyer - Product Manager Design Verification,OneSpin Solutions

Donato Kava - Associate Staff, MIT Lincoln Laboratory

Lee Moore - Lead Engineer, Imperas

Boris Shingarov - Senior Software Designer, Labware

Umesh Sisodia - SMTS, Circuitsutra Technologies PvtLtd

Francesco Vigli - Digital Hardware Designer, AizoOnGroup





https://tmt.knect365.com/risc-v-summit/poster-sessions-december-11

Adam Wiethuechter - Software Engineer, CriticalTechnologic Inc.

Shaomin Xiong - Technologist, Western Digital

Atif Zafar - CEO, Pixilica

Enabling AI on Low Power Endpoint DevicesUtilizing the QuickLogic and SiFive FreedomAware Templates



Battery-powered intelligent IoT devices require sensordata collection, analysis, & AI in order to determineactionable insights within a power-constrainedenvironment. Most applications today send endpointsensor data to the cloud for processing, which putsstress on the system's network & power requirements,adds latency and reduces security. Implementing AIdirectly at the endpoint solves these challenges buthas been impractical for most applications due to alack of efficient hardware and quality developmenttools dedicated to addressing the significant resourceconstraints of endpoint computing devices. TheFreedom Aware Templates, co-developed byQuickLogic and SiFive, optimize multiple RISC-V coresto balance power and performance to bring moreintelligence to endpoint devices. This presentationwill focus on predictive maintenance applications andhow the Freedom Aware Templates, and theircomplete AI endpoint development tools fromSensiML, offer much needed flexibility in hardwaredesign to enable the building of highly efficientsolutions while reducing development time and cost.Attendees will learn about: - Generating AI sensingalgorithms using SensiML toolkit for RISC-V baseddesigns to support predictive maintenance 4.0. - Lowpower design techniques to support always-onsensing - The flexibility of templates to create fastertime-to-market and reduced silicon developmentcosts.


Participants

Speaker: Brian Faith - CEO, QuickLogic Corporation

Formal Methods for Hardware-SoftwareIntegration on RISC-V Embedded Systems



Traditional systems integration of software, compilersand hardware relies on documentation which is oftenimprecise and incomplete, and on extensive testing,which can never cover all possible scenarios. Wepropose a way to improve this tedious and error-proneprocess: We augment a formal machine-readablespecification of the RISC-V ISA with platform specificdetails until it becomes precise enough to capture allassumptions the software makes about the hardware,and vice versa. Using a unified language forspecification, implementation, and verification calledCoq, we show how a C to machine code compiler canbe used on a simple pipelined RISC-V processor tobuild an IoT device, where all the assumptions thevarious systems make about each other are writtendown in a precise, machine-readable language andverified by a proof checker. This allows us to prove endto end correctness guarantees, where the interfacespecifications need not be considered any more inorder to know how the overall system behaves. Wehave a prototype IoT device running on an FPGAconnected to a light bulb and a network card todemonstrate the feasibility of our approach.


Participants

Speaker: Samuel Gruetter - PhD student in ComputerScience, MIT

RISC-V Software State of the Union



RISC-V hardware has taken the world by storm; RISC-Vsoftware is racing faster than Roadrunner from Wile ECoyote to catch up . This is a somewhat ironicsituation, given that ultimately it is the RISC-V softwareecosystem that will determine the success of theRISC-V platform, not the hardware. This talk overviewsthe current state of the union of RISC-V software. Thatstate includes views into progress made in softwarepast, glimpses into goals and plans for the softwarefuture, and proposals and ideas for how the RISC-Vsoftware community can better work together to drivethe ultimate success of the RISC-V revolution.


Participants

Speaker: Randy Allen - VP, RISC-V Software, SiFive

RISC-V For Heterogeneous Computing



During the Zurich Workshop we share the view thatRISC-V software ecosystem needs to reach beyonddevice SDK and into the cloud management platformas well as the application. In this talk we want toshare a more general view of the RISC-V ecosystembuilding in heterogeneous computing, not only in thesense of domain specific accelerators but also in therealm of edge computing, urban computing, serverlesscomputing, etc. We will talk about extensive RISC-Vsupport for things like new types of compiler (MLIR,Ark), new platforms (ONNX runtime), and newinterfaces (WASI)


Participants

Speaker: Justin Cormack - Security Lead, Docker

Production-ready RISC-V Support in LLVM/Clang 9.0 - How we Got There and What's Next



LLVM/Clang 9.0 is due to ship at the end of August. Itmarks a major milestone for RISC-V support in theproject, with the RISC-V backend promoted from"experimental" to an "official" target, with full supportfor RV32GC/RV64GC with hard or soft-float ABIs, anda demonstrated ability to build a large corpus ofprograms (e.g. a complex Linux rootfs, ~80% ofbuildroot applications). This effort has been led byAlex Bradbury at lowRISC CIC (upstream code ownerand primary author), and has attracted a growingcommunity of contributors. This includes engineersfrom a range of RISC-V Foundation membercompanies representing a real success story forcollaboration within the RISC-V ecosystem. This talkwill present the current status, give directions on howto get started, and look ahead to the future. It willdiscuss selected topics such as: work with the Rustcommunity, challenges of building a Linux rootfs withClang, latest figures on code size comparisons angenerated code performance, documentation /teaching materials, and experimentation withproposed instruction set extensions such as thebitmanipulation extension. [Although I have presentedon RISC-V LLVM are previous events, this talk willoverlap only in basic introduction. The focus is on thedevelopment that has taken place since then tomature the toolchain, support typical Linuxapplications, and alternative frontends such as Rust].


Participants

Speaker: Alex Bradbury - Director, lowRISC CIC





Ruby Sponsor SiFive presents: The SiFiveVector Processor



The migration of deep learning from the datacenter tothe edge and end point includes the use of neuralnetworks to process speech in handheld devices. Withthe SiFive Vector Processor you can create power-sipping cores with scalable vector processingcapabilities to enable voice and audio processing anddecision making, and other applications.


Participants

Speaker: Mark Throndson - Senior Director of ProductManagement and Marketing, SiFive

SweRV Cores Roadmap



RISC-V Instruction Set Architecture (ISA) has becomea key driver of open source hardware projects. Mostrecently we have for example seen a lot ofapplications in the Internet of Things (IoT),microcontrollers for a variety of traditional embeddedapplications, and applications requiring capability forlow power operation of Artificial Intelligence (AI)inference engines based on artificial neural networks.We have recently developed a super-scalar (2-way),9-stage pipeline, mostly in-order, open-source corebased on the RISC-V RV32IMC instructions set, namedSweRV EH1 (see Figure 1). It initially targets in-houseembedded Storage System on Chip applications. Wepresent some of the architectural details of the coreand implementation challenges, as well as discussapplication of the core for the Flash controllers. Wealso report performance measurements of Coremarkand Dhrystone benchmarks, which are traditionallyused for embedded core performance benchmarking.In this presentation, we will present a RISC-V coreroadmap (Figure 3) from Western Digital, introducing a2nd generation of SweRV cores: SweRV EH2, which ishigh performance upgraded SweRV EH1 core, andhighly power efficient small core SweRV EL2. Wediscuss architecture and performance details of thecores, and discuss a spectrum of embeddedapplications.


Participants


Speaker: Robert Golla - Senior Fellow, Western Digital

RISC-V Enclaves: A Clean Slate Approach ToLinux Security



When it comes to security, less is more. Linux enclaveshave historically suffered from an excess ofcomplexity and overhead that has constrained theiradoption to regulated markets and resulted in manyhigh-profile failures. With RISC-V, the basic securitybuilding blocks for running trusted workloads onuntrusted systems are built into the ISA. What ismissing is a simple and robust open standardframework that software developers can use to buildsecure applications without requiring in-depth securityknowledge. In this presentation, Cesare Garlati -Founder of Hex Five Security and long time member ofthe RISC-V Foundation - will introduce the concept ofan innovative enclave for RISC-V systems, itsunderlying zero-trust computing model, and will showan actual real-world example of deterministicexecution of mixed-criticality systems on actual multi-core RISC-V hardware. Garlati will present the free andopen standard enclave for Linux as a proposedstandard for adoption in the RISC-V community andbeyond. The multi zone enclave is like Docker at thechip level: it presents a minimalist API structuresuitable for a thin, formally verifiable micro kernel,secure communications across enclaves, peripheralsinterrupt mapping, and trap & emulation for secureexecution of micro-services. The proposed multi zoneAPI scales from tiny single core MCUs, used insensors and IoT devices, to multi-core SMP Linux, toAMP mixed applications for safety-critical, aerospaceand defense applications. The free and open standardAPI is provided as a combination of a simple datamodel and relative C header file that can beimmediately adopted as de-facto standard by industryand academia. Note for the program committee: -This session can be delivered as an hands-on tutorialto show step-by-step how to configure, build, and run acommercial-grade enclave on actual RISC-V hardware(SiFive U540 or Microsemi PolarFire). - The free andopen multi zone API for Linux is licensed for any useunder ISC permissive terms and freely available athttps://github.com/hex-five/multizone-api. -Presenter;s bio including recent public speaking:https://bringyourownit.com/about-cesare-garlati/


Participants

Speaker: Cesare Garlati - Co-Founder, Hex FiveSecurity

seL4 on RISC-V: Verified OS for True Security

1:50pm - 2:10pmSecurity/Verification.


We will present the port of seL4, the world;s firstoperating-system (OS) kernel with a correctness proof,and arguably the world's most secure general-purposeOS kernel, on to RISC-V. By the time of the summit, theformal verification of seL4 on RISC-V (scheduled forOctober) should be concluded, including the proof ofimplementation correctness and the tool chain forproving the correctness of the compiler output. Wealso have support for the draft hypervisor extensionsto the point that seL4 can boot Linux in a virtualmachine. The talk will report on our experience withthe RISC-V ISA in terms of functionality as well as easeof verifying software on top of it.

Session co-creators: Raf Kolanski, Leader, ProofEngineering Team, Data61 and Gernot Heiser,Professor UNSW Sydney

Participants

Speaker: Gernot Heiser - Professor UNSW Sydney andseL4 Evangelist, Data61, Data61 and UNSW Sydney





Processor IP Showcase with AndesTechnology, CHIPS Alliance, Codasip, ShaktiProject, SiFive, Syntacore, OpenHW Group



In the RISC-V community there are several RISC-V coreproducers who supply cores with varying degrees ofcapabilities. This session brings together thesesuppliers and gives them the opportunity in 5 minutesessions to reveal the capabilities of their current andfuture products. This session is open to bothcommercial and open-source suppliers of RISC-Vcores.

Organizations Presenting: Andes Technology, CHIPSAlliance, Codasip, Shakti Project, SiFive, Syntacore,OpenHW Group


Participants

Speaker: Kevin Chen - Senior Architect, AndesTechnology

Speaker: Drew Barbier - Sr. Manager, SiFive Core IPProduct Marketing, SiFive


Speaker: Karel Masarik - CEO and Founder, Codasip

Speaker: Arjun Menon - Senior Project Officer, IITMadras | Shakti Project

Speaker: Alexander Redkin - Executive Director, Co-Founder, Syntacore

Speaker: Rick O' Connor - Founder, President & CEO,OpenHW Group

Moderator: Gajinder Panesar - CTO, UltraSoC

Speaker: Anand Joshi - Anlayst, Computer Vision & AI,Tractica

Break




Integrate RISC-V to build Open CommonAutomotive Platform



In recent years we can see vehicles in evolution. Therapid explosion in the today’s automobiles withaddressing the complex E/E systems are designedwith more than 70 ECU, even 100. In the future theautomotive industry will continue developing ADAS toeither enable connected vehicles or self-driving carwith many new hardware components and softwarecomponents. The automotive industry needs tovirtualize in-vehicle systems and AMP at this point inits development. Vehicles have become increasinglydependent upon more power microprocessors andsystems over the years in order to provide for the useof advanced technologies for driving complex head-units, hundreds of ECM’s, electronic dashboards,diagnostics, telematics, autonomous driving,infotainment systems, electric charging, and V2Xscenarios. Time to market is critical and technologymust be used to reduce the product design cycle, notincrease it. Here we are trying to bring out HW-assisted virtualization solution and AMP framework toaccelerate this evolution with addressing somesignificant challenges: • Software Defined Modern Car– Flexibility, interoperability and compatibility • Costs –Software and hardware consolidations • Security --Isolation for different domain • Mixed criticality -- ASIL• Decoupled license issue specific to App – supportingeasily different Apps align with Linux, Android,commercial RTOS, etc • Automotive Edge Computing –Put cloud management down to edge inside car. So,with this poster, our mission is to explore how todesign a next generation automotive platform basedon RISC-V with the enterprise virtualization thatguarantees secure isolation, maintenance,interoperability, flexibility while ensuring highperformance, open standards and intelligence. Weprobably can make a complex SOC with RISC-V toprovide a single multiple core platform where we’d liketo lead such a BoF discussion of if we can integrateheterogeneous architectures like other CPU arches,GPU, FPGA, etc to build one common open sourceautomotive platform.


Participants

Speaker: Tiejun Chen - Technical Leader and StaffEngineer, VMware

RISC-V: A New Zero-Trust Model for CyberResilient Avionics



This paper presents a 'zero trust' Avionics SecurityArchitecture (ASA) developed by Northrop GrummanAerospace Systems (NGAS). The ASA utilizes RISC-Vand Hex-Five multi zone security as a key componentsof a layered defense to implement a robust, cyberresilient and adaptable system for both manned andunmanned aircraft. The Cyber Resilient VehicleManagement System (CRVMS) group in San Diego,California is developing the ASA to provide end to endFlight Security for an operational mission. The ASA istransitioning to TRL Level 4 (Summer 2019). Thesecurity of an operational mission is centered in theVehicle Management Computer (VMC), also known asthe flight computer, and is extended to all phases ofthe mission: including the development of the OFP(Operational Flight Program) software, the MissionPlan (for unmanned vehicles) and communicationswith the Ground Stations. The security of the datarequired to support the operational mission isanchored in a Trusted Factory (TF). The TF managescrypto keys and digital security certificates throughend-of-life. Together, the VMC and the TF implementend to end security coverage in a cyber-contestedenvironment.


Participants

Speaker: Kevin Kinsella - System Architect, NorthropGrumman





Different Trace Methods and Efficient Ways toUtilize Them



Full application trace give endless possibilities toanalyze your products behavior. With complete insightinto your application, you can track every singleinstruction. How could you best utilize the advantageof trace that is now available for RISC-V? We willexplore a holistic approach to trace using severalpossible data sources. However, collecting the data isnot enough, you will also need to find ways to filter theinformation into actual knowledge and insights and wewill discuss different approaches to overcome thischallenge. Visualizing and analyzing using differenttrace viewers creates a true description of yourproduct (as it runs) and its dynamic behavior. Thisdescription will provide valuable insights, and the endresult will be achieving the goal of tracking downcomplex bugs that would be hard, or even impossible,to find in a standard debug scenario.


Participants

Speaker: Thomas Andersson - Product Manager, IARSystems

Speaker: Robert Chyla - Lead Emulation Architect, IARSystems

OneSpin presents: More than the Core:Verifying RISC-V SoCs



Verifying RISC-V designs is critical for technical andcommercial success. Compliance to the standardspecifications and complete interoperability areessential to complete with older processor familieswith decades of proven silicon. RISC-V processordesigners, whether in-house or core providers, mustapply the most rigorous verification methodologiesand document this process to build the confidence ofpotential integrators.

Successful RISC-V verification extends beyond thecore itself. This talk focuses on the needs of engineersintegrating one or more RISC-V processors into asystem-on-chip (SoC) design. The SoC team faces fourmajor verification challenges. The first is re-runningsome or all of the verification performed on thestandalone core as part of their acceptance criteria.This is much easier if the verification is performedusing a third-party solution.

The flexibility of the RISC-V architecture and the manychoices for the core integrator add to the verificationcomplexity. It may be possible to configure the corewithin the range of optional functionality defined bythe RISC-V Instruction Set Architecture (ISA). RISC-V isdefined to accommodate a wide range ofmicroarchitectural implementations, and these mustalso be verified.

Further, the ISA specifications permit extensions, suchas addition of custom instructions, which must beverified to ensure that the new functionality works andthat none of the baseline functionality is broken.Complete core verification goes well beyondcompliance to the baseline ISA, covering architecturaloptions, microarchitecture, and extensions. This taskis the second major verification challenge for SoCteams.

Many RISC-V applications have security and trustrequirements, so integrators need to check that nodesign errors offer vulnerabilities for adversary attackand that no hardware Trojans have been deliberatelyinserted. Many of the security and trust checks shouldbe run on the rest of the SoC and not just on the core.In addition, for safety-critical applications, safetyverification must be performed at the full-chip level ofthe SoC.

Safety, trust, and security verification is the third majorchallenge faced by teams integrating a RISC-V coreinto their SoC. The final challenge is verifying that thecore has been properly integrated into the completechip. This involves using formal connectivity checkingto ensure that all signals are hooked up correctly. Infact, all four challenges can be addressed by averification methodology based largely on formaltechnology.

This talk presents an available solution that addressesall four verification challenges for SoC teams adopting

RISC-V. It presents examples of issues found usingthis approach on actual chip designs, includingPULPino, available in open-source repositories. It isappropriate, and highly recommended, for managers,designers, and verification engineers developing orintegrating RISC-V processor cores.

Participants

Speaker: Nicolae Tusinschi - Product SpecialistDesign Verification, OneSpin Solutions

Debugging on Homogeneous andHeterogeneous Multicore SoCs Containing aMix of RISC-V and non-RISC-V Cores



This paper will outline the concept of debuggingsoftware on both homogeneous and heterogeneousmulticore SoCs containing a mix of RISC-V corestogether with other processor cores such as ARM, ARCor MIPS. Increasingly, SoCs contain a mix ofarchitectures which complicates the task of softwaredebugging. For complex real-time applications runningon a multicore heterogeneous device, the task ofdebugging embedded software requires specialisttools to enable simultaneous debugging on multiplecores. Ashling's RiscFree platform is an Eclipse-basedIntegrated Development Environment (IDE) for ARM,ARC, MIPS and RISC-V development. It provides acomplete, seamless, single environment for ARM, ARC,MIPS and RISC-V software development includingsupport for writing, building (compiling), simulating,hardware debugging/tracing and performanceanalysis across all cores simultaneously. This paperwill also provide an illustration of Custom RISC-V toolsfor use with heterogeneous multicore devicesincluding: \tHeterogeneous multi-core support withina single toolchain \tDebug support for multi-threadand multi-core implementations \tHardware Debugand Trace integrated into Multi-core Debugger\tAdvanced Debug Features and on-chip trace anddebug analytics support \tProfiling, performanceanalysis, code coverage, power analysis withcomparative metrics \tIntegrated RTOS/OS debugsupport \tIntegrated Serial Terminal \tHigh-level RISC-V Register Viewer (XML database driven) \tROM orRAM based debugging support \tScript language forautomating debugging sessions \tSingle-shot installerthat installs and configures 'out-of-the-box' Keyemphasis will be on the seamless integratedheterogeneous multicore debug and streamlineddebug methodology with helpful project wizards andpre-built examples, adding to and complementing anincreasing body of knowledge in the RISC-Vecosystem.


Participants

Speaker: Hugh O'Keeffe - Engineering Director, Ashling

Speaker: Roisin O'Keeffe - VP, Business Enterprise,Ashling





Networking Break



Innovation in CPU Architecture, Pushing Datafrom Edge to Cloud



The C960 processor is an ultra-high-performancemulti-core processor developed by T-HeadSemiconductor Co., Ltd., which is compatible with theRISC-V architecture and supports a flexible andconfigurable multi-core architecture. As we know, theperformance of the C960 processor is better than allthe other RISC-V processor cores currently available inthe market.

The C960 processor adopts an advanced 12superscalar pipeline and introduces a deep out-of-order architecture with over 100 instructions in the out-of-order window. The C960 processor can decode 3instructions and issue 8 instructions in parallel. Inorder to improve the efficiency of instruction fetchingand memory accessing bandwidth, the C960processor further introduces several innovativetechnologies, including high-performance hybridbranch processing and multi-mode dynamic adaptivedata prefetching technology.


Participants

Speaker: Caffrey Chen - Chief Processor Architect,Alibaba

RISC-V Processor Verification based on Open-source Framework and State-of-the-art Cloud-based Methodologies



RISC-V Processor Verification Co-Authors: Lee Moore,Imperas Software Simon Davidmann, ImperasSoftware Richard Ho, Google, Inc. Tao Liu, Google, Inc.Doug Letcher, Metrics Technologies Inc. Aimee Sutton,Metrics Technologies Inc. Abstract: The RISC-V OpenISA's permits freedom for implementors to modify andextend the processor as well as micro-architecturalflexibility. Now SoC developers have expanded optionsto source processor IP: From commercial IP suppliers,build in-house or download one of the many open-source options. All options have various factors toconsider but the universal requirement is to fully testthe design during the SoC development, as anyextension or custom instruction could affect theoriginal core. Traditional SoC designs flows are basedon known good IP assumptions, until recentlyprocessor verification was not a market addressed bythe EDA industry. The chip and IP firms with traditionalISA's kept the know how in-house as a commercialadvantage. Based on an initial concept of an opensource RISC-V instruction stream generator, goldenreference model and cloud-based tools, the resultingframework has subjected a popular open-source coresto extensive test and verification analysis. Resultsinclude coverage reports and advice on testing yourcores in your next project.


Participants

Speaker: Lee Moore - Lead Engineer, Imperas


Headline Sponsor Western Digital presents:RISC-V Hypervisor Support


Grand Ballroom 220-C

In this talk, we show the current state of RISC-Vhypervisor support in QEMU, OpenSBI, Xvisor, KVM,and KVMTOOL. We will also provide details on futuredirections for RISC-V hypervisor support andshowcase hypervisors (Xvisor and KVM) running onQEMU.


Participants

Speaker: Alistair Francis - Principal System Engineer,Western Digital

Speaker: Anup Patel - Technologist, Western Digital

Andes RISC-V Processor Solutions: From MCUto Datacenters



To serve the fast-growing demands for commercialRISC-V processors, Andes continues to broaden ourproduct portfolio. Andes V5 Processor IP solutionshave been adopted by a wide range of RISC-V basedSoCs: from tiny low-power MCUs for consumerproducts, to chips powering enterprise-grade productsand datacenters; from one ultra compact 2-stagepipeline core to a thousand GHz+ cores workingcohesively; from using standard V5 ISA in the cores toadopting Andes Custom Extensionâ„¢ (ACE)framework to design new instructions to meet SoCrequirements.

In this talk, we will give an overview of Andes existingprocessor solutions. Then, we will introduce newAndes processor IPs as well as a new version of thepowerful ACE tool to address the rising demands forhigher performance, intelligence and flexibility. Inaddition, we will present embedded multiprocessorarchitectures from a handful of cores to over 1000cores made possible by Andes V5 processors.


Participants

Speaker: Charlie Su - CTO and SVP of R&D, AndesTechnology Corporation

Ruby Sponsor SiFive presents: EnablingSecurity with AWS Qualified IoT Devices



The SiFive Learn Inventor developer kit is the world'sfirst RISC-V device to be Amazon FreeRTOS qualified.In this talk, David Lee will discuss the systemarchitecture and process for rapidly developing IoTboards that meet AWS qualifications for security andconnectivity.


Participants

Speaker: David Lee - Director of Product Management,SiFive





Working Towards a Common C Library forSmall RISC-V Systems



Working Towards a Common C library for Small Risc-Vsystems 8- and 16- bit micro-controller developmentenvironments generally come with a standard C libraryimplementation offering math, string and "OS"functionality. The same is not universally true for32-bit or larger systems, such as Risc-V and ARM.When building embedded systems for these targets,the developer often has to find (and build) a suitable Clibrary as a part of the project. Building a common Clibrary for these systems will reduce the developmentcosts for systems based on these more capableprocessors. This talk will start by presenting a librarybuilt by combining newlib and a heavily modified avr-libc. This library blends the robust functionality ofnewlib's math and string functions with the lightweightstdio design from avr-libc. Next, some proposals onchanges in this library going forward so that it can beusable by many developers working on both ARM andRisc-V projects. Finally, I'll present some proposedchanges in GCC's handling of multilib paths toautomate selection of libraries based on targetarchitecture.


Participants

Speaker: Keith Packard - Principal Engineer, SiFive

Ara 2.0: 64-bit RISC-V Vector Processor in22nm FD-SOI



In this talk, we detail our experience in the design andimplementation of the RISC-V Vector Extension(v0.7.2) in an advanced silicon process. First unveiledduring the last Summit, Ara is a 64-bit vector processorimplemented in GlobalFoundries 22FDX FD-SOItechnology, running at 1.2Â GHz at typical conditions.In terms of performance, Ara achieves up to 97% FPUUtilization when running a 256 Ã— 256 double-precision matrix multiplication. Under the sameconditions, Ara achieves an energy efficiency of up to67 DP-GFLOPS/W. We push the architecture to itslimits by analyzing its performance on smallerproblems. When the vector length is comparable to thenumber of physical lanes, the vector unit hits the vonNeumann bottleneck. We use this use case to discussinsights into performance limitations for vectorprocessors, and directions to maintain high energyefficiency even for small matrix sizes, together withupdated area, performance and power results for inthe 22FDX process.


Participants

Speaker: Matheus Cavalcante - PhD Student, ETHZurich

Verifying RISC-V Vector and Bit ManipulationExtensions using STING Design VerificationTool



Vector and bit manipulation are the latest extensionsadded to the open RISC-V ISA for advanced use caseslike cryptography and machine learning. In this paper,we present the different mechanisms andmethodologies employed in the STING designverification tool to test the functional correctness ofvector and bit manipulation extensions andinteroperability with other extensions and privilegemode of execution in open source and commercialRISC-V designs.


Participants

Speaker: Shubhodeep Choudhury - CEO, Valtrix

Rambus presents: Challenges and Benefits ofCertification for Security Hardware



As chip designers increasingly see requirements forsecurity, they also have more and more options forsecurity hardware IP. They can build it themselves, use“free” IP that comes along with other components, usesomething open source, or buy it from an IP vendorthat specializes in security. There are pros and cons toeach approach, but one consideration that is oftenoverlooked is the need for certification for security andfunctional safety. This talk will look at some of thecommon certification regimes, the costs and benefitsof them, and how this impacts selection of security IP.


Participants

Speaker: Ben Levine - Senior Director, ProductManagement, Rambus

Prototyping RISC-V Based HeterogeneousSystems-on-Chip with the ESP Open-SourcePlatform



ESP is an open-source research platform forheterogeneous SoC design that allows the rapid FPGAprototyping of complex SoCs based on RISC-Vprocessors. By combining a modular tile-basedarchitecture with a flexible design methodology, ESPsimplifies the development and integration of coarse-grain accelerators as well as the reuse of third-partyopen-source components. With ESP's automationcapabilities, we can rapidly prototype, for example, anSoC that features: the Ariane RISC-V processor corebooting Linux, a multi-plane network-on-chipsupporting a partitioned memory hierarchy withmultiple DRAM controllers, and tens of accelerators,including the NVIDIA NVDLA as well as acceleratorsdesigned with various languages and synthesis tools(C with Vivado HLS, SystemC with Stratus HLS, KerasTensorFlow and PyTorch with hls4ml, Chisel, andVerilog/VHDL). Compared to other RISC-V relatedprojects, ESP is focused on scalability (with a NoC-based architecture), heterogeneity (with emphasis onloosely-coupled accelerators), and flexibility (withsupport of different design flows).


Participants

Speaker: Luca Carloni - Professor, Columbia University





An Efficient Runtime Validation Frameworkbased on the Theory of Refinement



We introduce a new methodology based on refinementfor testing the functional correctness of hardware andlow-level software. Our methodology overcomesseveral major drawbacks of the defacto testingmethodologies used in industry: (1) it is difficult todetermine completeness of the properties and testsunder consideration (2) defining oracles for tests isexpensive and error-prone (3) properties are defined interms of low-level designs. We introduce a newapproach to dynamic verification based on the theoryof refinement. In the last decade, refinement-basedmethodology has been successfully used to staticallyverify correctness of several practical systems likepipelined microprocessors, operating systemsmicrokernels and distributed systems. Refinementshows that the behaviors of a concrete system, say apipelined machine, are suitably related to thebehaviors of an abstract machine, say an instructionset architecture, that serves as the specification. Theidea behind our method is simple. We compile arefinement conjecture into a runtime-check that isperformed during simulation. This allows us to checkfor functional correctness during testing using onlythis one check. We describe our methodology, discussalgorithmic issues, and provide experimentalvalidation using a 5-stage RISCV pipelinedmicroprocessor.


Participants

Speaker: Mitesh Jain - Staff R&D Engineer, SynopsysInc

SafeRV: Building Blocks for Safety CriticalRISC-V Systems



As our dependence on electronic subsystemscontinues to grow (ranging from aircrafts topacemakers), it has become all the more critical thatthese systems guarantee correct functionality underunexpected or altered conditions (such asenvironmental changes). While modern day space andautomotive applications employ multi-core systems toprovide high performance and improved features, theyalso demand a high amount of reliability as well. Thisarticle discusses the effort carried out by the SHAKTIteam at IIT-Madras in collaboration with Thales andSYSGO, to build a RISC-V based multi-core systemwhich can cater to such critical requirements (ofspace and avionics) and provide a stable open-sourceplatform for the community to build on. The goal ofthe work is to build a scalable multi-core SoCsubsystem using the SHAKTI cores. This system mustnot only support mixed-critical tasks but also providereasonable fault tolerance while maintainingperformance. The design includes multiplecomponents - primary compute cores, monitoringcores, network-on-chip, cache-coherency and muchmore. This article aims to provide details of each ofthe components and various design choices made sofar to meet the final target.


Participants

Speaker: Neel Gala - CTO, InCore Semiconductors Pvt.Ltd.

Speaker: Bertrand Tavernier - VP Software Research &Technologies, Thales





TIME EXPO HARDWARE/AR-CHITECTURE

HARDWARE/AR-CHITECTURE.

KEYNOTES NETWORKING POSTER GALLERY REGISTRATION SECURITY/VERI-FICATION

SECURITY/VERI-FICATION.

SOFTWARE

8:00AM 8:00am - Regis-tration

9:00AM 9:00am - Wel-come

9:05am - RISC-Vand Chips Al-liance Addressnew ComputeRequirements

9:25am - AnOpen Source Ap-proach to Sys-tem Security

9:45am - HowRISC-V made theQuick Jump fromAcademia to In-dustry and Why itwill Change theEntire Semicon-ductor Industry -a Venture Capitalperspective

SCHEDULEWEDNESDAY, DECEMBER 11 - 11/12/2019








SOFTWARE

10:00AM 10:05am - OpenSource Proces-sor IP for HighVolume Produc-tion SoCs: CORE-V Family of RISC-V Cores

10:25am -Keynote Panel:Opportunity andRisks in OpenSource Hardware

11:00AM 11:30am - ExpoHall

11:10am - Qual-comm DiamondSponsor Session:Global Ambitionsfor RISC-V

11:30am - LunchBreak

11:30am - PosterGallery on ExpoFloor

12:00PM 12:50pm - En-abling AI on LowPower EndpointDevices Utilizingthe QuickLogicand SiFive Free-dom Aware Tem-plates

12:50pm - For-mal Methods forHardware-Software Integra-tion on RISC-VEmbedded Sys-tems

12:50pm - RISC-V Software Stateof the Union









SOFTWARE

1:00PM 1:20pm - RISC-VFor Heteroge-neous Comput-ing

1:50pm - SweRVCores Roadmap

1:20pm - RubySponsor SiFivepresents: TheSiFive VectorProcessor

1:50pm - RISC-VEnclaves: AClean Slate Ap-proach To LinuxSecurity

1:50pm - seL4on RISC-V: Veri-fied OS for TrueSecurity

1:20pm -Production-readyRISC-V Supportin LLVM/Clang9.0 - How we GotThere and What'sNext

2:00PM 2:20pm - Proces-sor IP Showcasewith Andes Tech-nology, CHIPS Al-liance, Codasip,Shakti Project,SiFive, Synta-core, OpenHWGroup

2:20pm - Break

2:30pm - RISC-V:A New Zero-Trust Model forCyber ResilientAvionics

2:50pm - Differ-ent Trace Meth-ods and EfficientWays to UtilizeThem

2:50pm - One-Spin presents:More than theCore: VerifyingRISC-V SoCs

2:20pm - Inte-grate RISC-V tobuild Open Com-mon AutomotivePlatform









SOFTWARE

3:00PM 3:40pm - Innova-tion in CPU Ar-chitecture, Push-ing Data fromEdge to Cloud

3:10pm - Net-working Break

3:00pm - Debug-ging on Homoge-neous and Het-erogeneous Mul-ticore SoCs Con-taining a Mix ofRISC-V and non-RISC-V Cores

3:40pm - RISC-VProcessor Verifi-cation based onOpen-sourceFramework andState-of-the-artCloud-basedMethodologies

3:40pm - Head-line SponsorWestern Digitalpresents: RISC-VHypervisor Sup-port

4:00PM 4:10pm - AndesRISC-V Proces-sor Solutions:From MCU toDatacenters

4:40pm - Ara 2.0:64-bit RISC-VVector Processorin 22nm FD-SOI

4:10pm - RubySponsor SiFivepresents: En-abling Securitywith AWS Quali-fied IoT Devices

4:40pm - Verify-ing RISC-V Vec-tor and Bit Ma-nipulation Exten-sions usingSTING DesignVerification Tool

4:40pm - Ram-bus presents:Challenges andBenefits of Certi-fication for Secu-rity Hardware

4:10pm - Work-ing Towards aCommon C Li-brary for SmallRISC-V Systems









SOFTWARE

5:00PM 5:10pm - Proto-typing RISC-VBased Heteroge-neous Systems-on-Chip with theESP Open-Source Platform

5:10pm - SafeRV:Building Blocksfor Safety CriticalRISC-V Systems

5:10pm - An Effi-cient RuntimeValidationFrameworkbased on theTheory of Refine-ment





Registration


RISC-V Verification for Processor Cores andOptional Custom Extensions

9:00am - 10:30amHardware/Architecture


The Open ISA for RISC-V allows designers greatfreedoms to implement and expend a processor, thistutorial will highlight the verification methodologiesthat scales to address these freedoms within the baseratified specification and also covers customextensions.

For developer looking to implement a processorthemselves, or start with a pre-built IP from one of thecommercial vendors or open source options thistutorial with provide some useful Insights as you planthe verification for your next project.

This tutorial covers RISC-V Verification with the Googledeveloped open source RISC-V Instruction StreamGenerator, combined with the Imperas referencemodels and Metrics could-based RTL simulation.

Imperas

Outline for the overall verification flow and details onthe latest updates to the RISC-V reference model,riscvOVPsim, plus highlights on the RISC-VFoundation's Technical Committee task group forcompliance and the latest compliance test suites.

Google

Based on industry standard SystemVerilog (SV) andUniversal Verification Methodology (UVM) theverification platform utilizes an open source randomRISC-V assembly Instruction Stream Generator (ISG).To match the flexibility of the RISC-V Open ISA the ISGfeatures configuration and control options to addressa range of test cases and verification scenarios.

Metrics

Cloud based tools offer flexible capacity for designverification based on a complete SystemVerilog IEEE1800-2012 compliant simulator and infrastructuremethodologies.

This tutorial covers the key first steps to manage theset-up and configuration for a RISC-V verification flowand highlights the latest results from some popularopen source RISC-V cores.

All Access or Tutorial pass required to attend Thursdaytutorial sessions.

Participants

Speaker: Simon Davidmann - CEO, Imperas

Speaker: Lee Moore - Lead Engineer, Imperas


Speaker: Doug Letcher - President and CEO, MetricsTechnologies, Inc.

A Tour of the RISC-V ISA Formal Specification

9:00am - 11:45amSecurity/Verification


In this hands-on tutorial, we would like to familiarize abroad RISC-V community with the RISC-V ISA FormalSpecification, with a view to encouraging its use on adaily basis. We hope to cover the following: (1) Areading tour of the spec, so people are subsequentlyable to consult the spec on their own; (2) How to buildand execute the spec on RISC-V binaries (from ISAtests to operating systems) to produce referenceexecutions; (3) How to build and execute the spec onthe Compliance Suite. If there is time and interest,additional topics are: (4) How to extend the spec fornew and custom ISA extensions; and (5) A descriptionof how the spec is being used for formal proofs ofcompiler and OS correctness, and hardwareimplementation correctness. The target audience forthis tutorial are people who are NOT specialists informal methods, but who wish to use the spec in dailypractice (e.g. use cases 1-3 above). Attendees whocan run Linux on their laptops (natively, in a VM, orremotely) will be able to follow the speaker in a hands-on manner.


Participants

Speaker: Rishiyur Nikhil - CTO, Bluespec, Inc.

SESSIONSTHURSDAY, DECEMBER 12 - 12/12/2019




Fomu: Python, RISC-V, and FPGA in your USBPort

9:00am - 10:30amSoftware


The tutorial will give the audience hands-on experiencewith customizing a fully open source RISC-V designrunning the Zephyr RTOS in a tiny FPGA that fits in yourcomputer's USB port (Fomu - FPGA Open Micro USB) -an ultimately portable RISC-V developmentenvironment. The tutorial attendees will receive theirvery own Fomu board, which they will program usingan open toolchain, building a small yet practicalapplication. During the workshop, examples of how theRISC-V core can be customized, simulated usingVerilator and Renode (including fast co-simulation), aswell as interfaced with your PC will be shown. Theadvantages of partitioning of the design using anEtherBone bridge for a rapid development turnaroundwill also be explained. After the tutorial, theparticipants will walk away not only with a Fomuboard, but also with practical knowledge of how towork with a real FPGA RISC-V design effectively andhow to modify it to their own needs.


Participants

Speaker: Tim Ansell - Software Engineer, Google

Speaker: Michael Gielda - VP Business Development,Antmicro

Designing and Building Modern Modular SoCsusing Open-Source Federation Tools

10:45am - 11:45amHardware/Architecture


Open-Source tools and a modern design reusemethodology based on modularity permit the creationof advanced SoCs in a simpler and more efficientmanner. In this tutorial, SiFive will demonstrate how touse Federation tools to integrate Verliog IP into anexisting Freedom SoC design, with the resulting RTLmapped to an FPGA instance. SiFive will thendemonstrate the use of the open-source SiFiveFreedom Metal library to write a portable bare-metaldriver and perform verification tests in both simulationand FPGA hosted instances.


Participants

Speaker: Jack Koenig - Engineer, SiFive

An Introduction to RISC-V Boot Flow

10:45am - 11:45amSoftware


A well-supported and standard boot flow is veryimportant for the RISC- V software ecosystem beforeRISC-V can be a truly competitive alternative toexisting mainstream ISAs. However, RISC-V also needsits own trusted firmware to handle RISC-V specificfeatures such as Supervisor Binary Interface (SBI) thatallows the operating systems to interact with thesupervisor execution environment (SEE). In this talk,we will discuss the status of a stand-alone opensource SBI implementation (aka OpenSBI) thatprovides RISC-V specific run time services and how ithelps in porting other common boot loaders such asU-Boot, coreboot and EDK2 to RISC-V. We will alsodiscuss how the RISC- V boot process compares toother ISAs and where the community is heading. Thispresentation will give developers more insight intohow the RISC-V boot process works and which areasthey can contribute to improve the RISC-V softwareecosystem.


Participants

Speaker: Atish Patra - Principal R&D Engineer, WesternDigital

Speaker: Anup Patel - Technologist, Western Digital

Lunch Break

11:45am - 1:00pmLunch

Location: TBD

GNU CGEN for RISC-V Tool ChainCustomization



CGEN has been a mainstay of GNU tool chains for twodecades. From a specification of an ISA's syntax andsemantics in Scheme it generates a GNU assembler,disassembler and instruction set simulator. There isnow a CGEN specification for RISC-V. For mostarchitectures, with their fixed ISAs, use of CGEN is aone off exercise in the early days of the architecture,which never need to be revisited. However, for anextensible architecture like RISC-V, it is the perfect toolfor rapid delivery of support for new instruction setextensions within the tool chain. This tutorial followson from a general tutorial on CGEN given by JeremyBennett at the GNU Tools Cauldron 2018. In this newtutorial we'll focus on the use of CGEN for RISC-V, andillustrate the approach throughout using our workadding the Bit Manipulation instruction set extension.By the end of the tutorial, attendees should beconfident they can add their own custom extensionsusing CGEN to generate their own assembler,disassembler and simulator. We will conclude ourtutorial with a look at future work on such technology,specifically the use of SAIL, with its more rigorous ISAdescription as a successor to Scheme within CGEN.


Participants

Speaker: Mary Bennett - Engineer, University of Surrey

Speaker: Ed Jones - Engineer, Embecosm





seL4 on RISC-V Renode



The seL4 kernel is the worlds first open-source andmathematically verified microkernel. A key linchpin tothese claims is the assumption that the hardware it isrunning on can be trusted. This big assumption canbe verified or even strengthened by pairing seL4 withRISC-V. While RISC-V development boards are stillsomewhat hard to procure, emulation provides a keystep in the development process that allows thesystem to be vetted before hardware is available.Antmicroâ€™s Renode emulation framework providesa powerful and flexible environment to developembedded systems. It offers well thought-outinterfaces that enable embedded developers toemulate and debug virtual time synced complexsystems. Antmicro partnered with Microsemi toimplement support for the Microsemi RISC-V platform,Mi-V and DornerWorks provided support to get theseL4 kernel running on the Mi-V Renode emulatedsystem. This tutorial will outline both of thesetechnologies and show how to set up and build andconfigure the software necessary to emulate a non-trivial seL4 based application on the Mi-V Renodesystem. This tutorial will provide a starting point forembedded developers to start building the next highlysecure systems with seL4 on RISC-V.


Participants

Speaker: Jesse Millwood - Embedded Engineer,DornerWorks

Chipyard and FireSim: End-to-End ArchitectureExploration with RISC-V SoC Generators,FPGA-Accelerated Simulation and Agile TestChips



This tutorial will introduce the Chipyard and FireSimframeworks for the purposes of full-stack architectureexploration and digital system design. The Chipyardframework incorporates multiple open-source Chisel-based generators within the Rocket-Chip SoCgenerator ecosystem into a single “one-stop-shop”framework enabling design, simulation, and physicaldesign flows. Simulation flows include integration withthe open-source Verilator RTL simulator, as well as theFireSim FPGA-Accelerated simulation platform on theAWS public cloud for full-system end-to-endevaluation. The tutorial will demonstrate basicheterogeneous Rocket/BOOM-based SoC systemdesign using the Rocket Chip parameter system withaccelerator interfaces, as well as full systemevaluation of such SoCs using the various design-cycleflows within the Chipyard framework. In particular, itwill spotlight end-to-end HW/SW evaluation using theFireSim FPGA-accelerated simulation framework.


Participants

Speaker: Alon Amid - Graduate Student, UC Berkeley

Speaker: David Biancolin - Ph.D Candidate, Universityof California, Berkeley, U.C. Berkeley

Speaker: Abraham Gonzalez - Ph.D. Student, U.C.Berkeley

Speaker: Sagar Karandikar - PhD Student, UC Berkeley,UC Berkeley

Speaker: Colin Schmidt - Graduate Student, UCBerkeley

Speaker: Jerry Zhao - PhD Student, UC Berkeley, UCBerkeley

RISC-V Bit-Manipulation ISA Extension: Spec,Hardware, Software



RISC-V BitManip is a set of standard ISA extensionsaiming at improving performance for bit-manipulationand general purpose code. This tutorial features an in-depth discussion of the proposed ISA extensions andinstructions. We also discuss reference hardwareimplementations and support in RISC-V software tools(compilers, simulators), and show practical codeexamples that make use of the new instructions.


Participants

Speaker: Ken Dockser - Senior Director of Technology,Corporate R&D, Qualcomm

Speaker: Clifford Wolf - CTO, Symbiotic EDA





How to Secure a RISC-V System in 90 minutes- From Single Core MCU to Mixed CriticalitySMP Linux



The impressive growth of the RISC-V ecosystem is oneveryone’s lips. Originally developed at UC Berkeley,the free and open ISA promises to bring the innovationand collaboration of the open source community to thehardware world - and to dramatically disrupt the wholesemiconductor industry in the process. However,hardware and software engineers used to traditionalclosed-source proprietary architectures and tools mayfind difficult to orient themselves in this highly-fragmented galaxy of RISC-V technologies, opensource tools and development frameworks.

So really the question is: How do I get started withRISC-V? This class will show exactly that: how todownload, build, configure, debug and test acompletely free and open source RISC-V developmentenvironment that scales from tiny single-core mcu tosmp Linux.

Part 1 - The basics

• download and burn to FPGA a fully customizableRISC-V softcore (33-bit Rocket)

• download and build the full RISC-V GNU toolchain -both 32-bit and 64-bits

• download and build the full OpenOCD / JTAGdebug stack

• download and configure Eclipse IDE with the RISC-V embedded development plugin

• develop, compile, debug and test on actualhardware your first RISC-V “Hello World”application

Part 2 - Software-defined Trusted ExecutionEnvironment (mcu / IoT)

• develop a secure embedded application with front-end, Root of Trust and Secure Boot functions

• install and configure a software-defined multi-domain Trusted Execution Environment

• “plug-in” the functions to the Trusted ExecutionEnvironment

• flash the resulting firmware to an actual FPGAboard running a RISC-V Rocket core

• run the complete application to test overall safetyand security of the system

Part 3 - Linux Enclaves (mixed-criticality smp Linux /amp RTOS)

• download & build a modified Linux distro for use inmixed criticality systems - MicroSemi PolarfireFPGA

• download & build a modified secure boot loaderthat supports multiple Linux enclaves

• download and build a demo application with foursoftware-defined enclaves and an IPC Linux driver

• run the complete application to test the resiliencyof the isolation provided by the system

This class is a must-attend for hardware designers,software developers, and security practitioners who

need security through isolation but can't afford thetime and the risk of figuring out all the details of aproper implementation.


Participants

Speaker: Cesare Garlati - Co-Founder, Hex FiveSecurity

Speaker: Sandro Pinto - Research Scientist and InvitedProfessor, Universidade do Minho





TIME HARDWARE/ARCHITECTURE HARDWARE/ARCHITECTURE. LUNCH REGISTRATION SECURITY/VERIFICATION SOFTWARE

8:00AM 8:00am - Registration

9:00AM 9:00am - RISC-V Verificationfor Processor Cores and Op-tional Custom Extensions

9:00am - A Tour of the RISC-VISA Formal Specification

9:00am - Fomu: Python, RISC-V, and FPGA in your USB Port

10:00AM 10:45am - Designing andBuilding Modern ModularSoCs using Open-Source Fed-eration Tools

10:45am - An Introduction toRISC-V Boot Flow

11:00AM 11:45am - Lunch Break

12:00PM

1:00PM 1:00pm - GNU CGEN for RISC-V Tool Chain Customization

1:00pm - Chipyard and FireS-im: End-to-End Architecture Ex-ploration with RISC-V SoC Gen-erators, FPGA-AcceleratedSimulation and Agile TestChips

1:00pm - seL4 on RISC-V Ren-ode

2:00PM 2:15pm - RISC-V Bit-Manipulation ISA Extension:Spec, Hardware, Software

2:15pm - How to Secure aRISC-V System in 90 minutes -From Single Core MCU toMixed Criticality SMP Linux

SCHEDULETHURSDAY, DECEMBER 12 - 12/12/2019




Documents

SESSIONS RISC-V Summit · particularly important for embedded computing and IoT device. One obstacle to measuring code size and settling this issue has been the lack of an open benchmark