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Sequential Circuit Synthesis. Virendra Singh Indian Institute of Science Bangalore. IEP on Digital System Synthesis IIT Kanpur. Computer Hardware = Datapath + Control. Concept of the State Machine. Qualifiers. Registers Combinational Functional Units (e.g., ALU) Buses. - PowerPoint PPT Presentation
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Sequential Circuit Synthesis
Virendra SinghIndian Institute of Science
Bangalore
IEP on Digital System Synthesis
IIT Kanpur
2Sequential@iitkDec 13,2007
Concept of the State MachineComputer Hardware = Datapath + Control
RegistersCombinational Functional Units (e.g., ALU)Buses
FSM generating sequences of control signalsInstructs datapath what to do next
"Puppet"
"Puppeteer who pulls thestrings"
Qualifiers
Control
Control
Datapath
State
ControlSignalOutputs
QualifiersandInputs
Dec 13,2007 Sequential@iitk 3
Serial Adder
AdderX1
X2Z
X1 0 1 1 0 0
X2 0 1 1 1 0
--------------------------
Z 1 1 0 1 0
Dec 13,2007 Sequential@iitk 4
Serial Adder
00/1
A B
11/0
01/1
00/0
10/1
01/0
10/0
11/1
PS NS,Z
x1x2
A
B
A,0 A,1 B,0 A,1
A,1 B,0 B,1 B,0
Dec 13,2007 Sequential@iitk 5
Serial Adder
y NSX1x2 00 01 11 10
ZX1x2 00 01 11 10
0
1
0 0 1 0
0 1 1 0
0 1 0 1
1 0 1 0
Dec 13,2007 Sequential@iitk 6
Memory Elements
R
S
Q
Q’
Dec 13,2007 Sequential@iitk 7
SR FFQ(t) S(t) R(t) Q(t+1)
0 0 0
0 0 1
0 1 1
0 1 0
1 1 0
1 1 1
1 0 1
1 0 0
0
0
?
1
1
?
0
1
RS = 0
Q(t+1) = R’Q(t) + S
Dec 13,2007 Sequential@iitk 8
SR FF
Circuit change
From To
Required Input
S R
0 0
0 1
1 0
1 1
0 --
1 0
0 1
-- 0
Excitation Table
Dec 13,2007 Sequential@iitk 9
JK FF
Circuit change
From To
Required Input
J K
0 0
0 1
1 0
1 1
0 --
1 --
-- 1
-- 0
Excitation Table
Dec 13,2007 Sequential@iitk 10
T FF
Circuit change
From To
Required Input
T
0 0
0 1
1 1 1 0
0
1
0
1
Excitation Table
Dec 13,2007 Sequential@iitk 11
D FF
Circuit change
From To
Required Input
T
0 0
0 1
1 1 1 0
0
1
1
0
Excitation Table
Dec 13,2007 Sequential@iitk 12
Serial Adder
y NSX1x2 00 01 11 10
ZX1x2 00 01 11 10
0
1
0 0 1 0
0 1 1 0
0 1 0 1
1 0 1 0
Dec 13,2007 Sequential@iitk 13
Serial Adder
Y = x1x2 + x1y + x2yZ = x1’x2’y + x1’x2y’ + x1x2’y’
+x1x2y
14Sequential@iitkDec 13,2007
Basic Design Approach
Six Step Process
1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state minimization
4. Perform state assignment
5. Choose FF types to implement FSM state register
6. Implement the FSM
15Sequential@iitkDec 13,2007
Basic Design ApproachExample: Vending Machine FSM
General Machine Concept:
deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change
Block Diagram
Step 1. Understand the problem
Vending Machine
FSM
N
D
Reset
Clk
OpenCoin
SensorGum
Release Mechanism
Draw a picture!
16Sequential@iitkDec 13,2007
Vending Machine Example
Tabulate typical input sequences:
three nickelsnickel, dimedime, nickeltwo dimestwo nickels, dime
Draw state diagram:
Inputs: N, D, reset
Output: open
Step 2. Map into more suitable abstract representation
Reset
N
N
N
D
D
N D
[open]
[open] [open] [open]
S0
S1 S2
S3 S4 S5 S6
S8
[open]
S7
D
17Sequential@iitkDec 13,2007
Vending Machine ExampleStep 3: State Minimization
Reset
N
N
N, D
[open]
15¢
0¢
5¢
10¢
D
D
reuse stateswheneverpossible Symbolic State Table
Present State
0¢
5¢
10¢
15¢
D
0 0 1 1 0 0 1 1 0 0 1 1 X
N
0 1 0 1 0 1 0 1 0 1 0 1 X
Inputs Next State
0¢ 5¢ 10¢ X 5¢ 10¢ 15¢ X
10¢ 15¢ 15¢ X
15¢
Output Open
0 0 0 X 0 0 0 X 0 0 0 X 1
18Sequential@iitkDec 13,2007
Vending Machine ExampleStep 4: State Encoding
Next State D 1 D 0
0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X
Present State Q 1 Q 0
0 0
0 1
1 0
1 1
D
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
N
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Inputs Output Open
0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X
19Sequential@iitkDec 13,2007
Vending Machine ExampleStep 5. Choose FFs for implementation D FF - easiest to use
D1 = Q1 + D + Q0 N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
8 Gates
CLK
OPEN
CLK
Q 0
D
R
Q
Q
D
R
Q
Q
\ Q 1
\reset
\reset
\ Q 0
\ Q 0
Q 0
Q 0
Q 1
Q 1
Q 1
Q 1
D
D
N
N
N
\ N
D 1
D 0
K-map for OpenK-map for D0 K-map for D1
Q1 Q0D N
Q1
Q0
D
N
Q1 Q0D N
Q1
Q0
D
N
Q1 Q0D N
Q1
Q0
D
N
20Sequential@iitkDec 13,2007
Vending Machine ExampleStep 5. Choosing FF for Implementation
J-K FF
Remapped encoded state transition table
Next State D 1 D 0
0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X
Present State Q 1 Q 0
0 0
0 1
1 0
1 1
D
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
N
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Inputs K 1
X X X X X X X X 0 0 0 X 0 0 0 X
K 0
X X X X 0 1 0 X X X X X 0 0 0 X
J 1
0 0 1 X 0 1 1 X X X X X X X X X
J 0
0 1 0 X X X X X 0 1 1 X X X X X
21Sequential@iitkDec 13,2007
Vending Machine ExampleImplementation:
K-map for K1K-map for J1
Q1 Q0D N
Q1
Q0
D
N
Q1 Q0D N
Q1
Q0
D
N
K-map for K0K-map for J0
Q1 Q0D N
Q1
Q0
D
N
Q1 Q0D N
Q1
Q0
D
N
J1 = D + Q0 N
K1 = 0
J0 = Q0 N + Q1 D
K0 = Q1 N
7 Gates
OPEN Q 1
\ Q 0
N
Q 0 J
K R
Q
Q
J
K R
Q
Q
Q 0
\ Q 1
\ Q 1
\ Q 0
Q 1
\reset
D
D
N
N
CLK
CLK
Dec 13,2007 Sequential@iitk 22
Modulo 6 Counter - Specification
• A module 6 counter is a 3-bit counter that counts through the following sequence:– 000->001->010->011->100->101->000->…– 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 0 …
• It doesn’t use value 6 (110) nor 7 (111)• It has an input U that controls the counter:
– When U=1 the counter increments its value on the rising edge of the clock
– When U=0 the counter retains its value on the rising edge of the clock
• The value of the count is represented as three bit value (V2V1V0)
• There is an additional output C (Carry) that is 1 when going from 5 to 0 and 0 otherwise (the C output remains 1 until the counter goes from 0 to 1)
Dec 13,2007 Sequential@iitk 23
Modulo 6 Counter – State table
• For each state examine what happens for all possible values of the inputs– In state S0 input U can be either 0
or 1– If U=0 the state machine remains in
state S0 and outputs C=1 and V2V1V0=000
– If U=1 the state machine goes in state S1, outputs C=1 and V2V1V0=001
• In the same manner, each state goes to the next state if U=1 and remains in the same state if U=0
Present State
U Next State
C V2V1V0
S0 0 S0 1 000
S0 1 S1 0 001
S1 0 S1 0 001
S1 1 S2 0 010
S2 0 S2 0 010
S2 1 S3 0 011
S3 0 S3 0 011
S3 1 S4 0 100
S4 0 S4 0 100
S4 1 S5 0 101
S5 0 S5 0 101
S5 1 S0 1 000
Dec 13,2007 Sequential@iitk 24
Modulo 6 Counter - Mealy state diagram
• The outputs are represented on the arcs as CV2V1V0
Dec 13,2007 Sequential@iitk 25
Modulo 6 Counter – Moore state diagram
• The outputs are represented adjacent to the state• The inputs are represented on the arcs
Dec 13,2007 Sequential@iitk 26
Assigning State Values
• Each state must be assigned to a unique binary value; for a machine with n states we have [log2n] bits;
• For the modulo 6 counter example, we have six states. We will assign state value 000 to S0, 001 to S1, and so on, up to 101 to S5.
Dec 13,2007 Sequential@iitk 27
Assigning State Values
• Any values can be assigned to the states, some values can be better than others (in terms of minimizing the logic to create the output and the next state values)
• This is actually an iterative process: first the designer creates a preliminary design to generate the outputs and the next states, then modifies the state values and repeats the process. There is a rule of thumb, that simplifies the process: whenever possible, the state should be assigned the same with the output values associated with that state. In this case, same logic can be used to generate the next state and the output
Dec 13,2007 Sequential@iitk 28
Mealy and Moore Machine Implementations
• The current state value is stored into the register
• The state value together with the machine inputs, are input to a logic block (CLC) that generates the next state value and machine outputs
• The next state is loaded into the register on the rising edge of the clock signal
Dec 13,2007 Sequential@iitk 29
Mod 6 Counter – Mealy Implementation
• The logic block (CLC) is specific to every system and may consist of combinatorial logic gates, multiplexers, lookup ROMs and other logic components
• The logic block can’t include any sequential components, since it must generate its value in one clock cycle
• The logic block contains two parts:– One that generates the outputs
(f function, CLC1)– One that generates the next
state (g function, CLC2)
Dec 13,2007 Sequential@iitk 30
Mod 6 Counter – Moore Implementation
• The outputs depend only on the present state and not on its inputs
• Its configuration is different than the Mealy machine– The system output depends only on the present state, so the implementation of the
output logic is done separately
– The next state is obtained from the input and the present state (same as for the Mealy machine)
Dec 13,2007 Sequential@iitk 31
Generating the Next State
• Since the Mealy and Moore machines must traverse the same states under the same conditions, their next state logic is identical
• We will present three methods to generate the next state logic:– (i) Combinatorial logic gates– (ii) Using multiplexers – (iii) Using lookup ROM
• To begin with, we need to setup the truth table for the next state logic
Dec 13,2007 Sequential@iitk 32
Modulo 6 Counter - Next State Logic
• The system inputs and the present states are the inputs of the truth table
• Next state bits are the outputs• We have to construct a
Karnaugh map for each output bit and obtain its equation
• After that we design the logic to match the equations
Present State
P2P1P0
U Next State
N2N1N0
000 0 000
000 1 001
001 0 001
001 1 010
010 0 010
010 1 011
011 0 011
011 1 100
100 0 100
100 1 101
101 0 101
101 1 000
Dec 13,2007 Sequential@iitk 33
Modulo 6 Counter – Next State Logic
• N2 = P2P0’ + P2U’ +P1P0U
• N1 = P1P0’ + P1U’ + P2’P1’P0U
• N0 = P0’U + P0U’
Dec 13,2007 Sequential@iitk 34
• Modulo 6 Counter – Next State implementation using logic gates (i)
Dec 13,2007 Sequential@iitk 35
State Minimization
X-Successor – If an input sequence X takes a machine from state Si to state Sj, then Sj is said to be the X-successor of Sj
Strongly connected:- If for every pair of states Si, Sj of a machine M there exists an input sequence which takes M from state Si to Sj, then M is said to be strongly connected
Dec 13,2007 Sequential@iitk 36
State Equivalence
• Two states Si and Sj of machine M are distinguishable if and only if there exists at least one finite input sequence which, when applied to M, causes different output sequences, depending on whether Si or Sj is the initial state
• The sequence which distinguishes these states is called a distinguishing sequence of the pair (Si, Sj)
• If there exists for pair (Si, Sj ) a distinguishing sequence of length k, the states in (Si, Sj ) are said to be k-distinguishable
Dec 13,2007 Sequential@iitk 37
State EquivalenceMachine M1
PS NS, z
X = 0 X = 1
A E, 0 D, 1
B F, 0 D, 0
C E, 0 B, 1
D F, 0 B, 0
E C, 0 F, 1
F B, 0 C, 0
(A, B) – 1 Distinguishable
(A, E) – 3 Distinguishable
Seq - 111
k-equivalent – The states that are not k-distinguishable are said to be k-equivalent
Also r-equivalent r<k
Dec 13,2007 Sequential@iitk 38
State Equivalence
• States Si and Sj of machine M are said to be equivalent if and only if, for every possible input sequence, the same output sequence will be produced regardless of whether Si or Sj is the initial state
• States that are k-equivalent for all k < n-1, are equivalent
• Si = Sj, and Sj=Sk, then Si=Sk
Dec 13,2007 Sequential@iitk 39
State Equivalence
• The set of states of a machine M can be partitioned into disjoint subsets, known as equivalence classes
• Two states are in the same equivalence class if and only if they are euivalent, and are in different classes if and only if they are distinguishable
Property: If Si and Sj are equivalent states, their corresponding X-successors, for all X, are also equivalent
Dec 13,2007 Sequential@iitk 40
State Minimization Procedure
1. Partion the states of M into subsets s.t. all states in same subset are 1-equivalent
2. Two states are 2-equivalent iff they are 1-equivalent and their Ii successors, for all possible Ii, are also 1-equivalent
PS NS, z
X = 0 X = 1
A E, 0 D, 1
B F, 0 D, 0
C E, 0 B, 1
D F, 0 B, 0
E C, 0 F, 1
F B, 0 C, 0
P0 = (ABCDEF)
P1 = (ACE), (BDF)
P2 = (ACE), (BD), (F)
P3 = (AC), (E), (BD), (F)
P4 = (AC), (E), (BD), (F)
Dec 13,2007 Sequential@iitk 41
Machine Equivalence
• Two machines M1, M2 are said to be equivalent if and only if, for every state in M1, there is corresponding equivalent state in M2
• If one machine can be obtained from the other by relabeling its states they are said to be isomorphic to each other
PS NS, z
X = 0 X = 1
AC - α β, 0 γ, 1
E - β α, 0 δ, 1
BD - γ δ, 0 γ, 0
F - δ γ, 0 α, 0
δ
Dec 13,2007 Sequential@iitk 42
ExampleMachine M2
PS NS, z
X = 0 X = 1
A E, 0 C, 0
B C, 0 A, 0
C B, 0 G, 0
D G, 0 A, 0
E F, 1 B, 0
F E, 0 D, 0
G D, 0 G, 0
P0 = (ABCDEFG)
P1 = (ABCDFG) (E)
P2 = (AF) (BCDG) (E)
P3 = (AF) (BD) (CG) (E)
P4 = (A) (F) (BD) (CG) (E)
P5 = (A) (F) (BD) (CG) (E)