Sequential SynthesisSequential Synthesis

HistoryHistory: : Combinational LogicCombinational Logic single FSMsingle FSM Hierarchy of FSM’sHierarchy of FSM’s

MISIIMISII Sequential Sequential Circuit Circuit

PartitioningPartitioning

Facilities for Facilities for managing managing networksnetworks

of FSMsof FSMs

VIS (“handles” VIS (“handles” hierarchy)hierarchy)

Sequential Circuit Sequential Circuit Optimization (single Optimization (single

machine)machine)

SISSISFacilities for handling Facilities for handling

latcheslatches

Sequential SynthesisSequential Synthesis

Original Final

Sub ckt 1 Sub ckt n

...

Verify

Partition

Optimize

Interface logic(asynchronous?)

Combine/Flatten

Partition forlayout

What are Combinational What are Combinational Circuits?Circuits?

DefinitionDefinition: A circuit is : A circuit is combinationalcombinational if it computes a if it computes a function which depends function which depends onlyonly on the current inputs on the current inputs applied to the circuit; applied to the circuit; for every input set of values, for every input set of values, there is a unique output set of valuesthere is a unique output set of values..

• Acyclic circuits are necessarily combinationalAcyclic circuits are necessarily combinational• Cyclic circuits can be combinational, Cyclic circuits can be combinational,

– in fact, there are combinational circuits whose in fact, there are combinational circuits whose minimalminimal implementation must have cycles implementation must have cycles [Kautz 1970][Kautz 1970]

• Recent work on checking if circuit is combinational Recent work on checking if circuit is combinational [Malik ‘94, Shiple ‘95].[Malik ‘94, Shiple ‘95]. These are based on These are based on X-valued X-valued simulation.simulation.

What are Sequential What are Sequential Circuits?Circuits?

SomeSome sequential circuits have memory elements. sequential circuits have memory elements.– Synchronous circuits have Synchronous circuits have clockedclocked latches. latches. – Asynchronous circuits may or may not have latches (e.g. Asynchronous circuits may or may not have latches (e.g.

C-elements), but these are C-elements), but these are not clockednot clocked..

Feedback (cyclic) is a Feedback (cyclic) is a necessarynecessary, but not sufficient , but not sufficient condition for a circuit to be sequential.condition for a circuit to be sequential.

Synthesis of sequential circuits is Synthesis of sequential circuits is notnot as well as well developed as combinational. developed as combinational. (only small circuits)(only small circuits)

Sequential synthesis techniques are Sequential synthesis techniques are not really usednot really used in commercial software in commercial software (except maybe retiming). (except maybe retiming).

Sequential Sequential verificationverification is a problem. is a problem.

ExampleExample

The above circuit is sequential since primary output The above circuit is sequential since primary output depends on the depends on the statestate and primary inputs. and primary inputs.

LatchPresent StatePresent State Next StateNext State

in1in1in2in2

in3in3

in4in4

out 1out 1

prim

ary

inpu

ts

primary output

0

1

---1/1

----/1

(--00, 11-0)/0

(1010, 0110)/1

Registers and Latches (Netlist) State Transition Graph (STG)

Representations of Representations of Sequential CircuitsSequential Circuits

Transition relationTransition relation is is T(pi,ps,ns)T(pi,ps,ns) or or T(pi,ps,ns,po).T(pi,ps,ns,po). It is the characteristic function It is the characteristic function of all of all edgesedges of the STG. of the STG.

T(pi,ps,ns) = (nsi fi(pi,ps))

LatchPresent State Next State

in1in2

in3

in4

out 1

prim

ary

inpu

ts

primary output

Registers and Latches (Netlist)

0

1

---1/1

----/1

(--00, 11-0)/0

(1010, 0110)/1

State Transition Graph (STG)

nsns11

=

=

=

=

nsns22

nsns33

nsnsnn

Transition RelationTransition Relation

ns’ns’nn

ns’ns’33

ns’ns’22

ns’ns’11pipi

psps

Representation of Representation of Sequential CircuitsSequential Circuits

Each representation has its advantages and disadvantages. Each representation has its advantages and disadvantages. • STGSTG is like a two-level description is like a two-level description

– can blow up. can blow up.

• NetlistNetlist only way for large circuits. only way for large circuits. • Transition relationTransition relation T usually represented by BDD’s. T usually represented by BDD’s.

– Can blow up, but Can blow up, but – can also express it as separate relations for each latch which are can also express it as separate relations for each latch which are

implicitlyimplicitly conjoined: conjoined:

T = Ti ( pii ,psi ,nsi )

Example - Highway Light Example - Highway Light (Verilog)(Verilog)module hwy_control(clk, car_present, enable_hwy, short_timer,

long_timer, hwy_light, hwy_start_timer, enable_farm);input clk, car_present, enable_hwy, short_timer, long_timer;output hwy_light, hwy_start_timer, enable_farm;boolean wire car_present;wire short_timer, long_timer, hwy_start_timer, enable_farm,

enable_hwy;color reg hwy_light;initial hwy_light = GREEN;assign hwy_start_timer = (((hwy_light == GREEN) &&

((car_present == YES) && long_timer)) || (hwy_light == RED) && enable_hwy);

assign enable_farm = ((hwy_light==YELLOW) && short_timer);always @(posedge clk) begin

case (hwy_light)GREEN: if((car_present == YES) && long_timer) hwy_light = YELLOW;YELLOW: if (short_timer) hwy_light = RED;RED: if(enable_hwy) hwy_light = GREEN;endcase; end

module

Finite State MachinesFinite State Machines

Finite State Machines in STG or transition relation Finite State Machines in STG or transition relation form are a form are a behavioralbehavioral view of sequential circuits. view of sequential circuits. – They describe their transitional behavior.They describe their transitional behavior.– They can distinguish among a They can distinguish among a finitefinite number of classes of number of classes of

input sequence historiesinput sequence histories: : – These classes are the These classes are the internal statesinternal states of the machine. of the machine.

Moore MachineMoore Machine: is a quintuple: M(S, I, O, : is a quintuple: M(S, I, O, , , ))– S: finite non-empty set of S: finite non-empty set of statesstates– I: finite non-empty set of I: finite non-empty set of inputsinputs– O: finite non-empty set of O: finite non-empty set of outputsoutputs : S x I : S x I S S transitiontransition (or next state) (or next state) functionfunction : S : S O O output function output function (note: output only a function of (note: output only a function of

present state)present state)

FSM’s (continued)FSM’s (continued)

Mealy MachineMealy Machine: M(S, I, O, : M(S, I, O, , , ) but) but : S x I : S x I O O (i.e. output depends on both present state and (i.e. output depends on both present state and

present input)present input)

– for digital circuits, typically I = {0,1}for digital circuits, typically I = {0,1}mm and O = {0,1} and O = {0,1}nn

In addition, In addition, (for both Moore and Mealy machines)(for both Moore and Mealy machines) certain certain states are classified as states are classified as reset or initial statesreset or initial states

Finite automataFinite automata are are similarsimilar to FSM’s, but to FSM’s, but– they do they do notnot produce any outputs, produce any outputs, – they just they just acceptaccept input sequences input sequences (an (an accepting set of states is accepting set of states is

givengiven).).

Representing State Representing State MachinesMachines

State Transition Graph State Transition Graph

ExampleExample: Traffic Light Controller - Mealy Machine: Traffic Light Controller - Mealy Machine

HGHG

FGFG

HYHYFYFY

not(not(c) or t1)/not(not(c) or t1)/hl=hl=REDRED; fl=; fl=GREENGREEN; st=0; st=0

not(c and t1)/not(c and t1)/hl=hl=GREENGREEN; fl= ; fl= REDRED; st=0; st=0

not(ts)/not(ts)/hl=YELLOW; fl=hl=YELLOW; fl=REDRED; st=0; st=0

not(ts)/not(ts)/hl=hl=REDRED; fl=YELLOW; st=0; fl=YELLOW; st=0

ts/ts/hl=hl=REDRED; fl=YELLOW; st=1; fl=YELLOW; st=1

c and t1/c and t1/hl=hl=GREENGREEN; fl= ; fl= REDRED; st=1; st=1

ts/ts/hl=YELLOW; fl=hl=YELLOW; fl=REDRED; st=1; st=1

not(c) or t1/not(c) or t1/hl=hl=REDRED; fl=; fl=GREENGREEN; st=1; st=1

Input predicate/outputsInput predicate/outputsSTGSTG

Representing State Representing State MachinesMachines

State Transition Table State Transition Table

Example:Example: Traffic Light Controller - Mealy Machine Traffic Light Controller - Mealy Machine

PS IN NS OUTHG not(c and t1) HG hl=GREEN; fl=RED; st=1HG c and t1 HY hl=GREEN; fl=RED; st=1HY not(ts) HY hl=YELLOW; fl=RED; st=0HY ts FG hl=YELLOW; fl=RED; st=1FG not(not(c) or t1) FG hl=RED; fl=GREEN; st=0FG not(c) or t1 FY hl=RED; fl=GREEN; st=1FY not(ts) FY hl=RED; fl=YELLOW; st=0FY ts HG hl=RED; fl=YELLOW; st=1

Transition and Output Transition and Output RelationsRelations

• R R I I S S S S O O is the transition is the transition andand output relation output relation

• r = (in, sr = (in, spsps, s, snsns, out) , out) R R iff input iff input inin causes a causes a transition from transition from sspsps to to ssnsns and produces output and produces output outout..

• Since Since RR is a is a setset, it can be represented by its , it can be represented by its characteristic function characteristic function (and hence as a BDD).(and hence as a BDD).

• Depending on the application, it may be preferable to Depending on the application, it may be preferable to keep the transition and output relation keep the transition and output relation separateseparate::

– Transition Relation: Transition Relation: RR I I S S S S

– Output Relation: Output Relation: RR I I S S O O

Non-Determinism and Non-Determinism and Incomplete SpecificationIncomplete Specification

In automata theory, In automata theory, non-determinismnon-determinism is associated with many is associated with many transitions; transitions; – From a given current state and under the same input conditions we may From a given current state and under the same input conditions we may

go to go to differentdifferent states and have states and have differentdifferent outputs. outputs. – Each behavior is considered Each behavior is considered validvalid. . – Non-determinism provides a Non-determinism provides a compactcompact way to describe a way to describe a setset of valid of valid

behaviors.behaviors.

In classical sequential function theory, transition functions and output In classical sequential function theory, transition functions and output functions can be functions can be incompletelyincompletely specifiedspecified (functions can have don’t (functions can have don’t cares),cares), i.e. defined only on a proper i.e. defined only on a proper subsetsubset of their input space. of their input space. – where it is undefined, we consider it to allow where it is undefined, we consider it to allow anyany behavior. behavior.

Both methods describe Both methods describe setssets of valid behaviors. of valid behaviors.

s0s1

s2

a/0

a/1

Non-Determinism versus Non-Determinism versus Incomplete SpecificationIncomplete Specification

Given an input and present state:Given an input and present state:• Non-determinismNon-determinism: : somesome next states and next states and

outputs may be ruled out. outputs may be ruled out. – Result is that only a Result is that only a subsetsubset of next states and of next states and

outputs are outputs are admissibleadmissible for a transition. for a transition.

• Don’t caresDon’t cares: : allall next states and outputs are next states and outputs are allowed. allowed. – these may be because the given state is these may be because the given state is

unreachableunreachable, so will never occur, , so will never occur, – or the state is a or the state is a binary code not usedbinary code not used during the during the

state assignment.state assignment.

Non-Determinism versus Non-Determinism versus Incomplete SpecificationIncomplete Specification

Incomplete transition structure:Incomplete transition structure: It may be that no next state It may be that no next state is allowed. is allowed. – If this is because that input will never occur at that state we If this is because that input will never occur at that state we

can can “complete”“complete” the description by adding transitions to all the description by adding transitions to all states and allowing all outputs. states and allowing all outputs.

– On the other hand, we may want the machine to do On the other hand, we may want the machine to do nothingnothing (e.g. as an automaton). (e.g. as an automaton).

• Sometimes we “complete” the transition structure by adding a Sometimes we “complete” the transition structure by adding a dummy statedummy state and calling it a and calling it a non-acceptingnon-accepting state or a state state or a state whose output is an error signal.whose output is an error signal.

All describe a All describe a set of behaviorsset of behaviors. These are used to describe . These are used to describe • flexibilityflexibility for the implementation during synthesis, and/or for the implementation during synthesis, and/or • to describe a subset of to describe a subset of acceptableacceptable behaviors. behaviors.

Non-Determinism versus Non-Determinism versus Incomplete SpecificationIncomplete Specification

• Optimization tools for logic synthesis and Optimization tools for logic synthesis and verification verification exploitexploit, in various fashions, , in various fashions, incomplete specification to achieve incomplete specification to achieve optimization objectives.optimization objectives.

• Methods to exploit flexibility given by non-Methods to exploit flexibility given by non-determinism have been devised determinism have been devised [Kim and [Kim and Newborn, Somenzi, Wang, Wanatabe, Kam and Newborn, Somenzi, Wang, Wanatabe, Kam and Villa]Villa]

• At the At the implementation levelimplementation level, only one of the , only one of the possible next states and outputs in chosen possible next states and outputs in chosen (complete specification).(complete specification).

Incompletely Specified Incompletely Specified MachinesMachines

• Next state and output functions have Next state and output functions have don’t caresdon’t cares. . • However, for an implementation, However, for an implementation, and and are are functionsfunctions, ,

– thus they are uniquely defined for each input and state thus they are uniquely defined for each input and state combination.combination.

• Don’t cares arise when some combinations are of no Don’t cares arise when some combinations are of no interest:interest:– they will they will not occurnot occur or or– their outputs will their outputs will not be observednot be observed

• For these, the next state or output may not be For these, the next state or output may not be specified. specified. – (In this case, (In this case, and and are are relationsrelations, but of special type. We , but of special type. We

should make sure we want these as don’t cares.) should make sure we want these as don’t cares.)

• Such machines are called Such machines are called incompletely specifiedincompletely specified..

ExampleExample

By adding a By adding a dummydummy state this can be converted to a state this can be converted to a machine with only the output incompletely specified. machine with only the output incompletely specified.

Could also specify Could also specify “error”“error” as the output when as the output when transitioning to the dummy state. transitioning to the dummy state.

Alternatively Alternatively (better for optimization),(better for optimization), can interpret can interpret undefined next state as allowing undefined next state as allowing any next stateany next state..

s1 s2

1/1

1/-

0/0

s1 s2

1/1

1/-

0/00/- 0/-

s1 s2

1/1

1/-

0/0

d

0/-

-/-

added added dummydummynon-acceptingnon-acceptingstatestate

added transitionsadded transitionsto all states andto all states andoutput any valueoutput any value

Initializing SequencesInitializing Sequences

ReferenceReference: [C.Pixley, TCAD Dec. 1992]: [C.Pixley, TCAD Dec. 1992]

QQ: How many states does a circuit : How many states does a circuit (implementation)(implementation) with with nn memory elements have?memory elements have?

AA: 2: 2nn, one for each possible vector of values of these memory , one for each possible vector of values of these memory elements. elements. – Must assume on Must assume on power onpower on, that any of the 2, that any of the 2nn states is possible. states is possible.

M1: No initialization sequence possibleM1: No initialization sequence possible M2: Initialization sequence is possibleM2: Initialization sequence is possible

States visited inStates visited innormal oerationnormal oeration

States that can beStates that can bevisited only at startupvisited only at startup

Initializing Sequences Initializing Sequences (cont)(cont)

ReferenceReference: [C. Pixley, TCAD Dec. 1992]: [C. Pixley, TCAD Dec. 1992]• The set of states of normal operation forms a The set of states of normal operation forms a

strongly connected component.strongly connected component.• Initializing SequenceInitializing Sequence:: A sequence of input A sequence of input

vectors that forces the machine into a known vectors that forces the machine into a known set of “reset states”.set of “reset states”.– May be implemented with extra hardware, using a May be implemented with extra hardware, using a

single reset signal.single reset signal.

Pixley: Pixley: If an aligning sequence exists for If an aligning sequence exists for eacheach state pair, then an initializing sequence exists.state pair, then an initializing sequence exists.

FSM ExtractionFSM ExtractionProblemProblem: Given a : Given a netlistnetlist, extract an FSM from it., extract an FSM from it.

Extraction of the Transition and Output Extraction of the Transition and Output RelationRelation

Method 1:Method 1: Represent it by its characteristic function, Represent it by its characteristic function, (i,p,o,n).(i,p,o,n).

PPII

OO

NN

()()

()()

Next state andNext state andoutput logicoutput logic

functionfunctionvariablevariable

(i,p,o,n) = ((i,p,o,n) = ((i,p) (i,p) n) n) ( ((i,p ) (i,p ) o) o)

is the characteristic function of the transition and output is the characteristic function of the transition and output

relation.relation.– may be represented in several ways, the ROBDD representation may be represented in several ways, the ROBDD representation

seems to be most useful.seems to be most useful.

FSM ExtractionFSM ExtractionExplicit/Semi-Implicit Extraction of all TransitionsExplicit/Semi-Implicit Extraction of all TransitionsMethod 2:Method 2: (Ref: (Ref: [Devadas,Ma,Newton 88][Devadas,Ma,Newton 88]))Visit states starting from the reset states (in breadth-first-Visit states starting from the reset states (in breadth-first-

order).order).

extract(C) {extract(C) { /* C is the given circuit *//* C is the given circuit */st_table := { };st_table := { };list := { };list := { };foreach(s in reset_states)foreach(s in reset_states)

add_listadd_list(list, s);(list, s);while((ps := while((ps := next_unvisitednext_unvisited(list)) != NIL) {(list)) != NIL) {

/* iterate until all states have been visited *//* iterate until all states have been visited */while([(in, ns, out) := while([(in, ns, out) := generate_nsgenerate_ns(ps)] != NIL) {(ps)] != NIL) {

/* generate transitions from ps one by one *//* generate transitions from ps one by one */st_table := st_table + {(in, ps, ns, out)};st_table := st_table + {(in, ps, ns, out)};if(! if(! in_listin_list(list, ns)) (list, ns)) add_listadd_list(list, ns);(list, ns);

}}mark_visitedmark_visited(list, ps);(list, ps);}}return(st_table); }return(st_table); }

Of course, could do this in DFS order too, but see next slide.Of course, could do this in DFS order too, but see next slide.

FSM ExtractionFSM Extraction

Semi-Implicit Extraction of all TransitionsSemi-Implicit Extraction of all Transitions

generate_nsgenerate_ns(ps):(ps):1. Set present state lines to 1. Set present state lines to psps..2. Select a 2. Select a valuevalue for the next state and output lines for the next state and output lines

(sequentially go through all possibilities).(sequentially go through all possibilities).3. Find input values 3. Find input values (possibly none)(possibly none) that will result in that next that will result in that next

state and output value. This need not be a minterm but may state and output value. This need not be a minterm but may be a be a cubecube. Use ATPG justification techniques to find input . Use ATPG justification techniques to find input cube cube (however, must also find a cover of input cubes - i.e. (however, must also find a cover of input cubes - i.e. must enumeration all possible edges).must enumeration all possible edges).

Semi-Implicit Extraction:Semi-Implicit Extraction:– method is exponential in the number of statesmethod is exponential in the number of states

– may not be possible to representmay not be possible to represent in reasonable space as in reasonable space as a STTa STT

Implicit MethodImplicit Method– Use BDD’s to represent Use BDD’s to represent ..

Interconnected FSMs - FSM Interconnected FSMs - FSM NetworksNetworks

Natural way of describing complex systems Natural way of describing complex systems (hierarchy, (hierarchy, decomposition).decomposition). – Naturally extracted from HDL’s with modules as sub-processes.Naturally extracted from HDL’s with modules as sub-processes.

L3L3

L2L2BBAA

CC

PIPI

POPO

POPOxx

Interconnected FSMs - FSM Interconnected FSMs - FSM Networks (cont)Networks (cont)

• Interconnected FSMs Interconnected FSMs Single product machine Single product machine (similar to (similar to flattening in Boolean circuits)flattening in Boolean circuits)

• Directed Graph - Each node an FSM. Directed Graph - Each node an FSM. – Arcs are variables used for Arcs are variables used for communicationcommunication..

• Similar to Boolean network, but Similar to Boolean network, but – each node is an each node is an FSMFSM – possibly possibly cycliccyclic..

FSM

FSM NetworksFSM Networks

• Consider k component machinesConsider k component machinesMMii = (I = (Iii, S, Sii, O, Oii, , ii, , i i ), i = 1,…,k), i = 1,…,k

interconnected to form a network of FSMsinterconnected to form a network of FSMs

MMNN = M = M11 x M x M22 x … x M x … x Mkk = (I, S = (I, SNN, O, , O, NN, , N N ).).• MMN N is a single FSM consisting ofis a single FSM consisting of

– the state set ofthe state set of M MN N isis S SNN = S = S11 x S x S22 x … x S x … x Skk, , andand N N andand NN are the next state and output mappings induced are the next state and output mappings induced

by the properties of the component machines.by the properties of the component machines.

• MMN N realizes the product realizes the product (flattened)(flattened) machine machine • Using BDD’s, the transition relation for the product Using BDD’s, the transition relation for the product

machine is:machine is:T T ((I,S,O,S’ I,S,O,S’ )) = = TTi i ((IIi i ,S,Si i ,O,Oi i ,S’,S’ii ) )

11

33

22 k-2k-2

44 k-1k-1

kk

FSM NetworksFSM Networks

If we had If we had perfectperfect optimization tools, single optimization tools, single (product)(product) machine is best, however: machine is best, however:– product machine is product machine is hugehuge (state explosion problem) (state explosion problem)– tools are tools are heuristicheuristic (imperfect) (imperfect)

Tools needed for:Tools needed for:– synthesissynthesis of a network of a network (optimize components (optimize components

separately, using global information)separately, using global information)– verificationverification on a network on a network (verify network of reduced (verify network of reduced

components)components)– restructuringrestructuring FSM networks FSM networks

(decomposition/flattening)(decomposition/flattening)

Tools Tools analogousanalogous to ones we have for Boolean to ones we have for Boolean networks.networks.

Sequential Input Don’t Sequential Input Don’t CaresCares

Input don’t care Input don’t care vector sequencesvector sequences

• Machine Machine AA does not output a certain combination does not output a certain combination ll at at xx, , when when BB is in set of states is in set of states SSl l . The transitions of . The transitions of BB from from states in states in SSll under input under input ll are therefore are therefore unspecifiedunspecified..

• Can exploit this in state minimization and state encoding Can exploit this in state minimization and state encoding algorithms.algorithms.

L3L3

L2L2BBAA

CC

PIPI

POPO

POPOxx

Sequential Input Don’t Sequential Input Don’t CaresCares

Input Input don’t care sequencesdon’t care sequences of vectorsof vectors

Suppose that machine Suppose that machine AA (left) drives machine (left) drives machine BB (right). (right). – The two The two outputsoutputs of A are the of A are the inputsinputs to B. to B. – We note that A does not produce all possible output sequences. We note that A does not produce all possible output sequences.

• for instance, (11,11) is a for instance, (11,11) is a don’t care input sequencedon’t care input sequence for B. for B.

– This implies that a certain sequence of transitions will not occur in This implies that a certain sequence of transitions will not occur in B.B.

However, note that we However, note that we can’t simply removecan’t simply remove states in B. states in B.

q1q1

q3q3

q2q2

1/01

1/01

0/10

0/00

0/11

1/10S3S3

S1S1

S5S5

S4S4

S2S2

S6S6

-0/1

-0/0

01/0

11/0

-0/1

11/0 11/0

11/1

-0/0

-0/0

-0/1

A B

Kim and Newborn Kim and Newborn ProcedureProcedure

1. In general, automaton may be 1. In general, automaton may be nondeterministicnondeterministic. . Then have to determinize it with Then have to determinize it with “subset “subset construction.”construction.”

M1 M2

11

22

33

1/01

0/11

1/01

1/10

0/00

1/10

11

22

33

01

11

01

10

00

10

AA BB CC

-0/1

-0/1 -0/1 -1/0

11/111/0

3A3A

1A1A 2B2B

3B3B

1B1B2C2C

01/1

01/1

01/1

11/0

11/1

10/1

00/1

10/1

01/0

10/1

10/1 00/1

FSM M1 AUTOMATONfor M1

M1M2 Product

MachineA1 x M2

2. 2. Note:Note: product machine is product machine is incompletelyincompletely specified. specified. – Can use this to Can use this to state-minimizestate-minimize M2. M2.– Input don’t care sequences are due to the constrained controllability Input don’t care sequences are due to the constrained controllability

of the driven machine B in a cascade A of the driven machine B in a cascade A B. B.– Papers by Papers by Unger, Kim-Newborn, Devadas, Somenzi, and WangUnger, Kim-Newborn, Devadas, Somenzi, and Wang to to

exploit input don’t care sequences for logical optimization.exploit input don’t care sequences for logical optimization.

End of lecture 22End of lecture 22

Sequential Output Don’t Sequential Output Don’t CaresCares

AA feeds feeds BB. The . The thirdthird transition of transition of AA can output either can output either I1I1 or or I2I2, without changing , without changing the terminal behavior of the cascade the terminal behavior of the cascade AA BB. .

Called Called output expansionoutput expansion. Note that now machine A has a don’t care on an . Note that now machine A has a don’t care on an output.output.

sa1 sa2

sa3

qb1qb1 qb2qb2

qb3qb3

i1/ l1

i1/ l1i2/ l1

i2/ l1i2/ l2

i1/ -

I1/o1I1/o1(l1 or l2)/o3(l1 or l2)/o3

l1/o4l1/o4

l2/o1l2/o1

l2/o2l2/o2

i1 sa1 sa2 l1i2 sa1 sa3 l2i1 sa2 sa1 l2i2 sa2 sa3 l1i1 sa3 sa1 l1i2 sa3 sa2 l1

I1 qb1 qb2 o1l2 qb1 qb3 o2l1 qb2 qb2 o3l2 qb2 qb2 o3l1 qb3 qb2 o4l2 qb3 qb3 o1

A B

Due to the Due to the constrained constrained observabilityobservability of the driving of the driving machine A.machine A.

Sequential Output Don’t Sequential Output Don’t CaresCares

Output expansion produces a multiple-output FSM in which a Output expansion produces a multiple-output FSM in which a transition outputs any element of a transition outputs any element of a subsetsubset of values of values (rather than any element of all possible values as in the (rather than any element of all possible values as in the case of an unspecified transition. Should be called output case of an unspecified transition. Should be called output non-determinism).non-determinism).

Modify state minimization procedures to exploit output don’t Modify state minimization procedures to exploit output don’t cares. In previous example cares. In previous example sa2sa2 becomes compatible with becomes compatible with sa3sa3. One less state after state minimization . One less state after state minimization (at the (at the beginning both A and B are individually state minimized).beginning both A and B are individually state minimized).

sa1sa1 sa2sa2

sa3sa3

i1/ l1i1/ l1

i1/ l1i1/ l1 i2/ l1i2/ l1i2/ l1i2/ l1

i2/ l2i2/ l2

i1/ -i1/ -

sa1sa1 sa2sa2

i1/ l1i1/ l1

i1/ l1i1/ l1

i2/ l1i2/ l1i1/ l2i1/ l2

StateStateminimizeminimize

Overview of FSM Overview of FSM OptimizationOptimization

InitialInitial: FSM description: FSM description1.1. providedprovided by the designer as a state table by the designer as a state table

2.2. extractedextracted from netlist from netlist

3.3. derivedderived from HDL description from HDL description• obtained as a by-product of high-level synthesisobtained as a by-product of high-level synthesis• translate to netlist, extract from netlisttranslate to netlist, extract from netlist

State minimizationState minimization: Combine : Combine equivalentequivalent states to reduce the number states to reduce the number of states. For most cases, minimizing the states results in smaller of states. For most cases, minimizing the states results in smaller logic, though this is logic, though this is not always truenot always true..

State assignmentState assignment: Assign a unique : Assign a unique binarybinary code to each state. The code to each state. The logic structure depends on the assignment, thus this should be logic structure depends on the assignment, thus this should be done optimally done optimally (NOVA, JEDI).(NOVA, JEDI).

Minimization of a node:Minimization of a node: in an FSM network in an FSM network

Decomposition/factoring:Decomposition/factoring: of FSMs, collapsing/elimination of FSMs, collapsing/elimination

Sequential redundancySequential redundancy removal:removal: using ATPG techniques using ATPG techniques