Self Adaptive Body Biasing Scheme for Leakage power reduction under 32nm CMOS regime

International Journal of Advanced Computer Science, Vol. 3, No. 9, Pp. 453-459, Sep., 2013.

Manuscript Received:

30,Apr., 2013

Revised:

23,Jul., 2013

Accepted:

30,Jul., 2013

Published: 15,Aug., 2013

Keywords

Self-adaptive

bias voltage,

subthreshold

leakage,

Band-to-band

tunneling

leakage,

gate

tunneling

leakage,

32nm CMOS

Abstract This paper presents techniques

to determine the optimal reverse body bias

(RBB) voltage to minimize leakage currents

in modern nano-scale CMOS technology. The

proposed self-adaptive RBB system finds the

optimum reverse body bias voltage for

minimal leakage power adaptively by

comparing subthreshold leakage current

(ISUBTH), gate tunneling leakage (IGATE), and

band-to-band tunneling leakage currents

(IBTBT) in standby mode. The proposed circuit

has been designed and tested using 32nm

bulk CMOS technology at 25ºC under a

supply voltage of less than 1V. The optimal

RBB was achieved at -0.38V with 15% error

in the test case of the paper, and the

simulation result shows that it is possible to

reduce the total leakage current significantly

as much as 69% of the total leakage using the

proposed circuit techniques.

1. Introduction

To achieve higher density, higher performance, and

lower power consumption, CMOS transistors have been

scaled aggressively for decades and the supply voltage has

been reduced along with the shrinking of device

dimensions. Therefore, the threshold voltage (Vth) of a

transistor has to be commensurately scaled to achieve high

performance. Unfortunately, due to the exponential

relationship between leakage current and threshold voltage,

decreasing of Vth leads to a dramatic increasing of

subthreshold leakage. Reverse body biasing (RBB) is one of

the most widely used methods to reduce subthreshold

leakage, which has already been introduced by ‎[1].

However, the increasing RBB increases drain-induced

barrier lowering (DIBL) and substrate doping density,

which leads to an increasing of band-to-band tunneling

leakage. At the same time, increasing of RBB will increase

Vth, causing short channel effect in ultra-small technology,

which results in an increase of gate tunneling leakage.

Previous researches ‎[2], ‎[3] show that, in the standby

mode, a certain fixed RBB can reduce ISUBTH while maintain

a relatively small IGATE and IBTBT. And it has been shown

in ‎[4] that correctly applying body bias reduces the impact

of die-to-die and within die parameter variations. Therefore,

the implement of optimal RBB can lead to both reduction of

leakage power and yield improvement.

In this paper, a novel leakage monitoring schematic is

proposed, and the principle of the scheme is illustrated in

Fig. 1. To monitor the leakage current components, ISUBTH,

IBTBT, and gate tunneling leakage (IGATE) currents are

generated from a test device and convert the difference of

ISUBTH and IBTBT current into voltage signals assuming the

gate tunneling leakage does not change due to changing of

RBB voltage as much as the other two leakage components.

The‎converted‎voltage‎called‎“Vc”‎goes‎to‎the‎charge‎pump‎

shown in Fig. 1 to charge and discharge the capacitor in the

charge pump. The voltage in the capacitor (error voltage) is

fed back to the leakage monitoring circuit through the

output stage in the Fig. 1 to control the body bias voltage of

the test device to reduce the total leakage and to form a

closed loop. The closed loop is necessary to make the

scheme adaptive and to maintain the optimal body bias

status continuously. An optimal RBB is achieved and

maintained in the steady state if the two leakage currents

become equal.

Leakage

monitoring circuit

Current

comparator

I1 I2

Charge pump

RBBOutput stage

Cc1

charging

Cc1

discharging

Voltage control

signal (Vc)

Fig. 1. Block diagram of optimal RBB generating system

This paper is organized as follows: Section 2 presents

the three major leakage current components in ultra-small

CMOS technology, and Section 3 explains the novel

schematic of our optimal RBB system. Section 4 presents

the results of the achieved optimal RBB and its VT

variations, followed by the conclusion of the paper in

Section 5.

2. Leakage Current Components

There are several leakage components in scaled CMOS

transistor as illustrated in Fig. 2. In terms of magnitude, the

major leakage components in nanoscale CMOS devices are

subthreshold leakage (ISUBTH), gate tunneling leakage

(IGATE) and band-to-band tunneling leakage (IBTBT) ‎[5].

Thus, the total leakage current can be expressed as

BTBTGATESUBTHLEAKAGE IIII (Eq. 1)

Self Adaptive Body Biasing Scheme for Leakage

Power Reduction under 32nm CMOS Regime Jing Yang and Yong-Bin Kim


International Journal Publishers Group (IJPG) ©

454

source drain

gate

IBTBT_S IBTBT_D

IGIDL

IGCDIGCS

IGB

ISUBTH IGDIGS n+ n+

bulk

n+ poly

Fig. 2. Leakage components in a 32nm bulk CMOS transistor in the

standby mode

Those three major leakage components need to be

understood for leakage reduction efforts and they are

explained in this section.

A. Subthreshold Leakage

When the gate-to-source voltage in a MOS transistor is

below VTH, the transistor is not completely turned off,

instead, there is weak inversion region having some

minority carriers along the length of the channel. This

makes a small current flow from drain to source in NMOS

case, which is called the subthreshold leakage and is

expressed as

VGS is the gate to source voltage, Vth is the threshold

voltage, kT/q is the thermal voltage, n is the body effect

coefficient ‎[6], and VDS is the drain to source voltage.

B. Gate tunnelling leakage

In order to keep short-channel effect under control and to

maintain a good subthreshold turn-off slope, gate oxide

thickness is reduced in proportion to channel length. When

VOX <‎ΦOX, this results in an exponential increase in the gate

leakage due to the direct tunneling of electrons through gate

oxide into the substrate (or vice versa) or from gate to

source/drain (or vice versa), VOX is potential drop across

oxide,‎ ΦOX is the SiO2-Si conducting band energy

difference. This current is referred to as gate leakage and its

current density is expressed as below ‎[8]:

Where JDT is the direct tunneling current density, m* is

the effective mass of an electron and TOX is the oxide

thickness. And potential drop across the oxide can be

obtained from

Considering IGATE does not changing significantly with

the changing of VGB, it is less sensitive to RBB. What is

more, gate leakage current issue can be overcome while

maintaining excellent gate control by using high-k dielectric

material. Therefore, when considering RBB adjustment to

reduce leakage power, IGATE can be ignored as in ‎[2].

C. Band-to-band Tunnelling (BTBT)

In a high electric field (>106V/cm), there are electrons

tunneling across the reverse biased PN junction of

drain-substrate and source-substrate. If both n and p regions

are heavily doped, the IBTBT significantly increases and

becomes a major contributor to the total leakage current,

and the current is expressed as below:

Where A is the junction area, E is the electric field at the

junction, Vapp is the applied reverse bias voltage, q is the

electron charge and ħ is the reduced Plank constant. Na and

Nd are the doping in p and n side, respectively, ɛsi is the

permittivity of silicon and Vbi is the build-in voltage across

junction.

The gate induced drain leakage (IGIDL) is the current from

drain to substrate caused by high electric field between gate

and drain. This leakage mechanism becomes worse by high

drain-to-body voltage and high drain-to-gate voltage. In this

paper, IGIDL is taken into account with IBTBT. Since both

currents are from drain to substrate, they are not easy to

measure from the simulation results and according to ITRS

and as explained in ‎[7], VGD=-VDD does not result in any

significant IGIDL, which means taking IGIDL into account in

IBTBT will not make significant difference to the result. In a

CMOS transistor, there also exists gate induced source

leakage, but it is relatively small compare with IGIDL, thus

can be ignored in leakage analysis.

3. Optimal Body-Biasing

Technique

The total standby leakage can be written as:

Yang et al.: Self Adaptive Body Biasing Scheme for Leakage Power Reduction under 32nm CMOS Regime.


455

MN1

MN2

P3

P5

P6

P4

P7

E2

Rf

IC2

MN6

M1

M3

M4 M5

P1 P2

E1

Rf

M2

IC1

IGD

IBTBT_S

ISUBTH

IGCD Vbn

Vbn

Vbn

IGD

IGCD

IBTBT_D

Ecomp

R3 R1

R2

R4

VA

V7

V7S

Fig. 3. The proposed leakage monitoring circuit

From Eq. (2) and Eq. (6), ISUBTH and IBTBT have the

opposite dependence on body bias, and it can be seen that

there exists an optimum RBB voltage to minimize the total

standby leakage ‎[2], ‎[9], ‎[10]. The ISUBTH and IBTBT can be

simplified as follows:

Where As, Bs, Ab and Bb are process dependent constants

and Vbn is the RBB voltage.

From Eq. (7), Eq. (8) and Eq. (9), the substrate voltage

that makes the minimum leakage current occurs when

∂Ileakage/∂Vbn=0. As IGATE is insensitive to body bias, the

standby leakage is minimized at the RBB at which

BsISUBTH=BbIBTBT. Assuming Bs=Bb, ISUBTH and IBTBT should

approximately be equal to reach a minimum leakage

current.

A. Prior Arts of leakage monitor

The ratio of ISUBTH and IBTBT is not easy to determine due

to process variations and the complexity of calculating the

electric field across the junction. In addition, the ratio varies

with technology and doping profile ‎[2]. Therefore, a leakage

monitoring circuit to compare ISUBTH and IBTBT is the

prerequisite to find the optimal RBB voltage. ISUBTH and

IBTBT comparison circuits have been designed in ‎[2], ‎[3], ‎[9]

and ‎[10].

C.Neau ‎[2] introduced a model to calculate

ISUBTH/2-I’SUBTH-IDG/2-IGIDL/2. While ignorance of IGB

causes a minor error in leakage calculation, the

drain-to-source voltage drop in PMOS current mirror also

causes errors in mirroring leakage components in the

approach. M.Nomura ‎[3] developed a more precise model

with consideration of IGB and IDG and maintaining the drain

voltages of current mirrors with op-amps. However, the use

of op-amp causes a voltage drop issue between the

connected PMOS and NMOS on the current subtraction,

which affects the mirror of the leakage currents as well.

K.K.Kim ‎[9] and H.Jeon ‎[10] provided improved model,

which separate ISUBTH and IBTBT by using current mirrors.

However, the circuits are complicated and delicate to design,

and the mismatch among current mirrors leads to erroneous

results in leakage current calculation. In ‎[15], subtraction of

threshold leakage and junction leakage is generated and the

subtraction is converted into voltage. The use of op-amp as

voltage shifters makes sure that the circuit works properly,

but too much op-amps takes up too much area and is power

consuming.

B. Proposed leakage comparator circuit

In this paper, a novel leakage current monitoring scheme

is proposed. Fig. 3 shows the circuit that generates leakage

currents, converts leakage components into voltages, and

compares them. The optimum RBB occurs at which the two

converted voltages is equal.

The source and gate tied NMOS transistor MN6 is in the

“off”‎state and the leakage current through MN6 is leakage

I1 and is given by I1-(ISUBTH+IDG+IGCD-IBTBTS). Current

through the drain of a gate-grounded‎“off”‎NMOS‎transistor‎

MN1 stacked on top of another NMOS transistor MN2 is

given by I2= (IDG+IGCD+IBTBTD). Considering the stack effect

of MN1 and MN2, the subthreshold leakage I’SUBTH through

MN1 is tremendously reduced by a factor of 10 compared

with ISUBTH of a single transistor and it can be even smaller

in 32nm NMOS technology ‎[11], ‎[12] with lower supply

voltage. The subthreshold leakage and the band-to-band tunneling

is around several hundred pico-amperes, thus, a more

accurate and precise current mirror is required as mentioned

in ‎[13], ‎[14]. As shown in Fig. 3, M3-M5 implement a

voltage shifter that makes the gate voltage of M1 one

threshold voltage below its drain, current source IC1 is

100nA, I1= (ISUBTH+IDG+IGCD-IBTBTS) is mirrored by M1, M2,

P1 and P2, the op-amp E1 with a feedback resistor is

used as a current to voltage converter and the converter

converts I1 into V7=-I1∙Rf. In a similar way, I2=

(IDG+IGCD+IBTBTD) is mirrored by transistors P6 and P7 and

then converted into V7s=-I2∙Rf by E2.

R1=R2=R3=R4 are set in Fig. 3. The difference between

V7 and V7s provides a means to compare ISUBTH vs. IBTBT.

Instead of comparing pA level current, it is relatively easier



456

to compare voltage by setting the feedback resistors high

enough. Therefore, we get VA=V7-V7s=-Rf ∙ (I1-I2)=-Rf ∙‎

(ISUBTH-IBTBTS-IBTBTD)=-Rf ∙‎(ISUBTH-IBTBT).

Level shifter in Fig. 4 using op-amp is used to adjust the

voltage level of VA and it generates VA’. The use of level

shifter makes the output voltage swing from zero to supply

voltage.

C. RBB regulator analysis

VA drives gates of the two CMOS transistors P20 and N25.

Fig. 4 shows the circuit schematic of the charge pump and

output stage of RBB. There are three operation modes for

the gate inputs of P20 and N25:

1) Case a: If ISUBTH>IBTBT, VA<0, and N25 is turned on

and capacitor Cc1 is discharging. Gate voltage of P22

decreases, drain current of P22 increases, and the absolute

value of Vbn (|RBB|) increases. Increasing of |RBB| leads to

decreasing of ISUBTH and increasing of IBTBT, which moves

whole circuit toward case b.

2) Case b: If ISUBTH=IBTBT, IA=0, VA=0, and P20 is

slightly on, Cc1 will be charging slowly towards Vdd. Gate

voltage of P22 increases slowly along with decreasing of

drain current through P22, and when the voltage on Cc1 is

greater than the threshold voltage of P22, P22will turn off and

the absolute value of RBB voltage will decrease until a

certain value. Then the voltage change through Cc1 is fixed

and |RBB| is hold.

3) Case c: If IBTBT>ISUBTH, IA>0, VA<0, P20 is in the

“on”‎state,‎Cc1‎is‎charging‎towards‎Vdd. The gate voltage of

P22 increases with its drain current decreasing, which drives

|RBB| to decrease. And the decreasing of |RBB| leads to an

increasing of ISUBTH and decreasing of IBTBT. The whole

circuit will go back to mode case b.

Eamp

Rbn

P17 P18 P19

P20

N25

N24N23N22N21Cc1

P22

Vdd

Vdd

VA’

Vbn

-

+VA

Vddn

Els

1kΩ2kΩ

1kΩ

2kΩ

Fig. 4. Charge pump and output stage to generate RBB

From the above three modes, we can see that, under the

control of VA, the output of Vbn (RBB) is continuously

regulated through charging and discharging capacitor Cc1

in the charge pump until the optimal RBB is reached.

The implemented optimal RBB circuit accomplishes

optimal RBB of NMOS transistors. In the exactly same way,

an optimal RBB of PMOS transistor can be achieved as

well.

4. Experiments and results

A. Experimental results

Fig. 5 shows an optimal RBB when leakage of ISUBTH

and IBTBT equals for single NMOS transistors in the

standby mode. For NMOS transistor ‎[16] ‎[17] that has

W/L=5um/32nm, optimal RBB voltage is achieved at

around -0.25V minimizing the total leakage currents.

Fig. 5. ISUBTH and IBTBT for single NMOS transistor in the standby mode

with W/L=5u/32nm at supply voltage of 1V and temperature of 25ºC

Fig. 6. Simulation results of the proposed current monitoring circuit

Error! Reference source not found. shows simulation

results of the proposed current monitoring circuit using

32nm bulk CMOS technology at the supply voltage of 1V

and temperature of 25ºC. The W/L ratio of the NMOS

transistors is 5µm/32nm. The standby mode NMOS

transistors MN6 and MN1 have different leakage

components as shown in Fig. 3, and they are denoted as I1



457

and I2 as explained in Section Error! Reference source

not found.. The subtraction of I1 from I2 is given by

ISUBTH-IBTBT and the zero value of ISUBTH-IBTBT indicates the

optimum RBB voltage point to minimize the total leakage

current. As shown in Error! Reference source not found.

the optimum RBB voltage turns out to be 0.38V in the case.

The mirrored current through P2 and P7 form the

current monitor and the subtraction of the two current

(almost same as ISUBTH-IBTBT) reaches its zero value at the

optimum RBB of 0.337V, which is around 0.6% error

compared to ISUBTH-IBTBT from MN6 and MN1. This result

proves that the proposed current monitor circuit is precise

enough to mirror the leakage components and perform the

subtraction accurately. The voltage through E1 and E2 was

compared and the zero value appears at 0.38V, which is

around 15% error compared to ISUBTH-IBTBT from MN6 and

MN1. The total leakage current is 82.57pA at the achieved

optimal RBB at -0.38V compared with 265.48pA at zero

body bias voltage, which demonstrates a significant

reduction as much as 69% of the total leakage.

ISUBTH-IBTBT flows through Rf and is converted to

voltage signal. The bottom two curves in Fig. 6 show the

trend of the relationship between ISUBTH-IBTBT and the

corresponding voltage output signal VA.

B. VT variations of leakage current

Systematic and random variations in supply voltage and

temperature causes leakage of low power circuits to vary

significantly under design values and these variations are

posing increasing challenge to nano-scale circuit design.

The demand for low power causes supply voltage scaling,

making voltage variations a significant design challenge.

What is more, the quest for growth in operational frequency

occurs at high junction temperatures and with die

temperature variations. Sections below show how

temperature and supply voltage changes affect optimal RBB

in the proposed circuit.

1) Temperature variations with RBB: Temperature

variations change the mobility of electrons and holes. An

increase in operating temperature causes the mobility to

decrease. From Eq. (2) and Eq. (3), with the increasing of

temperature and decreasing of µ0, ISUBTH will decrease and

the curve will be more flat. On the other hand, under high

temperatures, electrons have more energy and the tunnelling

across the reverse biased PN junction of drain-substrate and

source-substrate tunnels will be more probable, which

results in an increase of band tunnelling current. Eq. (6)

well explains that; increasing of temperature leads to an

increasing of IBTBT, which makes the curve sharper.

Therefore, the optimal RBB is decreased in this case. Figure

8 shows the ISUBTH-IBTBT curve at temperature ranging from

-25 ºC to 75 ºC. Fig. 7 shows the corresponding RBB under

temperature variations for IBTBT and ISUBTH. It is observed

that, the substrate needs to be more biased with temperature

increasing in order to achieve less leakage.

2) Voltage variations with RBB: Large current consumption

across long power lines with parasitic impedance causes

varied, low and unstable voltage levels on the power line.

This variation results in uneven supply voltage distribution

and temperature hot spots, causing transistor subthreshold

leakage variation across the die. As can be seen in Eq. (2),

increase of Vdd will result in increase of ISUBTH, making the

curve‎more‎“curvy”,‎and‎Eq. (6) shows that IBTBT will also

increase with increasing of Vdd. Therefore, the optimal

RBB is decreased as expected. Fig. 9 above shows the

corresponding optimal RBB at Vdd ranging from 0.8V to

1.1V. We can tell that with VDD increasing, we need the

substrate to be more biased in order to achieve less leakage

also.

Fig. 7. Temperature variations on IBTBT and ISUBTH of W/L=5u/32nm cmos

under 1V supply

Fig. 8. Effects on temperature variations on leakage currents of proposed

circuit

5. Conclusion

As technology scaling goes down below 90nm, the

standby leakage increases significantly. This makes the

circuit design technique for minimizing leakage power more

T=0ºC

T=75ºC

T=0ºC

T=-25ºC

T=75ºC



458

important. In this paper, a leakage monitoring circuit is

proposed and designed to determine the optimal RBB by

comparing the two major leakage components of ISUBTH and

IBTBT. It is possible to accomplish the minimum total

leakage power during standby mode by monitoring the

leakage current components. Using the information found in

the monitoring circuits, an optimal body bias (RBB) voltage

is found and applied to the substrate to accomplish the

minimal leakage during standby state.

Fig. 9. Effects on supply variations

Comparing the converted voltages from the measured

two major leakage current components, the optimum RBB

is generated using charge pump circuit. The voltage of the

capacitor in the charge pump is held once the optimal RBB

is reached. Otherwise, it keeps charging and discharging the

capacitor to adaptively adjust RBB. The optimal RBB was

achieved at -0.38V with a small error in the test case in this

paper. RBB also varies with supply voltage and temperature

variations. With the increasing supply voltage and/or

temperature, we need more negative biased RBB to achieve

leakage reduction. The result shows that it is possible to

reduce the total leakage significantly as much as 69% using

the proposed algorithm. This research can be a good

reference for the future research in leakage minimization.

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459

Jing Yang received the B.S. and M.S.

degree in physics from Shanghai Jiaotong

University, Shanghai, China in 2003 and

Northeastern University, Boston, MA in

2009 respectively. She is currently working

toward the Ph.D. degree in electrical and

computer engineering at Northeastern

University, Boston, MA. Her research

interests include low-power high-speed

analog circuit design, clock design and interconnect analysis.

Yong-Bin Kim received the B.S. degree in

electrical engineering from Sogang

University, Seoul, Korea, in 1982, the M.S.

degree in electrical engineering from the

New Jersey Institute of Technology,

Newark, in 1989, and the Ph.D. degree in

electrical and computer engineering from

Colorado State University, Fort Collins, in

1996. From 1982 to 1987, he was a Technical Staff Member at

Electronics and Telecommunications Research Institute (ETRI),

Daejeon, Korea. From 1990 to 1993, he was a Senior Design

Engineer at Intel Corporation involved in microcontroller chip

design and Intel Pentium Pro microprocessor chip design. From

1993 to 1996, he was a Technical Staff Member at Hewlett

Packard Company, Fort Collins, involved in HP PA-8000 RISC

microprocessor chip design. From 1996 to 1998, he was a Staff

Engineer at Sun Microsystems, Palo Alto, CA, involved in 1.5

GHz Ultra Sparc5 CPU chip design. From 1998 to 2000, he was

an Assistant Professor in the Department of Electrical

Engineering, University of Utah, Salt Lake City. He is currently

an Associate Professor in the Department of Electrical and

Computer Engineering, Northeastern University, Boston, MA. His

research focuses on low-power analog and digital circuit design as

well as high-speed low-power very large-scale integrated circuit

design and methodology.

Documents

Self Adaptive Body Biasing Scheme for Leakage power reduction under 32nm CMOS regime