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RTC Magazine SEPTEMBER 2014 | 3

The Magazine of Record for the Embedded Industry CONTENTS

12

06From Microcontroller to System-on-Chip: A Challenge to the Full-Custom ASIC?

EDITORIAL

10FPGAs Provide Glue AlternativesSMALL FORM FACTOR FORUM

08Latest Developments in the Embedded Marketplace

INDUSTRY INSIDER

44Newest Embedded Technology Used by Industry Leaders

PRODUCTS & TECHNOLOGY

DEPARTMENTS

TECHNOLOGY COREARM CORES OPTIMIZE PERFORMANCE AND POWER

18

by Matt Saunders, Silicon Labs

Tips and Tricks for Minimizing ARM Cortex-M CPU Power Consumption

12


Which ARM Cortex Core Is Right for My Application: A, R or M?

TECHNOLOGY CONNECTEDLOW POWER BLUETOOTH CONNECTS DEVICES

24

by Vishal Goyal, STMicroelectronics

Bluetooth Smart – A Revolution for Low Power Connectivity

TECHNOLOGY IN SYSTEMSMODULAR SYSTEMS FOR INDUSTRIAL AUTOMATION

28

by Dave Hughes, HCC Embedded

Software Optimization Can Reduce MCU “Active-Phase” Power Consumption

34

by Jon Trout, TrendPoint Systems

Intelligent Power Consumption and the Data Center

INDUSTRY WATCHBUILDING MANAGEMENT SYSTEMS

38

by Jim O’Callaghan, EnOcean

Energy Harvesting Wireless Solutions: Building Management and Beyond


HTRANS

HADDR

HRDATA

Fetch

Execute

NSEQ IDLE NSEQ

a4 a6

IDLE

i3 i4 i5 i6

i2 i3 i4 i5

i6 i7i4 i5

AHBaccess

CPUpipeline

18


34

Intelligent Power Consumption and the Data Center

38


4 | RTC Magazine SEPTEMBER 2014

RTC MAGAZINE

PUBLISHERPresidentJohn Reardon, [email protected]

Vice PresidentAaron Foellmi, [email protected]

EDITORIALEditor-In-ChiefTom Williams, [email protected]

Senior EditorClarence Peckham, [email protected]

Contributing EditorsColin McCracken and Paul Rosenfeld

Copy EditorRochelle Cohn

ART/PRODUCTIONArt DirectorJim Bell, [email protected]

Graphic DesignerMichael Farina, [email protected]

ADVERTISING/WEB ADVERTISINGWestern Regional Sales ManagerMike Duran, [email protected](949) 226-2024

Midwest, Canada, EMEA and Asia Sales Manager Mark Dunaway, [email protected] (949) 226-2023

Eastern Regional Advertising ManagerJasmine Formanek, [email protected](949) 226-2004

BILLINGVice President of FinanceCindy Muir, [email protected] (949) 226-2021

TO CONTACT RTC MAGAZINE:Home OfficeThe RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673Phone: (949) 226-2000Fax: (949) 226-2050Web: www.rtcgroup.com

Editorial Office Tom Williams, Editor-in-Chief 1669 Nelson Road, No. 2,Scotts Valley, CA 95066 Phone: (831) [email protected]

Published by The RTC GroupCopyright 2014, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.

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EDITORIAL

by Tom Williams, Editor-In-Chief

Consider the humble microcon-troller. In the vast majority of appli-cations—keyboards, toasters, coffee makers and more—it goes almost completely unnoticed. Yet since its appearance in the mid-1970s, and mostly in its 8-bit form, it continues to operate in the background of everything we do in our daily lives. However, in order to adapt this little device to its huge world of functionality, it has been necessary to modify the chip design around the basic MCU with a bewildering variety of on-chip peripherals, I/O and memory options. Perhaps the best known example of this is the Intel 8051, whose variants fill count-less catalog pages and for which compatible versions have been de-veloped by over 20 vendors. Each of these also has catalog pages of variants. Now, of course, the core is also available as IP for use in SoCs and FPGAs as well. 8-bit microcon-trollers are even showing up buried deep in powerful, multicore CPUs and SoCs to handle such mundane but vital tasks as on-chip power management.

This last little item leads us to the present, which is being driven by Moore’s Law and integration. There are, of course, much more compli-cated things for microcontrollers to do than run toasters. In fact, the con-cept of a microcontroller—a small processor to attend to detailed, limited control functions—has blos-somed into 32- and 64-bit multicore processors; multicore processors with different CPU, GPU or DSP architectures on the same device; multicore CPUs with FPGA fabrics on the same die; and the addition of huge numbers of peripherals, memory and I/O functions on-chip. This scale of integration blurs the

distinction between microcontroller and SoCs; for systems that must include audio and graphics, it pulls the traditional CPU with companion processors into the world of the MCU and calls into question the traditional role of the ASIC.

Take a look at the block diagrams for devices such as the PIC32MZ EC family from Microchip, the OMAP 5 family from Texas Instru-ments, the Atom-based Bay Trail from Intel, the NVIDIA Tegra K1, the Cyclone V from Altera and the Zync 7000 family from Xilinx, to name a few, and be astonished. We have moved beyond the mere multicore processor to the heterogeneous SoC with a wealth of other on-chip devices, processor cores, memory options and internal buses. Many of these are product families, meaning that even at this level of integra-tion, there are variants designed to address different market needs. The big advantage is that these devices are mass-produced and readily available at reasonable and predictable costs. The developer considering a complex and powerful product design will have to carefully consider the cost and time-to-mar-ket implications of such devices.

Even if such a device is not totally “custom,” that is, there may be on-chip peripherals, for example, that are not used in a particular applica-tion, it may still be advantageous to use it given cost and time-to-market considerations balanced with power and size requirements. One might initially think, for example, that given their size, power requirements and volume, smartphones would be a natural home for full-custom ASICs. However, a large number of smart-phones from different manufactur-ers are using the dual ARM Cortex-

A9-based OMAP4430 and 4460 devices from TI.

Not surprisingly, the big hurdle for heterogeneous SoCs as well as for ASICs is software develop-ment. Diverse processors on a chip require different versions of oper-ating systems, different compilers and different development tools. In addition to programming the different cores, such a device must also be configured for such things as defining shared memory, shared peripherals, priorities and the “peck-ing order” of the on-chip processor cores. At this point, the vendors of this generation of SoCs are well aware that if they are going to offer products with a ton of peripherals, they also need to supply drivers for them so that the customer can get up and running without having to worry about low-level details.

Software also drives the ASIC developer but in a different way. Since the hardware device is being designed for a specific application, the idea is not to write a bunch of drivers, but to move as much of the software functionality as possible into hardware. That means starting with a software definition to begin the hardware design and quite a bit of customization of application and operating system for optimal performance. The expected time to accomplish this is currently about 48 months. It would appear that if heterogeneous SoCs can get over their software hurdles with innova-tions in the tool arena, they could achieve a considerable leap over the conventional ASIC.

There are currently efforts under-way to do just that. A number of companies including AMD, ARM, Qualcomm, Samsung, TI and others have founded the Heterogeneous

From Microcontroller to System-on-Chip: A Challenge to the Full-Custom ASIC?


INDUSTRY INSIDER

Cornell UniversityAutonomousUnderwater VehiclePowered by AdlinkCOM Express Module

Adlink Technology has announced its sponsorship of the Cornell University Autonomous Underwater Vehicle (CUAUV) team’s entry into the 17th Annual International RoboSub competition that was held at the Space and Naval Warfare Command Research facility in San Diego, CA.

The CUAUV’s Gemini submarine is powered by Adlink’s Express-HL COM Express computer-on-module, featuring a fourth generation quad-core Intel Core i7 processor with Mobile Intel QM87 Express chipset. The Express-HL acts as Gemini’s lone onboard computer, tasked with all vision processing and decision-making required by the AUV. In addition, the Express-HL COM Express carrier board runs its own controller, as well as communicates with mi-cro-controllers on several custom-built peripheral circuit boards also included in Gemini’s design.

The CUAUV team, made up of 43 students from three of Cornell’s colleges, spends more than 20,000 person-hours per year designing its vehicle and has won the annual Ro-boSub competition four out of the last five years. The team began testing Gemini in pool and lake waters back in June, performing and perfecting anticipated manipulation tasks for the mission elements included in the competition’s obstacle course.

The international RoboSub competition is co-sponsored by the Association for Unmanned Vehicle Systems Interna-tional (AUVSI) Foundation and the U.S. Office of Naval Re-search (ONR) with the goal of advancing the development of AUVs. The event serves to foster ties between young engineers and organizations developing AUV technologies. The competition mission elements and tasks are designed to simulate real-world challenges, such as visual recogni-tion of objects, navigation and acoustic sensing.

Altera has announced it has joined the Embedded Vision Alliance (EVA), an industry group that brings together providers of the technology used to create practical applications of computer vision. Altera will offer the group its insights on programmable logic technologies that enable systems designers to use FPGAs, SoCs, IP and design tools for embedded vision applications in the industrial, surveillance, automotive, military, broadcasting and consumer sectors.

Altera FPGAs provide flexibility and performance benefits across the embedded vision processing pipeline, including image sensor interface, image signal processing, compression, transmission and video content analytics. An FPGA’s parallel architecture aids in the accelera-tion of vision processing algorithms, while the Altera SDK for OpenCL design tool offers easy implementations of parallel processing applications onto FPGAs.

“Altera is joining the alliance to propose solutions to address head-on the performance bottlenecks of CPUs, and to continue to offer new IP through the end-to-end vision processing pipeline,” said Dan McNamara, vice president of the Industrial, Automotive, and Broadcast Business Unit at Altera. “With our industry lead in OpenCL development tools, as well as a strong, evolving ecosystem of vision processing technologies, we are joining the alliance to facilitate further innovations in the embedded vision industry.”

“Embedded vision allows machines to see and understand the world around them, enabling them to be more responsive, safer and more capable,” said Jeff Bier, founder of the Embedded Vision Alliance. “Altera is an innovator in technologies that enable engineers to incorporate visual intelligence into their product designs. I welcome Altera to the Embedded Vision Alli-ance, and look forward to collaborating to advance the Alliance’s goal of empowering product creators to use embedded vision technology.”

Altera Joins the Embedded Vision Alliance

STMicroelectronics has announced it has opened a new MEMS Microphone Lab (Anechoic Chamber) in Taiwan to test and analyze high-performance audio appli-cations built with ST’s MEMS microphones. ST’s new advanced MEMS Microphone lab will focus on all-level audio performance testing from components (microphone or acoustic components) to modules and systems, including smartphones, tablets, notebooks, TVs and remote controls, ensuring superior recording and sound quali-ty, shorter debugging period, and faster time-to-market for end applications.

“With the increasing demand for advanced microphone applications in the Greater China region, it is imperative for ST to strengthen its local technology and application support,” said Francois Guibert, executive vice president and president of ST’s Greater China and South Asia Region. “Establishing a new advanced testing lab facility in Taiwan will allow us to work even more closely with our key custom-ers and partners in the region to optimize the quality of their products at all levels and develop innovative applications with excellent audio performance.”

Equipped with the APx525 Family Audio Analyzer from Audio Precision, ST’s new MEMS Microphone Lab in Taiwan complies with the ISO 3744/3745 industrial acoustic standard and environmental noise regulation, as well as Intel’s Speech and Voice Recognition Standard.

STMicroelectronics Opens MEMS Microphone Lab to Enhance Audio Performance


Altera has announced that it ranked #24 on the Newsweek 2014 Green Rankings of more than 500 U.S. companies. Newsweek’s annual Green Rankings is one of the world’s most recognized assessments of corporate sustainability and environmental impact. Newsweek evaluated compa-nies on eight specific indicators, including conservation and sustainabili-ty efforts in the areas of energy, carbon, water and waste productivity.

Company reputation was also taken into account in the ranking, and Altera earned the highest marks in this area. Reputation was scored by a consultancy called RepRisk, which collects and analyzes controversies related to human rights violations, poor working conditions, corruption and environmental destruction.

Among the green efforts is Altera’s recycling program, which diverts well over 80 percent of the waste generated on the San Jose, CA site away from landfills to be recycled, composted or reused. In addition, Altera installed Bloom Energy fuel cells in late 2012, which reduced the pur-chased-electricity carbon footprint by 34 percent. Altera’s strong focus on corporate social responsibility also includes guidelines and tracking of sustainable procurement, supply chain propagation, and employee health and safety initiatives.

Newsweek partnered with independent investment research company Corporate Knights Capital to complete the 2014 Green Rankings. To en-sure data collected was accurate and reliable, Corporate Knights Capital used a variety of techniques, including statistical analysis of industry trends and year-over-year shifts in performance; as well as manual investigations of outliers.

JumpGen Systems, an embedded hardware development company dedicated to purpose-built, high-performance hardware, has an-nounced that it is now a Cavium Partnership to Accelerate Customer End-solutions (PACE) member. Cavium is a provider of highly inte-grated semiconductor processors that enable intelligent networking, communications, storage, video and security applications. The Cavium PACE ecosystem is an extensive network of world class partners.

Targeting the needs of developers in deep packet inspection, net-work security and high frequency trading, in addition to other packet inspection applications, JumpGen Systems developed the O2E-100 high-performance network processor PCI Express packet processor card powered by the Cavium Networks OCTEON II CN68XX multicore processor. OCTEON III designs will be released Q4 2014.

“Uniquely qualified to break ground in new and emerging tech-nology, JumpGen Systems offers a compelling mix of high perfor-mance, fast time-to-market and affordability,” affirms President and CEO, Harry White. “Customers will benefit from our deep hardware development expertise and leading-edge, high-performance designs—packed into high-density implementations with limited power and cooling capabilities.”

JumpGen Joins CaviumPACE Program

The 18th meeting of the Global Standards Collaboration (GSC), a senior-lev-el gathering of the world’s leading information and communication technol-ogies (ICT) standards organizations, took place on 22 - 23 July 2014, hosted by the European Telecommunications Standards Institute (ETSI) in Sophia Antipolis, France. GSC enhances cooperation among standards organizations from different regions of the world to facilitate the exchange of information on standards development, build synergies and reduce duplication of work.

This GSC meeting focused on three topics where standards play a major role in the development of technologies that bring benefits to consumers and businesses: critical communications, machine-to-machine communications and software-defined networking.

The coverage of critical communications included subjects such as com-munications systems for public safety services, large-scale public warning systems, emergency calling systems and communications systems for disaster relief situations. Standards address each of these systems and there is a wealth of experience regarding their use in each region of the globe. It is essential that lessons learned be taken into account, and that teams of disaster relief special-ists do not face communications difficulties from incompatible equipment.

The interconnection of billions of devices and their generation of “big data” was also a topic of discussion at the meeting. The many standardization initia-tives underway and the relationships between them were explored. The success of machine-to-machine communications and the Internet of Things (IoT) will depend on the availability of globally accepted standards and associated economies of scale.

The GSC meeting also discussed the rapidly progressing topics of network functions virtualization (NFV) and software defined networks (SDN), which will provide greater flexibility to network operators, allowing them to provide new services faster and more efficiently. The GSC meeting provided an oppor-tunity to better understand the many distributed and potentially complemen-tary industry initiatives, as well as the synergies between NFV and SDN.

ICT Standards Organizations Collaborate on Emerging Technologies

With the number and variety of electric vehicles (EVs) definitely on the rise, there is a growing need for a standard means of communication between EVs, which need to charge, and the power grid that will be supporting an increasing number of charging stations in public locations. Such a platform would be a substantial building block for the emerging Smart Grid.

There is a need for a way for EVs to hook to the grid and communicate with the power company to identify themselves and provide information for payment for electricity used, and to let utilities manage charging. For example, too many vehicles charging at once in the same area could overload the transformer, so there needs to be a way for the power company to stagger charging and/or notify the driver so that he or she can find another charging station. There is also the future issue of using vehicles connected to the grid as batteries to feed back onto the grid when needed. All of this, of course, requires embedded intelligence.

Now a new alliance is forming involving California’s Pacific Gas and Electric Company, the Electric Power Research Institute (EPRI) and eight auto makers: Ford, BMW, Chrysler, General Motors, Honda, Mercedes-Benz, Mitsubishi and Toyota. So far, Nissan and Tesla have not joined. There are plans to begin testing a basic version of such a platform sometime later this year.

Move toward Communication Platform for Electric Vehicles

Altera Ranks among Top 25 Greenest Companies in U.S.


SMALL FORM FACTOR FORUM

by Colin McCracken

Where would we be without pro-grammable logic? In dire straits, cer-tainly. Imagine bulky, slow and rigid-ly defined systems that need to be overhauled even for minor changes. Many everyday functions are best implemented in field programma-ble gate arrays (FPGAs). These chips are popular across nearly all embedded market segments, from communications to military to med-ical. Once relegated to simple glue logic, data acquisition and decoding functions, FPGAs now handle heavy signal processing algorithms, en-cryption and transforms in hardware rather than software. In some cases, even the need for a discrete DSP has disappeared.

The programmability of these devices, even out in the namesake “field,” adds tremendous value to embedded systems, whether for optimization, fixes, or the imple-mentation of brand new algorithms. On-chip static RAM adds another full dimension of circuitry that can be implemented in a soft or firm way. Flip-flops to full memory func-tionality combine with very flexible routing (interconnects) and logic blocks to produce basic custom state machines and processors, giving high-end microcontrollers a run for their money.

Speaking of processors, many FPGA models come with full 32-bit CPU cores implemented in hard-ened IP blocks, or soft (changeable) gate-level synthesized processor blocks as well. Other I/O and IP blocks are sometimes implement-ed in hardened transistor circuits, improving the overall speed and

shrinking die size without sacrificing much of the flexibility. Certain FP-GAs start to get application-specific, almost like the ASICs and applica-tion-specific standard products that are worth replacing for time and de-velopment cost reasons. FPGAs re-duce system size and weight. Power and per-unit cost may get sacrificed in the process, but often there is no other straightforward way to imple-ment the desired functions.

One design challenge that pops up (hopefully anticipated prior to proto bring-up) is the time required for the programmable device to load its configuration from the external non-volatile storage device (a small 8-pin SPI bus chip, for example). So many bits need to be loaded se-quentially. The device is essentially lifeless prior to that, and will not enumerate properly as a peripheral on a host processor’s bus yet. If the processor doesn’t stop and wait, the I/O won’t be visible and its device driver won’t be loaded. Either some polling or handshaking needs to be designed in, or the entire processor needs to be held in reset until the FPGA loads its brains.

FPGAs moved into the high-speed serial interface era with SERDES PHYs that directly attach to differential pair topologies like PCI Express and others. These ports can be ganged together to form wide high-bandwidth links, such as PCIe x4, and run at Gen 2 speeds as well. Fat pipe applications such as image processing can be handled with modest CPU horsepower and high I/O bandwidth in this manner, using Atom, Celeron and AMD G-series

processors. It’s no longer necessary to choose a high-end embedded processor to get a x4 link; the x1 lanes can be merged using firmware settings.

Having a large number of I/O pins (balls) makes it straightforward to create parallel interfaces to A/D circuits for data acquisition, for example. FPGAs can provide a hub by bringing many low-speed buses into a central location, where data can be crunched and routed back out. Much of the character of the I/O is embodied within the pro-grammable device itself, as device drivers read and write registers.

FPGAs start out assigned to par-ticular functions. Once the design is essentially complete, they offer a chance to reduce component count by swallowing some leftover odds and ends. This saves space and cost, more so since contract manu-facturers charge per component in-sertion. Power management signals, system control signals, handshak-ing lines, counters, timers, delay circuits, decoders, synchronization, FIFO buffers and other assorted glue logic can be absorbed into the same FPGA(s). While often getting upstaged by microprocessors, these sophisticated logic devices shrink and hold together all of the various subsystems, putting the “small” into Small Form Factors (SFFs).

FPGAs Provide Glue Alternatives

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TECHNOLOGY CORE ARM CORES OPTIMIZE PERFORMANCE AND POWER

The choice of ARM cores can initially seem bewildering, but there is a carefully designed selection to help developers optimize their performance and power consumption options matched to the needs of their applications.

By Matt Saunders, Silicon Labs


Interrupt Control

CC1-400 Coherant Interconnect

Cortex-A15MPCore Cortex-A7

MPCoreCPU CPU

SCU + L2Cache

CPUCPU

SCU + L2Cache

FIGURE 1: ARM big.LITTLE processing is a

power-optimization technology where high performance ARM CPUs are

combined with the most efficient ARM CPUs to deliver peak performance

capacity, higher sustained performance, and increased parallel processing

performance, at significantly lower average power. The underlying big.

LITTLE software automatically moves workloads to the appropriate CPU based

on performance needs.


The ARM Cortex family of cores encompasses a very wide range of scalable performance options offering designers a great deal of choice and the opportunity to use the best-fit core for their application without being forced into a one-size-fits-all solution. The Cortex portfolio is split broadly into three main series:

• Cortex-A – application processor cores for performance-intensive systems

• Cortex-R – high-performance cores for real-time applications

• Cortex-M – microcontroller cores for a wide range of embedded applications

Cortex-A for Rich ApplicationsCortex-A processors provide a range of solutions for

devices that make use of a rich operating system such as Linux or Android, and are used in a wide range of appli-cations from low-cost handsets to smartphones, tablet computers, set-top boxes and also enterprise networking equipment. The first range of Cortex-A processors (A5, A7, A8, A9, A12, A15 and A17) is based on the ARMv7-A archi-tecture. Each core shares a common feature set including items such as the NEON media processing engine, Trust-zone for security extensions, and single- and double-pre-cision floating point support along with support for several instruction sets (ARM, Thumb-2, Thumb, Jazelle and DSP). Together this group of processors offers design flexibility by providing the required peak performance points while delivering the desired power efficiency.

While the Cortex-A5 core is the smallest and lowest power member of the Cortex A series, it offers the possi-bility of multicore performance and is compatible with the larger members of the series (A9 and A15). The A5 is a nat-ural choice for designers who have previously worked with the ARM926EJ-S or ARM1176JZ-S processors as it enables higher performance and lower silicon cost.

The Cortex-A7 is similar in power consumption and area to the Cortex-A5, but brings a performance increase in the range of 20 percent as well as full architectural compati-bility with the Cortex-A15 and Cortex-A17. The Cortex-A7 is a good choice for cost-sensitive smartphone and tablet implementations, and it can also be combined with a Cortex-A15 or Cortex-A17 in what ARM refers to as a “big.LITTLE” processing configuration.

The big.LITTLE configuration is essentially a power optimization technology; a high-performance CPU (e.g., Cortex-A17) and an ultra-efficient CPU (e.g., Cortex-A7) are combined to provide higher sustained performance and also to enable significant overall power savings by relying on the more efficient core in cases of low to moderate performance requirements from the application, saving po-tentially 75 percent of CPU energy and as such extending battery life (Figure 1). This configuration offers a significant advantage to the developer as the performance demands of smartphones and tablets are advancing much faster than the capacity of batteries can keep pace. Design meth-odologies such as big.LITTLE, as part of an overall system design strategy, can significantly help reduce this battery technology gap.

Moving to the other end of the Cortex-A scale, let’s con-sider the Cortex-A15 and Cortex-A17 cores. These are both very high-performance processors and again are available in a variety of configurations. The Cortex-A17 is the most efficient “mid-range” processor, and it squarely targets premium smartphones and tablets. The Cortex-A9 has been widely deployed in that market, but the Cortex-A17 offers an increase of more than 60 percent (cycle for cycle) compared to the Cortex-A9, and it achieves this perfor-mance while also improving overall power efficiency. The Cortex-A17 can be configured with up to four cores, each of which contains a fully out-of-order pipeline. As men-tioned previously, the Cortex-A17 can be combined with the Cortex-A7 for an effective big.LITTLE configuration, and it can also be combined with high-end mobile graphics pro-cessors (such as the MALI from ARM), resulting in a very efficient design overall.

The Cortex-A15 is the highest performance member of this series, providing (in a mobile configuration) twice the performance you would get from a Cortex-A9. While being perfectly adequate in applications such as high-end smartphones or tablets, a multicore Cortex-A15 proces-sor running at 2.5 GHz opens up the possibility of using a Cortex-A processor in applications such as low-power servers or wireless infrastructure. The Cortex-A15 is the first processor from ARM to incorporate hardware sup-port for data management and arbitration of virtualized software environments. Applications in those software

Cortex-A15

ARMv7 32b CPUVirtual 40b PA

NEONData Engine

Floating PointUnit

32k I-Cachew/parity

32k D-Cachew/ECC

Core

ARM CoreSight Multicore Debug and Trace

128-bit AMBA ACE Coherent Bus Interface

ACP SCU L2 Cache W/ECC

1 2 3 4

FIGURE 2: The Cortex-A15 is the highest performance ARM processor to date, and is targeted at next-generation smartphones, tablets, large-screen mobile computing and high-end digital home entertainment devices through to wireless base stations and enterprise infrastructure products.



environments are able to simultaneously access the sys-tem capabilities, making it possible to implement devices with virtual environments that are robust and isolated from each other (Figure 2).

The latest additions—the Cortex-A50 series—extend the reach of the Cortex-A series into low-power servers. These processors are built on the ARMv8 architecture and bring with them support for AArch64—an energy-efficient 64-bit execution state that can operate alongside the existing 32-bit execution state. An obvious reason for the move to 64-bit is the support of more than 4 Gbytes of physical memory, which is already achieved on Cortex-A15 and Cortex-A7. In this case, the move to 64-bit is really about providing better support for server applications where a growing number of operating system and application im-plementations are using 64-bit, and the Cortex-A50 series delivers a power-optimized solution for this scenario. The same is largely true for the desktop market, and support for 64-bit will enable the CortexA50 series to be more broadly adopted into this segment and will provide some level of future-proofing for the eventual migration of 64-bit operat-ing systems into mobile applications.

Cortex-R for Real TimeMoving on from Cortex-A, the Cortex-R series is the

smallest ARM processor offering in terms of derivatives and possibly the least well known. The Cortex-R proces-sors target high-performance real-time applications such as hard disk controllers (or solid state drive controllers), net-working equipment and printers in the enterprise segment,

consumer devices such as Blu-ray players and media players, and also automotive applications such as airbags, braking systems and engine management.

The Cortex-R series is similar in some respects to a high-end microcontroller (MCU), but it targets larger systems than you would typically implement using a standard MCU. The Cortex-R4, for example, is well suited for automotive applications. It can be clocked up to 600 MHz (delivering 2.45 DMIPS/MHz), has an 8-stage pipeline with dual-issue, pre-fetch and branch prediction, and a low latency interrupt system that can interrupt multi-cycle operations to quickly serve the incoming interrupt. It can also be implemented in a dual-core configuration with the second Cortex-R4 being in a redundant lock-step configuration with logic for fault detection, making it a good choice for safety-critical systems.

Networking and data storage applications are well served by the Cortex-R5, which extends the feature set offered by the Cortex-R4 to offer increased efficiency and reliability and enhance error management in dependable real-time systems. One such system-level feature is the low latency peripheral port (LLPP) to enable fast peripheral reads and writes instead of having to perform a read-mod-ify-write on the entire port. The Cortex-R5 can also be implemented as a “lock-step” dual-core system with the processors running independently, each executing its own programs with its own bus interfaces and interrupts. This dual-core implementation makes it possible to build very powerful, flexible systems with real-time responses.

The Cortex-R7 significantly extends the performance reach of the series, with clock speeds in excess of 1 GHz and a performance of 3.77 DMIPS/MHz (Figure 4). The 11-stage pipeline on the Cortex-R7 now adds out-of-order execution along with improved branch prediction. There are several options for multicore implementations as well: lock-step, symmetric multiprocessing and asymmetric multipro-cessing. The Cortex-R7 also has a fully integrated generic interrupt controller (GIC) supporting complex priority-based interrupt handling. It is worth noting, however, that despite its high-performance levels, the Cortex-R7 is not suitable for running rich operating systems (such as Linux and An-droid), which remains the domain of the Cortex-A series.

Cortex-M for EmbeddedFinally we come to the Cortex-M series, designed specif-

ically to target the already very crowded MCU market. The Cortex-M series is built on the ARMv7-M architecture (used for Cortex-M3 and Cortex-M4), and the smaller Cortex-M0+ is built on the ARMv6-M architecture. The first Cortex-M processor was released in 2004, and it quickly gained pop-ularity when a few mainstream MCU vendors picked up the core and started producing MCU devices.

It is safe to say that the Cortex-M has become for the 32-bit world what the 8051 is for the 8-bit world—an indus-try-standard core supplied by many vendors, each of which dip the core in their own special sauce to provide differenti-ation in the market. The Cortex-M series can be implement-ed as a soft core in an FPGA, for example, but it is much more common to find them implemented as an MCU with integrated memories, clocks and peripherals. Some are op-

Cortex-A53

ARMv8 32b/64b CPUVirtual 40b PA

NEONSIMD engine with

crypto ext.

Floating PointUnit

8-64k i-Cachew/parity

8-64k D-Cachew/Ecc

Core


128-bit AMBA ACE Coherent Bus Interface

ACP SCU L2 Cache W/ECC (128kb ~ 2MB)

1 2 3 4

FIGURE 3: The ARM Cortex-A53 processor is the lowest power 64-bit processor available and has been designed to provide the optimum blend of high levels of performance with high levels energy-efficiency.


Cortex-R7

ARMv7-R32b CPU

Core


Generic Interrupt Controller

ACP Snoop Control Unit

MRP

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FIGURE 4: The ARM Cortex-R7 processor brings new levels of extreme performance to the Cortex-R series of processors. The R7 offers more than 50 percent performance uplift through in-creased pipeline efficiency with enhanced branch prediction, advanced superscalar and out-of-order execution.

timized for energy efficiency, some for high performance, and some are tailored to a specific market segment such as smart metering.

The Cortex-M3 and Cortex-M4 are very similar cores. Each offers a performance of 1.25 DMIPS/MHz with a 3-stage pipeline, multiple 32-bit buses, clock speeds up to 200 MHz and very efficient debug options. The significant difference is the Cortex-M4 core’s capability for DSP. The Cortex-M3 and Cortex-M4 share the same architecture and instruction set (Thumb-2). However, the Cortex-M4 adds a range of saturating and SIMD instructions specifically optimized to handle DSP algorithms. For example, consider the case of a 512-point FFT running every 0.5 second on equivalent off-the-shelf Cortex-M3 and Cortex-M4 MCUs. For comparison, the Cortex-M3 would consume around three times the power that a Cortex-M4 would need for the same job. There is also the option to get a single precision floating point unit (FPU) on a Cortex-M4. If your application requires floating point math, you will get this done consid-erably faster on a Cortex-M4 than you will on a Cortex-M3. That said, for an application that is not using the DSP or FPU capabilities of the Cortex-M4, you will see the same level of performance and power consumption on a Cor-tex-M3. In other words, if you need DSP functionality, go with a Cortex-M4. Otherwise, the Cortex-M3 will do the job.

For applications that are particularly cost sensitive or are migrating from 8-bit to 32-bit, the smallest member of the



Cortex-M series might be the best choice. The Cortex-M0+ performance sits a little below that of the Cortex-M3 and Cortex-M4 at 0.95 DMIPS/MHz, but it is still compatible with its bigger brothers. The Cortex-M0+ uses a subset of the Thumb-2 instruction set, and those instructions are pre-dominantly 16-bit operands (although all data operations are 32-bit), which lend themselves nicely to the 2-stage pipeline that the Cortex-M0+ offers. This brings some over-all power saving to the system through reduced branch shadow, and the pipeline will in most cases hold the next four instructions. The Cortex-M0+ also has a dedicated bus for single-cycle GPIO, meaning you can implement certain interfaces with bit-bashed GPIO like you would on an 8-bit MCU but with the performance of a 32-bit core to process the data (Figure 5).

Another key difference on the Cortex-M0+ is the addition of the micro trace buffer (MTB). This periph-eral allows you to dedicate some of the on-chip RAM to store program branches while in debug. These branches can then be passed back up to the integrated

development environment (IDE), and the program flow can be reconstructed. This capability provides a rudimentary form of instruction trace and compensates for not having the extended trace macrocell (ETM) found on the Cor-tex-M3 and Cortex-M4. The level of debug information you can extract from a Cortex-M0+ is significantly higher than what you can get from an 8-bit MCU, meaning those hard to solve bugs just got easier to fix.

So the Cortex processor family offers many options regardless of the performance level you need for your appli-cation. With a little bit of thought and investigation, you will be able to find the right processor that suits your application needs, whether it’s for a high-end tablet or an ultra-low-cost wireless sensor node for the Internet of Things.

Silicon LabsAustin, TX.(512) 416-8500www.silabs.com

Cortex-M0+

CPU

Nested VectoredInterupt Controller

Wake Up InterruptController Interface

MemoryProtection

Unit

AHB-liteInterface

Low LatencyI/O Interface

DataWatchpoint

Breakpoint

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Port

FIGURE 5: The ARM Cortex-M0+ processor is the most energy efficient ARM processor available, and is the only ARM processor to employ a two-stage pipeline. The M0+ builds on the Cortex-M0 processor while extending the choice of design options It is intended for demanding entry-level microcontrol-lers and deeply embedded applications that require an area- and power-optimized processor.

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MULS r0,r1,r0 MOV R1,&MulOp1MOV R2,&MulOp2MOV SumLo,R3MOV SumLo,R4

(Memory mappedmultiply unit)

8-bit example (8051) 16-bit example ARM Cortex-MMOV A, XL; 2 bytesMOV B, YL; 3 bytesMUL AB, 1 byteMOV R0, A; 1 byteMOV R1, B; 3 bytesMOV A, XL; 2 bytesMOV B, YH; 3 bytesMUL AB, 1 byteADD A, R1; 1 byteMOV R1, A; 1 byteMOV A, ; 2 bytesADDC A, #0; 2 bytesMOV R2, A; 1 byteMOV A, XH; 2 bytesMOV B, YL; 3 bytes

MUL AB, 1 byteADD A, R1; 1 byteMOV R1, A; 1 byteMOV A, B; 2 bytesADDC A, R2; 1 byteMOV R2, A; 1 byteMOV A, XM; 2 bytesMOV B, YM; 3 bytesMUL AB, 1 byteADD A, R2; 1 byteMOV R2, A; 1 byteMOV A, B; 2 bytesADDC A, #0; 2 bytesMOV R3, A; 1 byte

Time: 1 clock cycleCode size: 2 bytes

Time: 8 clock cycleCode size: 8 bytes

Time: 48 clock cycles*Code size: 8 bytes

There are myriad CPU choices available to embedded devel-opers and each choice has its own idiosyncrasies, architectural benefits and array of power-saving techniques. To provide a useful context for the wide range of embedded CPU options, it’s helpful to focus on one widely used architecture: the ARM Cortex-M series. This architectural choice provides several CPU variants to explore and many different MCU devices from silicon vendors. The diversi-ty of options within the Cortex-M series is important, as minimizing the CPU power consumption is achieved not just through the CPU architecture itself but also by the supporting elements around it, such as interrupt controllers, memory interfaces, memory accelera-tors, low power modes and intelligent peripherals.

The ARM Cortex-M architecture has a wide variety of opportunities to save power and not all of them are obvious. By carefully considering and implementing combinations of these techniques, developers can realize substantial advantages.



Figure 1:Cycle Count Comparison for a 16-bit Multiply


Everything You Need to Know about Thumb-2

Let’s begin our look at power-saving techniques in a place that might not be an obvious starting point—the instruction set. Cortex-M CPUs all use the Thumb-2 instruction set, which blends the 32-bit ARM instruction set with the 16-bit Thumb instruction set and provides a flexible solution for both raw performance and overall code size. A typical Thumb-2 application on Cortex-M will be in the range of 25 percent smaller and 90 percent as efficient (when optimized for time) compared to code written entirely in ARM instructions.

Thumb-2 includes a number of powerful instructions that reduce the cycle count for basic operations. Reducing the cy-cle count means you can do the job at hand with a significant reduction in CPU power consumption. Consider, for example, a 16-bit multiply (Figure 1). Performing this operation on an 8-bit 8051-based MCU would take 48 clock cycles and 48 bytes. Using a 16-bit core such as C166, this operation would be in the range of 8 clock cycles and 8 bytes. In contrast, on a

Cortex-M3 core using Thumb-2, this is done in a single cycle and uses only two bytes of flash. The Cortex-M3 saves power by using fewer clock cycles to do the same job and by using much less flash memory and therefore far fewer accesses to flash to achieve the end result (in addition to potentially fitting the application into a smaller flash and reducing overall sys-tem power). We could spend a lot more time examining the Thumb-2 instruction set, but this example should give a sense of its potential for power saving.

Power-Saving Interrupt Controller Techniques

The interrupt controller (nested vectored interrupt control-ler or NVIC) in the Cortex-M architecture also plays a role in reducing CPU consumption. The Cortex-M3 NVIC takes just 12 cycles to get from the interrupt request to executing the interrupt code, compared to the “up to” 42 cycles that it took previously on the ARM7-TDMI, clearly bringing a benefit in efficiency and reducing wasted time for the CPU. In addition to the fast entry to the interrupt routine, the NVIC also man-ages moving from one interrupt routine to another much more efficiently.

On the ARM7-TDMI implementations, it was necessary to spend cycles moving from the interrupt routine back to the

Figure 2:Interrupt Response on ARM7 and Cortex-M3

Interrupt Response-Tail Chaining

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PUSH ISR 1 ISR 2POP POPPUSH

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• 26 cycles from IRQ1 to ISR1 entered • Up to 42 cycles if LSM• 42 cycles from ISR1 exit to ISR2 entry• 16 cycles to return from ISR2

Cortex-M3

• 12 cycles from IRQ1 to ISR1 entered • 12 cycles if LSM• 5 cycles from ISR1 exit to ISR2 entry• 12 cycles to return from ISR2

26 26 26

65% Saving in clock cycles



main application, and then back into the next interrupt routine, burning up to 42 cycles between interrupt service routines on just “push-and-pop” functions. The Cortex-M NVIC enables a much more efficient method for accomplishing this task called “tail-chaining.” This method uses a simple 6-cycle process for getting the necessary information to run the next service routine. With tail-chaining, there is no need to do a full push-and-pop cycle, resulting in an overall savings of 65 percent in clock cycles to manage interrupts (Figure 2).

Power-Saving Memory ConsiderationsMemory interfaces and memory accelerators can make a

significant impact on how much power the CPU consumes.

Branches and jumps in the code have the effect of flushing the pipeline feeding instructions to the CPU, and in that case the CPU will stall for a number of cycles while the pipeline is refilled. On a Cortex-M3 or Cortex-M4, the CPU is equipped with a 3-stage pipeline. Flushing this pipeline will cause the CPU to stall for three cycles—even longer if there are wait-states on the flash—while it is refilled. These stalls waste powerbecause effectively nothing useful is happening. To help mitigate the delay, the Cortex-M3 and M4 cores include a function called Speculative Fetch, which upon fetching a branch in the pipeline will also fetch the likely branch target. If that branch is taken, then the Speculative Fetch will have reduced the stall by one cycle. While this feature is useful, it is clearly not enough, and many vendors of Cortex-M devic-es add their own IP to enhance this capability.

Consider, for example, different approaches to instruction caches used in popular ARM Cortex-M class MCUs. An MCU with a simple instruction cache, such as an EFM32 de-vice from Silicon Labs, may store 128 x 32 (512 bytes) of the most recently executed instructions with logic to determine if the requested address is in the cache or not. The EFM32 reference manuals suggest a typical application will get a >70 percent hit rate on this cache, meaning far fewer flash accesses and faster execution of the code, and an overall reduction in power consumption.

In contrast, an ARM-based MCU using a branch cache with 64 x 128-bit buffers can store the first few instruc-tions—a minimum of four, maximum of eight for each branch depending on the mix of 16- or 32-bit instructions. A branch cache implementation can therefore fill the pipeline in a single cycle for any branch or jump that hits the cache, eliminating any stalls or wasted cycles for the CPU. Both of these cache techniques offer considerable improvements in performance and reductions in CPU consumption compared to the same CPU without these cache features. Both cache

Cortex-MO/MO+/M1TST

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Figure 3:The Cortex-M0+ Instruction Set

Figure 4:Alternate Clock Flash Access on Cortex-M0+

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types also minimize accesses to flash, enabling an overall reduction in MCU power consumption as well.

A Closer Look at the M0+ CoreFor power-sensitive applications where every nano-watt

counts, the Cortex-M0+ core is a good option. The M0+ is based on a von-Neumann architecture (whereas the Cortex-M3 and Cortex-M4 cores are Harvard architecture), meaning it has a smaller gate count for lower overall power

consumption figures and only a minimal hit on performance (0.93 DMIPS/MHz vs. 1.25 DMIPS/MHz for its bigger ARM siblings). It also uses a smaller subset of the Thumb-2 instruction set (Figure 3). Nearly all of the instructions have 16-bit opcodes (50 x 16-bit opcodes and 6 x 32-bit opcodes; data operations are all 32-bit), enabling some interesting options for reducing CPU power consumption.

The first of these power-saving options is to reduce the number of flash accesses. Having a predominantly 16-bit instruction set means you can access the flash on alternate cycles (Figure 4) and fetch two instructions for the pipeline with each access. This assumes that you have two instruc-

Figure 5:Pipeline and Branch Shadow

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advertisement_arm-overview_7,375x3,375mm.indd 1 03.06.2014 12:28:45



tions aligned in a 32-bit word in memory. In the case where the instructions are not aligned, then the Cortex-M0+ will disable half of the bus to conserve every last bit of energy.

Additionally, the Cortex-M0+ core can save power as a byproduct of the reduction to a 2-stage pipeline. In pipelined processors, subsequent instructions are fetched while the CPU executes the current instructions. If the program branch-es and does not use the subsequently fetched instructions, the energy used to fetch them (branch shadow) is effectively wasted. In a 2-stage pipeline this branch shadow is reduced so energy (admittedly a small amount) can be saved.

It also means there is one cycle less to refill the pipeline in the event it is flushed (Figure 5).

Another area where the Cortex-M0+ core offers some power savings is through its high-speed GPIO ports. On the Cortex-M3 and Cortex-M4 cores, the process of toggling a bit or GPIO port is to “read-modify-write” a 32-bit register. While the Cortex-M0+ can use this method too, it has a ded-icated 32-bit-wide I/O port that gives single-cycle access to the GPIO, making it possible to toggle the bit/pin efficiently. Note: this is an optional feature on the Cortex-M0+, so not all vendors will implement this useful GPIO feature.

Putting the CPU to SleepOne of the most effective ways to minimize CPU power

consumption is to switch off the CPU itself. There are a number of different sleep modes in the Cortex-M architec-ture, each offering a tradeoff between power consumption in the chosen sleep mode and startup time to executing code again (Figure 6). It is also possible to have the CPU enter a sleep mode automatically upon completing an interrupt service routine without the need for a line or two of code to do the job. This approach saves CPU cycles for a task that is likely to be very common in an ultra-low-power application.

In deep sleep mode, it’s also possible to use the wakeup interrupt controller (WIC) to offload the NVIO. When using the WIC, there is no need for a clock to the NVIC in low-pow-

er modes to wake up the CPU using external interrupts.Autonomous on-chip peripherals also can be a real ben-

efit for power reduction. Most MCU vendors have their own architectures for enabling autonomous interaction between peripherals, such as the Peripheral Reflex System (PRS) used in Silicon Labs’ EFM32 MCU devices. Autonomous peripheral implementations enable fairly complex chains of peripheral actions (triggers rather than data transfers) to take place while the CPU remains asleep. For example, using the PRS capability of an EFM32 MCU, the application could be configured such that in a low-power mode with the CPU asleep, the onboard comparator detects a voltage that cross-es its threshold, triggering a timer to start counting down. When that timer hits zero, it then triggers the DAC to start its output—all while the CPU remains asleep.

With such complex interactions occurring autonomous-ly, it is easy to get a lot done without CPU intervention. Furthermore, peripherals that have some built-in intelligence such as sensor interfaces or pulse counters can be config-ured to wake the CPU on an interrupt with a pre-configured condition, such as having counted 10 pulses. In this exam-ple, when the CPU wakes to that specific interrupt, it knows exactly what needs to be done and doesn’t need to check counters or registers to see what information has come in, thereby saving some cycles and getting on with other important tasks.

These are some of the easier-to-access methods of reducing CPU consumption on the wide choice of Cor-tex-M devices. There are, of course, other considerations impacting power consumption, such as the process node used to manufacture the device or the memory technology used to store the application code. Process and memory technologies can have significant impacts on both run-time power consumption and the leakage in low-power modes, and thus should be factored into an embedded developer’s overall power-saving strategy.

Silicon LabsAustin, TX.(512) 416-8500www.silabs.com

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Figure 6:Cortex-M Native Low-Power Modes

Untitled-5 1 9/26/13 9:29 AM


TECHNOLOGY CONNECTED LOW POWER BLUETOOTH CONNECTS DEVICES

External MCU

BLE Network ProcessorBlueNRG

Application

BLE Pro�les

BLE Protocol stack

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Application ControllerInterface

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FIGURE 1: Bluetooth Smart IC

Specification: Layered Architecture of

BlueNRG – Bluetooth Smart IC from

STMicroelectronics.

Small devices must minimize power yet communicate. Bluetooth Smart enables the smallest devices to communicate with larger, Classic Bluetooth devices, which can form bridges to the Web, making possible a huge sphere of connected applications, devices and users.

Bluetooth Smart – A Revolution for Low Power Connectivity

by Vishal Goyal, STMicroelectronics

Bluetooth Smart, or Bluetooth Low Energy (BLE), is a wireless personal area network that enables low-power devices and sensors to connect to smartphones and tab-lets. It uses radio transmission at the 2.4 GHz band. BLE is promoted by Bluetooth SIG and aimed at innovative appli-cations such as healthcare, fitness, security, wearable and home automation. Innovators can build new products that work seamlessly with the smartphone and benefit from the rich user interface and connectivity it provides, while supporting compact hardware accessories with incredible battery life.

Classic Bluetooth is a wireless technology standard for exchanging data or voice over short distance. It is wide-ly used for data, audio and video transmission between smartphones, laptop, PC peripherals, earpiece, etc. But Classic Bluetooth consumes high current, making it unsuit-able for battery powered applications, which are expected to run for a long period without the need of battery replace-ment or charging.

Bluetooth Low Energy (BLE) technology operates in the same spectrum as Classic Bluetooth technology, but uses a different set of channels. Instead of Bluetooth tech-nology’s 79 1 MHz wide channels, Bluetooth Low Energy technology has 40 2 MHz wide channels. Bluetooth Low Energy technology uses frequency hopping to counteract narrowband interference problems. BLE enables ultra-low power connectivity and basic data transfer for applications previously limited by the power consumption. A com-parison of Classic Bluetooth and Bluetooth Low Energy technologies is given in Table 1.

In addition, there are two flavors of Bluetooth Low Energy. Bluetooth Smart, another name for Bluetooth Low Energy, has ultra-low power consumption as it is a pure low energy implementation. Bluetooth Smart devices can run for months to years on a standard coin cell battery. These


TABLE 1: Comparison of Bluetooth technologies.

Technical Specification Classic Bluetooth technology Bluetooth low energy technology

Radio Frequency 2.4 Ghz 2.4 Ghz

Distance/Range 30 meters 50 meters

Over the air data rate 1–3 Mbit/s 1 Mbit/s

Application throughput 0.7–2.1 Mbit/s 0.2 Mbit/s

Active slaves 7-16,777,184 Unlimited

Security 64/128-bit and application layer user defined

128-bit AES and application layer user defined

Robustness Adaptive fast frequency hopping, FEC, fast ACK

Adaptive fast frequency hopping

Latency (from a non-connected state) Typically 100 ms 6 ms

Total time to send data 100 ms <6 ms

Government Regulation Worldwide Worldwide

Certification Body Bluetooth SIG Bluetooth SIG

Voice capable Yes Yes, with some limitation

Network topology Scatternet

Star-bus

Power consumption 1 as the reference 0.01 to 0.5 (depending on use case)

Peak current consumption <30 mA <15 mA

Service discovery Yes Yes

Profile concept Yes Yes

Primary use casesMobile phones, gaming, headsets, stereo audio

streaming, automotive, PCs etc.

Mobile phones, gaming, PCs, watches, sports and fitness,

healthcare, security & proximity, automotive, home electronics,

automation, Industrial, etc.

are accessory devices that send information to another Bluetooth Smart device or to Bluetooth Smart Ready-en-abled smartphones, tablets or laptops. Bluetooth Smart Ready is Classic Bluetooth + Bluetooth Low Energy on a single chip. These are hub devices that can receive data from both Classic Bluetooth and Bluetooth Smart devices and convert them into useful information. Table 2 shows the interoperability of Bluetooth devices

Bluetooth ICsFor use in its target application, a Bluetooth Smart IC

should have certain key attributes, especially low current consumption. Most of the applications of Bluetooth Smart run on battery, so current consumption directly affects the battery life and is a crucial feature in 90% of target applications. In a competitive BLE IC, power modes such as ultra-low-power sleep modes and very short transition times between operating modes allow very low average current consumption, resulting in longer battery life. ST’s BlueNRG is a very low-power Bluetooth Low Energy (BLE) single-mode network processor, compliant with Bluetooth


TECHNOLOGY CONNECTED LOW POWER BLUETOOTH CONNECTS DEVICES

specification v4.0. The BlueNRG allows applications to meet the tight advisable peak current requirements im-posed with the use of standard coin cell batteries.

If the Bluetooth SIG changes the stack, the compliancy is mandatory, so the Bluetooth Smart device should have the ability to update the stack. The entire Bluetooth Low Energy stack of ST’s BlueNRG IC runs on the embedded Cortex M0 core. The non-volatile Flash memory allows in-field stack upgrading.

To enable RF communication a BLE IC also needs Balun matching and a filter network. Often it may act as a bottle-neck because it is required to be perfect and to not con-sume critical PCB space. ST has introduced a silicon-based reliable Balun IC that is an integrated solution, thus saving PCB size, cost and making it easier to integrate.

System PartitioningThere are mainly two ways of partitioning a BLE system:

System on Chip (SoC) and network processor. An SoC integrates BLE transceiver and microcontroller. An SoC not only contains the BLE stack but also profiles and applica-tions. The advantage of the SoC is better integration and suitability to relatively simple systems. But an SoC does not offer flexibility for the user to select the right microcon-troller according to peripherals of a system, or to handle complex tasks such as managing multiple sensors.

A network processor uses an external microcontroller for running profiles and applications. The network processor may or may not contain the stack. If the stack is not pres-ent within the network processor, then it is required to be present inside an attached microcontroller. ST’s BlueNRG is a network processor with built-in stack and easy SPI interface with a microcontroller. This system partitioning offers flexibility to select the right microcontroller accord-ing to peripherals and complexity of the system. It allows better management of the system’s power requirements (Figure 1).

Applications for Bluetooth SmartAs devices get smaller and take lower power, the possi-

ble applications for Bluetooth Smart are rapidly proliferat-ing. Wearable and mobile devices for fitness are becoming increasingly popular. Connected Smart watches, activity monitors and pedometers enable users to monitor their fit-ness activity through their smartphones. It allows capturing biometrical data such as heart rate, speed/pace, distance, cadence, total steps and burned calories. BLE send this data to the app running on a smartphone or tablet, and allows it to be shared with social communities. It allows optimizing sports performance, goal monitoring, weight control, direction data and location sharing.

The same is true for healthcare and wellness. Heart rate monitors, glucose monitors and pulse oximeters can now be connected to smartphones through BLE. BLE not only allows these gadgets to connect to smartphones wire-lessly, but also to get connected to the Internet through smartphones. It allows tracking your activity and recording biometrical data all day long without necessarily needing 24-hour care. It will enable information to be stored on the Cloud and shared with doctors and family members. BLE has also enabled these gadgets to be worn on strategic locations such as on shoes or on the wrist. BLE supports many healthcare-related profiles such as glucose meters, heart rate monitoring, thermometers and blood pressure meters.

For the smart home, BLE offers a painless path to control lights, home appliances, door locks, garage doors, the secu-rity system, air conditioning and heater. These devices, when fitted with Bluetooth Smart, can communicate with Blue-tooth Smart-ready phones or tablets. Innovative apps can be developed to control the various elements of smartphones according to the person’s own requirements. BLE also pro-vides secure wireless communication that ensures accurate metering and control of electricity consumption at home.

BLE supports assisted living, which allows elderly people

If a device contains a Bluetooth version Below Device Examples The device is compatible with

Bluetooth devices below

Classical Bluetooth Smartphone, Tablet, TV, DVD, Laptop etc. Classical Bluetooth

Bluetooth Smart Ready Smartphone, Tablet, TV, DVD, Laptop etc. Classical Bluetooth

Bluetooth SmartWatch, Tags, Toys, Remote

controller, thermometer, portable healthcare etc.

Bluetooth Smart Ready

TABLE 2: Interoperability of Bluetooth devices.


to be remotely monitored by their children. A pillbox with an accelerometer and BLE can alert the user if the pills are not taken on time or the pill box is not opened. Using an accelerometer and BLE on home appliances, toilet seats and doors, the activity level of elderly people can be recorded on a smartphone. Their children can then be assured of the activity level of their parents and can reach help in case of an emergency without any manual intervention.

Today, infrared is the most popular media of wireless communication in a remote control. Infrared suffers limitations from its line of sight requirement and one way communication. BLE-compatible remotes do not need to be in line of sight and can also be used to make gesture-based remotes by integrating MEMS sensors. BLE-compatible remotes can even receive input from the main media such as turning on a remote LED light or finding the lost remote in a room. BLE has also made it possible to use Bluetooth Smart Ready smartphones as remote controllers. One just needs to add BLE in the main media and avoid the separate remote controller.

Industrial equipment can now send key performance and safety information without the need for long cables directly to a Bluetooth Smart Ready phone, tablet or computer. It allows for higher flexibility for machinery installation and easy inte-gration into the network.

A small BLE proximity and anti-theft accessory, when tagged to pets and kids, can alert the smartphone if they sneak out of reach or are abducted by aliens. BLE-enabled car keys can be found easily with the help of a connected smart-phone. Wallets and luggage tagged with BLE can alert the smartphone if someone trys to steal them. BLE supports proximity and “find me” profiles, which can seam-lessly enable these applications.

BLE allows displaying many features such as bike mileage, trip, key parameters, etc. on a smartphone. ST’s BlueNRG also has integrated key identification, so 1 million unique codes can be implemented without an encoder/decoder circuit. This feature makes it possible to pair a bike or car with the right remote or smartphone. Thus BLE can also be used to implement “find me” lamps, which can help search for a bike in a parking lot.

Bluetooth Smart CertificationA Bluetooth Smart product needs to be certified by the Bluetooth SIG before

it can be listed as a certified Bluetooth Smart product. A successful certification needs a qualified design listing, RF-PHY testing, qualification of stack and Blue-tooth GATT-based profiles. ST offers a certified stack in both master and slave role, so additional stack qualification is not needed.

BLE is a bridge between hub devices such as smartphones to peripherals and accessories. It has revolutionized the innovation of IoT and wearable devices, and reduced human intervention in decision making. BLE is now supported by major new smartphones along with key operating systems, such as iOS, Windows and Android. And we are already seeing that BLE is becoming a standard feature. This presence of millions of Bluetooth Smart Ready smartphones, laptops and tablets has provided a platform for Bluetooth Smart accessories. BLE offers ultra-low peak power, the ability to run for years on coin cell battery and low cost, so it has become a preferred choice for connectivity. At STMicroelectronics, we are invest-ing heavily in this technology and offer several sensors and analog products to complete the hardware offering.

STMicroelectronicsSanta Clara, CA.(408) 919-8400.www.st.com

ADLINK TECHNOLOGY, INCTel: 1-800-966-5200 [email protected]

with latest CPU technology

Supports SEMA functions Smart Embedded Management Agent


TECHNOLOGY IN SYSTEMS MODULAR SYSTEMS FOR INDUSTRIAL AUTOMATION

Software Optimization Can Reduce MCU “Active-Phase” Power ConsumptionA system-level design approach is essential to achieving optimal power consumption, but significant gains can be made by minimizing active-state power by reducing software execution time and the time spent driving external I/O and peripherals.

by Dave Hughes, HCC Embedded

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FIGURE 1: Task switching in a cooperative scheduler can lead to a highly efficient implementation since the number of context switches required is minimized.


Only a system-level view of a low-power application is going to achieve anywhere near the optimal solution for any product. This applies to both the active and inactive phases. When the active power mode is significant, then there is much to analyze, and the optimal solution is likely to be achieved by combining a detailed knowledge of the application with deep experience working with whatever communication methods are used.

Clearly we need to begin by understanding the func-tional specification of the product together with the power design goals and avoid unnecessary feature creep. It is unlikely that a generalized solution is going to be the most power-efficient for any specific set of requirements, although there are some obvious measures that can be taken as a first step; for example, using a compiler that optimizes for minimal power consumption and running it on the highest level of optimization.

There are two main ways to achieve low power con-sumption on any embedded application: minimizing power in the inactive/passive state and minimizing power in the active state. This article focuses on the role of software and the issue of minimizing the power consumption of a sys-tem in the active mode. The net benefit to be gained from working on these areas depends on the ratio of active and passive power consumption:

(average_active_power x active_time)

(average_passive_power x passive_time)

As one area is improved, the relative contribution of the other grows.

The important principle is that a system-level design approach to any application is essential to achieving opti-mal power consumption. That means carefully analyzing the requirements of the product so that the activities that take the most power can be analyzed and optimized, then constructing a hardware and software design that fulfills those requirements, eliminating unnecessary or redundant functionality. Most deeply embedded systems have one or more input sources and one or more outputs. Some sys-tems are more complex so naturally the options are more complicated, and this has an impact on the possibility for improvement. Active-phase design goals include reducing the execution time of software required to achieve any specific task as well as reducing the time spent driving external I/O and external peripherals.

System Task SchedulingThe simplest possible solution in any embedded system

is that every task when required is initiated by interrupts. All code is then event-driven: it should only do what is required and then return to a low-power mode. However, this is only likely to be practical for the simplest applications. Where data communication is required, it becomes impractical and the code overhead can build rapidly. The solution is to use a scheduler or similar operating system to handle task and data interactions, but each of those has a different impact on power consumption.

For example, use a super loop only if the application is very simple and power requirements are not critical. It pro-vides limited software reuse with no roadmap for future de-velopment. This method is less than ideal since by definition some unnecessary processing is required to decide what to execute next. It is also generally difficult, but by no means impossible, to use third-party components with super loops.

Another option is to use a pre-emptive RTOS. The devel-oper immediately gains a benefit because most systems can be event-driven, i.e., only executing code in response to a specific event. This makes for a very flexible system, though it is not always optimal when it comes to low-power design. RTOSs tend to be designed for high performance rather than low power. In particular, the response time of the highest priority task is designed to be minimized. This means that for RTOS-based designs, often the most import-ant feature is the context-switch time and the interrupt laten-cy. When looking at low-power systems, interrupt latency is unlikely to be critical in the context of modern processors, and context-switch time is unlikely to be critical given that the system is going to be mostly idle.

A co-operative scheduler (Figure 1) can be a good option since tasks will only relinquish control when they have com-pleted their work, allowing the next highest priority ready task to take over. This minimizes the number of context switches required.

Regardless of the scheduling method chosen, careful consideration should be given to interrupt handling. After an interrupt has occurred, the amount of work required to service that interrupt is not particularly critical to power con-sumption. The most important objective is to minimize the number of interrupts in the system by making best use of FIFOs and timeouts, and choosing a scheduling mechanism that can support low-power modes available on the target device (Figure 2).

Flash StorageStoring data in flash can be very complex, but it poten-

tially provides the source of the largest savings. There is a

T4

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ready

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wait(delay)

FIGURE 2: Choosing a scheduling mechanism that can support low-power optimization can have a significant impact on the system power consumption, especially if it makes use of low-power modes available on the target device.



vast range of storage options including NOR flash, NAND flash, SD cards and eMMC, to name a few of the more popular options used in embedded systems. Each has its own strengths and weaknesses, which are far too varied to examine here but some general principles apply.

All these devices have complex internal erase, read and write architectures that are most efficiently handled by mapping your use to the geometry of the flash device. Most also require wear-leveling but this can also depend on the use case; to wear-level a lightly used flash device would be wasteful of both time and power.

It is worth examining the benefits of using a file system. A file system has two primary roles: to make data accessi-ble by an external system (e.g., a FAT file system running on a PC), and to provide an easy-to-use API for the applica-tion to hide the underlying flash complexity. Naturally this implies some overhead that may not be appropriate for a system that needs optimized battery life.

HCC’s Smart-Meter File System (SMFS) seen in Figure 3 is a good example of a power-optimized approach to flash data storage. Instead of taking a layered “file system plus driver” approach, it maps databases directly to the flash device. This makes the application simpler and the required amount of flash management is minimized. These are ap-propriate attributes for a low-power solution since as little time as possible is expended processing complex file sys-tem operations, and the number of read/write/erase cycles required is reduced dramatically. This reduction in required

flash accesses alone, compared to using a full-featured file system, can result in significant system power savings.

It is also the case that some flash devices have low-pow-er modes that must be handled carefully to ensure the con-tents of their RAM buffers will not be lost. File systems that handle these types of flash devices most effectively should ensure that hooks are built in to indicate when the mode is entered and exited.

Aggregating data is very important when attempting to minimize power consumption. Practically all flash devic-es operate most efficiently when the size of data to be stored is a multiple of the base storage unit of the device. In some cases the difference in work required is large but this introduces other difficulties. If data is aggregated and the system resets, then data can be lost. It may be useful to consider a hybrid solution where some small static storage area (e.g., a small FRAM) is used for intermediate storage until data is ready for committing to the flash device.

There are also situations where reducing the amount of RAM may be counterproductive if you are trying to reduce power consumption. Being able to maintain cache and file system metadata in RAM will greatly reduce the need to access flash to retrieve information.

NetworkingTime spent actively driving an external network interface

is likely to use a significant amount of power. Returning from this state to a low-power mode as quickly as possible is essential. If possible, the designer should also minimize the number of data transfers required to ensure minimal power consumption.

Sockets interfaces used by many network stacks are inherently inefficient. Practically speaking, they enforce a copy of the data and additional handling that is not ben-eficial to a low-power system. Creating a system design

USB Device Interface TCP/IP Interface

FTP/TFTPEmbedded

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MST MTP

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Smart-meterFile SystemSAfeFlash

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PC

FIGURE 2: Smart Meter File System. An advanced Smart-Meter File System (SMFS) from HCC was custom-designed to meet the low power consumption requirements of smart-energy and smart-meter applications. The structured database reduces complexity of the application by using a minimum number of flash operations to preserve both the flash and the battery.

www.amd-embedded.com



where data can be directly accumulated to the buffer to be transmitted and then read directly from the Ethernet buffer is likely to be the most efficient solution. As with flash storage, aggregation of data into packets will further reduce the system load, but the implications of a system reset with untransmitted data must be care-fully considered.

Other important possibilities for improvement include switching off TCP check-sums where the underlying media is reliable (typically because it has its own checksums), or using UDP to send data. But UDP must be used with caution; it is a fire-and-forget protocol, and if you need to make sure the message arrives, you must add some management—which effectively implies a protocol very similar to TCP!

SecuritySSL/TLS modules can be power-optimized and it’s worth looking for these mod-

ules. Remember that TLS software offers three different functions: authentication to ensure you are talking to who you think you are talking to, encryption to ensure your data is not readable by a third party, and integrity to ensure your message has not been modified in transit.

Different algorithms are used for the different functions, and by default three al-gorithms are agreed to in a TLS handshake. The developer needs to look carefully at the design requirements and verify what is really required so that unnecessary processing can be avoided; for instance, data may be in a format that is not useful to an intruder, or tampering with the data is not practical because of the nature of the data used. If encryption and integrity are enforced with TLS, all data will pass through two additional processing steps—an encrypt/decrypt module and a hash-ing module.

Software-based security algorithms tend to be CPU-intensive. From a pow-er-consumption perspective, it is clearly advantageous to reduce the usage of these algorithms to the minimum required by the system rather than accept a default setup.

As this article stresses, analysis of the requirements and developing a design that accurately meets those goals is critical. But this concept should also be extended to all levels of the software implementation. Selecting components that are developed using a defined process is the best way of guaranteeing that they do what you want them to do, and that they do no more than you want them to. A very small “corner-case” with seemingly little implication on the device’s functional-ity could have serious implications to power consumption; for example, an IO that is not switched off after a particular exception condition could be extremely difficult to detect in normal test. Risk will inevitably be minimized by the use of tried and tested methods such as a full V model design.

HCC Embedded USANew York, NY.(212) 734-1345www.hcc-embedded.com

Why Should Researching SBCs Be More Difficult Than Car Shopping?Today’s systems combine an array of very complex elements from multiple manufactures. To assist in these complex architectures, ISS has built a simple tool that will source products from an array of companies for a side by side comparison and provide purchase support.

INTELLIGENTSYSTEMSSOURCE.COM is a purchasing tool for Design Engineers looking for custom and off-the-shelf SBCs and system modules.

INTELLIGENTSYSTEMSSOURCE.COM



Intelligent Power Consumption and the Data CenterWhen it comes to data center (DC) technology, gaining visibility into power consumption is a critical part of the business case for any provider, given that power is often the biggest expense. With proper planning and device selection, the integration of the thousands of

by Jon Trout, TrendPoint Systems

Figure 1:Display showing data center infrastructure efficiency along with power usage efficiency.


According to the U.S. Department of Energy, data cen-ters can consume 100 times more energy than a standard office building, and approximately three percent of all elec-tricity in the U.S. is used to power them. It is estimated that DC power consumption will only continue to rise.

Providing energy, cooling and maintaining the right tem-perature for rack equipment to run optimally are all parts of the equation; and misjudging capacity planning for energy usage also results in wasted money, wasted energy and lost opportunities for operational optimization. Addition-ally, a lack of accuracy in the metrics provided can result in downtime that can cost organizations millions in hard dollars as well as brand equity.

The solution we often hear from data center managers is their vision of a “Single Pane of Glass” to manage their facility. The “Single Pane” concept has fueled the explo-sion of the Data Center infrastructure Management (DCIM) market with the need for one system to have the ability to manage and control the entire facility. Typically, the power measurement and monitoring aspect of the data center consumes the majority of the data points that build the DCIM system. The power infrastructure is of utmost importance to the reliability and efficiency of the data center. Power monitoring combined with a DCIM system can provide insight into the various aspects of the facility. The DCIM software is the bridge that collects the raw data from the devices in the facility and translates the data into “actionable intelligence.”

Capacity planning is one example of how power mon-itoring, combined with a software system, can assist in data center operations. The software can alert and alarm on capacity issues that may impact the redundancy of the facility. Most facilities use A and B sources of power distributed to the server racks. If the A source and B source are both running at 70% and the B source is lost due to an outage or failure, the A source will not have the ability to in-dependently carry the entire server load. The software sys-tem can also identify areas in the facility that have excess capacity, enabling server loads to be redeployed, physically or virtually, to these locations. The DCIM system is the watchdog, constantly monitoring these types of conditions and delivering alerts when abnormalities are observed.

In addition to capacity management and reliability, data centers are also concerned about efficiency. We hear debate around the Power Usage Effectiveness (PUE) metric and whether the PUE calculation is the best way to measure efficiency. While the PUE metric may have its critics, it still provides a benchmark for facilities to compare their efficiency with others in the industry. However, the PUE metric should be derived from a granular point in the power distribution chain. Losses in the Universal Power Supply (UPS), transformers and distribution chain should be taken into account when measuring the efficiency of the facility. The workload is performed at the server level, so losses and wasted energy upstream should be moni-tored and considered when looking for areas to improve efficiency. Power monitoring through the power distribution chain can be analyzed in the DCIM or software system to calculate the true efficiency of a facility (Figure 1). Areas that are lacking the expected efficiencies can be seen easily

through the software system and action can be taken to make improvements.

Avoiding the PitfallsTypically power is monitored at every stage of the

distribution chain inside the facility to properly manage the reliability and efficiency of the data center. Utility feeds, generators, switchgear, distribution panels, power distribution units (PDUs) and remote power panels (RPPs) are all monitored so facility managers and operators can manage their infrastructure at every stage of the system (Figure 2). A comprehensive power monitoring solution will consist of many different types of meters. The integration of these devices into the DCIM system can be a costly and time-consuming project. Multiple communication protocols, onboard configuration, logging and alarming are essen-tial. These features need to be applicable to the business requirements of optimization, speed of information and speed of deployment.

It is important to assess the ease of integration of the solution as well as the scalability. This includes both the ability for a system to be flexible enough to be integrated in the correct manner the first time as well as the adaptability of the system to work with new software.

Think Flexibility: With all of the power distribution types (e.g., PDUs, panel boards, busway, etc.) that may be in your one or multiple data centers, and the variety of vendors who supply these products (e.g., Schneider Electric, Sie-mens, Eaton, GE) that might be present, the power monitor-ing products you install need to be able to interact effec-tively with all of them. Choosing a “platform” that covers the spectrum of power distribution types and vendors, as well as various amperage sizes and circuit configurations, will simplify deployment and streamline integration into software systems.

Stay Adaptable: We’re seeing a rise in the number

Figure 2:A data center requires coordinated monitoring of interacting power systems on a variety of different meters and devices.



of data centers that use busway power because of the adaptable power distribution system it provides. PDUs and panel boards are also frequently changed and modified to support the dynamic data center environment. Make sure that your power monitoring products can adapt when the power shifts—that way you’ll save money on rebuilding or replacing the existing meters.

Achieve Utility Grade Accuracy: Most data center power meters claim to offer accuracy that is within five percent of the actual power utilization. Although five percent is not insignificant, the best practice in power monitoring is to attain utility-grade accuracy, which is within one percent of the actual amount of power consumed. The reason? A utility-grade level of accuracy enables co-located and other data centers to fairly rebill clients for the cost of energy.

Additionally, the importance of accurately measuring power consumption grows in the aggregate. A 400,000 square-foot data center being off in measurement accura-

cy for all of the installed equipment significantly impacts the bottom line.

The right data collected from the right points within the facility at a granular level makes it possible to gain an end-to-end view of what’s happening. This enables better efficiency assessments and energy management in gener-al, making it possible to identify specific problem areas and boost optimization.

Knowing exact amperage eliminates tripped breakers; tracking voltage gives visibility to variations in power to prevent trouble; tracking the power factor can prevent inflated power bills; and tracking wattage allows visibility into the heat generated by each circuit (Figure 3). Operators can identify kilowatt hours to track energy by end user and groups.

Measuring wattage allows users to identify when an anomalous amount of power is going to a group of racks. If usage is off compared to the average, then it’s likely that something needs remediation. This enables root cause analysis of issues, minimizing maintenance and trouble-shooting costs.

Avoid Non-standard Protocols: Does your data center use SNMP to communicate between systems? Modbus TCP? BacnetIP? If the power monitoring meters don’t utilize standard communication protocols, it will be more time-consuming and costly to integrate the meters with a DCIM or Building Management System (BMS). The best

Figure 1:Measuring the heat generated by each unit in the system enables quick visibility into anomalous conditions.


way to avoid this problem is to make sure that any meter-ing system you purchase has the right communications protocols for the software system you plan to utilize. Ide-ally, your metering platform should be able to support all your power distribution products, communicate easily with the software, and interact seamlessly with all of the other components of the data center.

Look for Greater Device Functionality: Typical monitor-ing solutions require a complex and costly network of protocol conversions, middleware and data interpretations to provide the operations and engineering teams with a comprehensive picture of power consumption in the facility. Features such as onboard Ethernet, onboard data logging, onboard alarming and an accessible Web interface can reduce the failure points and cost associated with a monitoring deployment.

Data center power monitoring is not just about reducing energy costs; it is part of a larger conversation that affects the overall operations of your data center’s various sys-tems. Data centers are dynamic environments, where serv-er stacks and power distribution sources might need to be reconfigured based on the center’s changing needs over time. Ideally, your data center monitoring solutions need to connect, interact and integrate with all of the various “moving parts” within your data center—without incurring additional costs or complexities along the way.

Knowing your power consumption at a granular level can

be a powerful way to help achieve the overall initiatives in the facility. Selecting the right power monitoring system for your facility’s current and future needs is an important part of the selection process. Implementation and integration of the power monitoring system are steps that can be easily overlooked, but they play a big role in the effectiveness of the facility and the DCIM or BMS systems they comple-ment. Flexibility, adaptability, accuracy, communications and device functionality are important characteristics of a successful power monitoring system.

TrendPoint SystemsCorona, CA.(888) 363-7787www.trendpoint.com


INDUSTRY WATCH BUILDING MANAGEMENT SYSTEMS

Self-powered wireless sensor networks have become integral parts of building automation systems. Advancements in energy harvesting technology and IP connectivity are paving the way to the Internet of Things.

by Jim O’Callaghan, EnOcean



The intelligent control of buildings requires sensors to collect relevant data from several points of measurement, and controllers to process the information. The sensor networks in medium to larger facilities may be comprised of hundreds to thousands of these sensory nodes, all re-quiring power and communication capability. At the same time, the solutions should be easy to install with a fast return on investment, providing significant energy savings and increased comfort.

These requirements are met by energy harvesting wire-less solutions, now an established IEC standard, controlling sustainable buildings for the past ten years. By employing energy harvesting, the wireless modules generate their power from the environment and therefore work without batteries. A variety of energy sources can be utilized; an electro-dynamic energy converter uses mechanical motion, a miniaturized solar module generates energy from light, and a thermoelectric harvester with a DC/DC booster con-verts temperature differential as an energy source.

These highly efficient harvesters generate sufficient en-ergy to power sensors, analyze environmental conditions and then transmit a wireless signal. This includes switches, door/window contacts along with temperature, humidity, occupancy and light sensors, communicating with intel-ligent controllers and building automation systems. The en-ergy harvesting wireless technology is composed of three major components that are optimally matched to each other: micro energy converters, ultra-low-power electron-ics and an optimized wireless standard. This comes along with software tools that allow a user-friendly integration in applications (Figure 1).

Figure 1:The three components of energy harvesting wireless technology.

Figure 2:The technology’s flexibility allows positioning the batteryless sensors at any place of optimal measurement and data collection. Gateways can translate the energy-optimized radio protocol to other wireless standards or networks.



Optimized for Building AutomationFor architects, facility managers or installers, the self-pow-

ered technology offers several benefits in a building auto-mation system. Being wireless, the sensors and switches can be flexibly located to optimize effectiveness. If an office layout changes, the sensors can simply be removed and repositioned at any time. The radio communication is optimized for range and reliability, communicating through common home and office walls at a distance of up to 90 feet. But the actual highlight is the devices’ batteryless characteristic, making them maintenance-free. There are no power wires to pull, nor batteries to replace and dispose of properly. This yields to a low-cost, reliable system leveraging

an environmentally friendly technology (Figure 2).

Further Development for New ApplicationsEnergy harvesting technology is just getting started. When

we take a look beyond building automation, new application fields for self-powered wireless communication arise, includ-ing structural health monitoring, water quality control and forest fire prevention or smart city management.

For such applications, mainly outside the building, the components of energy harvesting wireless technology, consisting of energy converters, wireless transmitters, energy management, software and development tools as well as the energy-saving radio protocol, need to be further enhanced.

The next generation of energy harvesting radio tech-nology will enable up to ten times longer radio ranges to wirelessly transmit data over a distance of more than 1.7 miles, enabling new outdoor applications with higher range requirements. The increased energy need of such a long distance can be realized by the progress of other compo-nents, such as energy harvesters.

Motion is a stable and reliable energy source that can be harvested almost anywhere, for example in the movement of doors, windows or machine components, and in the vibra-tion of motors, the rotation of door handles or switches. New types of mechanical energy harvesters will make use of the energy of flowing gases and liquids in particular. These har-vesters will be used to power metering applications and help eliminate batteries from millions of these devices.

A second energy source, light, will play a significant role as future generations of miniaturized solar cells will com-bine reduced energy consumption with improved energy generation under low light conditions. While the limit of operation is light intensity of about 100 lux at 5% efficiency

Figure 3:Batteryless sensors connected to the Internet not only deliver information for a local unit. The data stored in the cloud rather can be the basis for several analyses and therefore reused for different purposes.

Cloud-based DataStorage

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Figure 4:The IPv6 header requires 40 bytes of protocol data.


today, next generation solar cells based on organic material or dye-sensitized technology can operate down to 10 lux light intensity with more than 10% efficiency.

Finally, temperature differentials contain significant en-ergy and are therefore ideally suited to powering devices. The cooling of just one drop of water by 1 degree Celsius releases energy for about 25,000 energy harvesting wireless telegrams. These harvesters will allow very robust sensor nodes, independent of light and therefore not sen-sitive to dirt.

Another contribution to the energy balance is reducing energy consumption. As the energy demand of sensor modules gets lower from generation to generation, the technologies’ suitability is enhanced. In addition, there are significant improvements in energy storage components. The target is to store sufficient harvested energy to operate weeks to several months and up to a year without addi-tional energy.

Next Decade of Internet With IPv6 providing an almost unlimited number of IP

addresses, machines (sensors, actuators, controllers) inter-acting directly with other machines on a broad scale will grow rapidly. Thus the Internet of Things (IoT).

Having a large network of sensors, actuators and control units interacting with each other and the user can bring several distinct benefits. More sensor data provides better

insight for the control system. Unlike the standard ap-proach of one or more sensors being connected to one central control unit, an Internet of Things allows the sharing and reuse of available information between different nodes. Thus, the system collects data only once but uses the information for several applications (Figure 3).

Current control systems are usually local; for exam-ple sensors, control unit and actuators are often in close proximity and wired or wireless, directly connected with each other. IPv6 connectivity no longer requires such proximity. It allows centralized, or even outsourced comput-ing resources (Cloud-based computing), thus driving down infrastructure cost. Besides this, the IoT allows dynamic creation of control networks. The networks can be formed or dissolved dynamically based on time, location or other parameters. For instance, cars could automatically query temperature sensors in the street to determine if there is a danger of ice on the roads and warn the driver accordingly. These examples illustrate the enormous potential that can be unleashed by an Internet of Things.

All required base technologies for forming such a network already exist today—sensors, actuators, local or Cloud-based control units and IPv6 to connect all of them together. Nevertheless, the energy harvesting sensors themselves cannot communicate directly over IP. Battery-less wireless transmission means that the chosen protocol must be optimized for ultra-low-power communication.



The payload associated with sensors is small (a few bytes), therefore the protocol overhead must also be limited as much as possible.

Employing IPv6 as the communication protocol at the individual sensor level is challenging because it includes significant overhead, as the IPv6 header alone requires 40 bytes of protocol data (Figure 4).

In addition to that, UDP, probably the simplest communi-cation protocol on top of IPv6, would require an additional 8 bytes of protocol data. Based on the IPv6 and UDP header structure, the transmission of 1 byte sensor data would re-quire an additional 48 bytes of low-level protocol data. IPv6/UDP is therefore not well-suited for energy-efficient commu-nication on the sensor level in a network (Figure 5).

In comparison, the EnOcean protocol for energy harvesting wireless applications only incurs 7 bytes of protocol overhead for the transmission of 1 byte of sensor data (Figure 6).

Translation of data between such an energy-efficient sen-sor protocol and IPv6 is provided by dedicated IP gateways that represent the state of each connected sensor node and act as their representative within the IPv6 network. This ap-proach allows exchanging data with individual sensors even while they are sleeping and therefore unavailable for direct communication. Upon wake-up, sensors will then update their state information in the gateway and retrieve messag-es/commands intended for them (Figure 7).

Sensory Organs for Worldwide UseWith the technology’s progress and the enhanced abil-

ities of IPv6, new application fields for energy harvesting

wireless communication become feasible. Finally, let’s take a look at how enhanced batteryless technology and IPv6 communication will turn the Internet of Things into reality.

Cloud-based computing resources could be used to combine local temperature data provided from batteryless sensors with an external weather forecast to compute the exact amount of water required for agricultural irrigation. This information would then be sent to a remote actuator controlling the water flow. Similar sensors could measure the degree of humidity or soil nutrients for an optimal sup-ply of water and care for plants.

Self-powered wireless sensors could also be placed over large areas to provide early warnings or to monitor farm animals and plants in order to react very quickly to chang-ing conditions. Temperature sensors, for instance, could send position data and an alarm signal when they measure the heat of a fire. Via a central gateway, a notification is im-mediately sent to the nearest fire station and/or via SMS to a responsible person’s smartphone. Such an early warning system could prevent the spread of forest fires.

Whether it is water, gas or oil—all resources on earth are limited and therefore need to be protected and used careful-ly. Batteryless sensor networks can support this by provid-ing the needed data to monitor water in terms of quantity and quality, or the movement of shoals of fish. In addition, detectors can use miniaturized solar cells or motion energy converters to power wireless signals that report water, oil or gas leaks to a gateway controller or directly to a valve. The energy harvesting technology prevents system malfunc-tions that otherwise could be caused by battery failures.

The fabric built of large structures including bridges, tunnels, dams or drilling platforms has to resist extreme forces like weather, earthquakes or traffic. Today, in the U.S. alone, nearly 25% of all bridges are deemed structurally deficient or functionally obsolete. In numbers, that is more than 150,000 bridges. Radio sensors, powered by light, temperature changes or vibrations that permanently moni-tor critical parameters, can warn against non-conformance and prevent breakdowns. These sensors would monitor parameters related to structural health, such as integrity,

Source Port Destination Port Length Checksum

0Byte 1 2 3 4 5 6 7

8 Bytes

RORG

1 Byte 1 Byte 4 Byte 1 Byte 1 Byte

8 Bytes

DATA SOURCE ID STATUS HASH

Figure 5:The UDP header on top of IPv6 comes with 8 bytes of protocol data. This causes a bandwith-intensive data transfer which needs a lot of power. There-fore, batteryless sensors are not suitable to directly communicate via IPv6.

Figure 6:The energy harvesting wireless protocol is particularly optimized for an ultra-low power communication, requiring only 7 bytes of protocol data.


A TQMP2020 modulewith a Freescale QorIQcan save you designtime and money

TQ embedded modules:

■ Are the smallest in the industry, without compromising quality and reliability

■ Bring out all the processor signals to the Tyco connectors

■ Can reduce development time by as much as 12 months

The TQMP2020 module comeswith a Freescale QorIQ™ PowerArchitecture® MCU and supports Linux and QNX operating systems.

The full-function STKP2020 StarterKit is an easy and inexpensiveplatform to test and evaluate theTQMP2020 module.

ConvergencePromotions.com/TQ-USATQ-USA is the brand for a module product line represented in N. America by Convergence Promotions, LLC

Technology in Quality

TQMP2020 V2 1-3 Page Ad.indd 1 2/3/14 3:57 PM

position and vibrations, and act as an early warning system. A similar functionality can provide an alert in the event of an avalanche or rock fall.

By 2030, 60% of people will live in a city—representing almost six billion people. Intelligent control will be needed to coordinate people’s daily lives and prevent a city from collapsing into turmoil. This includes automated control of traffic, street lights, energy supply and transportation of goods as well as waste disposal. This can only be realized with millions of self-powered sensor nodes collecting and de-livering the necessary data. Malfunctions of battery-powered sensors could cause chaos in such a deeply connected system. But cables are no alternative either, as they are too complex and costly to install. In contrast, energy harvesting-powered devices can overcome both issues. Solar-powered occupancy sensors, for exam-ple, notify when somebody is walking on a street and send a signal to activate the street light. The same can function with motion-powered sensors in the streets’ surface when a vehicle passes. Other fields of application are cold chain monitor-ing for food transportation, or the notification and automated repeat order when goods in a store run out.

Another wide field of application is making our life easier, more secure and comfortable. The demographic change necessitates modern technology for the elderly, when it comes to being able to live at home independently for as long as possible or if sickness occurs. Ambient assisted living systems can provide data on a tenant’s activities and send a notification to a caregiver or relative if there is a remarkable change in daily routines or too little activity. Alarm systems such as portable emergency buttons complement the system. In regards to flexibility and low maintenance effort, the common requirement for all components is to be wireless and batteryless.

EnOceanCottonwood Heights, UT.(801) 312-0115www.enocean.com

Figure 7:Gateways that reproduce a sensor’s state allows data translation in real-time even when the self-powered sensor is only active in specific wake-up cycles.

GatewayMapping

Virtual Device

State(of the Device)

Transmitting Transmitting /Receiving

Receiving Command(to the Device)

Translation

Con�guration

Display

Controller

ProtocolGatewayPhysical

Device



RTC PRODUCT SHOWCASE

Rugged SWaP-optimized 6U VPX Radar Solution

A rugged 6U VPX blade features a dual processor design based on quad-core fourth generation Intel Core i7-4700EQ processors. The VPX6000 from Adlink Tech-nology is a high performance blade designed to meet MIL-STD-810F for harsh environments and provide the high availability required for mission-critical applications, includ-ing radar, sonar, UAV and UGV in defense and aerospace.

The two CPU sub-systems are connected by a PCIe x8 Gen2 non-transparent bridge for high-speed, high-band-width data transfer. The VPX6000 is a SWaP-optimized platform designed to meet defense industry requirements for operation in harsh environments across wide operating temperature ranges (-40°C to +75°C at wedge-lock), with-standing high shock and vibration, while having a maxi-mum power consumption of only 160W.

With the Adlink VPX6000, system integrators can map multiple functions such as control, graphics and signal processing onto one blade. It can also run dual inde-pendent systems, reducing the card count and required number of spares to simplify logistical support in the field. The VPX6000 also supports multiple operating systems, including Windows Embedded, Linux and VxWorks, provid-ing flexibility for system design.

The VPX6000 provides all-in-one manageability, includ-ing SmartFusion IPMC, built-in self test (BIT) and Intel AMT. These features support remote monitoring and manage-ment of the VPX6000 to help or immediately correct any problems in order to avoid critical system crashes and maintain high availability.

The Adlink VPX6000 provides flexibility and reliability with rich and fast I/O, including VGA, GbE and 2x USB 3.0 on the front panel, HDMI/DVI, 3x USB 3.0, 2x serial ports, PS/2 keyboard/mouse, 8x GPIO and audio to the back-plane. In addition, an expansion plane of 2x PCIe x8 Gen2 with DMA is provided. The VPX60000 supports 16GB sol-dered dual-channel DDR3L ECC memory and upgradeable storage via SSD mezzanine card for flexible and rugged storage compared to traditional hard disk drives.

ADLINK Technology, San Jose, CA. (408) 360-0200. www.adlinktech.com

Mini-ITX Motherboard Based on Fourth Generation Core Processor

A new Mini-ITX motherboard is based on the Q87 chipset and designed to support socket LGA1150 fourth Generation Intel Core i7/i5/i3 desktop processors built on the latest 22nm process technology. The MI987 from IBASE Technology offers leading-edge processing per-formance as well as an increase in graphics performance compared to its predecessors, making it quite suitable for demanding applications in the gaming, automation and digital signage markets.

The MI987 is equipped with two DDR3-1600 SO-DIMM sockets to support up to 16GB of system memory and three types of graphics display interface, including VGA CRT, HDMI and DisplayPort. Alongside the display edge-connectors are one serial port, four USB 3.0 ports, two Gigabit Ethernet ports, audio connectors and a 19V DC-in jack that eliminates the need for a bulky internal power supply and shrinks the volume of the system chassis.

With long-term availability, the MI987 comes with many great features, such as two 6Gb/s SATA III interface, two serial ports, watchdog timer, digital I/O, TPM 1.2, iAMT and iSMART. While TPM allows systems to run applications se-curely, iSMART provides EuP/ErP power saving and intelli-gent scheduler for better environmental performance. The MI987 is available in both the Intel Q87 and H81 versions.

IBASE Technology, Taipei, Taiwan, 886-2-26557588 www.ibase.com.tw



IoT Gateway Based on Intel Quark SoC

A new IoT gateway is based on the new Intel 32nm Quark SoC X1000 series as part of the Intel Gateway Solutions for the Internet of Things. The PI-81 A0 from American Portwell brings years of embedded computing expertise in the industrial automation, network security and medical equipment markets for an extensive variety of In-telligent Gateway applications. In addition to this version of the Intel Quark SoC X1000 series based solutions, Portwell also plans to offer other Intel architecture-based Intelligent Gateways. Many will be packaged with Wind River Intelli-gent Device Platform (IDP) and McAfee Security stack.

. The PI-81A0 IoT gateway is designed with several high-ly-integrated features, including dual 10/100 Fast Ethernet, one USB 2.0 Host port, one USB 2.0 Device port, and 8-channel analog-to-digital convertor input interface. In addition, it features 512-kilobytes of on-chip flash memory, SRAM and an integrated DDR3 memory controller (sup-port up to 2G@800MTs), and an optional WiFi or Wireless module.

The PI-81A0 includes Wind River operating system and McAfee security software solutions. Portwell also provides speedy customization support and service for volume OEMs, including hardware design, mechanical design, complete system integration and manufacturing.

American Portwell, Fremont, CA. (510) 403-3399. www.portwell.com

Backplanes Available in COTS, Modified COTS or Custom Designed Configurations.

The Orbit Electronics Group has announced its VME-VPX portal, www.vmevpx.com, as a source for best-of-breed, more affordable backplanes, with eleven different COTS models in 6U and 3U form factors. Two to 21 Slots are standard, and virtually any custom performance config-uration can be provided.

For example, Orbit VITA 67 VPX 3U high-density backplanes are used for the latest embedded computing applications. The VITA 67 architecture enables coaxial/RF interconnects directly to the backplane and to the cards that interface the backplane. As with all Orbit VPX back-planes, the VITA 67 backplane enables the use of high-speed serial switch fabric technologies such as Ethernet PCI Express, Serial RapidIO, and others. It can be produced in 3U, 6U, or virtually any other configuration needed.

Features of the Orbit VITA 67 VPX backplane include:VITA 46.0 baseline; supports VITA 46.4 Full Mesh X4

PCI Express and VITA 46.10 with RTM connectors; 3U, 5 Slot, Full Mesh configuration with 6U variants available; M3 Power Taps, PCB size 128.7 mm x 145.41 mm x 3.92 mm; 14 PCB Layers; 5 HP from slot to slot (25.4 mm); Backplane Connectors with MULTI-GIGRT-2J; flexible keying and align-ment mechanism; JTAG connector on all slots; Geograph-ical address pins; Battery backup option set by Jumper J106; VBAT external or connected to 3.3 AUX; Power is VS1 = 12 V, VS2 = 3.3 V, VS3 = 5 V; Operating temperatures of -40° to +185°F (-40° to +85°C); and Storage temperatures of -40° to +185°F (-40° to +85°C). More than 135 different standard and customized VME-VPX components, prod-ucts, and options can be seen at www.vmevpx.com.

Orbit Electronics Group, Louisville, KY. (866) 319-8085. www.vmevpx.com



New FPGA Family Speeds Customization of ‘Killer’ Features for Mobile Devices

Lattice Semiconductor has introduced the iCE40 Ultra family, delivering unsurpassed integration of emerging infrared remote, barcode, touch, user identification, and pe-dometer functions with ample customization capabilities for makers of mobile consumer devices to quickly implement ‘killer’ features that differentiate their products.

iCE40 Ultra FPGAs deliver 5x more functionality at 30% smaller size than competing solutions. Lattice has also reduced power by 75% over previous devices. Combined, these enable designers to give their systems more compact form factors and longer battery life.

Lattice has shipped hundreds of millions of iCE40 FPGAs since their introduction in 2012, providing the fastest time to market for a diversity of capabilities in smartphones, tablets, wearables and other mobile devices.

“Lattice’s new iCE40 Ultra family further frees designers to customize any way they want in order to win big in their markets by implementing amazing features their customers can’t live without,” said Lattice Semiconductor President and CEO Darin Billerbeck.

The iCE40 Ultra family integrates LED drivers, multipliers and accumulators, serial interfaces and a whole host more of hardened IP. This ASSP-like integration reduces system power and speeds implementation so designers can spend more time on the customization.

With the smallest iCE40 Ultra device in a wafer level chip scale (WLCS) package measuring just 1.7mm x 2.1 mm x 0.45 mm, no other solution on the market delivers so much ca-pability and flexibility at low power in such a small package. iCE40 Ultra family devices are available from Lattice now. Software support is available in the Lattice iCECube2 tool.

Lattice Semiconductor, Hillsboro, OR. (503) 268-8000. www.latticesemi.com

System on Module Helps Develop Embedded Sys-tems Faster, With Less Risk

A new system on module combines the Xilinx Zynq All Programmable system on a chip (SoC) with support-ing components including memory on a small PCB and features a complete middleware solution and ready-to-go Linux-based real-time operating system (RTOS) already integrated. The NI SOM from National Instruments gives design teams the customizability of a SOM without the increased time and risk of developing custom software.

The NI SOM enables design teams to deploy reliable, complex embedded systems faster because it is based on and has the same rigorous design standards as the Lab-VIEW reconfigurable I/O (RIO) architecture. This architec-ture has already been used in high-reliability applications such as unmanned aerial vehicles and cataract surgery machines.

Key features include a complete middleware solution. The NI SOM is shipped with a complete middleware solu-tion out of the box to remove the time and risk associated with developing an embedded OS, custom software drivers and other common software components. The system also includes LabView FPGA integratiom. LabVIEW FPGA eliminates a design team’s need for hardware description language expertise, making powerful FPGA technology more accessible than ever before.

The NI SOM also offers a robust Linux-based RTOS, which gives design teams access to an extensive commu-nity of applications and IP. Design teams can use Com-pactRIO to quickly prototype their applications and then deploy them with the same code used for prototyping, which saves significant time and effort.

National Instruments, Austin, TX. (512) 794-0100. www.ni.com



RTOS Includes Hardware Virtualization

Sysgo has announced the release of version 3.5 of its hypervisor PikeOS. Focus of the innovation is the support of hardware virtualization enabling the execution of guest op-erating systems without any adaption. Additionally, PikeOS 3.5 is equipped with an enhanced PikeOS Native person-ality and improved Linux support by using ELinOS 6.0 and Android 4.3.1. The integrated development environment CODEO has also been updated and speeds up the configu-ration process of ELinOS and Android personalities.

PikeOS 3.5 seamlessly integrates support for the ARM Virtualization Extensions - introduced in the Cortex A-15 SoC family - into its safe and secure virtualization technology. The PikeOS Virtual CPU Personality allows execution of an unmodified guest operating system inside a PikeOS parti-tion without compromising performance. Benchmark results of a guest operating system are equal to a native setup in most scenarios. In particular benchmarks producing system calls or exceptions run without any penalty in a PikeOS partition. Guest operating systems are constrained by time and space partitioning as well as health monitoring and can be connected via the generic P4Bus to PikeOS interpartition communication services and the PikeOS file system.

The new ELinOS version 6.0 is compatible with Pike-OS 3.5 and can run inside a PikeOS partition, either as a para-virtualized or, on ARM Cortex A-15 based platforms, as a hardware virtualized guest operating system. In addition to ELinOS 6.0 an Android personality is available for the ARM architecture. The platform independent version is based on Android 4.3.1 and the version for Freescale i.MX 6 with direct I/O access from Android is based on Android 4.2.2.

PikeOS is a hypervisor intended for embedded sys-tems with safety and security requirements. With real-time, virtualization and partitioning, it provides all the features needed to build today’s multi-functional and high-integrated devices. The PikeOS architecture creates a foundation for critical systems allowing official approval by the authorities in reference to safety and security standards. PikeOS is the only European software platform for smart devices in the Internet-of-Things (IoT).

SYSGO, Klein-Winternheim, Germany. +49 6136 99480. www.sysgo.com

High Density 3U Networking Platform

A 3U networking platform system delivers high-density processing with up to 12 hot-pluggable blades powered by Intel Xeon E3 12xx series processors. In the PL-80540 from WIN Enterprises, these high performance quad-core processors deliver clock speeds of 3.2 GHz or 3.4GHz. In addition to its standard LAN complement of 2x 10GbE SFP, 2x GbE SFP and 2x GbE RJ45, the PL-80540 accommo-dates expansion modules for an additional 6x 10GbE SFP and additional 16x GbE copper/fiber LANs.

The hot-swappable blades enable the OEM to scale from moderate to high density server solutions for a variety of networking tasks from cluster computing, web hosting to Unified Threat Management (UTM). The unit features redundant power and provides four hot-swappable fans with speed control.

Features include configurability with up to 12 hot-plugga-ble nodes in a 3U rack mount chassis and support for up to 12 Intel Xeon E3 Series 12XX processors. There is maximum 32GB Dual-channel DDR3 1066/1333 MHz system memory and the system comes standard with 2x 10GbE SFP+, 2GbE SFP & 2GbE Copper ports via PCIe x4/x8.

There are redundant 80 Plus Platinum Level Power Sup-plies and an optional IPMI Remote Management Interface.

WIN Enterprises, North Andover, MA. (978) 688-2000. www.win-ent.com



USB 3.0 Cameras with 2 and 4 MP CMOSIS Sensors

Camera manufacturer Basler is expanding its portfolio of ace USB 3.0 cameras to models featuring 2 MP and 4 MP CMV2000 and CMV4000 CMOS sensors from image sensor manufacturer CMOSIS. The cameras are available in monochrome and color as well as in near-infrared.

USB 3.0 models combine the benefits of high-per-formance CMOSIS sensors with the bandwidth, simple plug&plug compatibility and reliability of USB3 Vision. They deliver a fast 165 frames per second at 2 MP and 90 frames per second at 4 MP resolution, all while placing only a very small CPU load. Image quality is excellent, with low noise, high dynamic performance and very strong sensi-tivity. The 5.5 µm² pixel size and the global shutter capture high-precision images even in difficult lighting conditions or fast movement situations. Also of interest for users: The cameras are extra small and light (29 x 29 x 29.3 mm at 80 g), making them perfectly suited for systems where space is at a premium.

Because of this combination, they are in high demand for nearly all areas of machine vision. This includes not just many classic industrial applications in factory automation, but also traffic, logistics, medicinal and laboratory automa-tion applications.

Basler, Ahrensburg, Germany. +49 4102 463 258. www.baslerweb.com

PCI Express Mini Card Enables Wireless Voice Com-munications

A mobile phone voice interface PCI Express mini card provides cost-effective wireless audio transmissions in rugged, mobile applications such as railway and on-road vehicle networks. The new PX4 from MEN Micro can be integrated into MEN Micro’s full line of rugged, flexible box PCs. This allows voice and phone functionality across many popular communication networks to be easily incor-porated into a mobile system.

Developers no longer need to implement a separate, costly audio system that enables the driver to call the con-trol room or the control room to make an announcement to the passengers, for example. The new Mini Card supports the transmission of the audio data via Ethernet or analog signals through a USB interface. An additional PCI Express Mini Card (Telit HE910) for wireless functions like UMTS, LTE or Edge mounted on the PX4 makes mobile telephony possible. One SIM card slot is also available.

All box PCs from MEN Micro are specially designed for demanding operation in buses and railway systems or in agriculture and building machines. Working at an extended temperature range of -40°C to +85°C, they conform to EN 50155 and can be certified to E-mark. Pricing for the PX4 is $250. Delivery is six to eight weeks ARO.

MEN Micro, Blue Bell, PA. (215) 542-9575. www.men-micro.com


RTC PRODUCT GALLERYRugged SBC | Real Time Development Tools

Intel® Core™ i7 PCIe/104 CPUs• Intel® Core™ i7 Quad-Core or Dual-Core and Celeron®

Single-Core Processors• 1.5 – 2.1 GHz clock speeds with up to 3.1 GHz Turbo

Boost• Up to 8GB soldered dual-channel DDR3 SDRAM with

robust Error Code Correction (ECC)• Up to 32GB SLC surface-mount SATA flash drive• Eight x1 PCIe links and Three x4 PCIe links• Dual GigE, 5 SATA ports, 4 Serial ports, 4 USB 3.0, 3

USB 2.0, VGA, DisplayPort• -40°C to +85°C operating temperatures• Standard and custom enclosures available

Phone: (814) 234-8087Email: [email protected]: Web: www.rtd.com/i7AS9100 & ISO 9001 Certified

Raptor Rugged COTS SystemDiamond’s Raptor COTS computer system features a rugged SBC with the 2.1GHz Intel Core i7-3612QE CPU housed in a sealed aluminum enclosure. A full suite of I/O, including on-board data acquisition, provides the connectivity for most applications. A wide operating temperature, high resistance to shock and vibration, and wide voltage input enables Raptor to excel in vehicles or harsh environments.

Phone: (650) 810-2500Email: [email protected]: http://www.diamondsystems.com/prod-ucts/raptorvega

MEN Micro’s Redundant CompactPCI PlusIO SBCMEN Micro’s SIL 4 certified, redundant CompactPCI PlusIO SBC provides safe computing for railway operations. Incorporating three Intel Atom processors and a safe QNX operating system, the new COTS-based F75P provides onboard functional safety. The SIL 4 certification package reduces risks, time to market and NRE costs.

Phone: (215) 542-9575Fax: (215) 542-9577Email: [email protected]: www.menmicro.com/

CM1-BT1 PC/104 Single Board Computer• Single/Dual-core Intel® Atom™ Processor System-

on-Chip• Up to 4GB DDR3L at 1333MHz• Supports VGA and LVDS• GbE (optional 2x GbE)• 1x SATA 3Gb/s (optional 2x SATA), 1x USB 3.0 + 2x

USB 2.0, 8x GPIO• Extreme Rugged™ operating temperature range:

-40°C to +85°C• Supports Smart Embedded Management Agent

(SEMA) functions

Phone: (408) 360-0200Email: [email protected]: www.adlinktech.com


RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to The RTC Group, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.

Company Page WebsiteAdlink Technology, Inc. .................................................................................................................... 27 .........................................................................................................................www.adlinktech.com

AMD .................................................................................................................................................................31 ........................................................................................................................................www.amd.com

American Portwell Technology, Inc. ..................................................................................... 52 ...............................................................................................................................www.portwell.com

Artila Electronics Co. Ltd. ................................................................................................................41 .......................................................................................................................................www.artila.com

Cadia Networks ..................................................................................................................................... 37 ...............................................................................................................www.cadianetworks.com

congatec, Inc. ........................................................................................................................................4, 11 ...............................................................................................................................www.congatec.us

Dolphin Interconnect Solutions ................................................................................................. 17 ..........................................................................................................................www.dolphinics.com

Intelligent Systems Source .......................................................................................................... 33 .....................................................................................www.intelligentsystemssource.com

Interface Concept ................................................................................................................................. 32 ......................................................................................................... www.interfaceconcept.com

Lauterbach Development Tools ................................................................................................21 .........................................................................................................................www.lauterbach.com

MSC Embedded, Inc. ...........................................................................................................................4 ............................................................................................................... www.mscembedded.com

One Stop Systems, Inc. ...............................................................................................................15, 23 ......................................................................................................www.onestopsystems.com

Orbit International Corp. ..................................................................................................................5 .............................................................................................http://orbitelectronicsgroup.com

Product Gallery ....................................................................................................................................... 49 ............................................................................................................................................................................

Real-Time & Embedded Computing Conference ........................................................50 ......................................................................................................................................www.rtecc.com

Trenton Systems .....................................................................................................................................7 ............................................................................................................. www.trentonsystems.com

TQ Systems GmbH .............................................................................................................................. 43 ..................................................................................convergencepromotions.com/tq-usa

WDL Systems ...........................................................................................................................................51 ......................................................................................................................www.wdlsystems.com

WinSystems, Inc. ...................................................................................................................................2 .......................................................................................................................www.winsystems.com

rtecc-printad-quarter-horizontal.indd 1 9/11/14 4:28 PM

ADVERTISER INDEX

The Embedded Products Source1.800.548.2319 www.wdlsystems.com

www.wdlsystems.com/mag/RTC/sep14.html

[email protected]

Fexible modular design for PC/104

Stackable system configuration in 1U, 2U and 3U heights

Various I/O ports supported

Customized configuration

Enhanced water resistance with up to an IP67 rating

Personalized laser engraving available

SMARC (Smart Mobile Architecture) COM Based on Freescale i.MX 6

CPU with single, dual and quad core ARM Cortex™-A9

Measures 82mm x 50mm

Dual display graphics controller with 2D/3D acceleration

3x PCI Express, 1x PCI support

Extended Temperature: -40°C to 85°C

InnoRobust II 2.5" SSD

sAMX6i

Matrix-513

eBOX-104

Atmel 9G45 400MHz ARM9 CPU

2 x Ethernet, 4 x RS-232/422/485

Dual miniPCIe for WLAN and 3G expansion

2x isolated digital input and 1 x relay output

Linux 2.6.38 with GNU C/C++ tool chain

Fexible modular design for all PC/104 modules

Stackable system configuration in 1U, 2U and 3U heights

Various I/O ports supported

Customized configuration

Enhanced water resistance with up to an IP67 rating

Personalized laser engraving available

Network Security Appliance

PICMG SBC

[email protected]

1-877-278-8899

Mini-ITX Small Form Factor System

COM Express Module

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