MOSFET
[F/cm-2]
[F/cm-2]
Cd Depletion Capacitance
Cox Oxide Capacitance
MOSFET
CMOS
1
10
100
1000
Years
EKV
BSIM4v4
MM9 (MosModel9) →Philips
TUC
Gate
Gate leak current is not ignorable due to the higher tunneling
probability
of thinner gate oxide
In latest CMOS compact model, several current sources as Igb, Igs,
Igd,
Igc(Igcs, Igcd) having Vg dependency, which gives bias dependence,
and
mathematical smoothing transforming function from accumulation
to
inversion mode, via depletion.
Ioff/Tr is ~100nA
This was focused as a big-problem to degrade Transistor performance
from 130nm
generation.
SBSA
SB difference from reference
STI stress effect –VTH shit of 130nm CMOS-
5 10 15 20 25 30 35 40 45 50 550 60
0.17
0.19
0.21
0.23
0.25
0.27
0.29
0.31
0.33
0.15
0.35
Finger_Num
s]
Finger_model
5 10 15 20 25 30 35 40 45 50 550 60
0.28
0.29
0.30
0.31
0.32
0.33
0.34
0.35
0.27
0.36
N o
rm al
iz ed
C ap
ac it
an ce
Observation of the RB scaling
0
2
4
6
8
10
12
Wf*NF
N o
rm al
iz ed
R B
NF-1*Wf-1
NFWf Rsh
RF-CMOS modeling summary
NfLgKCGB CGB
NFWf Rsh
110GHz S-parameter model vs measurement.
Existing modeling technology is applicable up to 110GHz
S11 S22
S22 MAG
S22 PHASE
S11 MAG
S11 PHASE
S21 MAG
S21 PHASE
S22 MAG
S22 PHASE
fMAX optimization of RF-NMOSFETs
40nm 2nd GenReduction of overlap capacitance (CGD) can make
40nm
CMOS widely available for IoT applications.
G
167GHz
Dietmar Kissinger “Millimeter- Wave Receiver Concepts for 77GHz
Automotive Radar in
Silicon-Germanium Technology”
04 Synchronization of compact model
with latest FAB output.
Ramp-up
High Volume measurement
Fab-link model parameters vs In-line data.
S/D
sheet
resistance
Thickness
Epsilon
directly or via process function completes fab-link model.
Channel
Doping
NDEP
RDSW
Typical,σ
Process
Function
F(Ndep)
How Process function looks like ?
Establish direct link of li-line data with compact model.
Channel
Doping
10
100
1000
10000
1.0E+14 1.0E+15 1.0E+16 1.0E+17 1.0E+18 1.0E+19
Impurity Concentration [cm-3]
statistics {
process {
percent=yes
fMAX fT
Rg Cgd
Cds gm
Fab-link model vs. measurement at 60GHz correlation. [1]
64
Future MOSFET Modeling Challenges
Actual
-35 -30 -25 -20 -15 -10-40 -5
12
14
16
18
20
22
10
24
Thermal Network.
References
2 Franz Sischka, “ICCAP Modeling Handbook”, Keysight
Technologies
3 Gennady Gildenblat, “Compact Modeling” Springer (2010)
4 Willy M.C. Sansen , “ ANQLOG DESIGN ESSENTIALS”, Springer
5 C.Enz, “Charge-Based MOS Transistor Modeling: The EKV Model for
Low-Power and RF IC Design” Wiley
6 Wladyslaw Grabinski,”Transistor Level Modeling for Analog/RF IC
Design”, Springer
7 Yogesh Chauhan,” FinFET Modeling for IC Simulation and Design,
1st Edition using the BSIM-CMG
Standard” Academic Press 2015.
Scientific, 2010.
9 M. Jamal Deen, Tor A. Fjeldly ,” CMOS RF Modeling,
Characterization and Applications”World Scientific (2002)
10 Chemning Hu,” Modern Semiconductor Devices for Integrated
Circuits 1st Edition”, Prentice Hall; 1 edition (April 1,
2009)
(Latest MOS-AK http://www.mos-ak.org/