RF Mixed Signal Guidi-McIllree-Stannard

24 www.rfdesign.com November 2001

The need for high data-rate transmission pre-sents significant hardware design challenges. A

flexible DSP-based modem project for high data-rate transmission applications has been jointlydeveloped by the University of South Australia andJNS Electronics Pty. (Melbourne).

The needBecause Australia has tight spurious emission

specifications for allocated channel bandwidth, spec-tral efficiency was the major objective of the modemdesign. Various methods were used to achieve high

spectral efficiency, minimizing spurious emissionsoutside allocated frequency bands of operation. Asecond objective for this project was to addressmicrowave terrestrial and satellite communications.

As the article progresses, the modem functionblocks are developed and each block is discussed.

Let’s modulateThe modulator processes the transmitted data

differently, depending on the choice of modulationand coding schemes. The chosen modulationscheme depends on whether power efficiency orspectral efficiency is more important.

Spectral efficiency (>2bits/s/Hz) is achieved withhigh-order modulation schemes such as eight-phaseshift keying (8PSK) and 16-quadrature amplitudemodulation (16QAM). The output of the modulatoris a bandpass signal centered on an intermediatefrequency (IF).

The upconverter performs translation of the sig-nal from an IF to a desired transmit (TX) IF. Formicrowave terrestrial link communications, thefinal TX frequency is L-Band. For satellite commu-nications, the upconverter provides a 70/140 MHztransmit IF interface for satellite earth stationapplications. The channel adds noise to the signaland, depending on the application, the signal can bedistorted a number of ways. Microwave digital radiois susceptible to frequency-selective fading becauseof the interference of multipath signal components,while satellite links are more susceptible to signalattenuation because of climactic effects such as rain.The downconverter operates in reverse from theupconverter, mixing the signal down to an IF. Thedemodulator is responsible for receive filtering andsampling the wanted signal. Once the signal is sam-pled, it is processed digitally to estimate and removecarrier phase and symbol timing offsets.

The digital modulator• Baseband I/Q modulatorFigure 2 shows a previously successful design of

a high-speed modulator developed by the SatelliteCommunications Research Centre (SCRC)1. The fig-ure shows an oversampling factor of four times persymbol period. The mapper generates in-phase andquadrature (I/Q) components. Each component isfiltered by a digital finite impulse response (FIR)filter implemented using a look-up-table (LUT) in aread-only memory (ROM). The LUT contains pre-computed convolutions of the input sequence withthe filter coefficients. The purpose of filtering is toshape the transmitted pulse (Root Nyquist α = 0.4)to eliminate intersymbol interference (ISI) betweenadjacent symbols. After digital-to-analog conver-sion, the signal is mixed up to an IF.

The problem associated with this implementa-tion is that its performance depends on the accura-cy of the analog quadrature modulator. Any ampli-tude and quadrature phase imbalance results in adegradation in system performance2. This factorbecomes more important as the order of the modu-Figure 1. The communication’s system modem block diagram.

Designing a high-speed modem for

microwave, satellitecommunications

Developing a DSP-based modemfor demanding high data-ratetransmission offers a number of design challenges. But the benefits will be well worth it.

By A. Guidi, P. McIllreeand John Stannard

mixed signal


lation scheme increases. Schemes suchas 8PSK and 16QAM are much moresensitive to quadrature modulatorimbalance than binary phase shift key-ing (BPSK) and quartenary phase shiftkeying (QPSK).

• Digital IF modulatorTo avoid the problems with the quad-

rature modulator mentioned in the pre-vious section, shift the signal from thebaseband digitally and reconstruct thebandpass signal centered on a low IF3.

Because the initial upconversion isperformed in the digital domain, iteliminates problems associated withthe quadrature modulator. The digitalupconversion process is simplified byexploiting a relationship between thelow IF and the sampling rate. Thisrelationship is given by:

fsampling = 4 • flow–IF (1)

As a result, the frequency upconversionsimplifies interleaving in-phase andquadrature components, with inver-sions of the data occurring for everysecond I and Q sample. Also, if theoversampling factor is equal to four, thelow-IF frequency equals the symbolrate. One other advantage of digital IFmodulation is that only one digital-to-analog (D/A) converter is required.Figure 3 gives a proposed implementa-tion of the low-IF modulator4.

• Hardware implementationTo keep the low IF and hence, all

bandpass filtering stages as fixed as pos-sible, the oversampling factor is doubledfor every halving of the symbol rate.Therefore, the lowest symbol rate willresult in the highest oversampling fac-tor. The greater the oversampling factor,the greater the number of lines requiredto address the transmit filter LUT4.

Techniques can be used to reduce thesize and speed of the ROM required.

For example, a field-programmable gatearray (FPGA) can be used to generatethe addresses for the LUT. The LUTsare implemented using EPROM/PROMtechnology, eliminating the extra inter-facing required to support RAM tech-nology. The low-IF modulator and thebaseband I/Q modulator are similar interms of required components.

An I/Q design requires two D/A con-verters, whereas the low-IF designrequires only one. The low-IF designdoes not require a combiner, 90° phasesplitter or additional mixer. Howeverthe low-IF design generally requiresmore memory. This factor is offset bythe continual decline in cost of memorycomponents.

Up/down conversionThe upconverter consists of two

stages: a UHF upconverter to a commonIF, followed by a microwave or satelliteIF converter (see Figure 4). The upcon-verter meets Australia’s tight spuriousemission mask specifications.

Another design feature of theup/down converter minimizes phasenoise so that modem performance is notdegraded. Also, no IF filtering mayintroduce significant amplitude andgroup delay distortion. The choice of acommon UHF frequency for microwaveradio and satellite applications allowssimplification of bandpass filteringdesign for both frequency converters.

The specifications for microwaveradio out-of-band emissions are estab-lished in Australia by the SpectrumManagement Agency (SMA). The SMAstates that the maximum spurious out-side the transmitted channel bandwidthis to be –50 dB measured relative to anunmodulated carrier5. The upconverterdesign aims to meet this figure furtherby 10 dB. The upconverter includes asurface acoustic wave (SAW) filter forclose in reduction of spurious emissions.

Another factor influencing the designand cost is the allowable frequency off-set. CCIR recommendations determinethe maximum frequency offsets allow-able in the design. None of the phase-locked loops (PLLs) present in theup/down converter may introduce sig-nificant phase noise, such that systemperformance (measured in terms of biterror rate and spectrum usage) isdegraded. The up/down converter pro-vides excellent phase-noise performanceby locking all PLLs to a single frequen-cy reference. The stable frequency refer-ence ensures long-term stability andaccuracy of the up/down converter.

The frequency plan of the downcon-verter is identical to the upconverter. Ituses the same UHF interface for satel-lite and microwave radio as the upcon-verter. The downconverter also incorpo-rates automatic gain control (AGC) andautomatic frequency control (AFC).

Digital demodulator• Baseband I/Q demodulator Figure 5 shows the front-end design

of a baseband demodulator applicablefor high-data-rate (Mb/s/sec) communi-cations. The signal is shifted down tonominal baseband by an analog quadra-ture downconverter. The I/Q demodula-tor is subject to the same amplitude andphase imbalance as the baseband I/Qmodulator. The signal plus noise is fil-tered using a filter having a frequencyresponse characteristic that is anapproximation to the Root Nyquistresponse. One such filter is an equalizedlow-pass Butterworth. After filtering,the signal is sampled and the digitaloutputs are processed to remove symboltiming and carrier phase offsets. Thefront end in Figure 5 has been previous-ly used by the SCRC and incorporatedwith the modulator described in theBaseband I/Q modulator section1.

Figure 2. A baseband I/Q modulator. Figure 3. A digital low-IF modulator.

Continued on page 28


Digital IF demodulatorThe front end of the digital low-IF

demodulator is shown in Figure 6. Thedownconversion process in the demodu-lator is the same as that in the modula-tor in that it exploits the same relation-ship between the low IF and the sam-pling rate1. The difference between thetwo is in hardware implementation. Onedifference between the two architecturesshown in Figures 5 and 6 is that, insteadof mixing the signal down to baseband,the signal is mixed down to a low IF.

Selection of a suitable analog-to-digi-tal (A/D) converter to sample the wide-band signal centered on the desired lowIF is important. The A/D must providesufficient bandwidth and signal-to-noise ratio so that performance is notdegraded over the frequency range ofoperation. Another difference betweenthe two architectures shown in Figures5 and 6 is that in Figure 6, the receivefiltering is performed in the digitaldomain after sampling. This hasadvantages because the TX and receivefilters can now be perfectly matched.Therefore, in a noiseless environment,no inter-symbol interference (ISI)would occur between adjacent symbols.Another advantage is that digital FIRfilters have constant group delay.

• Demodulator synchronizationOne of the most important functions

of the demodulator is to perform bothcarrier phase and symbol timing syn-chronization.

• Carrier phase synchronizationThe purpose of carrier phase syn-

chronization is to correct for anyinstantaneous phase offset in thereceived signal. The instantaneousphase offset needs to be estimated torotate the transmitted constellationback to its original position.

A QPSK constellation with a phaseoffset of a few degrees is shown in Figure7. The white points correspond to the

transmitted constellation location, whilethe black points correspond to the signalwith a phase offset. Phase offsets resultfrom differences in the instantaneousphase between quadrature oscillator sig-nals in the up/down converters and carri-er phase offsets induced by the channel.

Phase recovery algorithms are typi-cally implemented as first-order digitalphase-locked loops (DPLLs). The loopbandwidth is set so that the maximumfrequency offset likely to be present canbe tracked out.

• Symbol timing recoveryThe purpose of symbol timing recov-

ery is to adjust the phase of the sam-pling clock so that the signal is sampledat a point corresponding to maximumeye opening. Due to variations in thetransmission channel, the point of max-imum eye opening does not remain con-stant between symbols; therefore, aPLL is required to track this point.Symbol timing can be achieved withfeedback or feedforward schemes. Forhigh-speed applications, feedbackschemes are the most common 6.

With feedback schemes, the output ofa timing detector generates a signal thatpasses through a loop filter. The outputof the filter is a voltage proportional tothe timing error, which adjusts the fre-quency of a voltage-controlled crystaloscillator (VCXO) or numerically con-trolled oscillator (NCO) that samples thereceived signal. The PLL is implement-ed in a hybrid (analog/digital) form. Forfurther information on modem synchro-nization techniques, refer to [3].

Hardware implementationThe high data rates that need to be

supported with the low-IF demodulatorresult in the use of specialized hard-ware architectures to perform DSPfunctions. For data rates in the tens ofMb/sec, standard reduced instructionset computing (RISC) microprocessor-

based DSP devices cannot be usedbecause their maximum throughputand cycle times are too slow. Instead,algorithms are implemented in applica-tion-specific integrated circuits (ASICs)and FPGAs, which are effective in min-imizing product development cycles.

Digital filtering is achieved with FIRASICs having the flexibility to supportdata rates from 5 to 40 MHz. These fil-ters can be configured as interpolators(increase sampling rate) and decima-tors (decrease sampling rate). For thisapplication, the FIR filters are config-ured as decimators to reduce the over-sampling factor to 1 sample/symbol.

Decimating is required because thechosen symbol timing and carrierphase recovery algorithms operateusing only 1 sample/symbol7. The filtersare controlled with a simple, external-state machine implemented within anFPGA. A development system is cur-rently being prototyped and tested. Theprocess of downconverting the signalfrom a low IF to baseband is also car-ried out in the FPGA. The FPGA willoutput two streams (I and Q), whichwill then be filtered using the ASICsdescribed previously.

Figure 8 gives a general block dia-gram for a proposed architecture toachieve carrier phase synchronizationand symbol timing recovery. The dia-gram shows feedback schemes for tim-ing and phase synchronization.Because of the high-speed require-ments, the functions of timing andphase offset estimation are performedin LUTs using ROM. Field applicationof working systems have proven thatthe optimum detector and idea level ofquantization for each signal have beenachieved.

Other system considerations• Forward error correction (FEC)The baseband I/Q modem provided no

Figure 4. An RF upconverter. Figure 5. A baseband I/Q demodulator.


FEC to detect and correct errors withinthe data stream. The low-IF modem willallow for various FEC coding options.Not only does FEC provide coding gain,but it can also reduce spectral regrowthfrom the non-linear characteristic of ahigh-power amplifier (HPA) when oper-ating at or near its saturation region toprovide maximum power efficiency.

Along with the uncoded schemes, thelow-IF modem will provide FEC codingbased on Reed-Solomon codes and

almost constant envelope (ACE) modu-lation coding8,9. Some of these FECschemes will provide great coding gain(5 dB for 16QAM at a BER = 10–8), butwill provide poor performance in termsof spectral regrowth when subject tonon-linearities.

Modulation coding schemes do notprovide coding gain (–0.7 dB for 8PSKat a BER = 10–8 ), but have an excellentresponse when subject to non-lineari-ties. Some schemes will therefore be

suitable for microwave radio applica-tions while others will be favorable foruse in satellite transmission.

For QPSK-, 8PSK- and 16QAM-based systems, the same block-codedReed-Solomon code can be used.These codes only require hard deci-sions from the demodulator and pro-vide the flexibility of a programmablecode rate. Commercially availableReed-Solomon ASICs exist that can

Figure 6. The digital IF demodulator. Figure 7. Phase rotated QSPK constellation.

Continued on page 32


handle as much as 300 Mb/sec. Again, the control of such codecs is

done using an FPGA. ACE schemes aresimple to implement in hardware. Theprecoder and decoder required for ACEschemes are both of low complexity andcan be implemented within an FPGA.

Design of higher data-rate systemsmodels now allow for third-generationapplications to higher data-rate trans-mission to be implemented.

AcknowledgementThis work has been carried out

under an ARC research grant entitled“Versatile Spectrally Efficient DataLinks,” in collaboration with JNSElectronics Pty. (Melbourne).

References[1] Cowley, W.G., Morrison, I.S., and

Lynes, D.C., “Digital Signal ProcessingAlgorithms for a Phase Shift KeyedModem,” ISSPA, Brisbane, Australia,pp. 836 - 841, Aug 1987.

[2] Wojtiuk, J., “Analysis ofFrequency Conversion for M-QAM andM-PSK Modems,” M.Eng Thesis,University of South Australia, to besubmitted 1995.

[3] Miller, M.J., Vucetic, B., andBerry, L., “Satellite Communications,Mobile and Fixed Services” KluwerAcademic Publishers, Massachusetts,1993.

[4] Bolding, G., “Feasibility and CostBenefit Analysis of Low-IF Modulationfor 4MSym/sec. 16QAM/8PSK,”

Figure 8. Architecture for carrier-phase synchronization and symbol-timing synchronizations.

34 iwww.rfdesign.com November 2001

Satellite Communications ResearchCentre, Report, University of SouthAustralia, Feb 1994.

[5] “Microwave Fixed ServicesFrequency Co-ordination,” Dept ofTransport and Communications,Radiocommunications Division,Canberra, RALI : FX3, Oct 1992.

[6] Bolding, G., and Barbulescu, A.,“Performance of a new digital demodu-lator for remote sensing satellites,”Journal of Electrical and ElectronicsEngineering, Australia, Dec 1994.

[7] Cowley, W.G., “SynchronizationAlgorithms for Digital Modems,”ASSPA, Adelaide, Australia, pp. 201 -205, Apr 1989.

[8] Morrison, I.S., “ACE-QPSK: ANew Method of Coding QPSK for theNonlinear Transmitter,” Proc..IEEEInt. Conf. on Networks / Int. Conf. onInformation Engineering, vol. 2,Singapore, Sept 1993.

[9] Morrison, I.S., “ACE-8PSK:Band-limited 8PSK with an AlmostConstant Envelope,” submitted to The10th International Conference on

Digital Satellite Communications,Brighton, UK, May 1995.

About the authorJohn Stannard was born and educated in Melbourne, Australia. He obtained his

engineering qualifications from the Royal Melbourne Institute of Technology (RMIT),followed by extensive experience in the TV broadcast industry. His overseas experi-ence involved study at Ryerson Institute Toronto while specializing in low-light imageintensification for medical electronics with Westinghouse, (special products division)Baltimore as east coast service manager for the United States and Canada. He estab-lished JNS Electronic Industries in Australia, devoting 25 years to design and devel-opment of broadcast and telecommunications equipment with emphasis on RF trans-mission systems and the commercialization of spectrum-efficient microwave technolo-gy, the latter in conjunction with the University of South Australia. He is a commer-cial pilot with international experience. Stannard is a member of the IREE and IEA asa companion awarded for his endeavors to the telecommunications industry. He canbe contacted at i61 3 9439 8257 (Australia), 61 3 9439 1000 (fax) or e-mail:[email protected]

Andrew Guidi and Phil McIllree were design and development engineers with theInstitute for Telecommunications Research at the University of South Australia at thetime this work was performed.

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RF Mixed Signal Guidi-McIllree-Stannard