Rashid Rashidzadeh - University of Windsor€¦ · · 2007-02-16Digital Tester Architecture For a System-On-Chip Implementation A Built-in Self-Test for System-on-Chip Rashid Rashidzadeh

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Digital Tester Architecture For a System-On-Chip Implementation

A Built-in Self-Test for System-on-Chip

Rashid Rashidzadeh

University of Windsor

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Tester Architecture For a System-On-Chip Implementation


Objective : Design an intellectual property (IP) core which enables low speed Automatic Test Equipment (ATE) to perform test for aSystem-on- Chip (SoC)

Motive :Fast SoC market growingToday SoC accounts for about 20% Predictions : It will grow to 60% within the next four years.

Cost of testing – ATE:0.5-1.0GHz,1,024 digital pins ATE :price =$1.2M +1,024 x $3,000 =$4.272M

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Typical SOC

What is a SoC?SOC is a complex integrated circuit (IC) that integrates the major functional elements of a complete end-product into a single chip using IP blocks:

* Programmable processor* Controllers* Signal processors* On-chip memory

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Design For Test Methodologies

1- Scan Technique • Partial scan• Full scan• Boundary scan• Scan chain

2- IEEE 1500 Standard for Embedded Core Test• Test Wrapper

3- Build In Self Test ( BIST)

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Gate level stuck at faults

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Inputs

CLK

Out 1

Out 2

Scan Architecture

Sequential depth = 4Combinational width = 6

Non-Scan Sequential Circuit

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Scan Architecture

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Adding Scan Structure

SFF

SFF

SFF

Combinational

logic

PI PO

SCANOUT

SCANINTC or TCK

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Test Vector Generation

Set up the detect path (Controllability)

Pass 0 to observe the fault

Test vector to cover e @ 0In A=1 B=0 Out S=1

There are different CAD Toolsto generate Test Vectors (ATPG)RCIM: Tetramax by Synopsys

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SoC test challenges

1-Deeply Embedded Cores♦Controllability and Observability are limited. ⇒need Test Access Mechanism to transport test from

source to core and from core to sink

2-Protection of Intellectual Property♦ limited core design knowledge by chip integrator⇒need self- contained test without core design knowledge

3-Limited Input/Output Bandwidth♦ Fast data flow rates between cores inside the SoC compared to lower rates between IP cores and the external environment ⇒ need built-in-self-test

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Limited SoC Controllability and Observability

•Limited number of Pins

•Typical gates per pin =2000

•Large portion of chip would be

virtually untestable even if the

chip were completely

combinational untestable

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Build in Self Test ( BIST)

LFSR(Linear Feedback Shift Register )

Random Test Pattern Generator

DUT ( Device Under Test )

MISR (Multiple Input Shift Register)

Result Compression

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Memory Build in Self Test

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Delay Fault

2 4 61

1 3

5

3

10

0

0

2

2

Path P1

P2

P3

At-Speed test should perform to detect all possible delay faults. •Requires mach impedances to reduce transmission line affect•Needs advanced and costly ATE

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♦ Advanced timing specification of the DUT, delay and transient faults ⇒Precision timing and edge placement control for all test channels⇒ Require considerable memory (4M or more ) behind of each test

channel to carry out at_speed test

Challenges of At-Speed Testing

Data Bus WriteEnable

Clk

Timing constraints should be met to have a functioning circuit

Addr. Bus

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Tester IP Core Architecture

Test IP Core

LOW-COST

EXTERNAL

ATE

External Test IP Core Embedded on MEM Socket Die

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6mm

Compression Mass

HighBandwidth

Interface

Die Under Test

Scalable Vector RAM

Tester-on-Chip MEMSFixed Socket

MEMSRemovableSocket

HighBandwidth Interface

External Controller

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MEMS Socket Based Test Scheme



1- Minimizes the transmission line effect problem for high speed SoC testing

2- Lowers the cost of testing significantly by reducing the required performance of the ATE

3- Reduces the packaging cost by detecting faults at the die level and removing faulty dies before the packaging process starts

Roundtrip delay< 4.6 ps

Driver/Receiver for MEMS Based Test Head

Pin Electronic Die Under Test

Vref

+- < 700µ

Advantages of the Proposed Test Scheme

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l In the design of the Tester-on-Chip, one of the critical decisions was how to implement the on-chip timing generators for full flexibility in shaping the output waveform. The timing control circuit of the ToC allows the user to place edges near the beginning or end of the test cycle

l Separate timing generators for stimulus and response edge placement were considered for the ToC

l High speed test management circuit was designed to support at-speed test

ToC Design Consideration

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Write

ResetHiLo

Read

Status 324Addr

Clk

LFSR & MISR

Processing Circuit

Scalable VectorRAM

MUX

24

24

ClkData

WRAM

Enable

Capture

Formatter

Enable

Fail

8 3

Cap_C

lk

E_data

Mask

Control

Type

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Interface

Tester-on-Chip Building Blocks

Timing

Test Channel

Pin Electronics

High SpeedTest Management

Comparison

Driver1-256

External Controller

Error_RAM

PHI

9

USB

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Stimulus Waveforms Generated by ToC

0 1 1 Z 0NRZ

RZ

RZI

RO

ROI

RC

RTIN

Stimulus Data

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BIST For SoC State of the Art

2- Oscillator-Based Test Methodology for analog circuits • Low area overhead • CAD tools can implement this method simply • Can not be applied to all analog circuits(By: B. Kaminska, Opmaxx Inc.)

3- Twisted Counter Test Method for Digital Circuits• Generates test data for digital circuit inside the SoC• Requires an advanced test controller(By: Chakrabarty, K. , Duke University)

1- Coherent Tester/Oscilloscope IC• Covers delay faults and faults associated to interconnects • Considerable area overheadBy: Dr. G. W. Roberts, McGill University

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• Mathematical model of analog faults

• Investigating the potential of adding analog switches and switching capacitors for analog testing

• Developing a circuit for testing interconnects and crosstalk based on modified version of Phase Lock Loop ( Delay Lock Loop)

• Any solution should be integratable with CAD tools

Research Directions

Design an embedded IP tester core optimized for analog testing in a System-on-Chip environment



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• The nature of high speed faults (e.g. transmission line affect, crosstalk,…) is analog

Conclusions

• Growing gap between SoC internal and external speed makes Built-In Self-Test (BIST) a promising solution for testing

Documents

Rashid Rashidzadeh - University of Windsor€¦ · · 2007-02-16Digital Tester Architecture For a System-On-Chip Implementation A Built-in Self-Test for System-on-Chip Rashid Rashidzadeh