Quick Start Guide

Identify RTL Debugger

Quick Start Guide July 2008

Synplicity, Inc. 600 West California Avenue Sunnyvale, CA 94086, USA (U.S.) +1 408 215-6000 direct (U.S.) +1 408 990-0263 fax www.synplicity.com

PrefaceDisclaimer of WarrantySynplicity, Inc. makes no representations or warranties, either expressed or implied, by or with respect to anything in this manual, and shall not be liable for any implied warranties of merchantability or fitness for a particular purpose of for any indirect, special or consequential damages.

Copyright NoticeCopyright 1994-2008 Synplicity, Inc. All Rights Reserved. Synplicity software products contain certain confidential information of Synplicity, Inc. Use of this copyright notice is precautionary and does not imply publication or disclosure. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the prior written permission of Synplicity, Inc. While every precaution has been taken in the preparation of this book, Synplicity, Inc. assumes no responsibility for errors or omissions. This publication and the features described herein are subject to change without notice.

TrademarksSynplicity, the Synplicity logo, Simply Better Results, Amplify, Amplify FPGA, Behavior Extracting Synthesis Technology, Certify, HDL Analyst, Identify, SCOPE, Synplify, Synplify ASIC, and Synplify Pro are registered trademarks of Synplicity, Inc. BEST, IICE, MultiPoint, Physical Analyst, and System Designer are trademarks of Synplicity, Inc. All other names mentioned herein are trademarks or registered trademarks of their respective companies.

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ContentsQuick Start GuideBefore You Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Start the Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Design Flow with the Identify RTL Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Create a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Select Desired Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Configure the IICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Create the Instrumented Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Synthesize and Place and Route the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Open the Identify Project in the Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Set Trigger Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Run Debug Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 View Design Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Communication Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Debugging on a Different Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24


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Quick Start Guide

Before You StartBefore you can start to use the Identify Instrumentor (and the Identify Debugger), the Identify software must be installed and you must have a license to run the software. The Identify RTL Debugger uses a floating license based of the FLEXnet licensing technology. If you dont have a license, you will be prompted to supply one when you attempt to start the Identify Instrumentor. Please see the documents in the doc/licensing subdirectory where you installed the Identify RTL Debugger for licensing/configuration information.

Start the ToolThe Identify Instrumentor (and the Identify Debugger) can be started in the graphical mode, shell mode, or, when run in conjunction with the Synplify, Synplify Pro, Synplify Premier, or Certify synthesis tool, can be launched directly from the synthesis tools user interface.


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Synplicity Synthesis Tool LaunchThe Identify Instrumentor can be launched directly from the Synplify Pro or Synplify Premier graphical user interface or from the Certify graphical user interface in single-chip mode by selecting Run->Identify Instrumentor. Note: For instructions on launching the Identify Instrumentor from the Synplify synthesis tool, see Launching from the Synplify Tool in the Synplicity FPGA Synthesis User Guide. If your project currently does not include an Identify implementation, you are prompted to create one. Click OK.

When you launch the Identify Instrumentor, you are prompted for the location of the Identify Instrumentor executable and the vendor license type. After entering or verifying this information, clicking the OK button in the Launch Identify dialog box Brings up the Identify Instrumentor graphical interface. Automatically imports the project file (*.prj) for the open project in the Synplicity synthesis tool into the Identify Instrumentor tool and opens the project. Automatically compiles the project.

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Graphical ModeTo start the Identify Instrumentor or Identify Debugger in the graphical mode, do any of the following depending on your platform/operating system: In Windows, select Programs->Synplicity->Identify Instrumentor or Programs>Synplicity->Identify Debugger from the start menu or enter the appropriate command at the command prompt: path_to_identify_install_directory/bin/identify_instrumentor path_to_identify_install_directory/bin/identify_debugger In Linux, enter the appropriate command at the command prompt: path_to_identify_install_directory/bin/identify_instrumentor path_to_identify_install_directory/bin/identify_debugger Note that the Identify Debugger can only be run from the Linux (or Windows) operating system and that it is not supported by the Solaris operating system. The Identify Instrumentor or Identify Debugger can also be run with a Tcl startup file. To start the tool with a Tcl script, enter the appropriate command: path_to_identify_install_directory/bin/identify_instrumentor -f fileName.tcl path_to_identify_install_directory/bin/identify_debugger -f fileName.tcl

Shell ModeBoth the Identify Instrumentor and Identify Debugger can be started in a shell mode and controlled by Tcl commands. To start either tool in the shell mode, enter the appropriate command at the command prompt: path_to_identify_install_directory/bin/identify_instrumentor_shell path_to_identify_install_directory/bin/identify_debugger_shell


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Quick Start Guide

Vendor LicensesWhen you initially start the Identify Instrumentor or Identify Debugger, you are prompted to select the license type from the licenses available for your configuration. The following figure shows the Select available license dialog box with a full complement of license types.

To select a license type, highlight (click on) the entry and then click the Select button. To avoid being prompted for the license type each time you start the Identify Instrumentor or Identify Debugger, check the Save as default license type box before clicking the Select button. Note: When you select a vendor-only license, you cannot use another vendors device in your design. After opening the Identify Instrumentor or Identify Debugger, you can change the license type from within the tool by selecting Help->Preferred License Selection from the menu to display the Preferred license selection dialog box and then selecting a new license type as described in the previous paragraph.

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Design Flow with the Identify RTL DebuggerBecause the Identify RTL Debugger produces an instrumented version of your design, using this tool should be considered a pre-processing step in your current design flow. This Quick Start guide assumes that you currently have a working FPGA design flow for a Xilinx, Altera, or Actel device. If not, use a simple design (for example, the tutorial design counter_self) to establish a working flow that effectively moves an HDL design through synthesis, place and route, and programming of the chip. Only after this flow is established should you attempt to debug a design with the Identify RTL Debugger. Before you begin, it is also helpful to note the amount of unused resources available in your original design. The Identify Instrumentor provides an estimate of the additional resources necessary for instrumentation in the target device which can help maximize the debugging visibility. The following figure shows a typical design flow using the Identify RTL Debugger.


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Quick Start Guide

Synthesize

Working HDL

Place and Route

Create a New Project

Open Identify Project in Debugger

Import Project

Set Trigger Condition

Select Instrumentation

Run Debug Hardware

Configure IICE

View Design Data

Create Instrumented Design Identify Instrumentor Identify Debugger

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Figure 1: Identify RTL Debugger Design Flow

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Quick Start Guide

Create a New ProjectYou can import an existing Synplicity project directly into the Identify Instrumentor or you can create a new project from HDL source.

Creating a New Project from an Existing Synplicity ProjectFor Synplicity synthesis tool users, an existing Synplicity project file (*.prj) can be imported into the Identify Instrumentor to automatically create a new Identify project. To import a Synplify, Synplify Pro, Synplify Premier, or Certify (singlechip) project into the Identify Instrumentor, open the project in the corresponding Synplicity Project view and: 1. Right click on the project (Synplify) or implementation (Synplify Pro, Synplify Premier, or Certify) to be imported and select New Identify Implementation from the popup menu. 2. Verify or set the technology and device mapping options as required. Make sure that a Top Level Module is specified on the Verilog tab or that a Top Level Entity is specified on the VHDL tab (see the implementation option descriptions in the Synplicity FPGA Synthesis User Guide or Certify User Guide for more information). Click OK to close the dialog box; a new Identify implementation is added to the project view.

Identify Implementation

Note: Because multiple implementations are not supported in the Synplify synthesis tool, the existing implementation is replaced with the Identify implementation.


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Quick Start Guide

3. Right click on the Identify implementation and select Launch Identify from the popup menu (in Synplify, Synplify Pro, and Synplify Premier, you can also click the Launch Identify Instrumentor toolbar icon). 4. In the Launch Identify dialog box, make sure that the Locate Identify Installation field points to the Identify Instrumentor executable (use the browse button to the right of the field if necessary) and make sure that the proper License Type is selected. 5. Click OK. If prompted to save your changes, click Save. Clicking the OK button (or the Save button): Brings up the Identify Instrumentor graphical interface. Automatically imports the corresponding project file (*.prj) into the Identify Instrumentor tool and opens the project. Automatically compiles the project which allows the Identify Instrumentor to determine all of the potential locations for instrumenting breakpoints and watchpoints.

Creating a New Project from HDL SourceTo create a new project from HDL source using the Identify Instrumentor graphical user interface (GUI): 1. Open the Identify Instrumentor in the GUI. 2. Click the Add Files button to bring up the Add Design Files dialog box. 3. Navigate to the directory containing your HDL design files. All HDL files are listed in the dialog box. 4. Select (highlight) the design file or files to be added to the project and click Open to add the files to the project. Use the Control and Shift keys to add multiple files. 5. The order shown in the list of files is the order in which the files are compiled. Use drag and drop to correct any file-order dependencies. 6. In the Compile Options section of the project window, enter the name of the top-level module or LO entity into the Top level unit field. 7. Click the Compile button, select Actions->Compile from the menu, or click the Compile current project icon to compile your project.

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Note: Alternatively, you can create a TCL script to add the files to your design. For information on scripting and the compile add command, see the reference manual.

Select Desired InstrumentationWhen your design compiles successfully, your design with its possible instrumentation is displayed in the instrumentation window. The hierarchy browser on the left shows the design hierarchy and is used to browse your design. Double clicking any hierarchy symbol takes you to its corresponding code location in the HDL source code display on the right. In the source code display, each potential watchpoint is indicated by a glasses icon prefixing the signal name, and each potential breakpoint is indicated by a circle in the left margin of the source code.Watchpopint

Breakpoint

Figure 2: Potential watchpoints and breakpoints


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Quick Start Guide

WatchpointsA watchpoint is instrumented by clicking the watchpoint icon adjacent to the signal name and selecting Sample Only, Trigger Only, or Sample and Trigger from the pop-up menu. Sample-only signals are sampled by the debug logic. You can view the data from a sample-only signal, but you cannot use the signal to trigger the hardware during runtime. The lenses of the watchpoint icon are blue for sample-only signals. Trigger-only signals are not sampled by the debug logic and have no visibility. These signals are used to create trigger conditions to trigger the debug logic (IICE) during runtime. The lenses of the watchpoint icon are pink for trigger-only signals Sample and trigger signals connect to both the sample logic and trigger logic of the IICE. These signals are visible and can be used to trigger the debug logic. The lenses of the watchpoint icon are green for sample and trigger signals Note: A fourth selection is available with vectored (bus) signals for defining watchpoint types on partial buses; see the User Guide for more information.

BreakpointsBreakpoints are instrumented by clicking on the icon to the left of the breakpoint line. A breakpoint is essentially a control-flow trigger. It is used at runtime to trigger the debug logic based on the flow through case and if/then/ else statements. During debug, a breakpoint triggers the IICE whenever the corresponding branch in the code becomes active.

Resource EstimatesAs you select each watchpoint and breakpoint, the resource usage is updated in the console window. The usage reported is an estimate of the resources on the target device required for the additional instrumentation logic. The LO estimate depends on the number of signals and breakpoints selected for the instrumentation, as well as other IICE settings such as device family and sample depth. Please see the next section, Configure the IICE, for information about these settings.10 Identify RTL Debugger Quick Start Guide, July 2008

Quick Start Guide

Note: The Identify Instrumentor is not aware of the size of the target device and it is possible to add more instrumentation to the design than will fit on the device. Exceeding the device capacity causes errors during synthesis or place and route.

Configure the IICEConfiguring an IICE to match your debugging requirements involves the setting of a series of IICE parameters. The common IICE parameters are set in the project window and apply to all IICE units defined for the currently-active implementation; the IICE parameters unique to each IICE definition in a multi-IICE configuration are interactively set on one of two IICE Configuration dialog box tabs.

Common IICE ParametersThe common IICE parameters for the currently-active instrumentation are set in the project window after a design is successfully compiled. All IICE units in a multi-IICE configuration share these same parameter values. To redisplay the project window, click the project window tab at the bottom of the window. Device Family select the appropriate device technology for your Altera-, Xilinx-, or Actel-based design. Notice that when you change the device family, the report window in the IICE editor updates the area estimate for that device family and that the resources are reported in technologyspecific terms. JTAG Port make sure the JTAG port selection box is set to builtin. This setting configures the IICE to use the built-in JTAG resources of the device. If access to the built-in JTAG port is not available, you must use the soft JTAG scheme which inserts a JTAG controller into the design and connects it to four user-defined pins (see the User Guide for more information about the soft JTAG). Use skew resistant hardware make sure that the Use skew resistant hardware option is not checked; this option is used with designs that have no global clock buffer available for the JTAG clock. For more information, see the User Guide.


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Individual IICE ParametersThe individual parameters for each IICE are defined on the two tabs of the Configure IICE dialog box. To display this dialog box, select Actions->Configure IICE from the menu or click on the Edit IICE settings icon. When setting parameters for an individual IICE in a multi-IICE configuration, use the Current IICE field to specify the target IICE.

IICE Sampler TabThe IICE Sampler tab controls the size and implementation of the IICE sample buffer and defines the sample clock. When setting these parameters: Make sure that the Buffertype field is set to deviceram. This setting ensures that the sample buffer is efficiently built from technology-specific RAM cells. Select the desired depth of the sample buffer. This setting controls the size of the sample trace for each signal. Keep in mind that with Identify, you will be able to set very specific triggers and thus may be able to use a smaller trace than required by a logic analyzer. Changing this field also updates the IICE estimate at the bottom of the IICE editor dialog box. For information on using a logic/behavioral Buffertype or the advanced sampling modes, see the User Guide. The Allow qualified sampling check box, when checked, causes the Identify Instrumentor to build an IICE block that is capable or performing qualified sampling. When qualified sampling is enabled, one data value is sampled each time the trigger condition is true. With qualified sampling, you can follow the operation of the design over a longer period of time (for example, you can observe the addresses in a number of bus cycles by sampling only one value for each bus cycle instead of a full trace). Using qualified sampling includes a slight area and clock-speed penalty.

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The Allow always-armed triggering check box, when checked, saves the sample buffer for the most recent trigger and waits for the next trigger or until interrupted. When always-armed sampling is enabled, a snapshot is taken each time the trigger condition becomes true. With alwaysarmed triggering, you always acquire the data associated with the last trigger condition prior to the interrupt. This mode is helpful when analyzing a design that uses a repeated pattern as a trigger (for example, bus cycles) and then randomly freezes. You can retrieve the data corresponding to the last time the repeated pattern occurred prior to freezing. Using always-armed sampling includes a slight area and clock-speed penalty. The Sample clock determines when signal data is captured by the IICE. The sample clock can be any signal in the design that is a single-bit scalar type. Enter the complete hierarchical path of the signal as the parameter value. Note: You can also specify the sample clock signal by right-clicking on the watchpoint icon (or signal name) and selecting Sample Clock from the popup menu. Care must be taken when selecting a sample clock because signals are sampled on an edge of the clock. For the sample values to be valid, the signals being sampled must be stable when the specified edge of the sample clock occurs. Usually, the sample clock is either the same clock that the sampled signals are synchronous with or a multiple of that clock. The sample clock must use a global clock resource of the chip. Note: If you need help determining the hierarchical path of your clock, try finding it in the HDL source viewer. You may then add and remove it for instrumentation. The full hierarchical path of the signal will be echoed to the TCL command line. Remember that a signal cannot be used as the sample clock if it is instrumented. The Clock edge radio buttons determine if samples are taken on the rising (positive) or falling (negative) edge of the sample clock. The default is the positive edge.


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IICE Controller TabThe IICE Controller tab customizes the trigger logic available for triggering the sample buffer. Select the Complex counter option and set its size to 32 to instrument a 32-bit counter for use with the triggering logic. This setting will enable you to use advanced trigger operations such as counting the number of trigger events or delaying a trigger event by a set amount of clock cycles. The state machine setting can be used to create fully flexible trigger conditions including capturing samples based on sequences of trigger events. See the User Guide for more information on state machine triggering. The Export IICE trigger signal option brings out the IICEs global trigger signal to the top level of your design. This signal can then be used to trigger a logic analyzer or to trigger another IICE. The Allow cross triggering in IICE option, when enabled, allows the current IICE unit to accept a cross-trigger from another IICE unit.

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Create the Instrumented DesignWhen you are satisfied with the instrumentation, generate the new instrumented design by either selecting File->Save Project from the Instrumentor menu bar or clicking on the Save and instrument current project icon on the toolbar. When you generate the new instrumented design: the Identify Instrumentor writes out your identify project file (projectName.bsp) to the specified directory. This project contains the information about the design and the instrumentation that you have applied to that design; the project can be opened and saved by both the Identify Instrumentor and the Identify Debugger. the Identify Instrumentor creates the instrumentation directory named projectName_instr. This directory is created in the same directory as the project file and contains the design database used by the Identify Debugger and the instr_sources subdirectory that holds the newly instrumented sources created by the Identify Instrumentor. Once you have instrumented your design, you will begin the process of implementing the design and then debugging it. Note that any changes to the Identify project, the design files, or the instrumentation can cause the current project to become invalid. Take care not to change the instrumentation or otherwise overwrite the current project. The Identify Debugger takes many precautions to ensure correct sample data, and does not allow debugging of a design that has been changed or the viewing of files that have been modified. These types of changes may require you to re-run synthesis and place and route. The Identify RTL Debugger allows you to create multiple instrumentations for a single design using another target device as well as using different IICE configuration parameters. Also, you can make incremental changes to the instrumentation set during the debug phase and then only run a partial place and route flow which can drastically reduce the debug cycle time. For information on multiple instrumentations and the incremental flow, see the User Guide.


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Synthesize and Place and Route the DesignRepeat Original Design Flow with Instrumented DesignWhen you have successfully created an instrumented design, run the design through the Synplicity synthesis design flow. If you are using scripts to run synthesis, it may be necessary to modify the existing scripts to use the new instrumented sources created in the instr_sources subdirectory. Note: Always synthesize and place and route your instrumented design using all of the original constraints and settings.

Read the Project into Synplify/Synplify ProWhen you launch the Identify Instrumentor from a Synplicity synthesis tool, the project file is automatically updated to describe the resulting Identify directory/file structure for the instrumented design. When you synthesize the design, the additional instrumentation logic is automatically included in the design as displayed in the RTL and technology views. When you run the Identify Instrumentor in stand-alone mode (i.e., when the tool is not launched from a Synplicity synthesis tool), the Identify Instrumentor creates a Tcl script file named synplify.tcl in the instrumentation directory projectName_instr. This file is then imported into the Synplicity synthesis tool (Run->Run Tcl Script) to create the synthesis project file and load the instrumented design into the synthesis tool.

Add JTAG Clock ConstraintsDuring synthesis, it is important that the JTAG clocks added by Identify are properly constrained (the JTAG clock runs at a very slow speed and must not be optimized to the speed of the design clocks). These clock constraints are handled automatically by the Identify Instrumentor by the syn_dics.sdc constraint file from the projectName_instr/instr_sources directory referenced in the project file. Any signal with a name that LO includes identify_clk must be constrained to run at 25MHz (40ns) or less. For the place and route tools, the same precautions must be taken to constrain the JTAG clocks to run at 25MHz (40ns) or less.

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Altera Place and RouteFor most place and route tools, the flow should be unchanged from the original design flow. In the case of Altera Quartus, it may be necessary to add the following two files to the Quartus project directory before you can create the bit file. projectName_instr/instr_sources/{syn_sld_node.v|syn_sld_node.vhd} projectName_instr/instr_sources/syn_sld_node.esf

Note: These files are only required when a design utilizes the Altera built-in JTAG controller as described in this guide. The files are not added to the Quartus project, but are simply copied to the Quartus project directory where they are accessed. Quartus reports an error whenever these files are needed and they are not included in the project directory.

Program the Instrumented Bit File to the Target DeviceWhen all of the required project files are in place, program the instrumented bit file into the targeted device to load the design logic and the required instrumented logic.


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Open the Identify Project in the DebuggerAny project (*.bsp) that has been instrumented by the Identify Instrumentor can be opened in the Identify Debugger. The Identify Debugger appears similar to the Identify Instrumentor except that only instrumented signals and breakpoints are displayed in the Identify Debugger. If the Identify Debugger is being run on a machine that is different from the host where the design was instrumented, see Debugging on a Different Machine on page 24 of this guide.

Set Trigger ConditionSetting the trigger condition involves setting breakpoints and/or watchpoints in the source code window to trigger the IICE when the associated condition occurs.

Setting BreakpointsPotential breakpoints are indicated by a green circle in the margin to the left of the source code. Clicking on a breakpoint activates the breakpoint and changes the color of the circle from green to red.

Setting WatchpointsWatchpoint triggers can be specified on any sampled signal. The watchpoint condition, which is any legal VHDL or Verilog expression that evaluates to a constant, is set through the user interface. To set a simple watchpoint: 1. Click on the signal 2. Select Set trigger expressions from the popup menu to display the Watchpoint Setup dialog box 3. In the First value field, enter a value for the watch expression. LO The setting of the watchpoint trigger is noted by the breakpoint icon next to the watched signal changing from green to red. 4. Click OK

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Multiple Breakpoints and WatchpointsWhen an instrumented design has more than one activated breakpoint, the breakpoint events are ORed together which effectively allows the breakpoints to operate independently only one activated breakpoint must trigger to cause the sampling buffer to acquire its sample. When an instrumented design has more than one activated watchpoint, the watchpoint events are ANDed together which effectively causes the watchpoints to be dependent on each other all activated watchpoint events must occur coincidently to cause the sampling buffer to acquire its sample. When an instrumented design has one or more activated breakpoints and one or more activated watchpoints, the result of the OR of the breakpoint events and the result of the AND of the watchpoint events are ANDed together. The result of this AND operation is called the Master Trigger Signal. This ANDing effectively causes the breakpoints and watchpoints to be dependent on each other one activated breakpoint and all activated watchpoint events must occur coincidently to cause the sampling buffer to acquire its sample.


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Run Debug HardwareThis guide assumes that the Identify Debugger communicates with the instrumentation through the same cable that was originally used to program the device. If another communications methodology is being used, see the Connecting to the Target System chapter in the user guide. Before running the debug hardware, test your communications setup with the com check command. This command: checks the cable connection auto-detects the devices on the JTAG chain auto-detects the device with instrumentation that matches the current project If errors are reported, see Communication Errors on page 22 for possible explanations. After all of the desired breakpoints and/or watchpoints have been activated, the IICE trigger circuits on the FPGA device are then armed and wait for the watchpointed condition to occur. To arm the IICE trigger circuits on the active IICE, click the Arm current IICE for triggering icon. To arm more than one IICE in a multi-IICE configuration, open the project window in the Identify Debugger, check the individual IICE units to be armed, and then click the Run button. Either of these actions downloads the trigger information to the IICE. The IICE now waits for the trigger condition (watchpoint or breakpoint) to occur. When a watchpoint or breakpoint trigger occurs, sampling is stopped (the hardware continues to run), and the sampled data is transferred back to the debugger where it is displayed in yellow adjacent to the sampled signals in the source code. A small arrow is displayed to the left of the breakpoint or watchpoint icon to indicate the condition that was responsible for the trigger (identifying the trigger condition is important when multiple breakpoints or watchpoints are active).

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View Design DataThe sample buffer display can be varied by time. The Cycle display in the middle of the menu bar shows the value zero. This is the point in the sample data buffer where the trigger occurred. By clicking on the up-down arrows on the right, you can increase or decrease the cycle count to show sample buffer values before or after the trigger point. You can change where the trigger point is in the buffer by selecting one of the Early, Middle, or Late buttons and then clicking on the Run button again. The trigger location changes the next time that the IICE triggers.

Early

Middle

Late

Figure 3: Trigger-location selection buttons

Waveform DisplayIn addition to displaying the sampled data for the selected signals, the Identify Debugger can export the sample buffer contents for display in a variety of waveform viewers (GTKWave, Aldec Active-HDL, Novas Debussy).

Select GTKWave PreferenceSelect Options->Debugger preferences from the menu bar. Verify that GTKWave is the selected choice in the Waveform Viewer Preferences dialog box. Note: GTKWave is the freeware waveform viewer that is distributed with the Identify RTL Debugger.

Click Waveform ButtonSelect Window->Waveform or click the icon labeled Open Waveform Display in the Identify Debugger toolbar. A GTKWave waveform display is shown which displays all of the sampled data for each of the sampled signals. Identify adds two signals to this waveform: identify_cycle an integer that shows the position in the sample buffer. A value of 0 indicates the cycle in which the trigger event occurred.


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identify_sampleclock a single-bit signal that shows the edges of the reference clock.

Communication ErrorsThe following are common errors that you may encounter when setting up communications with the Identify Debugger. " ERROR: Communication is stuck at one/zero. Please check the cable connection. The Identify Debugger is unable to communicate with the instrumented device. This error is usually attributed to a cable connection problem. Make sure that the cable is correctly connected between the parallel/ USB port and the JTAG port of the board and verify that the cable type is set correctly in the project editor (select File->Edit Project or use the com cabletype TCL command). Note: IMPORTANT This error is often caused by an incorrect parallel port setting. Please try all choices for the communications port setting using either the command line or the selection box in the Identify Debugger project editor. " ERROR: Cannot find valid instrumented design. This error indicates that the design on the programmable chip is NOT the instrumented version of the design. Verify that the bit file you are programming is actually created from the instrumented sources and that the debug logic (IICE) has not been removed during implementation. Verification can often be done by searching the intermediate place and route files (for example, a Xilinx NCD file) for the word identify. " ERROR: Instrumented design on FPGA differs from design loaded into Identify Debugger. This error indicates that the Identify Debugger cannot find a device in the JTAG chain that has been instrumented by the Identify Instrumentor. In this case, the ID of the instrumentation does not match the ID of the currently loaded project. Please verify that the correct project is loaded for the corresponding bit file. The error occurs when the project is LO re-instrumented without regenerating a bit file. If you have changed the design or its instrumentation, you must create a new bit file before debugging the design.

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" ERROR: No hardware devices were found. Please check the cable connection. This error indicates that no devices are visible in the JTAG identification register chain. The error is usually caused by a bad cable connection or an incorrect cable type setting. " ERROR: The hardware has not seen an active clock edge of the sample clock. This error usually indicates that the Identify hardware is functioning correctly and that the Identify Debugger is able to communicate with the device, but that the sample clock is not being toggled. This error can be caused if the wrong clock is chosen in the Identify Instrumentor. Please verify that the correct sample clock is selected using the iice clock command. Also check that the clock signal is using the global clock resources of the chip. Note: This error often occurs when the clock signal is not assigned correctly to the clock pin on the board. Verify that, during placement, the clock signal (sample clock) is correctly assigned to the chip pin that is connected to the clock oscillator on the board. " ERROR: Hardware driver failure. This error usually indicates that the correct port driver is not installed on the debug system. Please see the release notes for help installing the port driver.

Clock SkewWhen the data returned from the Identify Debugger appears incorrect or does not properly relate to the given trigger condition, there may be an issue with clock skew on the JTAG clock. Make sure that the identify_clk signal is using the global clock resources on the chip. If there is no clock buffer available, you may have the Identify Instrumentor build skew-resistant hardware. Please see the user guide for more information on skew-free hardware.


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Debug ModeIf you are experiencing a communication error that is not listed above or if you have not been able to resolve the error, contact [email protected]. If may be helpful to run the Identify Debugger in debug mode as outlined below: 1. If open, close the Debugger. 2. Right-click the Identify Debugger shortcut on the desktop and select Properties from the popup menu to display the Properties dialog box. 3. Append the -debug flag to the path to the executable in the target field. 4. Restart the Identify Debugger and reopen the project. 5. Enter the following two commands at the command prompt in the Console window: chain clear com check 6. Make a copy of the log file and send it with any other important details about your particular setup/flow as well as the Identify project file (*.bsp) to [email protected].

Debugging on a Different MachineIt is not unusual for the instrumentation phase and the debugging phase to be performed on different machines. For example, the debug machine is often located in a hardware lab. When a different machine is used for debugging, you must copy both the Identify project file (projectName.bsp) and the instrumentation directory (projectName_instr) to the lab machine. Because the Identify RTL Debugger allows you to debug your design in the HDL, the Identify Debugger must have access to the original source files. Depending on the type of your network, the Identify Debugger may be able to access the original sources files directly from the lab machine. If this is not possible or if the two computers are not networked, you must also transfer the original sources to the debug machine. If the Identify Debugger cannot LO locate the original source files, it will open the project, but an error will be generated for each missing file, and the corresponding source code will not be visible in the source viewer.

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Copying the source files to the debug machine can be done in two ways: Identify can automatically copy the original source files into the instrumentation directory so that when you copy the instrumentation directory (projectName_instr) to the lab machine, the original sources will be included. The Identify Debugger automatically looks in this directory for any missing source files. This preference can be set before instrumentation by selecting Options->Instrumentation preference and making sure that Save original source in instrumentation directory is checked. The original source files can be manually copied to the lab machine or may already exist in a different location on this machine. In this case, it may be necessary to help Identify find the design files using the searchpath command. Simply call this command from the command line before loading the Identify project file (*.bsp). The argument is a semi-colonseparated list of directories in which to find the original source files. searchpath {d:/temp;c:/Documents and Settings/me/my_design/} The Identify Debugger will only display files that match the CRC taken at the time of instrumentation. Note: If there are security issues with having the original source files on the lab machine, the Identify Instrumentor can password-protect the original sources for use with the Identify Debugger (for information on file encryption, see the User Guide).


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