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QuartusIIDesignFlow:BasicStepsSummary
1.RequiredFiles
$ pwd /Users/talarico/VTut $ ls -1 light.csv light.v light_tb.v
# File: light.csv (comma separated values) # Pin Assignments To, Direction, Location x1, input, PIN_AB28 x2, input, PIN_AC28 f, output, PIN_E2
/* File: light.v Simple Tutorial to demonstrate the Verilog based design flow with Altera/Modelsim. The code implements a 2-input exor gate */ module light(x1,x2,f); input x1,x2; output f; assign f = (x1 & ~x2) | (~x1 & x2); endmodule
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// File: light_tb.v // Test Bench for the light module // author: Claudio Talarico `timescale 1ns / 1ns module light_tb; // inputs to device under test (DUT – i.e. RTL Hardware) reg ain; reg bin; //outputs from DUT wire cout; // instantiate the DUT light dut( .x1( ain ), .x2( bin ), .f( cout ) ); // output the simulation in graphical format initial begin $dumpfile("light.vcd"); $dumpvars(0, dut); end //initialize inputs to DUT initial begin ain = 0; bin = 0; end // generate ain values (ain test vectors) always begin # 20 ain = ~ain; end // generate bin values (bin test vectors) always begin # 40 bin = ~bin; end // output the simulation in textual format initial begin $monitor("At time %t, X1 is = %b, X2 is %b, F is %b", $time, ain, bin, cout); end
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// stop the simulation from running forever initial begin # 200 $stop; end endmodule 2.CreateProject
Aprojectconsistsof:
*ProjectNameandDirectory*Nameofthetop-leveldesignmodule*ProjectFilesandLibraries*TargetDeviceFamilyandDevice*EDAToolSetting
File>NewProjectWizard
Step1.
Lowercaset
UppercaseT
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Step2.
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Step3.
Tomodifyaprojectuse:Project>Add/RemoveFilesinProject
ToeditanewVerilogFilewithQuartusTextEditoruse:File>New>(DesignFiles>VerilogFile)
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Step4.
Family:CycloneIVEDevice:EP4CE115F29C7
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TomodifytheFPGAfamilyorthespecificdeviceuse:Assignments>Device
Step5.
TomodifytheEDASettinguse:Assignments>Settings
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Step6.
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3.FilesandDirectoriesuptothispoint
$ ls -1p VTut.qpf db/ incremental_db/ light.cvs light.qsf light.v light_nativelink_simulation.rpt light_tb.v output_files/ simulation/ $cat VTut.qpf QUARTUS_VERSION="17.0"DATE="14:01:19August15,2017"#RevisionsPROJECT_REVISION="light" $ cat light.qsf set_global_assignment-nameFAMILY"CycloneIVE"set_global_assignment-nameDEVICEEP4CE115F29C7set_global_assignment-nameTOP_LEVEL_ENTITYlightset_global_assignment-nameORIGINAL_QUARTUS_VERSION17.0.2set_global_assignment-namePROJECT_CREATION_TIME_DATE"14:01:19AUGUST15,2017"set_global_assignment-nameLAST_QUARTUS_VERSION"17.0.2LiteEdition"
Quartusprojectfile
Quartussettingsfile
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set_global_assignment-nameVERILOG_FILElight_tb.vset_global_assignment-nameVERILOG_FILElight.vset_global_assignment-namePROJECT_OUTPUT_DIRECTORYoutput_filesset_global_assignment-nameMIN_CORE_JUNCTION_TEMP0set_global_assignment-nameMAX_CORE_JUNCTION_TEMP85set_global_assignment-nameERROR_CHECK_FREQUENCY_DIVISOR1set_global_assignment-nameNOMINAL_CORE_SUPPLY_VOLTAGE1.2Vset_global_assignment-nameEDA_SIMULATION_TOOL"ModelSim-Altera(Verilog)"set_global_assignment-nameEDA_TIME_SCALE"1ps"-section_ideda_simulationset_global_assignment-nameEDA_OUTPUT_DATA_FORMAT"VERILOGHDL"-section_ideda_simulationeda_simulation
4.StartCompilingtheDesign
Processing>AnalyzeCurrentFile>Start>Analysis&Elaboration
MakesuretoverifyallInfo/Warnings/Errors
Tools>NetlistViewers>RTLviewer
Checksyntax&translateHDLintogenericBooleanequations
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Processing>AnalyzeCurrentFile>Start>Analysis&Synthesis
Tools>NetlistViewers>TechnologyMapViewer(PostMapping)
SynthesizeHDLintotargetTechnology
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4.PinAssignments
Moreoftenthannot,thePinPlannerhasissuesloadingautomaticallythepinoutassignmentssavedinlight.csv.Puttheassignmentsinatextfilelight.txtandloaditmanuallyusing:
Assignments>ImportAssignments(filenamelight.txt)
$ cat light.txt # Pin Assignments To, Direction, Location x1, input, PIN_AB28 x2, input, PIN_AC28 f, output, PIN_E21
OntheDE2-115board,theinputPIN_AB28isphysicallymappedwiththeswitchSW[0]OntheDE2-115board,theinputPIN_AC28isphysicallymappedwiththeswitchSW[1]OntheDE2-115board,theoutputPIN_E21inmappedwiththegreenlightemittingdiodeLEDG[0]
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6.ContinueCompilingtheDesign
Processing>Start>StartFitter
Tools>NetlistViewers>TechnologyMapViewer(PostFitting)
Place&Route
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7.Simulation
Step1.
StartModelsim.Thepathtotheexecutableshouldbelocatedtosomethingsimilarto:C:/intelFPGA_lite/17.0/modelsim_ase/win32aloem/
Forconveniencecreateashortcuttoit:
Step2.
File>New>ProjectProjectname:VTutSimProjectLocation:Z:/Users/talarico/VTut/simulation/modelsim
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Alternatively,1)ignorethepopupwindow(i.e.,hitclose),2)switchfromtheLibraryTabtotheProjectTaband3)select:Project>Addtoproject>ExistingFile:Z/Users/talarico/VTut/light.vhdZ:/Users/talarico/VTut/light_tb.vhd
Ifthefilesarenotreadyandyouneedtocreatethemfromscratchuse:Project>Addtoproject>NewFile.
Step3.
Compile>compileall
Step4.
Incaseyoudonotseethetwocompiledfilesundertheworklibrary,removetheworklibrary.The
worklibrarywillberegeneratedwiththecorrectinfo!
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Simulate>StartSimulation+work+light+light_tb
vsim>viewwave
vsim>addwavesim:/light_tb/*
vsim>run–all
Tostopthesimulation,youcanuse:
Simulate>break
Thesimulationrunsforever!!!
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Abetterapproachistoautomaticallystopthesimulationbyusinga$stopstatementinthetestbenchcode.
Afewotherusefulcommandstorememberare:
vsim>restart–forcevsim>run–allvsim>wavezoomoutvsim>wavezoomfull
8.FinishCompilingtheDesign
Processing>Start>Assembler
sof=SRAMobjectfilejdi=JTAGDebuggingInformation
9.ViewReports
Makesuretoreadcarefullythereportsgeneratedateachstepofthedesignprocess.ThereportscanbeaccessedthroughtheQuartus’workspacewindowordirectlyintheoutput_filesfolder.
GeneratingProgrammingfiles(light.sofandlight.jdi)
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10.ProgrammingandConfiguringtheFPGA
BeforeProgrammingtheFPGAmakesuretosettheboardinRUNmode(JTAGmode).
Tools>Programmer
Edit>AddFile(Z:/Users/talarico/VTut/output_files/light.sof)
ThehardwareSetupmustbeUSB-Blaster[USB-0]
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11.TestingtheCircuitontheDevelopmentBoard
