Presenter: Hsiang-Hao Liang2014/09/26

National Sun Yat-sen University

Embedded System Laboratory

Progress report

2014/09/26

Last midweek, I had a Final Summer Training Course online exam and the Course End.

Clerical work ： professor personal website update. Call History check

Read MDK-3D EVB High Performance Soc development platform training materials chapter 2 、 chapter 5.1. Codewarrior-compile the code AXD-simulation the code Multi_Ice-connect MDK-3D EVB and PC RVDS-put the .axf on MDK-3D EVB

Current Progress

2

Course categories ： Linux Introduction

• commands teaching• linux os recognition

Matlab 、 System C• Tool environment usage 、 syntax and testbench

teaching HDL_verilog

• Verilog syntax and how to write the testbench teaching• RTL simulation-modelsim usage• Consider three level-behavior 、 gate 、 structural level

Design Compiler• Synopsys design vision tool usage• Synthesis Verilog code 、 report timing and Area

Summer Training Course(SOC DESIGN FLOW & TOOLS LABORATORY)

3

Testing• Setting up Design Constraints• Create Test Protocol-Set Scan Configuration• TetraMax Usage-automatic Test Pattern Generator(ATPG)

Memory Compiler• GCD substitution ： Register -> SRAM(2R1W)

Full custom(bottom-up)• Custom-IC design Tool teaching• schematic/symbol->layout• DRC(Design rule check)• LVS(Layout V.S. Schematic )• PEX( 進行寄生萃取 )

Summer Training Course(SOC DESIGN FLOW & TOOLS LABORATORY) (.cont)

4

We already finish to transfer the environment form RVDS to DS-5,and test the LCD and IDCT program on MDK-3D EVB. Dstream setting and connect to MDK-3D EVB and PC Write the script file(.ds) and generate the .axf file DS-5-put the program Use Debug Configurations setting and execute

Select Target-ARM processor USB connection Download-the executing file name.axf Debugger-Memory mapping file name.ds

New ARM-Development Tool：DS-5

5

Finish reading MDK-3D EVB High Performance SoC development platform training materials chapter5.2

Edit the DS-5 Experiment flow ： 1. 實驗目的 2.DS-5 環境說明 3. 實驗步驟

Trace the testbench and Consider the ARM10 architecture by Verdi Tool

Next Progress

6