Exercise 2: Dynamic Operation of a JK Flip-Flop - Lab … FLIP-FLOP Digital Logic Fundamentals Exercise 2: Dynamic Operation of a JK Flip-Flop ... CLOCK, OPEN COLLECTOR, and JK FLIP-FLOP

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208 FACET by Lab-Volt

JK FLIP-FLOP Digital Logic Fundamentals

Exercise 2: Dynamic Operation of a JK Flip-Flop

EXERCISE OBJECTIVE

your results by comparing the input and output logic states.

EXERCISE DISCUSSION

50 kHz clock signal is used.

The Q and Q

However, if the PR or CLR inputs are logic 0, the toggle action of the outputs with the clock signal is

overridden, and the outputs are held in the set or reset state.

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FACET by Lab-Volt 209

Digital Logic Fundamentals JK FLIP-FLOP

Q outputs will

a.

b.

This timing diagram shows the relationship between the CLK signal and the Q and Q output signals.

Q and Q toggle (change state) at every negative edge of the clock signal.

Because Q and Q are complementary, Q is logic 1 when Q is logic 0 and vice versa.

The Q and Q signals have one cycle for every two clock cycles.

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The Q and Q frequencies are each half of the CLK frequency because they change logic states only on

the negative edge of CLK.

During the positive edge of CLK, Q and Q do not change logic states.

If the frequency of the CLK signal is 50 kHz, the frequency of the Q and Q outputs is

c. 50 kHz.

d. 25 kHz.

complementary.

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(negative edge).

a. inverted and connected to the K input.

b. always maintained at logic 1.

after every negative edge of the clock signal, and the Q output equals the complement of J.

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If the logic state of the J input changes and then returns, between negative clock transitions, to its original

logic state, the outputs do not change.

When the PR or CLR inputs are logic 0, the outputs are held in a set or reset condition.

shown?

c. logic 1

d. logic 0

PROCEDURE

Locate the INPUT SIGNALS, CLOCK, and JK FLIP-FLOP circuit blocks.

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Connect A at the INPUT SIGNALS circuit block to A (J input) at the JK FLIP-FLOP circuit

block.

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Set toggle switch A in the HIGH position to put a logic 1 at the J and K inputs.

block: there are 50,000 negative edge clock signals every second.

With the J and K inputs each set to logic 1, the

a.

b.

The Q and Q

logic states

a. at every negative edge of the clock signal.

b. only when the J and K inputs change to

logic 0.

Connect the oscilloscope channel 1 probe to the CLK input, and connect the channel 2

Connect the probe ground clips to a ground

terminal on the circuit board.

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Adjust and synchronize the oscilloscope to observe the CLK signal on channel 1 and the Q

output on channel 2.

When the CLK signal changes from logic 0 (0 Vdc) to logic 1 (positive transition), the logic state

of the Q output

a. does not change.

b. changes.

When the CLK signal changes from logic 1 (about 5 Vdc) to logic 0 (negative transition), the

logic state of the Q output

a. does not change.

b. changes.

For every two cycles of the clock signal, there are how many cycles of the Q output signal?

a. 1

b. 2

c. 3

On the oscilloscope screen, measure the period (time) of one cycle of the Q output signal,

which is shown on channel 2. Enter your answer in microseconds.

Period of Q output signal (T) = s (Recall Value 1)

Calculate the frequency (f) of the Q output signal by using your measured period of Q

(T = s [Step 10, Recall Value 1]).

f = 1000 x (1/T) = kHz (Recall Value 2)

Your calculated frequency (f = kHz [Step 11, Recall Value 2]) of the Q output signal

is approximately

a. two times the CLK frequency of 50 kHz.

b. half of the CLK frequency of 50 kHz.

Connect the channel 1 oscilloscope probe to the Q output, and connect the channel 2 probe

to the Q output.

Observe the Q and Q outputs on the oscilloscope screen.

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Are Q and Q in phase or out of phase?

a. in phase

b. out of phase

The Q and Q output signals have

a. the same frequency.

b. different frequencies.

PRESET).

Q

a. yes

b. no

Remove the two-post connector from PRESET.

CLEAR).

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Q

a. yes

b. no

Locate the INPUT SIGNALS, CLOCK, OPEN COLLECTOR, and JK FLIP-FLOP circuit blocks.

Connect A at the INPUT SIGNALS circuit block to A (J input) at the JK FLIP-FLOP circuit

block.

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Connect input J to the B input at the OPEN COLLECTOR circuit block, and connect the output of

With these connections, the J and K inputs will always be complementary.

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Set toggle switch A in the HIGH position.

a.

b.

The Q and Q

logic states at

a. every negative edge of the clock signal.

b. a negative edge of the clock signal only

when the J input changes.

Connect the oscilloscope channel 1 probe to the CLK input, and connect the channel 2

Connect the probe ground clips to a ground terminal on the circuit board.

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Adjust and synchronize the oscilloscope to observe the CLK signal on channel 1 and the Q

output on channel 2.

When the CLK signal changes from logic 1 to logic 0 (negative transition), the logic state of

the Q output

a. does not change.

b. changes.

While observing the logic states of the J input on channel 1 and the Q output on channel 2,

change the J input to logic 0 and then back to logic 1 several times. Do this by moving toggle

switch A at the INPUT SIGNALS circuit block from HIGH to LOW and back to HIGH several

times.

The Q output changes to equal the

a. logic state of the J input.

b. complement of the J input.

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PRESET).

While observing the logic states of the J input on channel 1 and the Q output on channel 2,

change the J input to logic 0 and then back to logic 1 several times. Do this by moving toggle

switch A at the INPUT SIGNALS circuit block from HIGH to LOW and back to HIGH several

times.

a. yes

b. no

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CONCLUSION

•

•

change state after every negative clock edge.

• When the PR and CLR inputs are logic 1 and the J input is inverted and connected to the K input,

negative clock edge.

•

respectively.

REVIEW QUESTIONS

1.

a.

b.

c.

d.

2.

a. equals the J input after a negative clock edge.

b. is the complement of the J input after a negative clock edge.

c. changes state after every negative clock edge.

d. equals the logic state of the clock signal.

3.

a. 200 kHz.

b. 50 kHz.

c. 25 kHz.

d. 150 kHz.

4.

a.

b.

c.

d.

5.

a. equals the J input after a negative clock edge.

b. is the complement of the J input after a negative clock edge.

c. changes state after every negative clock edge.

d. equals the logic state of the clock signal.

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Exercise 2: Dynamic Operation of a JK Flip-Flop - Lab … FLIP-FLOP Digital Logic Fundamentals Exercise 2: Dynamic Operation of a JK Flip-Flop ... CLOCK, OPEN COLLECTOR, and JK FLIP-FLOP