VMWARE BASICS

BYDUDDALA RAJANBABU

Hypervisor:

A hypervisor or virtual machine monitor (VMM) is a piece of computer software, firmware or hardware that creates and runs virtual machines. A computer on which ahypervisor is running one or more virtual machines is defined as a host machine. Each virtual machine is called a guest machine.

CLUSTER:

A cluster is  a  group  of  hosts.  When  a  host  is  added  to a cluster,  the  host's  resources  become  part  of the cluster's resources.  The cluster manages  the  resources of  all  hosts  within  it. Clusters enable  the  vSphere  High Availability  (HA)  and  vSphere  Distributed  Resource Scheduler (DRS) solutions.

REGULAR 16BIT SQRT CSLA

DELAY AND AREA EVALUATION OF THE BASIC ADDER BLOCKS The AND, OR, and Inverter (AOI) implementation of an XOR gate.

The gates between the dotted lines are performing the operations in parallel and the numeric representation of each gate indicates the delay contributed by that gate.

AREA EVALUATION METHODOLOGY OF REGULAR 16-b SQRT CSLAGate count=57(HA+FA+MUX)FA=39(3*13)HA=6(1*6)MUX=12(3*4)

PROBLEMS IN EXISTING SYSTEM

The problem in CSLA design is the number of full adders are increased then the circuit complexity also increases.

The number of full adder cells are more thereby power consumption of the design also increases

SOLUTION OF THE PROBLEM The parallel RCA with Cin=1 is replaced with Binary-Excess 1 converter( BEC).    

                                  

                                                                  

                                                                   

                                                                                                                                                               four-bit BEC

Modified CLSABasic function of CLSA is obtained by using the 4-bit BEC together with the mux.

PROPOSED SYSTEM(16-b CLSA)

In this system we use the BEC to reduce the RCA circuitsHere based on the carry input the MUX will be select corresponding inputIn this design we give the MUX inputs are RCA output and BEC output Compare to regular design the area of the design is less

Contd…

AREA EVALUATION METHODOLOGY OF MODIFIED 16-b SQRT CSLA

GATE COUNT= 41(HA+FA+MUX+BEC) (13+6+12+10)

COMPARISIONGROUP REGULAR MODIFIED

GROUP 2 57 43

GROUP 3 84 61

GROUP 4 117 84

GROUP 5 147 107

RTL SCHEMATIC

Simulation Result  Carry select adder existing system

Simulation Result  Carry select adder proposed system For 16 bit

SynthesisResult

TOOL USEDProgramming language: VERILOG HDL

Tool : Xilinx ISE (10.1)

ADVANTAGESLow power consumptionLess area (less complexity)More speed compare regular CSLA

APPLICATIONSArithmetic logic unitsHigh Speed multiplicationsAdvanced microprocessor designDigital signal process

CONCLUSION  A simple approach is proposed in this paper to reduce the area and power

of SQRT CSLA architecture. The reduced number of gates of this work offers

the great advantage in the reduction of area and also the power. The modified

CSLA architecture is therefore, low area, low power, simple and efficient for

VLSI hardware implementation.

REFERENCES

[1] B. Ramkumar, Harish M Kittur “Low power and Area efficient carry select adder,”IEEE Trans,Vol.20,Feb 2012.

[2] T. Y. Ceiang and M. J. Hsiao, “Carry-select adder using single ripple carry adder,” Electron. Lett., vol. 34, no. 22, pp. 2101–2103, Oct. 1998.

[3] Y. Kim and L.-S. Kim, “64-bit carry-select adder with reduced area,” Electron. Lett., vol. 37, no. 10, pp. 614–615, May 2001.

[4] J. M. Rabaey, Digtal Integrated Circuits—A Design Perspective.Upper Saddle River, NJ: Prentice-Hall, 2001.

[5] Samir Palnitkar, “Verilog Hdl: A Guide to Digital Design and Synthesis”2005,2nd Edition.