ppt trailokya nath.pptx

7/29/2019 ppt trailokya nath.pptx

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Presented By

TRAILOKYA NATH SASAMAL


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OUTLINE

. Educational background

. A glimpse of the research carried out during MTECH programme

. Area of interest during PHD

. Teaching subjects

. Long term goals


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EDUCATION

Indian Institute Technology,BHU,Varanasi,India

Master of Technology (M.Tech), CGPA: 8.4/10 (Honours)

Specialization DTI (Digital Techniques & Instrumentation), July 2011.

Krupajala Engineering College, Bhubaneswar, B.P.U.T, Orissa, India

Bachelor of Engineering (B.Tech), Aggregate: 79.4% (Honours)

Electronics & Telecommunication, June 07.AWARDS:

All India Rank 520, Percentile score 98.7 in Graduate Aptitude Test in Engineering(GATE), 2009.

Awarded MHRD scholarship in M.TECH(2009-2011) IIT,BHU

Awarded merit scholarship in B.Tech for being in top 3% students of the college.


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WORK EXPERIENCE

Currently working as Asst.Prof in Electronics & Comm. Dept. at NIT kurukshetra,Haryana

since June 2012.

Worked as Asst.Prof in Electronics & Comm. Dept. at Mewar University,

Chittorgarh during June 2011 to June 2012.

Conducted Lab sessions of Fault tolerance Design course (1st year M.Tech) under

the guidance of Prof. Anand Mohan, IIT,BHU, Summer 2009-10.

Conducted Lab sessions of Embedded System Design course (2nd year M.Tech) under the

guidance of Prof. Anand Mohan, IIT,BHU, Winter 2010-11.

Worked as a Visiting Faculty at IETE, Varanasi during February '11 to May '11.


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A glimpse of the research carried outduring MTECH programme


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Fault Tolerant Design & its Necessity:

Fault Tolerant Design System Design Incorporating

Fault Tolerance Attributes for Predefined Set of Faults

Ability to Perform Correctly in Presence of Faults

Redundancy

Reconfiguration

Self-repair Combination of the Above

Necessity of Fault Tolerant Design:

High Availability

Maintenance Postponement / Long Life Systems

Critical Systems


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Triple Modular Redundancy(TMR )

Triplicated TMR, Majority Voting

Truth Table and Schematic

of 1-Bit Majority Voter


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Fault Diagnosis of Comparator Module &Global structure of the proposed scheme


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FAULT CONSIDERED

Single event effects

Single Event Transient(SET)

Single Event Upset(SEU)

Stuck _at Faults single event may cause one or more voltagespulses (i.e. glitches) to propagate through the

circuit, referred to as a Single Event Transient

SET latched in asequential logic unit

considered an SEU


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Single Event Effects

persists until the configuration memory is refreshed by scrubbing

Failure mode is the flipping of an

SRAM cell in the configuration memory.

Causes an error in the logic function

cosmic ray showers

aviation, nuclear research and space

applications

mostly neutrons


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Single Event Upsets(SEU) in Aircraft

Avionics

Number of neutrons that pass through

each square centimeter of surface every

second (the neutron flux)

cumulative number of memory upsets

after a given number of hours in the air.

Data were taken from a research paper by Taber and Normand (1993), and published in the IEEE Transactions on Nuclear Science,

vol. 40, No. 2, pp 120.


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Digital designs synthesized in SRAM-based FPGAs

are sensitive to upsets in the FPGA customization

cells.

Design

clk

E1

E2

E1

E3

E2

E3

Synthesis

Customization bits

10101011110001101010

M M M M

Upset = bit-flip

10101011100001101010

clk

E1

E2

E1

E3

E2

E3fault


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Fault injection

validation technique of the

Dependability of Fault Tolerant SystemsFault injection techniques classified in three main categories:

.Hardware implemented fault injection

. Software implemented fault injection

. Simulated fault injection

By loading an incorrect partial bitstream to the FPGA

First method directly modifies a correct partial bitstream

second method modifies the source VHDL file then

synthesized to provide a faulty bitstream.

change the model by adding saboteurs or using

mutants of the model components


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Fault types implemented in the saboteur

Fault type Expression for saboteur output

Stuck-at 0 0

Stuck-at 1 1

Bit-flip Not(I)

Open-line Z (high impedance)


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Mutants:

A component which replaces another component. While inactive, it works like the original

component, but when activated, it behaves like the component in presence of faults. It is

relatively easy to implement this replacement technique by using the VHDL configuration

mechanism .

Fault name Code modification

Stuck-then Replacement of the condition by true

Stuck-else Replacement of the condition by false

Assignment control Disturbing an assignment operation

Dead process Elimination of the sensitivity list of a

process

Fault models by modifying syntactical units in behavioral Descriptions


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Bitstream Modification

FPGA Editor incorporating difference based partial reconfiguration


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Design of Fault Insertion Block in VHDL

Flow chart of Transient faults

insertion processPercentage of time a fault is inserted in

the system per the No. of bits matched


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Area of interest during PHD


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Environment subject to high radiation, Particles cause

portions of the reprogrammable circuitry to change states.

A survivable system is one that continues to perform identified set o

critical functions under operationally threatening conditions.

Survivable systems differ from fault tolerant system in respect ofcontinuance of critical functionality.

cosmic radiations, lightening, global system faults

like power supply and clock failures etc.

systems are being implemented on (FPGAs) due to hardware

reconfigurability and low implementation cost.


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SURVIVABLE DESIGN

System Design Incorporating Survivability

Attributes for

Survive What?

Hardware/software faults

Man-made accidents

Malicious cyber attacks

Natural disasters

capability of a system to complete its

missions in a timely manner, in the

face of adverse conditions


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Survivability

Value

time


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Teaching subjects

Vhdl modeling

Microprocessor


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Long term goals

Contribute whole life in the field of research


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Documents

ppt trailokya nath.pptx