Embed Size (px)
Citation preview
284498 280'8369 Serial HnpuitlOetput Conitroilerr
Product Specification
March 1981
Features Two independent full-duplex channels, with separate control and status lines for modems or other devices.
Data rates of 0 to 5OOK blts/second in the xl clock mode with a 2.5 MHz clock (2-80 SIO), or 0 to 800K bitsfsecond wlth a 4.0 MHz clock (Z-80A SIO).
Asynchronous protocols: everything necessary for complete messaqes in 5, 6, 7 or 8 bits/character. Includes variable stop bits and several clock-rate multipliers; break generation and detection; panty; overrun and framing error detection.
Synchronous ;rotocols: everything necessary for complete bit- or byte-oriented tz messages in 5. 6, 7 or 8 bits/character, C
including 1BE.I Bisync, SDLC, HDLC, CCITT-X.25 ar.d others. Automatic CRC qeneratiodckecking, sync character and zero insertion deletion, abort genera- tioddetectior. 2nd flag insertion.
6 Receiver data :egisters quadruply buffered, transmitter rec:sters doubly buffered.
Iiighly sophisrlcated and flexible daisy- chain interruc: vectoring for interrupts without exterrsi ioglc.
bit-or~ented, and e r io rms all of the iunctions traditionally doce by UARTs, USARTs and synchronous cormunication controllers com- blned, plus adci:ional functions traditionally performed by the CPU. Moreover, it does this on two fully-ince?endent channels, with an exceptionally sc;.iisticated interrupt structure that allows very =st transfers.
Full interfac1r.q is provided for CPU or DMA
General Tne 2-80 SIO Serlal InpuVOutput Control- Description ler 1s a dual-channel data commun~cat~on
Interface w~th extraordinary versatility and capability Its baslc functions as a serlal-to- parallel, parallel-to-serlal converter/controller can be programmed by a CPU for a broad range of serlal cornmunlcatlon appl~cat~ons.
The device supports all common asyn- chronous and synchronous protocols, byte- or
a. I.DA - iizx -
4 IxDA - =GEi - -
S I Y U - - 0, w1- - - 06
CIIAIIYEL A - -
I -
CONTROL I - CPU - -
+dv a h cia
Figure I . 2-00 S10/2 Pin Functions Figure 2. 2-80 S10/2 Pin Auignments
2642-01 11, 0120 71
-7
S W 2 rn - - Y1
,666 I.08 - iiii 1.c.8 -
TxOa --c
W6 XEE-
arii Wm6W -
m CUAIY
C-
t f t
General control. In addition to data communication, thk The 2-80 SIO is an n-channel silicon-gat< Description circuit can handle virtually all types of serial depletion-lwd device packaged in a 40-pin (Continued) I/O with fast (or slow) peripheral devices. plastic or ceramic DIP. It uses a single +5
While designed primarily as a member of the power supply and the standard 2-80 family 2-80 family, its versatility makes it well suited single-phase clock. to many other CPUs.
- Pin Figures 1 through 6 illustrate the three pin CE. Chip Enable (input, active LOW). A Lo Desaiption configurations (bonding options) available in level at this input enables the SIO to accep
the SIO. The constraints of a 40-pin package command or data input from the CPU durir make i t 9 o s s i b l e to bring out the Receive write cycle or to transmit data to the CPU Clock (RxC), Transmit Clock (m), Data Ter- during a read cycle. mind1 Ready ( T R ) and Sync (SYNC) signals C L ~ . system clod (input)., ~h~ SIO uses +, for both channels. Therefore, either Channel B standard 2-80 system clock to synchronize lacks a signal or two signals are bonded internal signals. This is a single-phase cloc together in the three bonding options offered:
2-80 SI012 lacks SYNCB CTSA. CTSB. Clear To Send (inputs, activl Low). When programmed as Auto Enables,
2-80 SIOll lacks DTRB Low on these inputs enables the respective 2-80 SIOIO has all four signals. but transmitter. If not programmed as Auto and RxCB are bonded together Enables, these inputs may be programmed.
The first bonding option above (S1012) is the general-~ur~ose inputs. Both inputs are Schmitt-trigger buffered to accommodate sl
preferred version for most applications. The risetime signals. The SIO detects pulses on pin descriptions are as follows: these inputs and interrupts the CPU on botl B/A. Channel A Or B Select (input. High logic level transitions. The Schmitt-trigger I selects Channel B). This input defines which fering does not guarantee a specified noise. channel is accessed during a data transfer level margin. between the CPU and the SIO. Address bit Ag from the CPU is often used for the selection D~-b' System Bus
function. 3-state). The system data bus transfers data and commands between the CPU and the Z
c/B. Control Or Doto Select (input, High SIO. Do is the least significant bit. selects Control). This input defines the type of - - information transfer performed between the DCDA' DCDB' Carrier Defect (jnputs CPU and the sIO. A High at this input during active Low). These pins function as receive a CPU write to the SIO causes the information enables if the SIO is programmed for Auto
on the data bus to be interpreted as Enables; otherwise they may be used as
man^ for the channel selected by B/A, A L~~ general-~ur~ose input pins. Both pins are
at C / ~ means that the information on the data Schmitt-trigger buffered to accommodate sl
bus is data, Address bit is often used for risetime signals. The SIO detects pulses on
this f u n c t a these pins and interrupts the CPU on both I b n ~ a ~ - , logic level transitions. Schmitt-trigger bu!ft
EA - h D A -
> CIUWN1.L A
I"W - m- 5 5 - G-
S m T - iiii
m
r5v on0 cuc Figure 3. 2-80 SlOll Pin Functions Figure 4. 2-50 SlOll Pin As8ignrncnts
- Pin ing does not guarantee a specific noise-level ~esaiption margin. (Continued) W A . m. Doto Terminal Recdy (outputs,
active Low). These outputs follow the state pro- grammed into Z-80 SIO. They can also be pro- grammed as general.purpose outputs-
In the 2-60 SIOil bonding option, DTRB 1s omitted.
IEI. Interrugi K ~ c b l e Ir! (input, active Xigh). l n i s signal is used :vith IEO to form a orloricy daisy chain when there :s more than one interrup!-driven device. A High on :his line indicates that no other device of hiqher pri- ority is being serviced by a CPU interrupt ser- vice routine.
IEO. Interrupt Enable Out (output, active High). IEO is High only if IEI is High and the CPU is not servicing an interrupt from this SIO. Thus, this signal blocks lower priority devices from interruotina while a hiaher
ously, the CPU is acknowledging an interrupt and the SIO automatically places its interrupt vector on the CPU data bus if it is the highest priority device requesting an interrupt. - MI. Machine Cycle(Input from 2-60 CPU, active Low). When M1 is active and W is also active, the 2-60 CPU is fetching an instruction from memory: '"hen nkac t ive&e I T Q is active. :he SIO accepts MI and IORQ as an interrupt acknowledge if the SIO is the highest priority device <hat has interrupted the 2-80 CPU. -- RxCA. RxCB. Receiver Clocks (inputs). Receive data is sampled on the rising edge of RxC. The Receive Clocks may be 1, 16, 32 or 64 times the data rate in asynchronous modes. These clocks may be driven by the Z-80 CTC Counter Timer Circuit for prcqrammable baud : rate generation. Both inputs are Schmitt- trigger buffered (no noise level margin is
priority device is being serviced by its CPU 'pecified).
interrupt service routine. In the 2-80 SIO/O bonding option. is ' bonded together with 'ixCB. KT. Interrupt Request (output, open drain. -
active Low). Whenthe SIO is requesting an CPU, interrupt, it pulls INT Low. active LOW). If RD is active, a memory or I/O
re& oxeration is in progress. RD is used wlth KQ. In.~uu-ut Request (input from CPU, B/A, CE and IORQ to transfer data from the active Low). IORQ is used in conjunction with SIO to the CPU. BIA, C/B. a and to transfer commands and data bet.ueen the CPU and the SIO. When RxDA, RxDB- Receive Data (inputs. active - CE. and are all acrive, the channel High).Seria1 data at TTL levels. selected by B/A transferedata to*CPU (a RESET. Reset (input, active Low). A Low read operation). When CE and IORQ are RESET disables both receivers and transmit- active-but is inactive, the channel selected ters, forces TxDA and TxDB marking, forces by B/A is written to by the CPU with either the modem controls High and disables all data or control information as specified by interrupts. The control registers mus: be C/6. If 1 m Q and are active simultane-
COWTAOL
1 1 I r S V ON0 CLK
CLK
Flgum 5. 280 StO/O Pln Funaiolu Figure 6. 2-00 SiOlO Pln hlgnm.nts
?C42-01! !, 3120 73
P i n rewritten alter the SIO is reset and before data Description is transmitted or rece~ved. (Continued) m, m. Request To Send (outputs,
active Low). When the RTS bit i n x r i t e Register 5 (Figure 14) is set, the RTS output goes Low. When the RTS bit is reset in the Asynchronous mode, the output goes High after the t r a ~ m i t t e r is empty. In Synchronous modes, the RTS pin strictly follows the state of the RTS bit. Both pins can be used as general- DurDose outouts. . . -- SYNCA. SYNCB. Synchronization ( inpu t s /~~ : - puts, active Low). These pins can act either as inputs or outputs. In the asynchronous receive mode, they are inputs similar to CTS and - DCD. In this mode, the transitions on these lines affect the state of the Sync/Hunt status bits in Read Register 0 (Figure 13), but have no other function. In the External Sync mode, these lines also act as inputs.-n external synchronization is achieved, SYNC must be driven Low on the second rising edge of RxC after that rising edge of RxC on which the last bit of the sync character was received. In other words, after the sync pattern is detected, the external logic must wait for two f u l l Receive Clock cycles to activate the SYNC - input. Once SYNC is forced Low, it should be kept Low until the CPU informs the external synchronization detect logic that synchroniza- tion has been lost or a new message is about to start. Character assembly begins on the rising edge of RxC t h a t m e d i a t e l y precedes the falling edge of SYNC in the External Sync mode.
Ir. the rnternal synchronization mode (Monosync and Bisync), these pins act as ou puts that are active during the part of the receive clock (RxC) cycle in which sync characters are recognized. The sync conditin is not latched, so these outputs are active ea time a sync pattern is recognized, regardles: of character boundaries.
In the 2-80 S10/2 bonding option. S m is omitted. -- TxCA. TxCB. Transmitter Clocks (inputs). I: asynchronous modes, the Transmitter Clock: may be 1, 16, 32 or 64 times the data rate; however, the clock multiplier for the transm: ter and the receiver must be the same. The Transmit Clock inputs are Schmitt-trigger bt fered for relaxed rise- and fall-time require- ments (no noise level margin is specified). Transmitter Clocks may be driven by the Z-E CTC Counter Timer Circuit for programmai: baud rate generation.
In the Z-80 SIO/O bo-g option, TB i! bonded together with RxCB. TxDA. TxDB. Transmit Data (outputs, active High). Serial data at TTLLvels. TxD change from the falling edge of TxC. ---- W/RDYA. W/RDYB. WaiffReody A, Wait/ Ready B (outputs, open drain when pro- grammed for Wait function, driven High anc Low when programmed for Ready function). These dual-purpose outputs may be pro- grammed as Ready lines for a DMA controllt or as Wait lines that synchronize the CPU to the SIO data rate. The reset state is open drain.
INTERNAL CONTROL
'%:%! MOOEMOR
SIATUL ) OTHE. COIITR,
OAT*
B Y I U O LNTERUU BUS
CONTROL - - u LINES
REOISTERS
VAITIREADI
Figvre 7. Block biagram
Functional The functional capabilities of the Z-80 SIO the SIO offers valuable features such as ncn- Description can be described from two different points oi vectored interrupts, polling and simple hand-
view: as a data communications device, ~t shake capability. transmits and receives ser~al data in a wide Figure 8 ~llustrates the conventional devices variety of data-communication protocols; as a that the SIO replaces. Z-80 family peripheral, it interacts with the The first part of the following discussion 2-80 CPU and other peripheral circuits, shar- covers SIO data-communication capabilities; ing the data, address and control buses, as the second part describes interact:ons between well as being a part of the Z-80 interrupt struc- the CPU and the SIO. ture. As a peripheral to other mlcroprocessors.
I
Figure 8. Conventional Devices Replaced by the 2.80 Sf0
Data The SIO provides two independent full- Cornrnuni- duplex channels that can be programmed for cation use ~n any common asynchronous or synchro- Capabilities nous data-commun~cation protocol. Figure 9
illustrates some of these protocols. The follow- Ing 1s a short description of them. A more detailed explanation of these modes can be found in the 2-80 SIO Technical Mcnuol.
Asynchronous Modes. Transmission and reception can be done independently on each channel with iive to eight bits per character. plus optional even or odd parity. The transmit- ters can supply one, one-and-a-half or two stop bits per chdracter and can provide a break output at any time. The receiver break- detection logic interrupts the CPU both at the start and end of a received break. Reception is protected from spikes by a transient spike- rejection mechanism that checks the signal one-half a bit time after a Low level is detected on the recelve data input (RxDA or RxDB In Figure 5). If the Low does not persist-as in the case of a translent-the character assembly process IS not started.
Framing errors and overrun errors are detected and buffered together with the partial character on which they occurred. Vectored
~ - ~ - - - ~-~ ~
interrupts allow fast servicing of error condi- tions using dedicated routines. Furthermore, a built-ln checking process avoids interpreting a framrng error as a new start bit: a framing error results in the addition of one-half a b ~ t time to the point at which the search for the next start bit is begun.
The SIO dces not require symmetric transmit and recelve clock signals-a feature that allows it to be used with a Z-80 CTC or many other clock sources. The transmitter and recelver can handle data at a rate of 1. 1/16, 1/32 or 1/64 of the clock rate supplied to the recelve and transmit clock i n p u L
In asynchronous modes, the SYNC pin may be programmed as an input that can be used for functions such as monitoring a ring indicator.
Synchronous Modes. The SIO supports both byte-orlented and brt-oriented synchronous communication.
Synchronous byte-oriented protocols can be handled in several modes that allow character synchronization with an %bit sync character (Monosync), any 16-bit sync pattern (Bisync). or with an external sync signal. Leading sync
Data characters can be removed without interrupt- Communi- ing the CPU. cation Five-, six- or seven-bit sync characters a r e Cupabilities detected with 8- or 16-bit patterns in the SIO (Continued) by overlapping the larger pattern across multi-
ple in-coming sync characters, as shown in Figure 10.
CRC checking for synchronous byte- oriented modes is delayed by one character time so the CPU may disable CRC checking on specific characters. This permits implementa- tion of protocols such as IBM Bisync.
Both CRC-16 (Xi6 + XI5 + X2 + 1) and CCITT (XI6 + X12 + X5 + 1) error checking polynomials are supported. In all non-SDLC modes, the CRC generator is initialized to 0's; in SDLC modes, it is initialized to 1's. The SIO can be used for interfacing to peripherals such as hard-sectored floppy disk, but it cannot generate or check CRC for IBM-compatible soft-sectored disks. The SIO also provides a feature that automatically transmits CRC data when no other data is available for transmis- sion. This allows very high-speed transmissions under DMA control with no need for CPU intervention at the end of a message. When there is no data or CIiC to send in syn- chronous modes, the transmitter inserts 8- or 16-bit sync characters regardless of the pro- grammed character length.
The SIO supports synchronous bit-oriented protocols such as SDLC and HDLC by per- forming automatic flag sending, zero insertion and CRC generation. A special command can be used to abort a frame in transmission. At the end of a message the SIO automatically transmits the CRC and trailing flag when the transmit buffer becomes empty. If a transmit
underrun occurs in the middle of a message an external/status interrupt warns the CPU c this status change so that an abort may be issued. One to eight bits per character can i: sent, which allows reception of a message wi no prior information about the character strc ture in the information field of a frame.
The receiver automatically synchronizes o the leading flag of a frame in SDLC or HDLI and provides a synchronization signal on thc
pin; an interrupt can also be pro- grammed. The receiver can be programmed search for frames addressed by a single byte only a specified user-selected address or to global broadcast address. In this mode, fran that do not match either the user-selected or broadcast address are ignored. The number address bytes can be extended under softwa control. For transmitting data, an interrupt ( the first received character or on every character can be selected. The receiver automatically deletes all zeroes inserted by I transmitter during character assembly. It a11 calculates and automatically checks the CR( to validate frame transmission. At the end of transmission, the status of a received frame available in the sta:us registers.
The SIO can be conveniently used under DMA control to provide high-speed receptic or transmission. In reception, for example, t SIO can interrupt the CPU when the first character of a message 1s received. The CPI. then enables the DMA to transier the messac to memory. The SIO then issues an end-of- frame interrupt and the CPU can check the status of the received message. Thus, the CI is freed for other service while the message being received.
EXTERNAL SVWS
CRC- CRCI FLAG
IDLCIHDLCIX.25
Figure 9. Some 2-80 SIO Protocols
I/O Interface The SIO offers the choice of polling. inter- capabilities rupt (vectored or non-vectored) and biock-
transfer modes to transfer data, status and con- trol information to and from the CPU. Tne block-transfer mode can also be impiernented under DMA control.
Polling. Two status registers are updated at appropriate times for each function being per- iormed (for example, CRC error-status valid at the end of a message). When the C?U ;s operated in a polling iashlon, one oi the SIC'S two status registers is used to indlcate whether the SIO has some data or needs some data. Depending on the contents of this register, the CPU will either wr~te data, read data, or just go on. Two bits in the register indicate :hat a data transfer is needed. In addition, error and other conditions are indicated. The second status register (special receive conditions) does not have to be read in a polllng sequence. until a character has been received. All inter- rupt modes are disabled when operating the device in a polled environment.
Interrupts. The SIO has an elaborate interrupt scheme to provide fast interrupt service in real-time applications. A control reg~ster and a status register in Channel B contaln the inter- rupt vector. When programmed to do so, the SIO can modify three bits oi the interrupt vec- tor in the status register so that ~t polnts direct- ly to one of eight Interrupt service routines In memory, thereby servicing conditions in both channels and eliminating most of the needs for a status-analysis routine.
Transmit interrupts, receive interrupts and external/status interrupts are the matn sources of interrupts. Each interrupt source is enabled under program control, with Channel A hav- lng a higher prlority than Channel a, and with receive, transmit and external/status interrupts orioritized in that order w~thin each channel. when the transmit interrupt is enabled, the
CPU is interrupted by the transmlt buifer becoming empty. (This implies that the transmitter must have had a data character written into it so ~t can become empty.) I n e receiver can interrupt the CPU in one of two ways:
s Interrupt on first rece~ved character
;I Interrupt on ail received characters
Interrupt-on-first-received-character :s :yplcally used with the block-!ransier ~ o c e . Interrupt-on-all-recei~red-characters has the option of modifying the interrupt 7rec:or !r. the event of a parity error. Borh of these interrupt modes will also Interrupt under speciai receive conditions on a charac:er or message basis (end-oi-frame interrupt in SDLC, for example). This means that the speciai-receive condition can cause an interrupt only if the intenup:-on- first-received-character or interrupt-cn-ail- received-charac!ers mode 1s seiected. In interrupt-on-first-received-character, an inter- rupt can occur from special-receive cond!tions (except parity error) after the iirst-received- character interrupt (exampie: receive-overrun interrupt).
The main function of the external/status interrupt is to m o n i t c h e s~gnal transi:ions oi t h e l e a r To Send (CTS ), Da-rrier Detect (DCD) and Synchronization (SYNC) pins (Figures i through 6). In addition, an exter- nal/s;atus interrupt is also caused by a CRC- sending condition or by the ceteckion oi a break sequence (asynchronous mode) or abort sequence (SDLC mode) in the data stream. The interrupt caused by the breaklabor! sequence ailows the SIO to interrupt when the breaWabort sequence is detected or ter- minated. This feature facilitates the proper ter- mination of the current message, correct initiaiization oi the next message, and the accurate timlnq of the breauabort condlt~on in external logic.
I/O Interface in a 2-80 CPU environment (Figure 11). SIO Capabilities interrupt vectoring is "automatic": the SIO (Continued) passes its internally-modifiable 8-blt interrupt
vector to the CPU, which adds an additional 8 bits from its interrupt-vector (I) register to form the memory address of the interrupt-routine table. This table contalns the address of the beginning of the interrupt routine itself. The process entails an indirect transfer of CPU control to the interrupt routine, so that the next instruction executed after an Interrupt acknowledge by the CPU is the first instruction of the interrupt routine itself.
CPU/DMA Block Transfer. The SIO's block- transfer mode accommodates both CPU block transfers and DMA controllers (2-80 DMA or other designs). The block-transfer mode uses the WaiffReady output signal, which is selected wlth three bits in an internal control register. The WaiVMdy output signal can be programmed as a W A I T i n the CPU block- transfer mode or as a READY line in the DMA block-transfer mode. -
To a DMA controller, the SIO READY output indicates that the SIO is ready to tran&data to or from memory. To the CPU, the WAIT out- put Indicates that the SIO is not ready to transfer data, thereby requesting the CPU to extend the I10 cycle.
CPU
-
Figure 11. Typical Z-80 Environment
W - W
Internal The internal structure of the device includes Structure a Z-80 CPU interface, internal control and
interrupt logic, and two full-duplex channels. Each channel contains its own set of control and status (write and read) registers, and con- trol and status logic that provides the interface to modems or other external devices.
The registers for each channel are desig- nated as follows:
WRO-WR7 - Write Registers 0 through 7 RRO-RR2 - Read Registers 0 through 2
The register group Includes live 8-bit control registers, two sync-character registers and two status registers. The interrupt vector is written into an additional 8-bit register (Write Register 2) in Channel B that may be read through another 8-bit register (Read Register 2) in Channel B. The bit assignment and functional grouping of each register is configured to simplify and organize the programming pro- cess. Table 1 lists the functions assigned to each read or write register.
DNA
Read Reaister Functions
T , - ZClTO,
crc - - zmo, INT - LC0
RRO Transm~WReceive buffer status, interrupt status and external status
RRI Special Receive Condition status
1 'El I D *
RR2 Modified interrupt vector (Channel B only)
- - w x - -
I >
_IE1 -
Write Register Functions
- U -
--t
IT0 W
101
O Y I
- ~-~
WRO
1 E L =A IN, - T x C I 110
.ii ,;is
wIII.I.
$10
WR5 WR6 WR?
Reqlster pointers, CRC initialize, initializa- tion commands for the various modes, etc. TransmiWReceive Interrupt and data transfe mode definition. Interrupt vector (Channel B only) Receive parameters and control TransrniVReceive m~scellaneous parameters and modes Transmit parameters and controls Sync character or SDLC address field Sync character or SDLC flag
~nternal The logic tor both channels provldes for- Structure mats, synchronization and vaiidatlon for data ;continued) :ransierred to and from the channel interface.
Themodern control inputs, C l e a r L S e n d (CTS ) and Data Carrier Detect (DCD), are monitored by :he external control and status loglc under program control. All external control-and-status-logic signals are general- purpose in nature and can be used ior func- tions other than modem control.
Data Path. The transmit and recelve data pa:h illustrated for Channel A in Figure 12 is iden- tical for both channels. The recelver has three 8-bit buffer registers In a FIFO arrangement, In addition to the 8-bit receive shift register. This scheme creaies additional time ior the
C?U to service an tn!errupt at :he begi~nlng 3: a block of high-speed data. Incomlng oata :s routed through one of several paths (data or CRC) depending on the selected mode and-in asynchronous modes-the charac!er iencth.
The transmitter has an 8-bit iransmlt data buiier reglster that is loaded from the ~nrernai data bus, and a 20-blt rransmit snii: rects:er that can be ioadea from :he sync-charscrer buiiers or irom rhe !:snsrr.it aata'reg:s:er. Decendlng on the operatlonai mode, ou:gc:nq cara is routed :hrouci: one oi four main paths beiore it IS transmitted from ;he Transmit Data ourput (TxD).
TO CHANNEL I. E X I E R H I L STATUS LOGIC.
C O H T l O L L001C. ETC.
CPU YO
RECLlVE RECElVL UII, WIld - - - - - - - - - - - - SYNC PEGlSTER 1 I SYNC RECISTEP (TRANsM'TDAT'
DATA ERROR - - - - - & - - - - - -
1110 FIFO
SYNC ASINC
DATA DATA
LOGIC HUH? MODE IBlSIUQ r - - - - - - - - 7
SYNC *SYNC O l T A C I C
Figure 12. Transmit and Receive Data Path (Channel A)
Programming The system program first issues a series of commands that initialize the basic mode of operation and then other commands that qualify conditions within the selected mode. For example, the asynchronous mode. character length, clock rate, number of stop bits, even or odd parity might be set first: then the interrupt mode; and finally, receiver or transmitter enable.
Both channels contain registers that must be programmed via the system program pcor to operation. The channel-select input (BIA) and the controlldata input (CID) are the command- structure addressing controls, and are normal- ly controlled by the CPU address bus. Figures 15 and 16 illustrate the timing relaiionships for programming the write registers and transfer- ring data and status.
Read Registers. The SIO contains three read registers ior Channel B and two read registers for Channel A (RRO-RR2 in Figure 13) that can be read to obtain the status information: RR2 contains the internally-modifiable interrupt vector and is only in the Channel B register set. The status information includes error con- ditions, interrupt vector and standard communications-interface signals.
To read the contents of a selected read register other than RRO, the system'program must first write the pointer byte to WRO in exactly the same way as a write register opera- tion. Then, by executing a read insrruction, . the contents of the addressed read register can be read by the CPU.
The status bits of RRO and RR1 are carefully grouped to simplify status monitoring. For example, when the interrupt vector indicates that a Special Receive Condition interrupt has occurred, all the appropriate error bits can be read from a s~ngle register (RR1).
Write Registers. The SIO contains eight write registers for Channel B and seven write registers for Channel A (WRO-WR7 in Figure 14) that are programmed separately to con- figure the functional personality of the chan- nels; WR2 contains the interrupt vector for both channels and is only tn the Channel B register set. With the exception of WRO. pro- gramming the write registers requires two bytes. The first byte is to WRO and contains three bits (Do-D2) that point to the selected register; the second byte is the actual control word that is written into the register to con- figure the 310.
WRO is a special case in that all of the basic commands can be written to it with a single byte. Reset (internal or external) initializes the poinier bits Do-D2 to point to WRO. This implies that a channel reset must not be com- bined with the pointing to any register.
READ REGISTER I t
O ~ ~ D . L D ~ . D . ~ O ~ ; D ~ ~ O ~ . ~
I I I I I I I -ALLSENT I I I I L D BITS 1 FIELO l l T S IN IN PIEVIOUS SECOND PREVIOUS
1'111 OWE 0 1
.-=rue 3r. ie. <go,
CIICIFIAYINC ERROR END OF FRAME lSDLCl
READ REGISTER 2
ID,~D.;D.,F, O , : O : ~ D , I O ,
Figure 13. Read Ragirler Bit Functions
p,~aramming WRITE REGISTER o WRITE REG IS^ 4
0 0 P HULLCOOE 0 0 1 SENDABOITISOLCI I I 0 RESEi EXTlSlATUS IHIEIIIUPrS 0 1 3 CHANIIELRES- I 0 0 ENABLE lHT OH HEX7 R x CHARACTER . I U I I E S E I 7. N T PENOIHO ? 1 0 ERROR RESET % I 3 RETURN FROM 1HTICH.I ONLY!
10,'D, 0, D..O1'O,,0. Dl!
0 0 SYNC MOO11 EN18LE a 3 t STOP snicnnarcisa 1 D I ) . STOP B I I Y C H I I I I C T E I 1 > 2 STOP S l T U C H A I I I C T B I
0 1 I B . 1 SY*C C Y I O I C t E l , I ' 6 I.. I*.C C M I I I I C I I I I > I D . 2 "OOI O ? l l l l . " r:*=. I I !.-Em*.. IV.C *ODE
k x l a r r o r o* Pn ..3' en
Is;:::; ::::::"* :,no scrr.r. .,on
WRITE REGISTER 2 (CHANNEL B ONLY1
b7 I D * 8 0, i 0. < 0, i 0, i 0% ! 0,)
WRITE REGISTER 3
D 1 1 D . , 0 , 1 0 1 1 0 , , O , ~ D . . 0 ,
8 8
9 o a. 5 a c r l C H l n r C l E n 0 I I. 1 I I I O I C H I R I C T E R I O 8 . 6 BlTYCHAIACIER I 3 (I. I B I I Y C * * I I C I F R
W R f E REGISTER 6
O,.D,,Ol.o.,o,,o,:D. 0,
WRITE REGISTER 7
O.iO~,D,i0..0,,D, 0. 0,
Figure 14. Write Register Bit Functions
Timing The SIO must have the same clock as the CPU (same phase and frequency relationship. not necessarily the same driver). Read Cycle. The timing signals generated by a Z-80 CPU input instruction to read a data or status byte from the SIO are illustrated in Figure IS. Write Cycle. Figure 16 illustrates the timing and data signals generated by a 2-80 CPU out- put instruction to write a data or control byte into the SIO. Interrupt-Acknowledge Cycle. After receiv- ing an interrupt-request signal from an SIO (F?T pulled Low), the 2-80 CPU sends an interrupt-acknowledge sequence (m Low, and
Low a few cycles later) as in Figure 17. The SIO contains an internal daisy-chained
interrupt structure for prioritizing nested inter- rupts for the various functions of its two chan- nels, and this structure can be used within an external user-defined daisy chain that prioritizes several peripheral circuits.
The IEI of the highest.priority device is terminated High. A device that has an inter- rupt pending or under service forces lts IEO Low. For devices with no interrupt pending or under service, IEO = IEI.
To insure stable conditions in the daisy chain, all interrupt status signals are pre- vented from chanqinq while W is Low. When
is Low, the highest priority interrupt requestor (the one with 1.a High) places its interrupt vector on the data bus and sets its
internal interrupt-under-service latch.
Return From Iniermpt Cycle. Figure 18 illustrates the return from interrupt cycle. Normally, the Z-80 CPU issues a RETI (Retu From Interrupt) instruction at the end of an interrupt service routine. RETI is a 2-byte opcode (ED-4D) that resets the interrupt- under-service latch in the SIO to terminate interrupt that has just been processed. This accomplished by manipulating the daisy c h ~ in the following way.
The normal daisy-chain operation can be used to detect a pending interrupt; howeve! cannot distinguish between an interrupt unc service and a pending unacknowledged intc rupt of a higher priority. Whenever "ED" is decoded, the daisy chain is modified by for, ing High the IEO of any interrupt that has r yet been acknowledged. Thus the daisy cha identifies the device presently under servici the only one with an IEI High and an IEO L If the next opcode byte is "4D." the interru~ under-service latch is reset.
The ripple time of the interrupt daisy cha: (both the High-to-Low and the Low-to-High transitions) limits the number of devices tha can be placed in the daisy chain. Ripple tin can be improved with carry-look-ahead, or extending the interrupt-acknowledge cycle. For further information about techniques i o ~ increasing the number of daisy-chained devices, refer to the Z-80 CPUProduct Specification.
DATA
Figure IS. Rwd Cyclm
Fipun 16. Write Cycle
Figure 17. Interrupt Adninvlodge Cyclm
&,lute Voltages on all inputs and outputs Stresses greater than those listed under Absolute Maxi-
~ ~ ~ i ~ U m with respect to GND. . . . . . . . . . -0.3 V to + 7.0 V mum aatinss may cause permanent damwe to device. This is a stress ratlnq only; operation of :he devtce at any
Ratings Operating Ambient As Specified in conditmn above those indicated ~n the operational seaions Temperature . . . . . . . . . . .Ordering Information oi these specificattons is not implied. Exposure to absolute
maximum rating condit~ons lor extended periods may affect Storage Temperature. . . . . . . . -65OC to + 150°C device rellabllLry. - --
Test The characteristics below apply for the. The product number for each operating ~ ~ ~ d i t i o n s following test conditiozs, unless otherwise temperature range may be found in ;he oraer-
noted. All voltages a re reierenced to GND ing iniormation section. (0 V). Positive current flows into the reier- e n c e d pin. Available operating temperature -3"
ranges are: T
S -55'C to +12S0C, + 4 . 5 v s v c c s + 5 . 5 v
DC Symbol Parameter Min Max Unit . Test Condition Chamc- teristics v!:c Ciock Input Low Voltage -0.3 +0,45 V
":HC Clock input Htgn Iioltaqe Vcc-0.6 25.5 V v ! ~ input Low Voltage .-0.3 +0.8 V
v! % input High Voltage -2.0 i j . 5 '1
v~~ Output Low Voltage -0.4 V IOL = 2.0 mA V~~ Output High Voltage i 2 . 4 V ICH = -250 PA IL! Input Leakage Current -10 -10 pA 0<VjN<VCC I2 3-State OutputIData Bus input Leakage Current -10 10 prl 0 < V!:: < Vcc ILLsyi SYNC Ptn Leakage Current -40 + 10 pA O<ViN<VCC ICC Power Supply Current 100 mA
Over rpecltled tern3eralure and rollage range.
Capacitance Symbol Pcrcmeter Min Max Unit Test Condition
C C!ock Capacitance 40 pF Unmeasured
c:x Input Capacitance 5 pF pins returned
C,3uT Ourput Capacttance 10 3F to ground
Over ipsclhra !+mnerarure ranse: ! = :M%=
Electrical Character- istics
?Z, cr8, sr i I / !
Number Symbol Parameter 2-80 SIO Z80A SIO 2-BOB SIO
Min Max Min Max Min Max U -- - - ~
1 TcC Clock Cycle Time 400 4000 250 4000 165 4000 2 TwCh Clock Width (High) 170 2000 105 2000 70 2000 3 TfC Clock Fall Time 30 30 15 4 TrC Clock Rise Time 30 30 15 5-TwC1- Clock Width (Low) 170-2000 -105-2000 -70 -2000- - 6 TsAD(C) CE, C/B, B/A to Clock 1 Setup Time 160 145 60 7 TsCS(C) KQ, W to Clock 1 Setup Time 240 115 60 8 TdC(D0) Clock 1 to Data Out Delay 240 220 1 50 9 TsDI(C) Data In to Clock I Setup (Write or r l Cycle) 50 50 30
IO-T~RD(DOZ)-W 1 to Data Out Float Delay 230 - 110 90 - 11 TdlO(DO1) 1 to Data Out Delay (INTACK Cycle) 340 160 100 - 12 TsMl(C) MI to Clock 1 Setup Time 210 90 75
13 TslEI(I0) IEI to iORQ I Setup Time (INTACK Cycle) 200 140 120 - 14 TdMl(IE0) M1 1 to IEO 1 Delay (interrupt before miil 300 190 160 15-TdIEI(IE0r)-IEI 1 to IEO I Delay (after ED decode) 150- 100 70-
16 TdlEI(IE0f) IEI 1 to IEO 1 Delay 1 50 100 70
17 TdC(1NT) Clock 1 to iiSi: I Delay 200 200 150 18 TdIO(W/RWf) mQ i or 1 to W/R= 1 Delay Wait 300 210 175
Mode) 19 TdC(W/RR) Clock 1 to v/m I Delay (Ready Mode) 120 120 100 20-TdC(W/FiWz)-Clock I to m/RDY Float Delay (Wait M o d e ) l S O - 130-110- 21 Th Any unspecified Hold when Setup is specified 0 0 0
AC Electr ical 5, m, s m c Charac te r - I - "- istics ( ~ o n t ~ n u e d )
--I KE
1 , /
+zq t f I - - d \
7 x 0 X -2-
llRDI
=
K c
RxO X 1 x 1 L Q 4 I
- WIRD" I I
W I I I
2-80 SIO 2-80A SIO 2-80B SIO Number Symbol Parameter Mln Max Min Max Min Max Unit
1 TwPh Pulse Width (High) 200 200 200 ns 2 TwPi Pulse Width (Low) 200 - 200 200 r;s
3 TcTxC Cycle Time 400 m 400 m 330 m ns - 4 TwTxCl TxC Width (Low) - I80 m 180 m 100 m ns 5-T.~Txch- TxC Wldth (High) 180-m---180-m-100-m- ns- - 6 TdTxC(TxD) TxC I to TxD Delay (xi Mode) 400 300 220 ns 7 TdTxC(W/RRf) TxC I to W/m 1 Delay (Ready Mode) 5 9 5 9 5 9 Clk Per:ods'
8 TdTxC(1NT) I to I Deiai - 5 9 5 9 5 9 Clk Periods* 9 TcRxC RxC Cycie Time - 400 m 400 m 330 ca ns
10-TwRxC1- RxC Width (Low) 180-m-180-m-100-m-ns-
11 TwRxCh RxC Width (Hlqh) 180 m 180 m 100 m ns
12 TsRxD(RxC1 RxD to RxC I Setup Time (xl Mode) 0 0 0 ns 13 ThRxD(RxC) EC 1 to RxD Hold Time (xl Mode) 140 140 100 ns 14 TdRxC(W1RRf) RxC 1 to W l m I Delay (Ready Mode) 10 13 10 13 10 i3 C!i Per:ods.
1S--TdRxC(INT)-RxC I t o m 1 Delay 10- 13-10-13-10-13-C:k ?erlods'- 16 TdRxC(SYNC) RxC I to SYNC 1 Celay (Oufput Modes) 4 7 4 7 4 : Clk Periods' 17 TsSYNC(RxC) SYNC I to l Se:up (External Sync
Modes) -100 -100 130 ns
e i p . & e r . the Syrrern C!ocr rare must be .! !east ::ve :1_7_?3 :me -ax!midm C C : ~ 13%
":>cT rcur: be active a m:nirnum 01 one ccpp!e!e Cbcr C. :.*. '%stern C:OCX
Ordering Product Package/ Produa Package/ Information Number Temp Speed h a i p i i o n Number Temp Speed Derrcripiiorr
DE,DS 4.0 MHz
PE,PS 4.0 MHz CE,CM 6.0 MHz
CMB,CS 2.5 MHz DE,DS 2.5 MHz PE,PS 2.5 MHz CE.CM 4.0 MHz
Same as above Same as abovi BOB SIO/l (40-pin)
Same as above Same as above BOA SlO/O (40-pin1
Same as above Same as above
CMB.CS 6.0 MHz D E E 6.0 MHz PE,PS 6.0 MHz
CE.CM 2.5 MHz
Same as above Same as above
CMB,CS 4.0 MHz DE,DS 4.0 MHz PE,PS 4.0 MHz
CE.CM 6.0 MHz
Same as above 280 SIOl2 (40-pin) Same as above
BOB SIOIO (40-pin)
CMB,CS 2.5 MHz DE.DS 2.5 MHz PE.PS 2.5 MHz
CE.CM 4.0 MHz
Same as above Same as above Same as abovt ZBOA SIOD (40-pin) Same as above Same as abovi Same as abovt BOB SI012 (40-pin)
Same as abovl
CMB.CS 6.0 MHz DE,DS 6.0 MHz PS,PS 6.0 MHz
CE,CM 2.5 MHz
Same .=s above Same as above Same as above
280 S1011 (40-pin)
CMB.CS 4.0 MHz DE,DS 4.0 MHz PE,PS 4.0 MHz
CE,CM 6.0 MHz CMB,CS 2.5 MHz DE,DS 2.5 MHz PE,PS 2.5 MHz CE,CM 4.0 MHz
Same as above Same as above Same as above BOA SIOI1 (40-pin)
CMB,CS 6.0 MHz DE.DS 6.0 MHz PE,PS 6.0 MHz
Same as abovl Same as abov~ CMB,CS 4.0 MHz Same as above
NOTES: C - Ceramtc. D = Cerdrp. P = Plarnc E = -4O.C lo -85%. M - -SSeC :o + 125'C. MB = - 5 - C to r 125.C wtth MIL.STD-883 vttb Clan B pro~esnp. S = 0.C to +7O0C.
