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Features The instruction set contains 158 instructions. The 78 instructions of the 8080A are included as a subset: 808OA software com- patibility is maintained.

P Six MHz, 4 MHz and 2.5 hiHz clocks for the Z80B. BOA, and Z80 CPU result in rapid instruction execution with consequent high data throughput.

The extensive instruction set includes string, bit, byte, and word operations. Block searches and block transfers !ogether with indexed and relative addressing result in the most poweriul data handling capabilities in the microcomputer indl;s:ry.

P The 280 microprocessors aod associated family of peripheral contrcllers are linked by a vectored interrupt system. This system

ui i

svsrem

CONTROL

CPU

COMT::; {

Figure 1. Pin Functions

March 1981

may be daisy-chained to allow implemen- F tation of a priority interrupt scheme. Little, C if any, additional logic is required for G

daisy-chaining. C: %

a Duplicate sets of both general-purpose C(

and flag registers are provided, easing the desi<n and operation of system soit- ware through single-context switching, background-foreground programming, and single-level interrupt processing. In addi- tion, two 16-bit index registers facilitate program processing of tables and arrays.

a There are three modes oi high speed inter- rupt processing: 8080 compatible, non-Z80 peripheral device, and 280 Family peripheral with or without daisy chain.

On-chip dynamic memory refresh counter.

u

Flgure 2. Pin Assignments

General Description

The 280, Z80A, and Z80B CPUs are third- generation single-chip microprocessors with exceational computational power. They offer higher system throughput and more efficient memory utilization than comparable second- and third-generation microprocessors. The internal registers contain 208 bits of readwrite memory that are accessible to the programmer. These registers include two sets of six general- purpose registers which may be used individually as either 8-bit registers or as 16-bit reglster pairs. In addition, there are two sets of accumulator and flag registers. A group of "Exchange" instructions makes either set of main or alternate registers accessible to the programmer. The alternate set allows operation in foreground-background mode or it may

be reserved for very fast interrupt response. The 280 also contains a Stack Pointer, Pro-

gram Counter, two index registers, a Refresh register (counter), and an Interrupt register. The CPU is easy to incorporate Into a system since it requires only a single + 5 V power source, all output signals are fully decoded and timed to control standard memory or peripheral circuits, and is supported by an extensive family of peripheral controllers. The internal block diagram (Figure 3) shows the primary functions oi the 280 processors. Subsequent text provides more detail on the 280 I/O controller iamily, registers, instruction set, interrupts and daisy chaining, and CPU timlng.

1-1 INTERFACE

8 SYSILUS $ CPU A W D C I U CDUTRDL CDHiROL l H P Y T I DUrPuIS

Figure 3. 280 CPU Block Dimgmm

280 Micro- The Zilog 280 microprocessor is the central each of which has a n &bit prescaler. Each processor element of a comprehensive microprocessor of the four channels may be coniigured to Family product family. This family works together in operate in either counter or timer mode.

most applications with minimum requirements for additional logic, facilitating the design oi efficient and cost-effective microcomputer- based systems.

Zilog has designed five components to pro- vide extensive support for the Z80 micro- processor. These are:

E The P I 0 (Parallel InpuWOutput) operates In both data-byte VO transfer mode (with handshaking) and in bit mode (without handshaking). The P I 0 may be coniig- ured to interface with standard parallel peripheral devices such as printers, tape punches, and keyboards.

The CTC (CounterITimer Circuit) features four programmable 8-bit counter/timers,

280 CPU Figure 4 shows three groups of registers Registers within the Z80 CPU. The first group consists of

duplicate sets of 8-bit registers: a principal set and an alternate set (designated by ' [prime], e.g., A'). Both sets conslst of the Accumula- tor Register, the Flag Register, and six general-purpose registers. Transfer of data between these duplicate sets of registers is accomplished by use of "Exchange" instruc- tions. The result is faster response to interrupts and easy, efficient implementation of such ver- satile programming techniques as background-

a The DMA (Direct Memory Access) con- troller prov~des dual port data transier operations and the ability to terminate data transfer as a result of a pattern match.

The SIO (Serial InpuWOutput) control!er oifers two channels. It is capable oi operating In a variety oi programmable modes ior both synchronous and asyn- chronous communication, including Bi-Synch and SDLC.

a The DART (Dual Asynchronous Receiver/ Transmitter) device provides low cost asynchronous serial communication. It has two channels and a full modem control interface. f

c

foreground data processing. The second set of ! registers consists of six reg~sters with assigned c functions. These are the I (Interrupt Register), the R (Refresh Register), the IX and IY (Index Registers), the SP (Stack Pointer), and the PC (Program Counter). The third group consists oi two interrupt status flip-flops, plus an addi- tional pair of flip-ilops which assists in identi- fying the interrupt mode at any particular time. Table 1 provides further iniormation on these registers.

I I ACCUYULITOI I F ?LAO IEOISIE. I 1. ICCUHULAIOR I F. FLAO REGISTER I I 8 CENERALPVRPOIE I C GENERILPURPDPE I 8' GENERALPURPOSE 1 C. GENERALPURPOSE I I D GENERALPURPOSE I E GEHEIAIPURPOSE I 0' GENERAL PURPOSE I F OEHEIAIPURPOSE I

I X INOEX UEGlSlER

Is INDEX REGISTER

I PC PROGRAM COUNTER I I INTERRUPT VECTOR

= INTERWITS OlLllBLEO 4: a INTERRUPTS ENA8LED SERVICE

l N l E R R U l 1 MODE FLlPFLOPS

H' CEHEUAI PURPOSE

3 MEMORY REFIEIW

Figure 4. CPU Registers

L' CENIRAL DUIPOSE

- 8 m r s -

280 CPU Register Sirs (Bits) Registers -

(Continued) " A' Accumulator 8 F. F' Flags 8 B, B' General Purpose 8 C. C' General Purpose 8 D, D' General Purpose 8

E, E' General Purpose 8 H. H' General Purpose 8

L. L' General Purpose 8

I Interrupt Register 8

R Refresh Register 8

U Index Register 16

IY Index Register 16

SP Stack Pointer 16

PC Program Counter 16

IFFI-IFF2 interrupt Enable Fl~p-Flops

IMFa-1MFb Interru~t Mode F h ~ - F l o ~ s

Rammks

Stores an operand or the results of an operation.

See instwctlon Set.

Can be used separately or as a 16.bit register wtth C. See B, above.

Can be used separately or as a 16-bit register with E. See D, above.

Can be used separately or as a 16-btt register with L.

See H, above.

Note: The (B.C). (D.E), and (H,L) sets are combined as iollows: B - High byte C - Low byte D - High byte E - Law byte H -High byte L - Lcw byte

Stores upper etght bits of memory address for vectored interrupt procehzlng.

Provides user4ransparent dynamrc memory refresh. Automabcally incremented and placed on the address bus during each instructlor. fetch cycle.

Used for indexed addressing.

Same as IX, above.

Stores addresses or data temporarily. See Push or Pop in instruc- tion set.

Holds address of next instruction.

Set or reset to indicate interrupt status (see Figure 4).

Reflect Interru~t mode (see Figure 4).

T d l . 1. Z B O CPU R.gLt*ra

Interrupts: The CPUaccep t sLo interrupt :nput signals: General NMI and INT. The NMI is a non-maska& Operation interrupt and has the highest priority. INT is a

lower priority interrupt since it requires that interrupts be e n e e d insoftware in order to operate. Either NMI or INT can be connected to multiple peripheral devices in a wired-OR configuration.

The 280 has a single response mode for interrupt service for the non-maskable inter- rupt. The maskable interrupt, INT, has three programmable response modes available. These are:

E Mode 1 - Peripheral Interrupt service, for use with non-8080/Z80 systems.

a Mode 2 - a vectored interrupt scheme, usually daisy-chained, for use wiih 280 Family and compatible peripheral devices.

The CPLservices interrupts by sampling the - NMI and INT signals at the rising edge of the last clock of an instruction. Further interrupt service processlng depends upon the type of interrupt that was detected. Details on inter- rupt responses are shown in the CPU Timing Section.

Mode 0 - compatible with the 8080 micro- processor.

Interrupts: Non-Maskable Interrupt (m). The non- General maskable interrupt cannot be disabled by pro- Operation gram control and thereforewill be accepted at (Continued) at all times by the CPU. NMI is usually

reserved for servlclng only the highest priority type interrupts, such as that for orderly shut- down after power failure& been detected. After recognition of the NMI signal (providing BUSREQ is not active), the CPU jumps to restart location 0066H. Normally, software starting at thls address contains the interrupt service routine.

Maskable Interrupt (m). Regardless of the interrupt mode set by the user, the 280 response to a maskable interrupt input follows a common timing cycle. After the interrupt has been detected by the CPU (provided that interrupts are enabled and BUSREQ is not actwe) a special interrupt processing cycle b e g i n s . m is a special fetch (MI) cycle in which IORQ becomes actlve rather than m, as in? normal r l cycle. In addition, this s p e X M 1 cycle is automatically extended by two WAIT states, to allow for the time required to acknowledge the interrupt request and to place the Interrupt vector on the bus.

Mode 0 Interrupt Operation. This mode is compatible with the 8080 microprocessor inter- rupt service procedures. The Interrupting device places an instruction on the data bus, which is then acted on six times by the CPU. This is normally a Restart Instruction, which will initiate an unconditional jump to the selected one of eight restart locations in page zero of memory.

Mode 1 Interrupt Operation. M o d d o p e r - ation is very similar to that for the NMI. The principal difference is that the Mode 1 inter- rupt has a vector address of 0038H only.

Mode 2 Interrupt Operation. This Interrupt mode has been deslgned to utilize most effec- tively the capabilities of the 280 mlcroproc- essor and ~ t s associated peripheral family. Tine Interrupting per~pheral device selects the starting address of the interrupt service routine. It dces this by placinq an 8-bit address vector on the data bus durlng the interrupi acknowledge q c i e . The hlgh-order byte of the Interrupt servlce routine address IS

supplied by the I (Interrupt) register. This ilex- ibility in selecting the inierrupt service routine address allows the peripheral devlce to use several different types oi service routines. These routines may be located at any available

location in memory. Slnce the interrupting device suppl~es the low-order byte of the 2-byte vector, bit 0 (Ao) must be a zero. '

Interrupt Priority (Daisy Chaining and Nested Interrupts). The interrupt prioriv of each peripherai device is determined by its physical location within a daisy-chain config- uration. Each devlce in the chain has an inter- rupt enabie input line (IEi) atid an, interrupt enable output line (IEO), whlch is fed to the next lower pricr:ty devlce. The first devlce in the daisy cham has its IEI input hardwared to a High level. T'ce first device has highest priority, while each succeeding device has a corresponding lower priority. This arrange- ment permits the CPU to select the highest prlority interrupt from several s~multaneously interrupting peripherals.

The interrupting device disables its IEO line L

to the next lower priorlty peripheral until it has ' been serviced. M e r servicing, its IEO line 1s :. raised, allowlng lower priorlty peripherals to t

demand interrupt servicing. The 280 CPU will nest (queue) any pending

interrupts or interrupts received while a selected peripheral 1s being serviced.

Interrupt Enable/Disable Operation. Two flip-flops, IFFl and IFF2, referred to in the register description are used to signal the CPU interrupt status. Operation of the two flip-flops is desczbed in Table 2. For more details, reier to the Z80 CPU Technical Manual and Z80 Assembly Language Maaual.

CPU Reset

Dl lnstructlon execution

Ei mstruct~oa execution

LD A.1 ins1ruc:ion execution

LD d.3 :nstruc:lan execution

Accept NMI

IFF2 Comments

0 Maskable Interrupt cdisabled

0 Mtkable interrup: INT disabled

1 Maskable :ntern?st mf enabled

IFFl iF i1 - i F f 2 ( M a s k s e :nrer- rapt INT dtrablec)

1iFz - IFF: at ccrnplerion ol an

EerYICB

r0u::T.e.

Table 2. Stare ol Fllp-Flops

Instruction The Z80 microprocessor has one of the most Set powerful and versatile instruction sets

available in any 8-bit microprocessor. It includes such unique operations as a block move for fast, efficient data transfers within memory or between memory and I/O. It also allows operations on any bit in any location in memory.

The following is a summary of the 280 instruction set and shows the assembly language mnemonic, the operation, the flag status, and gives comments on each instruc- tion. The 280 CPU Technic01 Manual (03-0029-01) and Assembly Language Programming Manual (03-0002-01) contain significantly more details for programming use.

The instructions are divided into the following categories:

D 16-bit arithmetic operations

Rotates and shifts

0 Bit set, reset, and test operatlons

Jumps

D Calls, returns, and restarts

O Input and output operations

A variety of addressing modes are implemented to permit efficient and fast data transfer between various registers, memory locations, and inpuvoutput devices. These addressing modes include:

Immediate

Immediate extended

Modified page zero

Relative . .

8-bit loads D Extended

16-bit loads 0 Indexed

Exchanges, block transfers, and searches Register

8-bit arithmetic and logic operatlons 0 Register ind~rect

D General-purpose arithmetic and CPU Implied

control Bit

&Bit SYAIIE n.9- opcod. ~ 0 . 0 1 NO.^ M ~ 0 . 0 1 T b.monis Load b p m l o n S Z H PIV N C IS Y1 110 Ha= Bfl- C ~ l n Srmr a- .nu

Group LD r. r' r - r' - . x - x . . . o i r r ' I I 4 7 . r . R . LD7.n r - n . x - x . . . 0 3 r 1 1 0 2 2 7 d

- n - rnl c LD r. IHLI i - IHL) . - X . X . . . O l r l l O 1 2 7 010 D LD I. I IXtdI r - lIX+dl X . X . . . I I O I I I O I DD 3 5 19 011 E

01 i I01 103 ir - d - I01 L

LDr. IlY+dl , - IIY-d) . x . X . . l l I l l lo1 FD 3 5 19 111 A 01 r 110

- d - LD IHLI. r IHLI - r • . X . X . . . 0 1 1 1 O r 1 2 7 LDIIX+dl , r IIX-dl- r . X X . b . 1 1 0 1 1 1 0 1 D D 3 5 19

01 110 ,

- " - LD A. IBCI A - IBCI • - x . x . . ~ M I O I O O A 1 2 7 ..D A. (DE) k - IDEl • . X . X . . . W 0 1 1 0 1 0 1 A 1 2 7 LD A Inn1 A - Inn1 X . X . . 0 3 l l l O l O U L 3 4 13

- n - - n -

LD IBCl. A ( 0 3 - A • . x . x . . . ~ 3 0 ~ 1 0 1 0 0 2 1 2 7 LD 1DEI. A IDEI - A . . X . X . . . W 0 1 0 0 1 0 1 2 1 2 7 LD Inn). A (nnl - A . X . X . . . 0 3 1 1 0 0 1 0 3 2 3 4 13

- n - LIiA.1 A - : I I X 0 X IFF o . 11 101 10: ED 2 2 P

L 3 A . R A - a 01 010 11: 5:

: I,): 0 X l F i C . I : l O l l O l ED 2 2 9

1 D I . A 1 - A 01 011 111 5.: . . X . X . . . 1 : : 0 1 1 0 1 E D 2 2 9

1 D R . A R - A 01033 i i i 47 . . X . X . . . 11101101 ED 2 2 P 01 031 I l l 4F

IiOTES- r . : men% any c! ~ n r recisSers h L, i 3. E i:. L 111 m. conle.?: o! s c ~mlcrrupi emmr li.~lio;, ;IFFi ir s.p,cd >.lo 8". P i Z f1.s

Fc7 .lexpi..s.llo* .! l4DC nol.l,on an. ."moo,. ,ci rnmnonic :emcs, r* Srrnmi~: Yrlc~lon .erilor. ,.i,or,ng ,.o,c.

16-Bit Load S+UC nap. Opcod. N0.01 N 0 . d M N..olT Mn.rnonlc O~...~I.. s z H PIV N C 76 143 110 Ha. By?" Cydr S t m t r Comanu

Group LD do, rn dd - nn X . X . . . COldOWl 3 3 10

- " - a s c

- n - LD IY. nn !Y - nn . X . 1 . . . ! I ! O F 4 4 : I

W I W C01 2.

- 1 -

LD IX, inn1 IXH - inn+ 11 . . X - X - . . il 011 101 DD 4 d 20 !XL - ("") W 101 010 U

- n - LDIY. (on) !YH - r r n r l i

[YL - Inn1

LD Inn!. HL !nn* I! - H in01 - L

LD lnnl. dd Inn+ 11 - d d ~ Inn1 - 5bL

Exchange. ix o ~ , HL

Block EX <IF. AP' EXX

Transfer. Block Search EX HL

Groups EX ISPI. iX

Ex (SPI. L'I

DE - HL kF - A P 3C - 3c DE - DE' EL - HL' H - iSP - I ) L - (SPI U(3 - IS?+!) !XL - ISPI 1% - lSP+I) !YL - (SP1

. . X . X . . .

. . X . X . . .

. . X . X . . .

0

I1 100 Oli 83

LDI (DEI - (HLI . . X 0 X ! 0 9 I: 101 I01 ED 2 4 !6 Loao tHLl :nio DE - DL-! !O !W MO A0 :DEI. ~ n c m m e s H L - H L + I :he pasn:en anz E C - 3 C - I ;eC:emen, Lhe 0y.e

E L - H L t l BC - E C - I Seaeat ""ti1 3C = c

Exchange. S Y ~ ~ ~ O I I C F I ~ ~ . opsod. NO.OI N D . ~ M NO.OI T

Block Mn.nro3c Oprmlon S Z H PIV N C R 543 210 H.x B p s Cyc1.s Stmt.r Comm.mls

Transfer. 0 Block Search lDD tDE, - IH- . . X C X I (I . I1 101 10: ED 2 i IF

C i - 3 E - ; 1G 10: iO? A€ Groups :?I - HL- : (continued) ac - a=-:

CP: h - !EL: H L - HL- I a C - a t - ;

HL- HL-I BC - B C - I R e p a t un!rl h = 1x11 0;

ac = 0

CPD A - IHL: H i - HL-I EC - B e - I

CPDR h - IHL:

HL - HL-I BC - Kc-! Repat mtll A = I!iL!C ac = o

A r lHL' l O l l l W l B P 2 1 16 I ! B C = O O I

A = IHLI

Ii01E5 a PA' llap 8% 0 I! Inc re,*!; ol I:-. - C cr%mrL P,i' I ! 0 2 l i a ~ IS i I! A - IHL:. oimnmw 2 - C

8-Bit A D D A . , A - A + ,

Arithmetic ADD A . n A - A - n and Logical Group ADDA. IHLI h - A t IHL;

A D D A 1lX.d) h - A - IIX-cl

ADD A. ( I ?+d l A - A - : lY+dl

A D C A . a A - A - s - C ?

SUB h - A - ~

S E C A . a A - A-I -CV

A N D s A - A A S

OR r * - A " ,

XORr A - A e s

C P r h - s

INC r r - r + l

INC IHLI (Hi1 -!HLlr I INC IlX + d: IlX+ d! -

I IX*d l+ 1

1NC I!Y r d : I IY+d l - I l Y + d l - I

. I. any O! r. n. IHL!. l lX+d l , !I? + d l 01 shown fo i ADD i iuliunm. ine lndlcated blt,

iepldce fne rn m

the ADD Ie, cmvr

m 15 any of r. IHLI. !IX*dL, IIY *d! ar shown lor 1NC DEC ram. lormat and stater as INC Replace @ xat.

," o~...;.

General- s ~ u c oped. n0.d k.d x NO.& I Purpose s4nmmmis opMtlen s z P Ptv a c n s43 210 H a B,t., c ~ l n st-..

Arithmetic D"A C~"ema.T.:on.en, I : X : X P . I i O i S ! i l 27 : 1 I 3-7*,a.%un :am pcied I C D ~e:z.umr~c.

and M ~ O W ~ C ~ a d ,, CPU Control suomo rch cackm

BCD a;erardl. Groups C?L A - X . x : x - : . :a :JI iil 2~ ; ! i ~ ~ ~ ~ : ~ ~ ~ ~ t

1CClrr...C?.I I%..

ccm,l*aenrl. ?IEG A - J - A I : X : < ' : I a i 0: I i 2 3 )leoa:e ezc. ' v c i

--- :I a tic0 44 --- 2 - W ,.e-er.::.

--: . . I X :< . . : :C . : i ::! d i . : + Zcx3.er .e~: :*:>;

sc: -3: - : :.do

,.-, r . :< : 6 . ; . c 5 : 5 . : 4 ter ::;rv :.a= ..-. !!o :perr:sa . . .< . . . . :c :M ::C :C . . 4

?.-..a ,C?U La,:*" . . i . Y . . . : : : : , i

3: . .-- : ! i El ,r: - i . . !! . :i . . . :: ; i i :;; '3 i . 4 !M 0 Set l a : t r r ~ i ! . . I . I . . . ! 0 : ? : 2 I 4

-- - -- -

16-Bit ADD XL. ss XL - HL . ss . . x x x - 0 I W ~ S I C O I I 3 11 -2 N 3C

Arithmetic ADCHL. IS HL - HL+n-CY I I X Y I 'l 0 l I1 101 I01 LD I 4 5 01 3i Group >i oia 10 :-:L , , c3

56CHL n

ADD IX. pp

ADD !Y :r

;:<c 5s :::c :x

i:1c :Y

JEC ss DEC :x

DEC :Y

- --- -~ - - - ~ - - - ~ ~ . . - - - --

Rotate and L

Shift Group % C A L L ! - - - . x : :< . j : <a 3, 1 I r a o n : ~ .el! :;rcu,ar ,CiY.?.ild:i.

: : I I :< ? O r i ! xi 2: 1 CB 2 1 5 :::,:e .er z::z.,,,

s ?<% SCI -*:,<:*: : : ! x 2 : ? : , i : : ; 2 i i3 L-25 . .

;0 :w :I; ... " : .. -

Jump Group S ~ I I C nmm opcod. n0.d NO.OI K NO.OI T (Continued) O p m l o n S 2 B P/V N C 76 543 110 H.. B v r C y c l r S t m r hm.r.1.

-

Call and tau "0

Return Group

CALL cc, nn

RST .

IS?- 11 - ?CH IS?-21 - PC; PC - nn :I condrtion m ,, , a h mnunus. othen,u, rame a, CALL on

157-11 - PCH ISP -21 - PCI PCu - 0

, SOTP .SETS iao lii2 - l i f l

Input and IN A. 1.1 a - 1.1 . . x . x . . . II OIL OII Da 2 3 :I .to AO - A: - n - Acc. :o A8 - ,Ii5

Output Group IN r, (CI r - ICI I I a t x p o . IIIOIIOIED 2 3 :2 c : o ~ ~ J - A , :I r = 110anly fh Ol r m 3 :D .:8 - ,Ii5 IIrqr r~ll b. ailened

IN1 IHLI - LC1 0

X I X X X I I . 11101101ED 2 4 :6 " : = & - A ? B - 8-1 I0 I W 010 A2 3 : o h - A 1 j SL - xi r I

!NIR lHL1 - iC1 X I X X X X I . l l l 0 1 1 0 l L D 2 5 21 C:oAo-A. l s - 3 - 1 10 !:a OIC a2 III 3-01 , - 3:.irg - a15 HL - PL r 1 2 4 .D

sepal UO,~I tit a-0) 9 - 0

0 i l lD IHLI - ICI I I I X X X I ( l l i 0 1 1 0 1 D D 2 4 !S C : a A o - A ?

a - 8 - 1 10 10; 010 M 3 !$ag - dl$ HL - HL- I

INDR !HL: - 10 X I X X X X 1 . 11101101ED 1 5 :! Z : o h - A ? a - a- I !O ii! 010 3~ 11 a-a: 3 : 0 i ~ - A : ~ HL - H I - I 2 4 .E aewt r;ntl~ :I! a=a i a - o

OUT lnl. A In1 - A - a X . X . . . : 1 0 1 0 0 1 1 3 i 2 3 :' n.a.An-d7 - a - .AC;. ., aa - A: OUT ICI, r 1Cl - r . . X X . . - !1 !01:01ED 2 3 .2 'C.aAo-A:

A .>I : W I 2:cAg - A!s W

OUT1 lC1 - IHLI X I X :( X X I . l ! : O l ! d i ED : i .6 Z:o.A:-.i- a - 8 - 1 I0 I M Oil A3 3 .. i3 - ':L - HL + :

OTiR >C! - ,XI X . K I X X ! . I l O ! ! 0 1 : i 1 1 3:;.:~-A7 3 - 3 - 1 !O l!O Ol! 83 (If 3-O: 3 ~3 - . HL - H I 7 1 2 4 .i cepea( untli :!I a=c ) 9 = *

OUTD :C: - IHLl 0

X X X X X I . i l : 0 1 1 0 1 E D 2 1 .d C - o ~ q - d r 3 - 3 - 1 10 101 CII -3 3 % ~ ~ - ::s HL - Hi- I

Input and S ~ O I I C slag. OPCO~. ~0.01 NO.O~ M N..OI T

Output Group M"'"""' OprmIton S Z H PIV N C 76 Y1 210 Ha. Byf.. Cycln St.%.. G~~.,. (Continued) OTDR ic, - ~ H L , x 1 x x x x : . I : . 5 t i C , O A ~ - ~ ,

5 - 0 - 1 HL - Hi-t

:< ... ;t: !i! BiO! 2 i I6

B ~ O A E - A I Z

Rcpeai ur.111 6 = 0

111 h=01

Summary of 1ruuuct1.n

D, Flag s z H PIV H 2 G~~... Opemtion ADE A . %. ADC A. 5 I I X i X V C I 6-bi: e=: r: aoa v;i. ca:iy.

SUB r. SBC A. r. CP r: NEG I I X I X V 1 I 8.bn s;.-.ran, ruo:ract wltr. carv compare an. nqate accuxula!~; AND I

OR s XOR s Il:C r DEC s ADD DD, u ADC HL. IS SBC Hi, u R U . RLCA. RRA. RRCA EL n: RLC n: RR n:

RRC m. SLA m: SRA e; SRL m

RLD RRb DAA

I I X 0 X P 0 . Ra:ale c.;.: ic!; an. ng!n

CPL I I Y. I X P . i Cec,mc. ::."I? .CCV~YI.,OT

SCF - ' x 1 X . i . Conpie-cr. a;cuno1a,or

CCF . X b X . G i Setcam

I N r ICI X X X - 0 I Comp.cze-.: car?

I I >: O X F . Inpa: r.;.sc: lnolrecl IN. IHD. OUT:. OUiD INiR, INDP,, OT13: OTDR $ I i 1) ~ ' o c r ;r=: and cutpn: z = o 11 B t ~othervlse z = c LD:: LDD LDIR. LDDR : : 2 : :} BIDDC ILTSC~ I ~ S ~ ~ L ~ C I I D ~ . P:v = I I! BC t 0. oinerrlre PIY = 0

CP!. CPI!: CPD. CPCR X I X X X I 1 . BIOFL KC::^. inrtmcl~onr. 2 = I i! A = IHLI. olherr~le Z = 0 PN

1D A. 1. iD A. ?. >i 3C = : o:nerwase PN = 0

8:: b. r I I X 0 X li? O . The =or:?-. s! tne ~nterrux enable lI~p-llo2 (IFF) 81 copled ~nlo the PN llaq X I X I X X 0 . Tne stax :'a>! b d emcalmn r 3s cooled :nfo the i tho.

Symbolic symbol Operation Symbol Operation

Notation s S s n lias. S = I 11 the MSB of the result a I. : The flag IS aliected accord~ng to the resalt ol the Z Zero flag. Z = 1 il the result 01 the operation n 0. operation. PN Par~ty or overflow Ilag. Farlty (PI and overllow . The ilag 1s unchangd by the operatton.

iV) share the same ilag. Loa~cal opeiatlons aliect C The !lag IS reset by the operation. this llag w:th the panty 01 the reauli whlie The flag IS set by the operatlan. arithmetic operat8or.s affect thss llag with the The flag 1s a "don't care." overilow 01 the result. Ii P/V holds parity. P/V = I' P/V ilsg aliec~ed according to the overllow resul: 1 11 the result 01 the operation is ever.. P N = 0 if ol thi: operalion. result is odd. 11 P N holds overliow. PiV = 1 11 5 P N llaq ailected accordang to the panty result of the result of the operation produced an overllow. the operation.

H Hall-carry llag. H = 1 11 the add or subtrca Any one oi the CPU reg~sters P.. B, C. D. E. H. L. operation produced c cerry Into or borrow irom F Any 8-blt locat~on lor all the addrens~ng nodes bit 4 of the accumuiator. aliowed ior the partrcular instruc~~on.

K AddfSubtract 113~. N = 1 11 the previous opere- ss Any i6-bl1 locat~or, lor ail the addressing modes tron was a subtract. allowed for that rnstruct,on.

H & N H and N flags are used tn con~unctlon with the :: Any one o! the two tndex registers IX or IY. decimai adlust znstruct~on (DAA) to pnper!y cor. R Reiresh counter. rect the result lnto packed BCD iormal lollow~ng s 6.~11 value ~n range < 0. 255 > . add~tion or subtraaion u s ~ n g operands with -- .... 16-b~l valve m range < 0. 65535 >. packed BCD lormat.

C CarrylL~nk flag. C = 1 11 the operatlon produced a carry from the MSB of the operand or result.

- Pin &-Al1, Address Bus (output. active High. Doscriptbaa 3-state). &-A15 form a 16-b~t address bus. The

Address Bus prov~des the address for memory data bus exchanges (up to 648 bytes) and for I/O devlce exchanges. m. Bus Acknowledge (output, actlve Low). Bus Acknowledge lnd~cates to the requesting devlce that the CTU address bus, data bus, and control siqnalsMREQ, 1 m . m, and T R have enterea their hgn- imuedance states. The external c:rcu:try can now ccntroi :hese ilnes. WQ. Bus Requesf (input. active Low). Bus Request has a h~gher prior~ty than and IS always recognized at the end of the cur- rent machlne cycle, - forces the CPU address bus, dakbus , adcont ro i signals -- MREQ, IORQ, RD, and WR to go to a high- impedance state so that other devlces can control these lines. BUSREQ is normally wire- ORed and requires an external ullu for these applications. Extended dkd periods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAMS.

DO-&. Dab Bus (inpuvoutput, active High, 3-state). Do-D7 constitute an 8-bit bidirectional data bus, used for data exchanges with memory and 110. m. Halt Sfate (output, active Low). Indicates that the CPU has executed a Halt instruction and is awaiting either a non- maskable or a markable interrupt (with the mask enabled) before operation can resume. While halted, the CPU executes NOPs to maintain memory refresh.

m. InterruptRequest (input, active Low). Interrupt Request is generated by UO devices. The CPU honors a request at the end of the current instruction if the internal software- controlled interrupt enable flip-flop (IFF) is enabled. is normally wire-ORed and requires an external pullup for these applications. - IORQ. InputIO-t Request (output, active Low, 3-state). IORQ indicates that the lower half oi the address bus holds a valid VO address for an I/O read or write operation.- 1 7 m is also generated concurrently with MI during an interrupt acknowledge cycle to indi- cate that an interrupt response vector can be

placed on the data bus. - MI. Machine CycI&e (output, active Low). - M1. together with MREQ, indicates that the current machine cycle is the opcod~fetch c y c l e h n instruction execution. MI, together with IORQ, indicates an interrupt acknowledge cycle. - MREQ. Memo R est (output, ac'j-re Low, 3state). M n d i c a t e s that the address bus nolds a vaiid address for a memory read or memory write operation. - NMI. NIV-~askdble Interrupt (input, active Low). NMI has a higher priority than INT. NMI is always recognized at the end of the cutrent instruction, independent of the status of the interrupt enable flip-flop, and automatically forces the CPU to restart at location 0066H.

m. Memory Read (output. active Low, 3-state). W indicates that the CPU wants to read data from memory or an I10 device. The addressed 110 device or memory shouid use this signal to gate data onto the CPU data bus. R=. Reset (input, active Low). initializes the CPU as follows: it resets the interrupt enable flip-flop, clears the PC and Reqisters I and R, and sets the interrupt status to Mode 0. Dunng reset time, the address and data bus go to a high-impedance state, and all control ou ut agnals go to the inactive state. Note that k must be active for a minimum of three full clock cycles before the reset operation is complete. - - WSH. Refresh (outnut, active Low). RFSH, together with m, indicath that the lower seven bits oi the system's address bus can be used as a refresh address10 the system's dynamic memories. - - WAIT. Wait (input, active Low). WAIT indicates to the CPU that the addressed =em- cry or I/O devices are not ready for a data transfer. The CPU continues to enter a Wait state as long as this signal is active. Extended WAiT periods can prevent the C?U from refreshing dynamic memory properly. m. Memory Write (output. active Low. 3-state). T R indicates that the CPU data bus holds valid data to be stored at the addressed memory or VO location.

CPU Timing The 280 CPU executes instructions by pro- The basic ciock per~od is reierred to as a ceeding through a specific sequence of opera- T t ine or cycle, and three or more T cycles tions: make up a machine cycle (MI. M2 or M3 lor

Memory read or write

B I/O device read or write

II Interrupt acknowledge

Instruction Opcode Fetch. The CPU places the contents of the Program Counter (PC) on the address bus at the start ol the cycle (Figure S).~proximately one-half clock cycie]ater. MREQ goes active. The falling edge of MREQ can be used directly as a ChipEnabie to dyna- mic memories. When active, RD indicates that the memory data can be enabled onto the CPU

:ns!ance). Machine cycles can be extended e~ the r by the CPU automatically inserting one or more Wait states or by the insertion 01 one or more Wait states by the user.

data bus. The CPU samples t h e m input with the

rising edge of clock state T3. During clock states T3 and T4 01 an MI cycle dynamic RAM refresh can occur while the CPU starts decoding and executing the Instruction. When the Relresh Control s~gnal becomes active. refreshing of dynamic memory can take place.

NOTE: T,-Wait cyck added when necessary lor slow anclil>ciy devlcer

Figure 5. Instruction Opcode Fetch

CPU Memory Read or Write Cycles. Figure 6 bus is stabie. so thai it can be used direcrly as Timing shows the tim!r.g of memory read orwrite a Chip Enable for dynamic memor~es. The FR (Continued) c y c l w e r r h a c n opcode fetch (MI) cycle. line is ac:ive when the data bus is stE?ple, so

The MREQ and R D signals iunction exactly as that it can be used direc!!y as an R/W pulse to +fetch q c i e . In a memory wrlte cycle, most sem~conductor memories.

MREQ also becomes ac:ive when the address

READ OPERATIOM

Flgure 6. Memory Read o r Write Cycles

CPU Input or Output Cycles. Figure 7 shows the inserts a single Wait state (Tw). This extra W: Timing timing for an I/O read or I/O write operation. state allows sufficient time for an VO port to (Continued) During I/O operations, the CPU automatically decode the address and the port address line

4 8 : I /

AD-A , X ' V.LIDPORTI\ODIESI ' " i i l i X

CjZE

00-07

NOTE: T,. = One Wait cycle automatically lnrerted by CPU.

Figure 7. Input or Output Cycles

Interrupt Request/Acknowledge Cycle. The During this-cle, I ~ Q becomes ac!ive CPU samples the interrupt signal with the ris- (instead of MREQ) to indicate that the inter- ing edge of the last clock cycle at the end of rupting device can place an 8-bit vector on t any instruction (FigureA). When an interrupt data bus. The CPU automatically adds two is accepted, a special M1 cycle is generated. Wait states to this cycle.

NOTE: 1) TL= La* state ol prenour tlutrueam. 2) Two Welt cycles automatically tmrtcd by CPU('!.

Figure 8. lntmupt RequestlAeLMwledge Cycl.

CPU - Non-Maskable Interrupt Request Cycle. that oi a normal memory read opera:lon except Timing NMI is sampled at the ssnei ime as the that data put on the bus by the msmory is (Continued) maskable interrupt inr;ut INT but has higher iqnorsd. The CPU ins:ead executes a restart

prlority and cannot be disac!ed ilnder soitware (RST! operation and ]?;mps to !he service control. The subsequent :im:ng ;s sirniiar :o :su:ine iocated at address COEGi l (Figure 9j.

- 'Akhauqn Nbli Iran aryr.ctrczcr;i ~r.=u:. .a ccarar.:ee i:r b c q aust occur-c~ ~ a i ~ c :ha" rte rsm? ecqe 01 :hs cloci iycie :ecaqnlreo an :he roiloa>og msc:.:zr i.!c;ie. % P s :a!i;cq nd;e preceainq BLAST.

Figure 9. Non.Maskable Interrupt Request Operation

Bus Request/Acknowledge Cycle. The CPU lines to a high-impedance state with the rising samples BUSREQ with the rislng edge of the edge of the next clock pulse. At [hat time, any last clock period of any machine cycle (Figure externai dev~ce can take control oi these lines, 10). If BUSREQ is actwe, the C P U e t s its - usually to transier data between memory and address, data, and mQ, I ~ Q , RD, and WR I10 devlces.

KT U I S I A I P T O

NOTE: TL= L-r: nta:e ol any :.I q i i e . Tx= An arb~crary c:ocr c.js:* used by :egoenlnq levtce.

Figure LO. Bus Request/Acknowledge Cycle

-- ~ - -

CPU Halt Acknowledge Cycle. When the CPU received. When in the Halt state, the iiALf Timing receives a HALT instruction, it executes NOP output is active and remains so until an inter- (Continued) states until either an or NMI input is rupt is processed (Figure 11).

NOTE: 1NT will 4 % farce a Halt exit. 'See note, Figure 9

Figure 11. Hmlt Acknowledge Cycle

Reset Cycle. -must be active for at least inactive, two internal T cycles are consumed three clock cycles for the CPU to properly before the CPU resumes normal processing accept it. As long as RESET remains active, the operation. m c l e a r s the PC register, so tt address and data buses float, and the control first opcode fetch will be to location 0000 outputs are inactive. Once -goes (Figure 12).

CLOCK

SEi

I O - A t l FLOAT

-lap- f ., FLOAT

Do-01 I

li /"

Figure 12. Reset Cyslo

- - .-

AC 280 CPU ZBOA CPV ZSOB CPU Chmac- Min Max Min Max Win M ~ l x teristics Number Symbol Parameter (-1 (N) (as) (n.7) (us) (as)

1 TcC Clock Cycle Time 400' 250' ."a

.35-

2 TwCh Clock Pulse 'Width (Hlgh) 180' Il0' rj. 3 TwCl Clock Pulse iYld:h (LOW) ie0 2000 110 2000 55 ZSCG

4 TIC Clock Fail Tine - 30 - 20 - 20

5 -Z;C - C!cck R~se ?me 30 30 20

5 TdCr(A1 Clock 1 tc Acd-ess Vaiid Delay - 145 - - 0 - -, d d

7 TdA(MREQf) Address 'Jaiid :o 125' - 53' - :-. -3 - 1 Delay -

8 TdCKMREQf) Clock I 10 MREQ I Deiay - i00 - 65 - 70

9 TdCr(MREQr) Clock I t o m I Deiay - 100 - 85 - 70

10 -TwMREQh - MREQ Pulse Width (High) - 170 ' -------- 1 10' ------- ? j ' - 11 TwMREQl m Q Pulse Width (Low) 360' - 220' - :3jq - c

12 TdCf(MREQr1 Clock I ! o m 1 Delay - 100 - 85 - 70 5 .. 13 TdCf(RDf) Clock 1 t o m I Delay - 130 - 95 - 14 TdCdRDr) Clock 1 t o m I De!ay - 100 - 85 -

80 c 70 e

I5 -TsD(Cr) - Deta Setup Time to Clock I - 50 35 30 - !6 ThD(RDr) Data Hold Time to % I - 0 - 0 - 0

- 17 TsWAIT(Cf) WAIT Setup Tine to C:ock 1 70 - 70 - iO - 18 ThWAIT(Cf) Hold Time after Clock 1 - 0 - 0 - 0

19 TdCrfMlf) Clock 1 t o m I Delay 130 - 100 - 80

20 -TdCr(Mlr) - Clock I ram 1 Delay 130 ------- !OO 50

21 TdCr(RFSHf) Clock I to I Delay - 180 - 130 - 1 10

22 TdCr(RFSHr) Clock l to l Delay - 150 - 120 - LC0

23 TdCI(RDr) Clock I to W I Delay - 110 - 85 - 70

24 TdCr(RDf) Clock I to fiiS I Delay , - lo0 - 85 - 7C

25 - TsD(Cf) - Data Setup to Clock I durlng - 60 SO $0 - M2. Mj, MI or Mj Cycles

26 TdA(I0RQf) Acd:ess Stable prlor to IORQ 1 320' - 180' - :lo' - 27 TdCr(iORQf1 Clock 1 to iORQ 1 Delay - 90 - 75 - dS

26 TdCXIORQr) Clock I to iORQ f Delay - 110 - 85 - 70

29 TdD(WRf) Data Stable prior t o m I 190' - 80. - 25' - 30 - TdCf(WRf) - Clock 1 to I Delay 90 '00 ?O

31 TwWR Pulse Width 350- - 220' - 135' - 32 TdCf(WRr) Ciock I to i Delay - 50 - 70 100 - 33 TdD(WRf) Data Stable prior to T R I 20' - -10' - -55. - 34 TdCr('NRf) Clock 1 t o m 1 Delay - 60 - 55 - 60

35 -TdWRr(D) - Data Stable from I - 120.- 50' --------- 10' - 36 TdCf(HALT1 Clock I to ii*iT f or 1 - 300 - 300 - 260 37 TwNMI NMI Pulse Width 80 - 80 - 70 - 38 TdUSREC(Cr) =Q Setup Time to Clock 1 80 - 90 - 50 -

'For c!ocr permcr c:%r ihan :he rnlnrnurrs niiown ~n !he ! a h . caicuiaie jaramelerr urmq the exprerriocs ~n :cs !a& on :he !o!tou>nq wge.

-

AC 280 CPU ZBOA CPU ZBOB C Charac- Min Max Min Max Min I teristics Number Symbol Parameter (N) (N) (N) (N) (as1 I

(Continued) 3 ThSUSiiEQ(Cr) BUSREQ Hold Time alter Clock I 0 - 0 - 0 40-TcC:(BUSAC.YI)-Clock I to BUSACY. I Deiay 120-100 - 41 TdCl(3USACY.:) Clock I to BUSACK I Deiay - ilC - 100 - 42 TdCr:Dz) Clock 1 to Data Float Delay - 00 - 90 - 43 TdCr(CT;) Clock I to Control 0utpu:s Float - 110 - 80 -

DelayJMREQ. IORQ. W. and WR)

44 TiCr(Az) Clock 1 to Address Float Delay - 110 - 90 - 45 - TdCTr(A) - Address Stage aiter E Q I ,- 160' 80' - 35' -

W Q I . RD 1, andm t

46 TsRESET(Cr) RESET to Clock 1 Setup Time 90 - 60 - 60 47 ThRESET(Cr) ST to Clock 1 Hold T~me - 0 - 0 - 48 TsINTf(C:) KT to Clock I Setup Tlme 80 - 80 - 70

49 ThINTr(Cr) INT to Clock I Hold Time - 0 - 0 - SO - ~ d ~ l f ( 1 0 ~ Q f ) - W I to WQ 1 Delay - 920' - 565' - 365' - 51 TdCf(I0RQf) Clock I to RQ I Delay - 110 - 85 - 52 TdCl(I0RQr) Clock 1 to mQ 1 Delay - 100 - 85 - 53 TdC!!DI Clock I to Data Valid Delay - 230 - 150 -

- -

'Far ciock ~ ~ : > S G S o!her :ha" :he rnlnlrnvrna shown In the !abie. ;aiculace para-ereis uslnq :he loiiowlnq expresstons. Caicuiated .,atues s w v e arrumec TrC = TfC = 20 ns.

Footnotes to AC Characteristics

Numbsr Symbol 280 ZBOA Z8OB

I TcC TwCh + TwCl + TrC + TIC TwCh + TwCl + TrC +TIC TwCh + TwC! + TrC +

2 TwCh Although slatlc by destgn. Although statrc by dengn. Although statlc by des~on. TwCh of greater than 200 pr TwCh 01 greater than 200 ps TwCh ol greater than 200 1 n not guaranteed 19 not guaranteed is not guaranteed

7 - TdAlMREQ1)-TwCh + TIC - 75 - TwCh + TIC - 65- TwCh + TIC - 50 - 10 TwMREQh TwCh 7 TIC - 30 TwCh * TIC - 20 TwCh + TIC - 20

11 TwMREQI TcC - 40 TcC - 30 TcC - 30

26 TdA(IORQ1) TcC - 80 TcC - 70 TcC - 55

29 TdD(WRI) TcC - 210 TcC - 170 TcC - 140

31- TwWR- TcC - 40 TcC - 30 TcC - 30

33 TdD(WR0 TwCI + TrC - 180 TwCl + TrC - 140 TwCI + TrC - 140

35 TdWRrlD) TwCI + TrC - 80 TwCl + TrC - 70 TwCl + TrC - 55

45 TdCT;(A) TwCi + TrC - 40 TwCl + TrC - SO TwCl * TrC - 50

50 TdMIl(I0RQl) 2TcC + TwCh + TIC - 80 2TcC + TwCh + TIC - 69 2TcC + TwCh + TIC - t

Absolute Storage Temperature. . . . . . . . -6SaC to + lSO°C Stresses Greater :.?an those i~rted under r\bsol*:e Maxi- Maximum Ratings

Temperature under Bias . . . . . . . .Specified operating range

Voltages on all inputs a n d ouiouts w ~ t h respect to ground . -0.3 V io + 7 V

Power Dissipation . . . . . . . . . . . . . . . . . . . . l . 5 W

mum Raanqr may cause permanenr damage :o ~5.e device. This 1s a sireas ratinq only: aperailon 01 the devlce at any condit~an m o v e those lncicaied ~n the aperatrond sec:lons of :hese s.cec~i!cat~or.s IS not ~mpi~ed. Exposure to absoiute rr.ax\murn ratmq cor.a~:ions ior sxrendec perlads nay aiiect dev;ce rellabtli!y.

S tandard The characteristics below apply for :he Test ioilowlna standard :est condit;cns, unless Conditions o:herw~se noted. A!l voltages a r e reierenced to

GND ( 0 V). Positive current f!ows into the referenced pin. Available operat1r.g temperature ranges are:

0 ° C to +7OoC, A 4.75 V s Vcc c + 5.25 V

-40°C to +8S°C, +4.75 V c Vcc c +5.25 V

# -55°C to + 12S°C. + 4 . 5 v 5 vcc 5 + 5 . 5 v

All a c parameters assume a ioac capac:!ance oi 50 pr'. Add !0 ns delay- for each 50 pF Increase in !cad u p :O a maximum ci 200 p? !or :be aara bus and 100 pF ior address and control Ilnes.

PROM OUTPUT UNDER TEST

DC Symbol Parameter Character- istics V ! ~ ~ Clock Input Low Voltage

V i ~ ~ Clock Input High Vollage VIL Input Low Voltage VIE Input Hlqh Voltage VOL Output Low Voltage VDH Output High Voltage k c Power Supply Current

ZEO ZEOA 2808

IL~ Input Leakage Current

- --

Min Max Unit Test Condition

-0.3 0.45 V

Vcc- 6 Vcc+ .3 V -0.3 0.8 V

2.0 v,, v 0 4 V b ~ = l . E n A

2.4 V b;~ = -250 PA

!LEAK 3-State Output Leakage Current in Float -10 lo3 pA V~~~=O.~~OV~- 1. Far mlil:avj ;race par::. !cc :5 iCO mA 3 .Af5-&, +DO. m. %. m, 3nd Fa . 2. igptcal rate :or BOA :r SO n A .

- --

Capaci tance Symbol Parameter Min Max Unit Note

CCLx:.: Clock Capac~tance 35 pP

c!x !npui Capacitance j p~ Unmeasured plns

COG: Output Capacltance returned ro ground

10 pF

-- --

Ordering Product Package/ Product Package/ Information Number Temp Speed Description Number Temp Speed Description

28400 CE 2.5 MHz ZS0 CW (40-pin) 28400E. DE 4.2 .Mi: ZEOA CPU (40

S4CO CX! 2.5 MAz Same as above Z8400A DS L C 4!Ez Same as above

Z8:ciO CMB 2.5 MHz Same as above B400F. P2 4.9 MHz Same as above

284CC CS 2.5 MHz Same as above Z8400A ?S 4.3 !4Ez Same as abow

ZSSCC 9 E 2.5 b!Hz Same as above Z8400B CE 6 3 : 2803 C?U !4G-

ZBr3O . DS 2.5 Miiz Sarne as above 3 4 c J 32 2.5 MHz Same as above

28100 PS 2.5 MHz Same as above

Z64COA C F 4.0 MHz ZSOA CPU (40-pin)

2340OA CM 4.0 MHz Same as above

23400A CMB 4.0 MHz Same as above

284OOA CS 4.0 MHz Same as above

!:OTES: C = C?:an>c. D = Cerd~p, ? = Plesttc: E = -4O'C :a -85 M!L-$73-683 C:ds 3 i.:ocessinq, S = O'C :m -7O.C.

284006 CM 5.: :"!Hz Same as aDCVE

Z8100B CMB 6.: .LIE: S-me an above

284009 CS 6.3 !d4z Same as above

Z8400B DE 6.3 MEz Same as acove

284009 DS 6.3 ! Same as abovt

Z8400B PE 6.5 MEz Same as abovt

Z8400B PS 6.0 SIEz Same as abovt

*c. M = -55'~ :o + I:~:c. :d5 = - 5 5 : ~ .o - ; z ~ - c