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640 Gbits/s photonic logic gates Antonella Bogoni, 1,2, * Xiaoxia Wu, 1 Zahra Bakhtiari, 1 Scott Nuccio, 1 and Alan E. Willner 1 1 Department of Electrical Engineering, University of Southern California, Los Angeles, California 90089, USA 2 Consorzio Nazionale Interuniversitario per le Telecomunicazioni (CNIT), Pisa, Italy *Corresponding author: [email protected] Received September 1, 2010; revised October 20, 2010; accepted October 20, 2010; posted October 26, 2010 (Doc. ID 134336); published November 23, 2010 We demonstrate 640 Gbits=s all-optical A AND B, and A AND B logic functions using pump depletion in a periodi- cally poled lithium niobate waveguide. Bit-error-rate measurements show the effectiveness of the scheme, with a penalty of <2 dB. © 2010 Optical Society of America OCIS codes: 200.4740, 060.4510. Ultrafast logic operations in the optical domain can po- tentially enable digital-signal-processing functions at a the high-speed transmission line rate such that network latency can be decreased or performance can be in- creased. Similar to electronic systems, even a few simple logic operations at very high speeds can dramatically im- prove system efficiency. Previously, there have been several demonstrations of logic functions AND/OR/XOR up to 40 Gbits=s based on different nonlinear media, such as optical fiber [1] or semiconductor devices [2]. An AND logic gate has been partially demonstrated, exploiting a nonlinear waveguide in demultiplexing experiments up to 1:28 Tbits=s[3]. Moreover, periodically poled lithium niobate (PPLN) waveguides have been used to demonstrate a demulti- plexer (essentially an AND gate) [4], half-adder and half- subtractor [5] at 160 Gbits=s combining sum frequency generation and difference frequency generation (SFG/ DFG) and pump depletion nonlinear processes. Funda- mental logic operations (i.e., XOR, OR, and half- subtractor, etc.) can be also obtained as a combination of simpler logic gates, such as A AND B, and A AND B [5], enabling the implementation of ultrafast logic op- erations. In addition, recent results show the possibility of using PPLN waveguides at room temperature to avoid the power consumption due to the temperature control [6]. In this Letter, we implement the logic gates A AND B, and A AND B at 640 Gbits=s, exploiting only the pump depletion effect in a PPLN waveguide for onoff keying signals. In this way, we can overcome the speed limita- tions imposed by group velocity mismatch in the SFG/ DFG processes. The obtained logic gates can enable XOR, half-subtraction, and OR operation. Bit-error-rate (BER) measurements confirm a penalty of <2 dB for both the presented logic gates. This represents a fourfold increase in bit rate when using a single nonlinear element for demonstrating fast optical logic functions [5]. As shown in Fig. 1, logic operations are obtained by nonlinear interaction between two synchronized in- coming 640 Gbits=s optical time division multiplexing (OTDM) signals A and B. In our implementation, the non- linear processing element is a PPLN waveguide. At the output of the nonlinear devices, the two signals at the wavelengths of signals A and B represent the two logic functions A AND B, and A AND B as explained in the following. Figure 2 shows the typical two pump configuration of a PPLN waveguide for nonlinear processing. The two pumps, A and B, can nonlinearly interact, and SFG oc- curs under the quasi-phase-matching condition (QPM). The generated signal can simultaneously interact with a cw to produce an idler in the C-band through the DFG process. However, the SFG/DFG processes suffer from group velocity mismatch between the signals in the C- band and the converted signal at the sum frequency, which leads to the broadening of the idler signal [7]. To overcome these limitations and obtain high bit-rate operations, we utilize only the pump depletion effect due to SFG, which occurs when both pumps are present. In our experiment, the two pumps correspond to two 640 Gbits=s OTDM signals. Looking at the 640 Gbits=s OTDM signals at the output of the PPLN, we can observe that they are depleted by the SFG interaction when both of the signals are present. In other cases, they can pass through the PPLN waveguide without noticeable distor- tions. As a consequence, the outputs are at low levels (bit 0s) in the case of both input signals at high levels, while they maintain their levels in the other cases where SFG does not occur. Therefore, they supply logic functions A AND B and A AND B at the pump A and B wavelengths, respectively. As shown in [5], the pump depletion effects cannot be simultaneously maximized for both pumps, since simultaneous optimization will decrease the system performance. Therefore, when the pump depletion is op- timized for the OTDM signal A, we get the A AND B logic function. A AND B logic operation is obtained when the depletion is optimized for OTDM signal B. The use of two PPLN waveguides allows us to simultaneously obtain both logic gates. In this case, additional amplification stages can be possibly avoided by amplifying both input signals to the highest required value (27 dBm) increased Fig. 1. (Color online) Concept of the logic gate based on pump depletion in PPLN waveguide. December 1, 2010 / Vol. 35, No. 23 / OPTICS LETTERS 3955 0146-9592/10/233955-03$15.00/0 © 2010 Optical Society of America

Photonic Logic Gates at 640 Gbits/sec

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Photonic logic gates using pump depletion in PPLN.

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Page 1: Photonic Logic Gates at 640 Gbits/sec

640 Gbits/s photonic logic gatesAntonella Bogoni,1,2,* Xiaoxia Wu,1 Zahra Bakhtiari,1 Scott Nuccio,1 and Alan E. Willner1

1Department of Electrical Engineering, University of Southern California, Los Angeles, California 90089, USA2Consorzio Nazionale Interuniversitario per le Telecomunicazioni (CNIT), Pisa, Italy

*Corresponding author: [email protected]

Received September 1, 2010; revised October 20, 2010; accepted October 20, 2010;posted October 26, 2010 (Doc. ID 134336); published November 23, 2010

We demonstrate 640 Gbits=s all-optical A AND �B, and �A AND B logic functions using pump depletion in a periodi-cally poled lithium niobate waveguide. Bit-error-rate measurements show the effectiveness of the scheme, with apenalty of <2 dB. © 2010 Optical Society of AmericaOCIS codes: 200.4740, 060.4510.

Ultrafast logic operations in the optical domain can po-tentially enable digital-signal-processing functions at athe high-speed transmission line rate such that networklatency can be decreased or performance can be in-creased. Similar to electronic systems, even a few simplelogic operations at very high speeds can dramatically im-prove system efficiency.Previously, there have been several demonstrations of

logic functions AND/OR/XOR up to 40 Gbits=s based ondifferent nonlinear media, such as optical fiber [1] orsemiconductor devices [2]. An AND logic gate has beenpartially demonstrated, exploiting a nonlinear waveguidein demultiplexing experiments up to 1:28 Tbits=s [3].Moreover, periodically poled lithium niobate (PPLN)waveguides have been used to demonstrate a demulti-plexer (essentially an AND gate) [4], half-adder and half-subtractor [5] at 160 Gbits=s combining sum frequencygeneration and difference frequency generation (SFG/DFG) and pump depletion nonlinear processes. Funda-mental logic operations (i.e., XOR, OR, and half-subtractor, etc.) can be also obtained as a combinationof simpler logic gates, such as A AND �B, and �A ANDB [5], enabling the implementation of ultrafast logic op-erations. In addition, recent results show the possibilityof using PPLN waveguides at room temperature toavoid the power consumption due to the temperaturecontrol [6].In this Letter, we implement the logic gates A AND �B,

and �A AND B at 640 Gbits=s, exploiting only the pumpdepletion effect in a PPLN waveguide for on–off keyingsignals. In this way, we can overcome the speed limita-tions imposed by group velocity mismatch in the SFG/DFG processes. The obtained logic gates can enableXOR, half-subtraction, and OR operation. Bit-error-rate(BER) measurements confirm a penalty of <2 dB forboth the presented logic gates. This represents a fourfoldincrease in bit rate when using a single nonlinear elementfor demonstrating fast optical logic functions [5].As shown in Fig. 1, logic operations are obtained by

nonlinear interaction between two synchronized in-coming 640 Gbits=s optical time division multiplexing(OTDM) signals A and B. In our implementation, the non-linear processing element is a PPLN waveguide. At theoutput of the nonlinear devices, the two signals at thewavelengths of signals A and B represent the two logicfunctions A AND �B, and �A AND B as explained in thefollowing.

Figure 2 shows the typical two pump configuration of aPPLN waveguide for nonlinear processing. The twopumps, A and B, can nonlinearly interact, and SFG oc-curs under the quasi-phase-matching condition (QPM).The generated signal can simultaneously interact with acw to produce an idler in the C-band through the DFGprocess. However, the SFG/DFG processes suffer fromgroup velocity mismatch between the signals in the C-band and the converted signal at the sum frequency,which leads to the broadening of the idler signal [7].

To overcome these limitations and obtain high bit-rateoperations, we utilize only the pump depletion effect dueto SFG, which occurs when both pumps are present. Inour experiment, the two pumps correspond to two640 Gbits=s OTDM signals. Looking at the 640 Gbits=sOTDM signals at the output of the PPLN, we can observethat they are depleted by the SFG interaction when bothof the signals are present. In other cases, they can passthrough the PPLN waveguide without noticeable distor-tions. As a consequence, the outputs are at low levels (bit“0”s) in the case of both input signals at high levels, whilethey maintain their levels in the other cases where SFGdoes not occur. Therefore, they supply logic functions AAND �B and �A AND B at the pump A and B wavelengths,respectively. As shown in [5], the pump depletion effectscannot be simultaneously maximized for both pumps,since simultaneous optimization will decrease the systemperformance. Therefore, when the pump depletion is op-timized for the OTDM signal A, we get the A AND �B logicfunction. �A AND B logic operation is obtained when thedepletion is optimized for OTDM signal B. The use of twoPPLN waveguides allows us to simultaneously obtainboth logic gates. In this case, additional amplificationstages can be possibly avoided by amplifying both inputsignals to the highest required value (27 dBm) increased

Fig. 1. (Color online) Concept of the logic gate based on pumpdepletion in PPLN waveguide.

December 1, 2010 / Vol. 35, No. 23 / OPTICS LETTERS 3955

0146-9592/10/233955-03$15.00/0 © 2010 Optical Society of America

Page 2: Photonic Logic Gates at 640 Gbits/sec

by 3 dB due to the use of a consecutive 50=50 optical cou-pler and, then, inserting two power unbalancing stageson the two PPLN waveguide inputs in order to optimizethe single power levels. This scheme requires an addi-tional 6 dB power cost than performing the operationwith independent amplifications, but reduces the overallcost.Note that pump depletion in the PPLN waveguide

introduces little distortion on the pumps. Residualchromatic dispersion induced broadening can be com-pensated using the proper amount of dispersion compen-sating fiber.In addition, as summarized in Fig. 3, by coupling to-

gether the two outputs we can obtain the logic operationXOR. At the same time, the XOR output represents thedifference between A and B, and the output signals atλA and λB individually give the function Borrow (B-A)and Borrow (A-B) respectively, allowing us to obtain ahalf-subtractor. Finally, by coupling together the inputsignal B and the output signal at λA or the input signalA and the output signal at λB, we can obtain the A ORB function.Notice that ultrafast nonlinear effects involved in the

PPLN waveguide keep the phase information [8]; conse-quently, they can be exploited for implementing logicfunctions also with phase-shift keying signals [9].Figure 4 shows the experimental setup. A 40 GHz

mode-locked laser (MLL) producing∼1 ps pulses at λC ¼1542 nm is modulated at 40 Gbits=s by using a 27 − 1PRBS sequence and then split into two branches. Thefirst one is directly 40-to-640 Gbits=s multiplexed byusing an optical-fiber-based multiplexer. The multiplexerhas a polarizer at the output so that the 16 tributarychannels in the 640 Gbits=s data frame have aligned po-larizations. Additionally, the PPLN waveguide requirespolarization aligned signals at its input to maximize theconversion efficiency. The second branch is used to

generate a 40 Gbits=s supercontinuum spectrum throughpropagation in a 200 m piece of highly nonlinear fiber(HNLF) with a chromatic dispersion value of −0:85 ps=nm=km at 1550 nm and a dispersion slope of 0:01 ps=nm2=km. We then filter the supercontinuum spectrumto obtain the 40 Gbits=s data signal at λS ¼ 1560 nm. An-other 40-to-640 Gbits=s optical-fiber-based multiplexerproduces the second 640 Gbits=s OTDM signal. Also, thismultiplexer has a polarizer at the output so that the 16tributary channels in the 640 Gbits=s data frame havealigned polarizations. We use polarization controllers(PCs) for both the 640 Gbits=s OTDM signals before theyare coupled, amplified, and sent into the PPLN wave-guide. To obtain the A AND �B logic operation, the peakpowers used are 16 and 27 dBm for the OTDM signals Aand B, respectively. The reverse power levels are usedfor the case of obtaining the �A AND B logic function,i.e., 27 dBm peak power for OTDM signal A and16 dBm for B. The input pulse widths are∼1 and∼0:9 psfor signal A and B, respectively. The length, loss, domaininversion period, effective cross-section area, and theQPM bandwidth for SFG/DFG of the PPLN waveguideare ∼5 cm, ∼5 dB, ∼15 μm, ∼50 μm2, and 0:6 nm, re-spectively. The total loss between input fiber and outputfiber is ∼13 dB and the waveguide temperature is set at∼92 °C. At the output of the PPLN waveguide, two cas-caded tunable bandpass filters (BPFs) and a low-noiseerbium-doped fiber amplifier are used to extract the de-sired logic gate. Finally, a 640-to-40 Gbits=s nonlinear-optical-loop-mirror (NOLM)-based optical demultiplexeris used to test the performance of the involved signals. A100 mHNLF with a zero dispersion wavelength (ZDW) of1558 nm and a dispersion slope of 0:02 ps=nm2=km isused in the NOLM. The 40 GHz clock with ∼1 ps pulsewidth for demultiplexing is obtained by splitting the out-put of the MLL. Depending on the wavelength of the sig-nal under test, a supercontinuum-based wavelengthconverter is used to tune the clock wavelength. Super-continuum generation is obtained through propagation

Fig. 2. (Color online) Nonlinear processing in a PPLN wave-guide. A and B generate an SFG signal that interacts with the cwto generate the idler signal by DFG.

Fig. 3. (Color online) Logic functions implemented exploitingpump depletion in a single PPLN waveguide (left). Enabled lo-gic operations (right).

Fig. 4. (Color online) Experimental setup. MLL, mode-lockedlaser; ODL, optical delay line; MZM, Mach–Zehnder modulator;BPF, bandpass filter; SC, supercontinuum; HNLF, highly non-linear fiber; PPLN, periodically poled lithium niobate.

Fig. 5. Eye diagrams of 640 Gbits=s signals at the PPLNwaveguide input and output.

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Page 3: Photonic Logic Gates at 640 Gbits/sec

in a 500 m piece of HNLF with a ZDW of 1565 nm and adispersion slope of ∼0:017 ps=nm2=km.Figure 5 shows the eye diagrams of the involved sig-

nals at the input and output of the PPLN waveguide. Notethat the input eye diagrams are captured with a more op-timized polarization condition at the input of the OTDMmultiplexers, generating better equalized channels.Moreover, different channels in the aggregate eye dia-gram could not be distinguished. Consequently, the fewchannels reported in the output eye diagrams do not ne-cessarily correspond to the input ones. The eye diagramsconfirm that the pump depletion effect introduces littledistortions on both the OTDM frames. We can see thatthe pulse width of the involved signals is slightly broa-dened by the residual chromatic dispersion.Figure 6 shows 640 Gbits=s BER performance. BER

measurements are made on the original 40 Gbits=s sig-nals, the 40 Gbits=s demultiplexed tributary channelsof the input 640 Gbits=s signals, and the 40 Gbits=s tribu-tary channel of the A AND �B, and �A AND B. The BERcurves are reported versus the peak power in order totake into account the different sequences of the inputand output signals. Note that, for the sake of clarity,we report here the BER performance concerning justone of the tributary channels. It is verified that the powerpenalty variations (evaluated at BER ¼ 10−9) for all thechannels are within 2:2 dB, partially due to the non-perfect channel equalization during the optical multi-plexing operation. From Fig. 6, we can see that the

demultiplexing of the back-to-back 640 Gbits=s signal in-troduces about a 2:5 dB power penalty with respect tothe back-to-back 40 Gbits=s case, while the logic opera-tions present a penalty of lower than 2 dB, for both theconsidered logic functions, with respect to the demulti-plexed input 640 Gbits=s signals. The required energy/bitfor the operations in this demonstration is about0:5 pJ=bit, considering all the coupling loss of the PPLNwaveguide. A further reduction of power consumption ispossible by use of devices with improved coupling losses.

We demonstrated logic functions for on–off keying sig-nals at 640 Gbits=s, exploiting only pump depletion in aPPLN waveguide, which overcomes the distortions in-duced by SFG/DFG nonlinear effects. 640 Gbits=s AAND �B, and �A AND B logic gates are obtained with apower penalty of <2 dB, which can enable XOR, OR,and half-subtraction operations. The results show the ef-fectiveness of using PPLN waveguides as compact andhigh efficiency nonlinear elements in all-optical signalprocessing for ultrahigh-bit-rate optical networks.

We acknowledge the support of Defense Advanced Re-search Projects Agency (DARPA) (contract FA8650-08-1-7820) and the U.S.–Italy Fulbright Commission. We thankProf. Martin Fejer’s group at Stanford University for pro-viding the PPLN waveguide.

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Fig. 6. (Color online) BER curves of one of the 40 Gbits=s tri-butary channels of the 640 Gbits=s OTDM frame at differentpoints of the setup.

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