IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 9, SEPTEMBER 2013 2703

Phase Change Liner Stressor for Strain Engineeringof P-Channel FinFETs

Yinjie Ding, Student Member, IEEE, Ran Cheng, Student Member, IEEE, Shao-Ming Koh, Student Member, IEEE,Bin Liu, and Yee-Chia Yeo, Member, IEEE

Abstract— A novel Ge2Sb2Te5 (GST) liner stressor for enhanc-ing the drive current in p-channel FinFETs (p-FinFETs) isdemonstrated. When amorphous GST changes phase to crys-talline GST (c-GST), the GST material contracts. This phe-nomenon is exploited for strain engineering of p-FinFETs.A GST liner stressor wrapping a p-FinFET can be shrunk orcontracted to generate very high channel stress for drive currentenhancement. Saturation drain current enhancement of ∼80%and linear drain current enhancement of ∼110% are observedfor FinFETs with c-GST liner stressor over the control orunstrained FinFETs. The drain current enhancement is higherfor 0° rotated FinFETs as compared with that of the FinFETswith 45° rotation, due to the orientation-dependent piezoresis-tance coefficients. The drain current enhancement increases withdecreasing gate length. GST liner stressor could be a strainengineering option in sub-20-nm technology nodes.

Index Terms— FinFET, Ge2Sb2Te5 (GST), multigate FET,phase change, strain.

I. INTRODUCTION

F inFETs or multigate transistors exhibit excellent con-trol of short-channel effects (SCE), and have been

adopted by the semiconductor industry at the 22-nm tech-nology node and beyond [1]–[15]. Various strain engineer-ing or mobility enhancement techniques were reported toenhance the transistor drive current IDsat. High-stress sili-con nitride (SiN) liner stressor or contact etch stop layerhas been adopted in the manufacturing of integrated cir-cuits based on planar transistors. In FinFETs, significantIDsat enhancement can also be achieved using the SiNliner stressor [8]–[12]. In p-channel FinFETs (p-FinFETs),diamond-like carbon (DLC) liner stressor has been demon-strated for strain engineering [13], [16]. DLC has an intrinsiccompressive stress of up to 10 GPa significantly greaterthan that of SiN and allows a higher channel stress tobe induced for a given liner thickness. DLC liner stressorhas been reported to give significant IDsat enhancement forp-FinFETs [13], [16]. The key concept of the abovementioned

Manuscript received March 31, 2013; revised May 22, 2013 and June 12,2013; accepted June 25, 2013. Date of publication July 17, 2013; date ofcurrent version August 19, 2013. This work was supported by the NationalResearch Foundation under Grant NRF-RF2008-09. The review of this paperwas arranged by Editor W. Tsai.

The authors are with Department of Electrical and ComputerEngineering, National University of Singapore, 117576 Singapore (e-mail:g0900276@nus.edu.sg; chengran@nus.edu.sg; shaomingkoh@nus.edu.sg;liubin@nus.edu.sg; yeo@ieee.org).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2013.2271643

SiN or DLC liner stressors is the mechanical coupling of theintrinsic stress from the liner to the FinFET channel.

Very recently, we demonstrated a new concept for strainengineering, where a liner material is formed over a tran-sistor and then configured to change volume postdeposi-tion, so as to induce mechanical stress in the channel.Phase change chalcogenide materials may be used as aliner material where such volume change may be effectedpostdeposition. For example, the liner material may beGe2Sb2Te5 (GST) When GST undergoes crystallization orphase change from the amorphous state (α-GST) to thecrystalline state (c-GST), its mass density increases and itsvolume is reduced. The mechanical stress induced by theGST contraction could be exploited for strain engineering ofp-FinFETs and initial results were reported in [17].

In this paper, we report details of the process developmentand integration of GST liner stressor for p-FinFETs, as wellas further analysis of the electrical characteristics. Extensiveelectrical characterization was performed and the performanceenhancement induced by the GST liner stressor will bediscussed.

II. KEY CONCEPT: GST AS SHRINKABLE LINER

STRESSOR

In this section, the volume reduction or contraction becauseof the change of phase of GST from amorphous to crystallineis discussed. The contraction or shrinkage of the as-depositedα-GST is a physical phenomenon that is exploited in this paperfor transistor strain engineering.

An experiment was carried out to investigate the amount ofvolume change during the GST phase conversion. A 70-nm-thick α-GST was deposited on a Si substrate, followed by a200 °C anneal for 10 min. The anneal crystallized the α-GST,forming c-GST with a reduced thickness. It is well known thatthe amorphous and crystalline phases of GST can be reversiblychanged. After crystallization of GST, we converted a selectedregion of the c-GST back into α-GST by a rapid laser-inducedmelt-quench process. A KrF excimer laser with a wavelengthof 248 nm and a pulse duration of 23 ns was used to irradiatec-GST in a 2 mm by 2 mm area in N2 ambient. The c-GSTin this area was melted during the ultrashort laser irradiationand the rapid cooling after the laser pulse converted it to theamorphous phase.

A scanning electron microscopy (SEM) image [Fig. 1(a)]shows the top view of a sample having α-GST and c-GSTregions adjacent to each other [Fig. 1(b)]. Examination of

0018-9383 © 2013 IEEE

2704 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 9, SEPTEMBER 2013

10 nm5 nm

0 5 nm

10 nm

α-GST

c-GST30 nm

15 nm

α-GST

c-GST

α-GSTc-GST

Si Substrate

~ 70 nm

~ 65 nm

(b)(a)

(c) (d)α-GST c-GST

~ 70 nm ~ 65 nm

50 nm

Fig. 1. (a) SEM image showing the top view of a c-GST sample with a partof it being selectively converted to α-GST using a shaped excimer laser beam.A single pulse of homogenized laser beam with a fluence of 150 mJ/cm2 wasused. (b) Illustration of α-GST and c-GST regions adjacent to each other. (c)Cross-sectional SEM image is shown that the thicknesses of the α-GST andc-GST regions are 70 and 65 nm, respectively. (d) Atomic force microscopy(AFM) scan across the boundary between the α-GST and c-GST regionsobtains a thickness difference of ∼5 nm.

the cross-sectional SEM image in Fig. 1(c) shows that thethicknesses of the α-GST and c-GST are 70 and 65 nm,respectively. Atomic force microscopy (AFM) was also usedto scan the boundary region between the α-GST and the c-GST regions [Fig. 1(d)]. The thickness difference between theα-GST and c-GST layers is ∼5 nm, which is consistent withthe SEM observation in Fig. 1(c). We therefore deduced thatthe c-GST has a 7% volume reduction as compared with theα-GST. This is consistent with reported values in [18] and[19].

Fig. 2(a) shows a GST liner stressor wrapped around aFinFET. Coordinate axes are also shown. Fig. 2(b) showsthe key concept of this paper using cross section schematicsof the transistor in the A-A′ plane (xz plane cutting throughgate line and perpendicular to fin) and B-B′ plane (yz planecutting through fin and perpendicular to gate line). The lineris amorphous when first formed over the FinFET. When GSTundergoes phase change or crystallization from α-GST toc-GST, the volume contraction causes it to constrict or tightenits grip on the FinFET structure. In the A-A′ plane, a largecompressive strain εxx and εzz can result from the GSTcontraction. The B-B′ plane view shows that the contractedc-GST increases the lateral compression εyy (source-to-draindirection) in the channel. The strain induced by GST in theFinFET channel was studied using nano beam diffraction andwas documented in [20].

III. FABRICATION OF STRAINED P-FINFETS WITH GSTLINER STRESSOR

The 8-in silicon-on-insulator wafers with Si thickness of35 nm were used for FinFET fabrication. A 248-nm deepultraviolet lithography was used for active patterning, followedby dry etching to define the fins. The fin height Hfin is35 nm and fins with width Wfin down to 40 nm were formed.SiO2 gate dielectric of 3 nm was thermally grown. This was

z <001>

x <110>

y <110>

A

A’B

B’

α-GST

c-GST

Amorphous

Crystalline

α-GST

BOXSi Substrate

Gate

α-GSTGate

Fin

BOXSi Substrate

A - A’

c-GST

BOXSi Substrate

Gate

c-GST Gate

GST Liner Contraction or Crystallization

Increased Lateral Compressive Stress

GST Contracts as itCrystallizes

B - B’

Fin Fin

BOXSi Substrate

(a)

(b)

Fig. 2. (a) 3-D schematic view of a FinFET wrapped around by GST linerstressor. Coordinate axes are also shown. When GST crystallizes, its volumeis reduced by ∼7%. (b) Cross section obtained in the A-A′ plane illustratingthe large compressive strain εxx and εzz that can result from GST contraction.The B-B′ plane view is shown that the contracted c-GST liner increases thecompressive strain εyy in the channel in the source-to-drain direction.

followed by poly-Si gate deposition and ion implantation ofboron. SiO2 hardmask was formed on the poly-Si gate, fol-lowed by gate definition using 248-nm lithography. Photoresistand hardmask trimming were sequentially performed. Poly-Sigate etch was performed using chlorine-based plasma dry etch.

After the gate etch, p+ source/drain (S/D) extension implantwas performed and SiN spacers were formed by chemicalvapor deposition of SiN followed by dry etch. After deepS/D implantation and dopant activation, the SiO2 hardmaskon the poly-Si gate was removed. A 10 nm of Ni was sputterdeposited and annealed to form NiSi on the gate and S/Dregions. Excess Ni was selectively removed with a sulfuricacid peroxide solution H2SO4 : H2O2 [4:1] at a temperatureof 120 °C for 120 s.

13 nm of SiO2 was deposited on the FinFETs by plasma-enhanced chemical vapor deposition, which provides electricalisolation between the device and the to-be-deposited GSTlayer. A thinner SiO2 layer is expected to improve the mechan-ical stress coupling between the GST stressor and the transistorchannel.

70 nm of α-GST was deposited by sputtering at room tem-perature using 100W dc power and at a pressure of 3 mTorr.A ∼10 nm of SiO2 cap layer was deposited on top of the GSTwithout breaking vacuum. Contact patterning and dry etchingusing inductively coupled fluorine-based plasma were done oncontrol and active devices, to remove SiO2 layer and SiO2/α-GST/SiO2 layers in the contact regions, respectively. A 200 °C

DING et al.: PHASE CHANGE LINER STRESSOR 2705

Fin DefinitionGate Stack and Spacer FormationS/D Implant and ActivationNickel SilicidationSiO2 Layer Depositionα-GST Liner and SiO2 Cap DepositionContact Patterning and EtchingGST Liner Contraction or Volume Reduction: Conversion of α-GST to c-GST

Process Flow for Strained FinFET(a) (b)

(c)

G

SD

G

S

D

Control FinFET

FinFET with c-GST

Fig. 3. (a) Process flow for fabricating p-FinFETs with GST liner stressor.GST deposition and liner contraction steps were skipped for the controlFinFETs. The SiO2 layer insulates the GST layer from the fin or the gate.(b) SEM image of control or unstrained p-channel FinFET. (c) SEM imageof p-channel strained FinFET with c-GST liner stressor.

50 nm

c-GST

S D

Buried OxideStrained-Si

SiO2

5 nm

c-GST

10 nm

Gate

(a) (c)

3 nm

1

1(b)

2

2

SiO2

Fig. 4. (a) Cross-sectional TEM image of a p-FinFET with c-GST stressorshowing a gate length of ∼30 nm. A FIB cut was performed in the source-to-drain direction across the gate. (b) Higher resolution TEM image showing thec-GST at region 1. Clear lattice fringes could be observed. GST crystallizationor contraction increases the compressive stress in the channel in the source-to-drain direction. (c) Higher resolution TEM image of the gate-stack (region 2).

10 min anneal was then performed for GST liner contraction,converting the α-GST to c-GST. The process flow is shownin Fig. 3(a). Fig. 3(b) and (c) shows the SEM images of thecontrol or unstrained FinFET and the strained FinFET withc-GST liner stressor, respectively. Electrical characterizationwas performed by probing the NiSi source, drain, and gatecontacts. In this paper, the probes on the NiSi in the S/Dregions are ∼50 μm from the gate edge. To ensure a faircomparison, only the α-GST deposition step was skipped forthe control or unstrained FinFETs.

A cross-sectional transmission electron microscopy (TEM)image of a FinFET with ∼70-nm-thick c-GST liner stressoris shown in Fig. 4(a). To obtain the TEM images in Fig. 4,focused ion beam (FIB) cut was performed in the channelregion across the gate in the source-to-drain direction. High-resolution TEM images show that the GST is crystallized[Fig. 4(b)]. The FinFET gate length is ∼30 nm as shownin Fig. 4(c). It is noted that the channel stress is not onlyintroduced by the intrinsic stress in the GST liner, but also bythe GST liner contraction during the phase conversion process.

To minimize the differences in electrical performancecaused by process variation across wafers or dies, the controland active FinFETs compared were processed on the same die.All devices were processed to the step before GST deposition,before the die was broken into pieces for the experimentalsplits.

(a) (b)

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| (μA/μm)

~66%

P-FinFET ControlP-FinFET with α-GST

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VD = -1.2 V

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= 45 nmL

G = 55 nm

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in C

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Gate Voltage VG (V)

P-FinFET ControlP-FinFET with α-GST

Fig. 5. (a) ID−VG characteristics of p-FinFETs with and without α-GST linerstressor showing comparable DIBL and SS. Gate length is 55 nm and fin widthis 45 nm. (b) Plot of off-state current |IOFF |(VG = VT,lin+ 0.2 V, VD = −0.05V) versus |IDlin|(VG = VT,lin–1.1 V,VD = −0.05 V). Wfin = 35 to 115 nm,and LG = 15 to 80 nm. At an off-state current |IOFF |of 10 nA/μm, FinFETswith α-GST liner stressor show ∼ 66% IDlin enhancement over the controlFinFETs. For each device split, ∼50 FinFETs were measured.

0

30

60

90

LG = 35 nm

Wfin

= 45 nm~ 81%

~ 30%

P-FinFETwith c-GST

P-FinFETwith α-GST

Dra

in C

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nt E

nhan

cem

ent (

%)

P-FinFET Control

Fig. 6. ∼30% and 81% IDsat (VG = VT,sat–1.1 V, VD = −1.2 V)enhancement were observed for p-FinFETs with α-GST and c-GST linerstressor, respectively, over the control FinFET. GST contraction duringamorphous-to-crystalline phase conversion induces stress that leads to furtherIDsat enhancement.

IV. ELECTRICAL CHARACTERISTICS AND DISCUSSION

Fig. 5(a) shows the ID−VG characteristics of FinFETs(LG = 45 nm andWfin = 115 nm) with and without α-GSTliner stressor. Both devices have similar drain induced barrierlowering (DIBL) and subthreshold swing (SS). Fig. 5(b) showsthe IOFF− IDlin characteristics of control FinFETs and FinFETswith α-GST stressor. At IOFF = 10 nA/μm, FinFETs withα-GST stressor show ∼66% IDlin enhancement over thecontrol FinFETs. This drain current enhancement is due tothe intrinsic compressive stress of α-GST (−332 MPa, asdetermined by wafer curvature measurement), similar to theeffect of SiN or DLC liner stressors with intrinsic compressivestress.

The IDsat enhancement for FinFETs with as-depositedα-GST and c-GST stressor, as compared with that for theunstrained FinFET is shown in Fig. 6. The intrinsic compres-sive stress in α-GST enhances hole mobility in p-FinFETs,resulting in ∼30% IDsat enhancement over the control.

When the GST is crystallized, the GST liner contractionor volume reduction increases the strain level in the channelfurther, leading to higher IDsat enhancement of ∼81% withrespect to the control. All the devices in Fig. 6 have the sameLG of 35 nm and Wfin of 45 nm.

FinFETs with c-GST stressor will be discussed next.Fig. 7(a) shows the ID−VG characteristics of FinFETs(LG = 45 nm and Wfin = 75 nm) with and without c-GST

2706 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 9, SEPTEMBER 2013

-1.8 -1.5 -1.2 -0.9 -0.6 -0.3 0.00

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Wfin = 75 nmLG = 45 nm

Dra

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μA/μ

m)

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P-FinFET Control P-FinFET with c-GST

(a) (b)

-2 -1 0 110-1310-1210-1110-1010-910-810-710-610-510-4

Tra

nsco

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e (μ

S)

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VD= -1.2V

VD= -0.05V L

G = 45 nm

Wfin

= 75 nm

P-FinFET Control P-FinFET with c-GST

0

15

30

45

Fig. 7. (a) ID−VG characteristics of p-FinFETs with and without c-GSTliner stressor showing similar DIBL and SS. The FinFET with c-GST hasa |VT,sat | that is slightly smaller (∼10 mV) than that of the control. Gatelength is 45 nm and fin width is 75 nm. Transconductance as a function ofgate voltage is also shown. The FinFET with c-GST liner stressor has a peaktransconductance improvement of ∼95% over the control FinFET. (b) ID−VDcharacteristics of the p-FinFET with c-GST liner stressor and the control,with gate length of 45 nm and fin width of 75 nm. Approximately 78% draincurrent enhancement over the control at gate overdrive of −1.2 V.

0 50 100 150 200 250 30010-11

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10-4

P-FinFET with c-GST

Off

-Sta

te D

rain

Cur

rent

|Iof

f| (A

/μm

)

Drain Current |IDsat

| (μA/μm)

P-FinFET Control

Fig. 8. Comparison of off-sate current |IOFF |(obtained at VG = VT,sat+0.2 V, VD = −1.2 V) versus |IDsat |(obtained at VG = VT,sat– 1.1 V, VD =−1.2 V) showing ∼88% IDsat enhancement for FinFETs with c-GST linerstressor over the control FinFETs at |IOFF |= 10 nA/μm. For each device split,∼60 FinFETs or data points were measured.

stressor. At a comparable SCE control such as DIBL, theFinFET with c-GST stressor has a slightly smaller thresholdvoltage than the unstrained FinFET. The band structure mod-ification by strain results in a narrowed energy bandgap andleads to a ∼10-mV reduction in the magnitude of the thresholdvoltage and higher leakage current [25]–[29]. Comparison ofthe saturation transconductance of these two devices as afunction of gate voltage is also shown in Fig. 7(a). The FinFETwith c-GST stressor has over 98% peak transconductanceenhancement over the control FinFET. Fig. 7(b) compares theID−VD characteristics of the devices in Fig. 7(a). ID is nor-malized by the device width (2Hfin +Wfin). IDsat enhancementof ∼78% was observed for the FinFET with c-GST stressorover the control FinFET at gate overdrive of −1.2 V. As theprocess flow is the same for these two devices except for theGST deposition and liner contraction, the difference in IDsatis due to the c-GST stressor. The drive current enhancementis consistent with the transconductance enhancement shown inFig. 7(a).

The IOFF −IDsat and IOFF − IDlin characteristics ofFinFETs with and without c-GST stressor are shown inFigs. 8 and 9, respectively. At a fixed IOFF of 10 nA/μm,we observe an enhancement in IDsat and IDlin of ∼88% and117%, respectively. For each device split in Figs. 8 and 9,

0 5 10 15 2010-11

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Off

-Sta

te D

rain

Cur

rent

|Iof

f| (A

/ μm

)

Linear Drain Current |IDlin

| (μA/μm)

P-FinFET with c-GST

Fig. 9. Plot of off-state current |IOFF |(obtained at VG = VT,lin+ 0.2 V, VD =−0.05 V) versus |IDlin|(obtained at VG = VT,lin– 1.1 V,VD = −0.05 V).At |IOFF |= 10 nA/μm, ∼117% IDlin enhancement for FinFETs with c-GSTliner stressor over the control FinFETs is observed. For each device split, ∼60FinFETs were measured.

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%)

Gate Length LG (nm)

Wfin

= 40 nm

0

20

40

60

80

100

120

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in C

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nt | I

Dsa

t| (μA

/μm

)

IDsat

Enhancement

Fig. 10. Comparison of IDsat (obtained at VG = VT,sat– 1.1 V, VD =−1.2 V) for p-FinFETs with and without c-GST liner stressor at different gatelengths. As gate length is reduced, the IDsat of FinFETs both with and withoutc-GST stressor increases. IDsat enhancement as a function of gate length isalso plotted. IDsat enhancement increases with decreasing gate length. Thestandard deviation of IDsat for a given Wfin and LG is shown as error bars.Enhancement values were calculated using the mean IDsat.

∼60 devices were measured. The observed IDsat enhancementinduced by the c-GST liner stressor is higher than thoseinduced by SiN and DLC stressors [12], [16].

The IDsat of FinFETs with and without c-GST stressor arecompared at different LG (from 15 to 55 nm) with a fixedWfin of 40 nm in Fig. 10. When gate length is reduced, IDsatgenerally increases. The IDsat of FinFETs with c-GST stressoris higher than that of the control FinFETs without stressorfor all LG . In addition, the current enhancement is higherfor smaller LG , which is attributed to higher strain inducedby the c-GST stressor at smaller LG . This trend is consis-tent with simulation results of FinFETs with SiN and GSTliners [31], [32].

To illustrate the effect of fin width on IDsat enhancement, theIDsat of p-FinFETs with and without c-GST stressor and IDsatenhancement as a function of Wfin for a fixed LG are shownin Fig. 11. IDsat enhancement increases with decreasing finwidth.

Drive current as a function of indicators of SCEs, suchas SS and DIBL, is shown in Figs. 12 and 13. The IDsatof FinFETs with c-GST stressor is 67% higher than that ofFinFETs without stressor at a fixed SS of 90 mV/decade(Fig. 12). At a fixed DIBL of 0.25 V/V, IDsat enhancement forFinFETs with c-GST stressor over control FinFETs is ∼60%(Fig. 13).

DING et al.: PHASE CHANGE LINER STRESSOR 2707

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Fin Width Wfin

(nm)

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| ID

sat| (

μA/μ

m)

Dra

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%)

IDsat

Enhancement

Fig. 11. Comparison of IDsat (obtained at VG = VT,sat– 1.1 V, VD =−1.2 V) for p-FinFETs with and without c-GST liner stressor at differentWfin and fixed LG of 20 nm. IDsat percentage enhancement (right) increaseswith decreasing Wfin. The standard deviation of IDsat for a given Wfin andLG is shown as an error bar. Enhancement values were calculated using themean IDsat.

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Dri

ve C

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nt I

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t (μA

/μm

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Subthreshold Swing (mV/decade)

Fig. 12. Plot of drive current versus SS for FinFETs with and without c-GSTliner stressor. At a fixed SS of 90 mV/decade, ∼ 67% IDsat enhancementcan be observed for FinFETs with c-GST liner stressor over the controlFinFETs. IDsat was measured at gate overdrive (VG − VT,sat) = −1.1 Vand VD = −1.2 V.

To verify the strain effect on carrier mobility enhancement,an approach based on the slope of a plot of RTotal versus LG

was employed for devices with short LG . Fig. 14 shows theRTotal–LG plot for FinFETs with c-GST stressor and controlFinFETs. The effective carrier mobility can be estimated usingthe following equation:

µ = 1

W QinvdRdL

(1)

where W is the channel width and Qinv is the inversion chargedensity. The smaller slope for FinFETs with c-GST stressoras compared with the control translates to a mobility enhance-ment of up to ∼130%. In addition, Fig. 14 shows ∼25% S/Dseries resistance (RSD) reduction for the FinFETs with c-GSTstressor as compared with the control FinFETs. This is likelyto be due to the stress-induced mobility enhancement in S/Dregions. A finite-element simulation shows a high compressivestress of up to −1500 MPa in the S/D regions induced bythe GST liner stressor [17]. Fig. 15 shows a transistor withW plug placed very close to the channel (as is the case inindustry) and a transistor in this paper where the probe tipcontacts the NiSi far (∼50 μm) from the channel. As shownin Fig. 15 (a), the path of current flow from the W plug to thechannel is much shorter compared with that in the transistorin this paper [Fig. 15(b)], where the current in the S/D regioncan spread from the NiSi into the unsilicided region under the

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DIBL (V/V)

Fig. 13. At a fixed DIBL of 0.25 V/V, IDsat enhancement of ∼60% overthe control FinFETs is observed for devices with c-GST liner stressor. IDsatwas measured at gate overdrive (VG − VT,sat) = −1.1 V and VD = −1.2 V.

0 20 40 602

4

6

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Slope = 19 kΩ-μm/nm

Slope = 45 kΩ-μm/nm

RTo

tal =

VD

S/ID

lin (k

Ω-μ

m)

Gate Length LG (nm)

RSD,Control

= 4375 Ω-μm

RSD, c-GST

= 3295 Ω-μm

P-FinFET Control P-FinFET with c-GST

Fig. 14. RTotal = VDS/IDlin as a function of LG(IDlin was taken atVGS–VT,lin = −1.1 V, VDS = −50 mV). FinFETs with c-GST liner havea smaller dRTotal /dLG , and exhibit mobility enhancement of ∼130%. Thestandard deviation of RTotal is shown as error bars. FinFETs with c-GST alsoshow ∼25% RSD reduction as compared with the control FinFETs.

NiSi over the long distance from probe to channel. The largecompressive stress induced by the GST in the S/D regionscan lead to resistivity reduction in the S/D regions. As shownin Fig. 15(c) and (d), the series resistance reduction can bemore significant in the transistor in this paper than in a typicaltransistor with short plug-to-channel distance, due to the longcurrent path between the probe and the channel.

As observed in some of the figures [e.g. Figs. 5(b),8 and 9], the data points from FinFETs with GST stres-sor are more widely scattered compared with those ofthe control. Some of this scatter could be explained byFinFETs with different Wfin having different amounts of draincurrent enhancement as observed in Fig. 11. In addition, theimmature process flow for integrating the GST stressor couldalso contribute to the device-to-device variation. Thicknessnonuniformity of the GST and the SiO2 insulating layer belowit, incomplete crystallization of the GST in some regions, andlateral etching of GST during the dilute HF etching of residualSiO2 can all result in variability of the stress levels, leadingto device-to-device variations in IDsat enhancement and S/Dseries resistance reduction.

We next explore the physical mechanisms in the strainedp-channel FinFET. In this paper, the top channel of the FinFETis (001)-oriented and the sidewall channels are (110)-oriented[Fig. 2(a)]. In an unstrained MOSFET, the degeneracy of theconduction and valence bands is lifted owing to quantum

2708 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 9, SEPTEMBER 2013

Gate SiN

NiSi

WPlug Gate SiN

NiSi

Probe

~ 50 μm

GST

SiO2

(a) Transistor with SmallPlug-to-Gate Spacing

Gate SiNNiSi

WPlug Gate SiN

NiSi

Probe

~ 50 μm

(b) Control Transistor in This Work

(c) Transistor with SmallPlug-to-Gate Spacing and Liner Stressor

(d) Transistor in This Workwith GST Stressor

Liner Stressor SiO2 Liner Stressor

Fig. 15. Schematics of (a) transistor with very short plug-to-channel distanceused in industry and (b) transistor in this paper, where the probe tip contactsthe NiSi far (∼50 μm) from the channel. The schematics in (c) and (d) aresimilar to those in (a) and (b), respectively, except that they have a linerstressor.

confinement due to the vertical electric field [33]. Understrain, the band edges can be shifted either additively orsubtractively to the confinement-induced splitting, and onlythe additive splitting induced by strain will lead to mobil-ity enhancement in the MOSFET. As the splitting due to<110>uniaxial compression is additive to the confinementeffect for valence bands [33], the longitudinal compressivestrain in the <110>direction induced by c-GST enhancesthe hole mobility in the p-channel FinFET. The mobil-ity enhancement because of the c-GST stressor is how-ever, different for the top channel and the sidewall chan-nels due to the different surface orientation. Besides caus-ing the band edge to shift, strain breaks crystal symme-try and alters the band structure away from the energyminimum. Applying stress along a lower symmetrical axiscauses more destructive of crystal symmetry and results ina greater band warping [34]. Ground-state subband warpingis the major reason for the different enhancement in the(001)-oriented top channel and the (110)-oriented sidewallchannels. The larger quantum confinement-induced band split-ting for the (110)-oriented sidewall channels results in moreholes occupying the ground state [33]. Thus, stress does notcause as much hole repopulation as in the (001)-oriented topchannel. Simultaneously, the density of states at the � pointincreases significantly with stress for the (001)-oriented topchannel, but does not change much for the (110)-orientedsidewall channels [33]. Therefore, <110>compression inducedby c-GST has a more pronounced effect on the top channel interms of hole mobility enhancement.

The drain current enhancements for different fin rota-tions are shown in Fig. 16, where the rotated FinFETswith c-GST stressor are compared with control FinFETsof the same rotation. For each fin rotation, ∼8–10 deviceswith LG = 45 nm and Wfin = 40 nm are compared.The standard deviation of the enhancements is shown as error

0 15 30 450

20

40

60

80

100

Wfin

= 40 nm

~ 37%

P-FinFET with c-GST P-FinFET Control

Dra

in C

urre

nt E

nhan

cem

ent (

%)

Fin Rotation (°)

~ 75%

LG = 45 nm

Fig. 16. Drain current enhancements at different fin rotations forp-FinFETs with LG = 45 nm and Wfin = 40 nm. Significant IDsat (VG =VT,sat –1.1 V, VD = −1.2 V) enhancement induced by c-GST liner stressoris observed for different fin rotations, with the highest improvement observedfor FinFETs with 0° fin rotation, i.e., fins oriented along <110> direction.

bars. The highest current enhancement (∼75%) is seen in0° -rotated FinFETs (<110>channel orientation). 45°-rotated(<010>-oriented) FinFETs with c-GST stressor show ∼37%IDsat enhancement as compared with the control FinFETs ofthe same orientation. It is theoretically and experimentallyproven that <110>uniaxial compressive stress is more effectivethan stresses in other directions for enhancing hole mobil-ity [35], leading to the observed higher enhancement in theunrotated FinFETs with <110>orientation as compared withthe rotated FinFETs.

The difference in IDsat enhancement between 0°− and45°− rotated FinFETs can also be explained by the direc-tional dependence of the piezoresistance coefficients, as shownin Fig. 17(a), where the room temperature piezoresistancecoefficients in the (011) and (001) planes of p-type bulkSi are shown, in units of 10−12 cm2/dyne [36] The rela-tionship between resistivity ρ and stress σ is described by�ρ/ρ= πlσl +πtσt, where πl and πt are the piezoresistancecoefficients in the longitudinal and transverse directions,respectively. σl and σt are the longitudinal and transversestresses, respectively. For a given amount of compressivestress, a larger piezoresistance coefficient results in higherresistivity reduction in p-type Si.

The piezoresistance coefficients of FinFETs with 0° and 45°fin rotations are shown in Fig. 17(b). For FinFETs with 0° finrotation, the sidewall channels have (110) surfaces and are<110>-oriented, with πl ≈ 72 and πt ≈ 0, while the top chan-nel has a (001) surface and <110>orientation, with πl ≈ 70and πt ≈ 0. On the other hand, in 45° -rotated FinFETs,the piezoresistance coefficients are ∼9 in the longitudinaldirection and ∼0 in the transverse direction for sidewall andtop channels. The piezoresistance coefficients of the sidewalland top channels in 0° -rotated FinFETs are higher thanthose in FinFETs with 45° fin rotation. Using the piezoresis-tance coefficients, we now quantitatively compare the mobilityenhancement due to GST-induced stress (assuming −1.3-GPacompressive longitudinal stress). For simplicity, we use thebulk values for πl and πt , though technically piezoresistancecoefficients should consider the 2-D nature of transport in

DING et al.: PHASE CHANGE LINER STRESSOR 2709

Piezoresistance Coefficients of p-Si in (011)

<100>

<111>

<011>

<111>

<011>50 100-50-100

5010

0-5

0-1

00πl

πt

<211><211>

Piezoresistance Coefficients of p-Si in (001)

<100><110>

<010>

<110>

<010>50 100-50-100

5010

0-5

0-1

00

πl

πt

0˚ Rotation 45˚ Rotation

Sidewall Channels Top Channel Sidewall Channels Top Channel

πl πt πl πt πl πt πl πt

72 0 70 0 9 0 9 0

(a)

(b)

<001><110>

<110>

<001>

<100>

<010>Gate

Fig. 17. (a) Piezoresistance coefficients of p-type Si in the (011) and(001) planes, in units of 10−12 cm2/dyne. (b) Piezoresistance coefficients of0° - and 45° -rotated FinFETs, for both sidewall and top channels. Directionaldependence of the piezoresistance coefficients is qualitatively consistent withthe experimentally observed IDsat enhancement for FinFETs.

MOSFETs and depend on temperature and doping [37], [38].The calculated hole mobility enhancement for the unrotatedFinFET is ∼94% and that for the 45° -rotated FinFET is∼12%. Thus, with the same amount of compressive strainin the channels (in the source-to-drain direction) induced bythe c-GST stressor, FinFETs with a 0°-rotated fin have higherresistivity reduction or mobility enhancement compared with45°-rotated FinFETs, which in turn explains the differences incurrent enhancement for FinFETs with different fin rotationsin Fig. 16.

V. CONCLUSION

We developed a new GST liner stressor for performanceenhancement of p-FinFETs, featuring stress enhancement bychanging the phase of as-deposited α-GST to the crystallinestate. IDsat enhancement of ∼30% is observed for the FinFETswith α-GST liner over unstrained control FinFETs, becauseof the intrinsic compressive stress in α-GST. When phasechanged to crystalline state, the c-GST contracts and exertsadditional stress on the channel region, increasing the holemobility further and giving a higher IDsat enhancement of upto ∼88% over the control. IDsat enhancement is higher forsmaller LG . Significant IDsat enhancement was observed forstrained FinFETs with various fin rotations, with the highestenhancement observed for 0° -rotated FinFETs because of thedirectional dependence of the piezoresistance coefficients.

ACKNOWLEDGMENT

Y. Ding would like to thank GLOBALFOUNDRIESSingapore Pte. Ltd. and Economic Development Board (EDB)of Singapore for a Graduate Scholarship.

REFERENCES

[1] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C.Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET—A self-aligned double-gate MOSFET scalable to 20 nm,” IEEETrans. Electron Devices, vol. 47, no. 12, pp. 2320–2325,Dec. 2000.

[2] J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy,D. Boyd, D. Fried, and H.-S. P. Wong, “Extension and source/draindesign for high-performance FinFET devices,” IEEE Trans. ElectronDevices, vol. 50, no. 4, pp. 952–958, Apr. 2003.

[3] J. Kedzierski, M. Ieong, T. Kanarsky, Y. Zhang, and H.-S. P. Wong,“Fabrication of metal gated FinFETs through complete gate silicidationwith Ni,” IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2115–2120,Dec. 2004.

[4] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski,E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian,T.-J. King, J. Bokor, and C. Hu, “Sub-50 nm P-channel Fin-FET,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 880–886,May 2001.

[5] F.-L. Yang, H.-Y. Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang,H.-K. Chiu, C.-C. Lee, C.-C. Chen, H.-T. Huang, C.-J. Chen, H.-J. Tao,Y.-C. Yeo, M.-S. Liang, and C. Hu, “25 nm CMOS omega FETs,” inProc. IEEE IEDM, Dec. 2002, pp. 255–258.

[6] H. Kawasaki, V. S. Basker, T. Yamashita, C.-H. Lin, Y. Zhu, J. Fal-termeier, S. Schmitz, J. Cummings, S. Kanakasabapathy, H. Adhikari,H. Jagannathan, A. Kumar, K. Maitra, J. Wang, C.-C. Yeh, C. Wang,M. Khater, M. Guillorn, N. Fuller, J. Chang, L. Chang, R. Muralidhar,A. Yagishita, R. Miller, Q. Ouyang, Y. Zhang, V. K. Paruchuri, H. Bu,B. Doris, M. Takayanagi, W. Haensch, D. McHerron, J. O’Neill, andK. Ishimaru, “Challenges and solutions of FinFET integration in anSRAM cell and a logic circuit for 22 nm node and beyond,” in Proc.IEEE IEDM, Dec. 2009, pp. 264.

[7] C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost,M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover,W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks,D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S.Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck,C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S. Ramey, T.Reynolds, J. Roesler, J. Sandford, J. Seiple, P. Smith, C. Thomas,D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, and K.Mistry, “A 22 nm high performance and low-power CMOS technologyfeaturing fully-depleted tri-gate transistors, self-aligned contacts andhigh density MIM capacitors,” in Proc. Symp. VLSI Technol., Jun. 2012,pp. 131–132.

[8] J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin,D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah,N. Zelick, and R. Chau, “Tri-gate transistor architecture with high-k gatedielectrics, metal gates and strain engineering,” in Symp. VLSI Technol.Dig. Tech. Papers, 2006, pp. 50–51.

[9] T.-Y. Liow, K.-M. Tan, D. Weeks, R. T. P. Lee, M. Zhu, K.-M. Hoe,C.-H. Tung, M. Bauer, J. Spear, S. G. Thomas, G. S. Samudra, N. Bal-asubramanian, and Y.-C. Yeo, “Strained n-channel FinFETs featuringin-situ doped silicon-carbon (Si1−yCy) source and drain stressors withhigh carbon content,” IEEE Trans. Electron Devices, vol. 55, no. 9,pp. 2475–2483, Sep. 2008.

[10] N. Collaert, R. Rooyackers, F. Clemente, P. Zimmerman, I. Cayrefourcq,B. Ghyselen, K. T. San, B. Eyckens, M. Jurczak, and S. Biesemans,“Performance enhancement of MUGFET devices using super criticalstrained-SOI (SC-SSOI) and CESL,” in Symp. VLSI Technol. Dig. Tech.Papers, 2006, pp. 52–53.

[11] T.-Y. Liow, K.-M. Tan, R. T. P. Lee, C.-H. Tung, G. S. Samu-dra, N. Balasubramanian, and Y.-C. Yeo, “N-channel (110)-sidewallstrained FinFETs with silicon-carbon source and drain stressors andtensile capping layer,” IEEE Electron Device Lett., vol. 28, no. 11,pp. 1014–1017, Nov. 2007.

[12] C. Smith, S. Parthasarathy, B. E. Coss, J. Williams, H. Adhikari,G. Smith, B. Sassman, M. M. Hussain, P. Majhi, and R. Jammy, “Strainengineering in nanoscale CMOS FinFETs and methods to optimizeRS/D,” in Proc. Int. Symp. VLSI Technol., Syst. Appl., Apr. 2010,pp. 156–157.

[13] K.-M. Tan, W.-W. Fang, M. Yang, T.-Y. Liow, R. T.-P. Lee,N. Balasubramanian, and Y.-C. Yeo, “Diamond-like carbon (DLC)liner: A new stressor for p-channel multiple-gate field-effect tran-sistors,” IEEE Electron Device Lett., vol. 29, no. 7, pp. 750–752,Jul. 2008.

2710 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 9, SEPTEMBER 2013

[14] C.-C. Yeh, C.-S. Chang, H.-N. Lin, W.-H. Tseng, L.-S. Lai, T.-H. Perng,T.-L. Lee, C.-Y. Chang, L.-G.Yao, C.-C. Chen, T.-M. Kuan, J. J. Xu,C.-C. Ho, T.-C. Chen, S.-S. Lin, H.-J. Tao, M. Cao, C.-H. Chang,T.-C. Ko, N.-K. Chen, S.-C. Chen, C.-P. Lin, H.-C. Lin, C.-Y. Chan,H.-T. Lin, S.-T. Yang, J.-C. Sheu, C.-Y. Fu, S.-T. Hung, F. Yuan, M.-F. Shieh, C.-F. Hu, and C. Wann, “A low operating power FinFETtransistor module featuring scaled gate stack and strain engineeringfor 32/28 nm SoC technology,” in Proc. IEEE IEDM, Dec. 2010,pp. 34.1.1–34.1.4.

[15] E. Karl, Y. Wang, Y.-G. Ng, Z. Guo, F. Hamzaoglu, U. Bhattacharya,K. Zhang, K. Mistry, and M. Bohr, “A 4.6 GHz 162 Mb SRAM designin 22 nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry,” in IEEE Int. Solid-State Circuits Conf. Dig.Tech. Papers, Feb. 2012, pp. 230–232.

[16] K.-M. Tan, M. Yang, T.-Y. Liow, R. T. P. Lee, and Y.-C.Yeo, “Ultra high-stress liner comprising diamond-like carbon forperformance enhancement of p-channel multiple-gate transistors,”IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1277–1283,Jun. 2009.

[17] Y. Ding, R. Cheng, S.-M. Koh, B. Liu, A. Gyanathan, Q. Zhou, Y. Tong,P. S.-Y. Lim, G. Han, and Y.-C. Yeo, “A new Ge2Sb2Te5 (GST)liner stressor featuring stress enhancement due to amorphous-crystallinephase change for sub-20 nm p-channel FinFETs,” in Proc. IEEE IEDM,Dec. 2011, pp. 35.4.1–35.4.4.

[18] K. Do, D. Lee, D.-H. Ko, H. Sohn, and M.-H. Cho, “TEM studyon volume changes and void formation in Ge2Sb2Te5 films, withrepeated phase changes,” Electrochem. Solid-State Lett., vol. 13, no. 8,pp. H284–H286, 2010.

[19] V. Weidenhof, I. Friedrich, S. Ziegler, and M. Wuttig, “Atomic forcemicroscopy study of laser induced phase transitions in Ge2Sb2Te5,”J. Appl. Phys., vol. 86, no. 10, pp. 5879–5887, 1999.

[20] Y. Ding, R. Cheng, A. Du, and Y.-C. Yeo, “Lattice strainanalysis of silicon fin field-effect transistor structures wrapped ina Ge2Sb2Te5 liner stressor,” J. Appl. Phys., vol. 113, no. 7,pp. 073708-1–073708-8, Feb. 2013.

[21] B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery,C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser,“FinFET scaling to 10 nm gate length,” in Proc. IEEE IEDM, Dec. 2002,pp. 251–254.

[22] F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu,C.-C. Huang, T.-X. Chung, H.-W. Chen, C.-C. Huang, Y.-H. Liu,C.-C. Wu, C.-C. Chen, S.-C. Chen, Y.-T. Chen, Y.-H. Chen, C.-L.Chen, B.-W. Chan, P.-F. Hsu, J.-H. Shieh, H.-J. Tao, Y.-C. Yeo, Y. Li,L.-W. Lee, P. Chen, M.-S. Liang, and C. Hu, “5 nm-gate nanowireFinFET,” in Symp. VLSI Technol. Dig. Tech. Papers, Jun. 2004,pp. 196–197.

[23] H.-Y. Chen, C.-C. Huang, C.-C. Huang, C.-Y. Chang, Y.-C. Yeo,F.-L. Yang, and C. Hu, “Scaling of CMOS FinFETs towards 10 nm,” inProc. Int. Symp. VLSI Technol., Syst. Appl., Oct. 2003, pp. 46–48.

[24] Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King,J. Bokor, and C. Hu, “Sub-20 nm CMOS FinFET technologies,” in IEEEIEDM Tech. Dig., Dec. 2001, pp. 19.1.1–19.1.4.

[25] J. G. Fossum and W. Zhang, “Performance projections of scaledCMOS devices and circuits with strained Si-on-SiGe channels,”IEEE Electron Device Lett., vol. 50, no. 4, pp. 1042–1049, Apr. 2003.

[26] T.-J. Wang, C.-H. Ko, S.-J. Chang, S.-L. Wu, T.-M. Kuan, andW.-C. Lee, “The effects of mechanical uniaxial stress on junction leakagein nanoscale CMOSFETs,” IEEE Trans. Electron Devices, vol. 55, no. 2,pp. 572–577, Feb. 2008.

[27] V. Moroz, N. Strecker, X. Xu, L. Smith, and I. Bork, “Modeling theimpact of stress on silicon processes and devices,” Mater. Sci. Semicond.Process., vol. 6, nos. 1–3, pp. 27–36, 2003.

[28] G. A. Armstrong and C. K. Maiti, “Strained-Si channel heterojunctionp-MOSFETs,” Solid State Electron., vol. 42, no. 4, pp. 487–498, 1998.

[29] R. People, “Physics and applications of Gex Si1−x /Si strained-layer heterostructures,” IEEE J. Quantum Electron., vol. 22, no. 9,pp. 1696–1710, Sep. 1986.

[30] M. S. Lundstrom, “On the mobility versus drain current relation fora nanoscale MOSFET,” IEEE Electron Device Lett., vol. 22, no. 6,pp. 293–295, Jun. 2001.

[31] N. Collaert, A. De Keersgieter, K. G. Anil, R. Rooyackers, G. Eneman,M. Goodwin, B. Eyckens, E. Sleeckx, J.-F. De Marneffe, K. De Meyer,P. Absil, M. Jurczak, and S. Biesemans, “Performance improvement oftall triple gate devices with strained SiN layers,” IEEE Electron DeviceLett., vol. 26, no. 11, pp. 820–822, Nov. 2001.

[32] R. Cheng, Y. Ding, B. Liu, and Y.-C. Yeo, “Modeling of a new linerstressor comprising Ge2Sb2Te5 (GST): Amorphous-crystalline phasechange and stress induced in FinFET channel,” in Proc. IEEE Int.Semicond. Device Res. Symp., Dec. 2011, pp. 1–2.

[33] M. Chu, Y. Sun, U. Aghoram, and S. E. Thompson, “Strain: A solutionfor higher carrier mobility in nanoscale MOSFETs,” Annu. Rev. Mater.Res., vol. 39, pp. 203–229, Aug. 2009.

[34] Y. Sun, S. E. Thompson, and T. Nishida, “Physics of strain effects insemiconductors and metal-oxide semiconductor field-effect transistors,”J. Appl. Phys., vol. 101, no. 10, pp. 104503-1–104503-22, 2007.

[35] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Keydifferences for process-induced uniaxial vs. substrate-induced biaxialstressed Si and Ge channel MOSFETs,” in IEEE IEDM Tech. Dig.,Dec. 2004, pp. 221–224.

[36] Y. Kanda, “A graphical representation of the piezoresistance coefficientsin silicon,” IEEE Trans. Electron Devices, vol. 29, no. 1, pp. 64–70,Jan. 1982.

[37] G. Dorda, “Piezoresistance in quantized conduction bands in siliconinversion layers,” J. Appl. Phys., vol. 42, no. 5, pp. 2053–2060, 1971.

[38] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass,T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic,L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, andY. El-Mansy, “A logic nanotechnology featuring strained-silicon,” IEEEElectron Device Lett., vol. 25, no. 4, pp. 191–193, Apr. 2004.

Yinjie Ding (S’11) received the B.Eng. (Hons.)degree in electrical engineering from the NationalUniversity of Singapore, Singapore, in 2009, wherehe is currently pursuing the Ph.D. degree in electricalengineering.

He is working on strain engineering for advancedtransistors.

Ran Cheng (S’11) received the B.Eng. degree inelectrical engineering from the National Universityof Singapore (NUS), Singapore, in 2009. She iscurrently pursuing the Ph.D. degree at NUS.

Shao-Ming Koh (S’07) received the B.Eng. (Hons.)and Ph.D. degrees from the National University ofSingapore, Singapore.

He is currently with GLOBALFOUNDRIES, Sin-gapore.

DING et al.: PHASE CHANGE LINER STRESSOR 2711

Bin Liu received the B.Eng. and Ph.D. degreesfrom the National University of Singapore (NUS),Singapore.

He is currently with NUS.

Yee-Chia Yeo (S’98–M’02) received the B.Eng(Hons.) and M.Eng degrees from the National Uni-versity of Singapore (NUS), Singapore, and the M.S.and Ph.D. degrees from the University of California,Berkeley, CA, USA.

He is currently with NUS.