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P.Ferrara7-Mar-02
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www.onsemi.com
D1600 PowerSense3 Semicustom Array
ELE 535 BiCMOS Design
University of Rhode Island
Author Name12-Feb-01
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D1600 PowerSense3 Semicustom Array
Agenda– Introduce You to the IC for Your Projects– Component Availability - Limitations– Device Characteristic Basics– Design Considerations for your Projects on this Array– Intro to Layout Considerations– Discussion on Project Selection
• and a few suggestions (pet projects)
– Q & A
Author Name12-Feb-01
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D1600 Array Summary
30,000 mil2 Die
• 52 Bond Pads - (protected)
• Bandgap Reg - (w/ 5 bit trim)• Charge Pump• 756 Logic Gates• 1200 MOS • 400 Bipolar• 43 DMOS• 9 MΩ Res.• 400 pF Cap
Author Name12-Feb-01
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D1600 Blocks
Mixed Analog BCD
A
A
ABandgapBias
LVMOS
LVBiC
AnalogMix
ChargePump
LVMOS
Switch cap
OpAmp
OpAmp
LOGIC CORE
15 Blocks
• ChargePump• Bandgap• 2 x OpAmp• SwitchCap• Bias • 4 x Mixed BCD• 4 Misc Analog • Logic Core
•+15 Logic I/O cells
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Mixed Analog BCD Block
• 29 NPN
• 31 PNP
• 62 NMOS
• 84 PMOS
• 7 DMOS• 1.3 MΩ resistance• 40 pF capacitance
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Mixed Analog Block – Detail Component Count
Device Type
Material/ Type
VoltageMultiplier/ #Collectors
/ Width
Size/ Value
Count
NPN NHV 10V 1 12x12 2NPN NHV 10V 1 20x20 DN+ 2NPN NHV 65V 1 20x20 24NPN NSD 65V 1 12x12 1
PNPL PHV 10V 4c 20x20 6PNPL PHV 65V 1 12x12 1PNPL PHV 65V 4c 20x20 20PNPS PHV 10V 1 20x20 4
CAPACITOR M1/P1 1 5pF 8NMOS LV 10V 1 8x8 36NMOS LV 10V 1 20x8 4NMOS MV 30V 1 8x8 22PMOS LV 10V 1 8x8 62PMOS HV 65V 1 16x13 9PMOS HV 65V 1 150x13 11PMOS HV 65V 1 360x13 2DMOS PWL 65V 1 1 5DMOS PWL 65V 1 3x5 1DMOS PWL 65V 1 10x10 1
RESISTOR PSD 65V 27udr 500 12RESISTOR PHV 10V 14udr 10K 53RESISTOR PHV 65V 14udr 2K 32RESISTOR PHV 65V 14udr 10K 42RESISTOR PHV 65V 27udr 6K 36RESISTOR NHV 65V 18udr 1.1K 4RESISTOR NHV 65V 18udr 5K 2RESISTOR NHV 65V 18udr 10K 4RESISTOR POLY1 14udr 200 32
ZENER PHV/NSD 65V 1 1 1
Author Name12-Feb-01
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Design Considerations• Device Availability
- Bipolar vs MOS, LV vs HV, Resistor types, etc
- Location / Accessibility of Devices• Breakdown Voltages
- C-E, E-B, D-S, G-B...
• Device Matching– Resistors: expect BEST CASE 1% using matched strings
: unmatched strings – SIGNIFICANTLY worse
– Bipolar : 1mV with care in layout– MOS: Order of magnitude worse than Bipolar
• Temperature Coefficient
- See PSPICE models
ON Semiconductor:
Add Bigger picture of Block
here, and list the considerations on a separate slide.
Mention matching of R’s and xistors, DLM, metal width
and pitch, via size, current
carrying capability, Metal resistance and drop, selecting
devices for breakdown V, tub
Biasing etc.
Maybe need follow-up lecture,
cover design issues here, and layout issues in
follow-up!
ON Semiconductor:
Add Bigger picture of Block
here, and list the considerations on a separate slide.
Mention matching of R’s and xistors, DLM, metal width
and pitch, via size, current
carrying capability, Metal resistance and drop, selecting
devices for breakdown V, tub
Biasing etc.
Maybe need follow-up lecture,
cover design issues here, and layout issues in
follow-up!
Author Name12-Feb-01
www.onsemi.com
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Device Performance - MOS TransistorsDevice (W/L) Parameter Target Min Max
LVN (40/4 udr)
Vt (v) 1.0 0.7 1.3Gm (u-mho) 74 53 95Id (ma) Lk (amp) Bv (v) 13 7 --
LVP (40/4 udr)
Vt (v) -1.1 -0.7 -1.5Gm (u-mho) 31 17.6 39.6Id (ma) Lk (amp) Bv (v) -14.0 -7.0 --
MVN (40/8 udr)
Vt (v) 2.0 1.6 2.4Gm (u-mho) 17.6 13.2 22.0Id (ma) Lk (amp) Bv (v) 23 18 --
MVP(40/11udr)
Vt (v) -1.6 -1.3 -2.0Gm (u-mho) 5.29 2.64 7.93Id (ma) Lk (amp) Bv (v) -40.0 -30.0 --
Device (W/L) Parameter (unit)
target min max
HVP (80/13 udr)Double sided
Vt (v) -1.55 -1.15 -1.95
Gm (u-mho) 7.9 5.3 10.6
Id (ma)
Lk (amp)
Bv (v) -100.0 -80.0 --
Note: 1. Vt is the line interception of Id / Vg at maximum slope where Vd = 0.1v.2. Gm is the maximum slope of Id / Vg.3. Id is at Vg = Vd = 5v.4. Leakage is at Vg = 0v, and Vd = 5v.5. Bv is at Id = 50 ua.
Author Name12-Feb-01
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Device Performance - DMOSDevice (area) Parameter (unit) Mean sigma Note:
Small DMOS with Pwell edge termination (21 cell)
Vt (v) 1.84 0.075 Vd = 0.1 v
Bv (v) 84.4 4.25 Id = 50 ua
Lk (amp) < 20 na Vg = 0v, Vd = 5v
Rdson (Vd / Id) 36.6 4.12 Vd @ Vg = 10v & Id = 10ma
Rdson @.2v (Vd/Id) 35.9 3.05 Id @ Vg = 10v & Vd = 0.2v
Note: 1. Vt is the line interception of Id / Vg at maximum slope where Vd = 0.1v.2. Bv is at Id = 50 ua.3. Leakage is at Vg = 0v, and Vd = 5v.4. Rdson is the ratio of Vd / Id at Vg = 10v & Id = 10ma.Rdson @.2v is the ratio of Vd / Id at Vg = 10v & Vd = 0.2v.
Author Name12-Feb-01
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Device Performance – MOS Specific Rdson (at 25°C)
Device type Min BVdss
Max operation V
Vgs Estimated specific Rdson (mohm-cm2)
LVNMOS 7v 5.5v 5v 1.0
MVNMOS 18v 16.5v 10v 4.5
LVPMOS -7v -5.5v -5v 2.5
MVPMOS -30v -16.5v -10v 12.5
HVPMOS -80v -65v -10v 60
N-VDMOS 65V 65v 65v 10v 3.6
Author Name12-Feb-01
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Device Performance - BipolarDevice Parameters(unit) Target min max
NHV - NPN
Beta @50u 140 70 300
Vbe (v) 0.658
Vsat @ 200u (v) 0.1
Bvceo (v) 30.0 20.0 --
Bvcbo (v) 60.0 40.0 --
Bvebo (v) 30.0 22.0 38.0
Lateral PNP
Beta @50u 25.0 10.0 40.0
Vbe (v) 0.670
Vsat @ 200u (v) 0.15
Bvceo (v) 55.0 40.0 --
Bvcbo (v) 60.0 35.0 --
Bvebo (v) 70.0 45.0 --
Substrate PNP
Beta @50u 40.0 25.0 70.0
Vbe (v) 0.672
Vsat @ 200u (v) 0.20
Bvceo (v) 40.0 20.0 --
Bvcbo (v) 70.0 45.0 --
Bvebo (v) 70.0 45.0 --
Note:1. Beta @50u is the transistor beta measured at Ic = 50 ua.2. Vbe is measured at Ic + Ib = 10 ua.3. Vsat @ 200u is the Vce measured at Ic = 200 ua.4. Bvceo, Bvcbo, Bvebo at I = 10 ua.
Author Name12-Feb-01
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Device Performance – Junction BreakdownsJunctions Target Min Max
Bl / Sub 100.0 70 --
Nsd / Pwell 17.5 15 --
Nhv / Pwell 45.0 35 --
Psd / Epi 30.0 22 --
Phv / Epi 70.0 55 --
Nsd / Phv 11.0 9 --
Nsd / Psd (in Pwell) 5.8 5.3 --
Pwell / Epi w/o Bl 110.0 90 --
Pwell / Epi w/ Bl 105.0 80 --
Zeners Target Min Max
BL / Iso 10.0 8.5 --
Nsd / Iso (7 udr)* 5.2 4.8 5.6
Nsd / Iso (9 udr) 5.6 5.2 6.0
Nsd / Psd(in Pwell) Min 5.8 5.3 6.3
Nsd / Phv(in Pwell) 10.5 9.0 12.0
Nsd / Pwell 19.6 17.5 21.7
Nsd / Hfb(in Pwell) 6.0 5.0 7.0
Author Name12-Feb-01
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Device Performance – Resistors
DeviceAbsolute deviation Matching %
6 um 12 um 30 um 6 um 12 um 30 um
Poly1 26.6 % 19.3 % 14.3 % 1.0 % 0.8 % 0.50 %
Poly2 26.5 % 23.7 % 24.4 % 1.3 % 0.9 % 0.60 %
PHV 24.0 % 21.6 % 21.5 % 0.8 % 0.22 % 0.20 %
PSD 17.6 % 13.4 % 10.8 % 0.15 % 0.10 % 0.08 %
NHV 46.3 % 41.9 % 39.9 % 0.3 % 0.17 % --
NSD 20.1 % 18.5 % 14.8 % 0.15 % 0.1 % --
Pwell 21.8 % 15.9 % 16.4 % -- 0.4 % 0.36 %
Author Name12-Feb-01
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14
Layout Considerations• Device Matching
- Proximity and orientation
- Use identical strings for Resistor matches
• Tub Bias - N-Tubs to Most + V used in tub, P-Tubs to most -.
• Metal Rules and Runs– Dual Level Metal
– M1: 4udr width, 4udr space, 1.75mA/udr, 0.052Ω/sq max– M2: 18udr width, 18udr space, 3.5mA/udr, 0.02Ω/sq max
– Must consider current carrying capability and Vdrops
• Temperature Coefficient
- See PSPICE models
ON Semiconductor:
Add Bigger picture of Block
here, and list the considerations on a separate slide.
Mention matching of R’s and xistors, DLM, metal width
and pitch, via size, current
carrying capability, Metal resistance and drop, selecting
devices for breakdown V, tub
Biasing etc.
Maybe need follow-up lecture,
cover design issues here, and layout issues in
follow-up!
ON Semiconductor:
Add Bigger picture of Block
here, and list the considerations on a separate slide.
Mention matching of R’s and xistors, DLM, metal width
and pitch, via size, current
carrying capability, Metal resistance and drop, selecting
devices for breakdown V, tub
Biasing etc.
Maybe need follow-up lecture,
cover design issues here, and layout issues in
follow-up!
Author Name12-Feb-01
www.onsemi.com
15
Open Discussion
ON Semiconductor:
Add Bigger picture of Block
here, and list the considerations on a separate slide.
Mention matching of R’s and xistors, DLM, metal width
and pitch, via size, current
carrying capability, Metal resistance and drop, selecting
devices for breakdown V, tub
Biasing etc.
Maybe need follow-up lecture,
cover design issues here, and layout issues in
follow-up!
ON Semiconductor:
Add Bigger picture of Block
here, and list the considerations on a separate slide.
Mention matching of R’s and xistors, DLM, metal width
and pitch, via size, current
carrying capability, Metal resistance and drop, selecting
devices for breakdown V, tub
Biasing etc.
Maybe need follow-up lecture,
cover design issues here, and layout issues in
follow-up!
Projects
-- Complexity– Samples– Pet Projects
Q & A