Pengukuran Arus dan Tegangan pada Sistem Penganalisis Komponen Frekuensi Harmonisa

Arus Beban Peralatan Listrik

TUGAS AKHIR

Diajukan untuk Memenuhi Salah Satu Syarat Memperoleh Gelar Sarjana Teknik pada

Program Studi Teknik Elektro

disusun oleh:

Frederik Erik

NIM : 045114071

PROGRAM STUDI TEKNIK ELEKTRO JURUSAN TEKNIK ELEKTRO

FAKULTAS SAINS DAN TEKNOLOGI UNIVERSITAS SANATA DHARMA

YOGYAKARTA 2009

i

Current and Voltage Measurement of Load Current Harmonic Frequency Component

Analyzer of Electrical Device

FINAL PROJECT

Presented as Partial Fulfillment of the Requirements to Obtain the SARJANA TEKNIK Degree

in Electrical Engineering

by:

Frederik Erik

Student Number : 045114071

ELECTRICAL ENGINEERING DEPARTMENT

FACULTY OF SCIENCE AND TECHNOLOGY

SANATA DHARMA UNIVERSITY

YOGYAKARTA

2009

ii

HALAMAN PERSEMBAHAN DAN MOTTO

”Segala perkara dapat kutanggung di dalam Dia

yang memberi kekuatan kepadaku”

(Filipi 4:13)

Kupersembahkan karya tulisku ini kepada:

Tuhan Yesus Kristus, atas kasih karunianya.

Bapak Ignatius Lias.B dan Ibunda Norbetha

S.pd serta adikku Nikolas Beatus, Jelita Katrin

terima kasih untuk doa dan pengorbanan kalian,

aku mencintai kalian seumur hidupku.

Seseorang yang jauh disana (we’.Be2R) trim’s

semangatnya.

Dango kamuda diri’ (dKd).....kuliah nang banar

boh cu’.......!

vii

INTISARI

Penggunaan beban peralatan listrik non linear, mengakibatkan bentuk gelombang arus tidak sama dengan bentuk gelombang tegangan. Bentuk gelombang (arus) yang tidak sinus akan menimbulkan adanya komponen harmonisa yang menyebabkan banyak implikasi pada jala-jala listrik Untuk memperoleh bentuk gelombang arus beban peralatan listrik, sistem menggunakan sensor arus berupa resistor yang akan diambil besaran tegangan pada saat resistor dialiri arus listrik, sedangkan sensor tegangan menggunakan resistor sebagai pembagi tegangan dan dilakukan penguatan tegangan. Sinyal tegangan keluaran penguat dari sensor arus dan tegangan

.Tegangan masukan AC dari keluaran rangkaian sensor arus dan tegangan terlebih dahulu melewati rangkaian penguat inverting yang dapat diatur penguatannya dengan relay sebagai pemilihan saklar agar sesuai dengan jangkauan ADC dan penguat operasional. Keluaran dari penguat inverting akan melewati penyearah presisi sehingga keluaran dari penyearah presisi selalu mempunyai nilai positif. Keluaran penyearah presisi diumpankan menuju ADC yang digunakan agar nilai tegangan masukan ADC bisa diproses oleh mikrokontroler karena sebelumnya merupakan sinyal analog yang perlu diubah terlebih dahulu menjadi sinyal digital.

Dari pengujian dan analisis, Alat dapat mengukur nilai Vrms dengan baik

pada jangkauan 195~240 Vrms karena tingkat kesalahan kurang dari 2%. Sensor arus dapat berkerja dengan baik pada saat skala pemilihan gain yang besar (5 Ampere), sedangkan skala kecil (0,5A dan 0,05 A) akan terjadi tegangan offset. Tegangan Offset tidak berpengaruh di pengukuran besar tapi pengukuran yang kecil saja. Untuk pengukuran arus terbaik, disarankan agar alat ini digunakan pada jangkauan masukan maksimal 5Vp (peak arus).

Kata kunci:. Harmonisa, ADC, gain, listrik non linear.

viii

ABSTRACT

The use of non linear load in electric equipment causing the current wave was not in the same form with the voltage wave. The current’s wave form that was not sinusoidal generations the components of harmonic.That cause multiplications in electric power line. In order to produc the current’s electricity wave form, the system used resistor as the current censor, where the voltage will be produced when the resistor receives electric current.

AC voltage input, which was the output of current and voltage censors, firstly passed the inverting amplifier circuit where the gain could be regulated with relay as the switch witch is optional in order to be conformed with the ADC range and operation. The output from the inverting amplifier will pass through the precision rectifier, so that the output from the precision rectifier will always have positive values. The precision rectifier output was put toward ADC, which was used to allow the ADC input voltage so that it is able to be processed by microcontroller since it was the analog signal that firstly needed to be inverted into digital signal.

From the observation and anallysis, the device was abel to measure the Vrms at the voltage range of 195 - 240 Vrms since the error level is below 2 percent. Current censor was capable to work well when the gain optional scale was substantial (5Ampere), while in the small scale (0,5 Ampere and 0,05 Ampere) the offset voltage will be produced. This offset voltage has no impact on substantial measurement, but only on the small one. In order to get the best current measurement, it was recommended to use this device in maximum range input 5 Vp (peak current).

Keywords: Harmonic, ADC, gain, non linear load.

ix

KATA PENGANTAR

Puji dan syukur penulis panjatkan kepada Tuhan Yang Maha Esa atas

berkat dan rahmat-Nya sehingga penulis dapat menyelesaikan karya tulis berjudul

Pengukuran Arus dan Tegangan pada Sistem Penganalisis Komponen Frekuensi

Harmonisa Arus Beban Peralatan Listrik.

Karya tulis ini merupakan salah satu syarat untuk memperoleh gelar

Sarjana Teknik pada Program Studi Teknik Elektro Universitas Sanata Dharma.

Penulisan skripsi ini didasarkan pada hasil-hasil yang penulis dapatkan selama

tahap perancangan, pembuatan dan pengujian alat.

Penulisan skripsi ini tidak terlepas dari bantuan berbagai pihak. Untuk itu,

penulis mengucapkan terima kasih kepada:

1. Kedua orang tua penulis yang telah memberikan semangat dan doa yang tak

pernah putus sehingga penulis dapat menyelesaikan tugas akhir ini.

2. Bapak Martanto, S.T., M.T., selaku dosen pembimbing I karya tulis yang telah

meluangkan waktu, tenaga, dan pikirannya untuk membimbing penulis.

3. Bapak A. Bayu Primawan, S.T., M.Eng., selaku dosen pembimbing II karya

tulis yang telah meluangkan waktu, tenaga, dan pikirannya untuk

membimbing penulis.

4. Ibu Bernadeta Wuri Harini S.T., M.T. selaku Ketua Jurusan Teknik Elektro

Universitas Sanata Dharma Yogyakarta.

5. Bapak Yosef Agung Cahyanta, S.T, M.T Selaku Dekan Fakultas Teknik

Universitas Sanata Dharma Yogyakarta.

x

6. Rekan-rekan seperjuangan yang telah membantu penulis dalam pengerjaan

karya tulis ini: Guntur TE’03 , Uci TE’03, Zainal TE’04.

7. Segenap dosen dan laboran Teknik Elektro Universitas Sanata Dharma.

8. Segenap karyawan sekretariat Fakultas Teknik.

9. Teman-teman mahasiswa jurusan Teknik Elektro dan semua pihak yang tidak

dapat disebutkan satu persatu atas setiap bantuannya.

Penulis menyadari bahwa masih banyak kelemahan dan kekurangan dari

penulisan karya tulis ini. Oleh karena itu segala kritik dan saran yang bersifat

membangun sangat penulis harapkan.

Akhir kata, semoga skripsi ini berguna bagi semua pihak dan dapat

menjadi bahan kajian lebih lanjut.

Yogyakarta, 24 Januari 2009

Penulis

xi

DAFTAR ISI

HALAMAN JUDUL ................................................................................. i

HALAMAN JUDUL DALAM BAHASA INGGRIS ...................... ii

HALAMAN PENGESAHAN OLEH PEMBIMBING .................... iii

HALAMAN PENGESAHAN OLEH PENGUJI ............................... iv

PERNYATAAN KEASLIAN KARYA ............................................... v

LEMBAR PERNYATAAN PERSETUJUAN PUBLIKASI

KARYA ILMIAH UNTUK KEPENTINGAN AKADEMIS.......... vi

PERSEMBAHAN DAN MOTTO ......................................................... vii

INTISARI ..................................................................................................... viii

ABSTRACT ................................................................................................ ix

KATA PENGANTAR .............................................................................. x

DAFTAR ISI ....................................................................................................... xii

DAFTAR GAMBAR ................................................................................ xv

DAFTAR TABEL ...................................................................................... xvii

DAFTAR LAMPIRAN ............................................................................ xix

BAB I. PENDAHULUAN ....................................................................... 1

1.1 Latar Belakang ........................................................................................... 1

1.2 Tujuan ........................................................................................................ 3

1.3 Manfaat ...................................................................................................... 3

1.4 Batasan Masalah ........................................................................................ 4

1.5 Metodologi Penelitian ................................................................................ 4

1.6 Sistematika Penulisan ................................................................................ 5

BAB II. DASAR TEORI........................................................................... 6

2.1 Pengukuran ................................................................................................ 6

2.1.1 Pengukuran Tegangan dan Pengukuran Arus ................................... 7

xii

2.2 Nilai rms (root-mean square) ..................................................................... 9

2.3 Penguat Operasional (Op-Amp) ................................................................ 12

2.3.1 Penguat Operasional sebagai penguat inverting ............................... 12

2.3.2 Penguat Operasional sebagai Penyearah Gelombang Penuh ............ 13

2.3.3 Penguat Operasional sebagai Penyangga Tegangan ....................... 15

2.4 Relay .......................................................................................................... 15

2.5 Transistor sebagai Saklar ........................................................................... 16

2.6 Dioda Memancarkan Cahaya (Light Emitting Diode) ............................... 19

2.7 Phototransistor ........................................................................................... 20

2.8 Pembagi Tegangan……………………………………………………….. 21

2.9 Pengubah Analog ke Digital……………………………………………... 22

BAB III. PERANCANGAN RANGKAIAN ....................................... 26

3.1 Diagram Blok............................................................................................. 26

3.2 Perancangan Perangkat keras.................................................................... 27

3.2.1 Rangkaian Sensor Arus ..................................................................... 27

3.2.2 Rangkaian Sensor Tegangan............................................................. 29

3.2.3 Rangkaian Penguat inverting dengan Gain = 1 ................................ 30

3.2.4 Rangkaian Penguat inverting dengan Relay sebagai Saklar………... 31

3.2.5 Otocopler……………………………………………………………. 34

3.2.6 Transustor sebagai Pengaktif Relay………………………………… 36

3.2.7 Rangkaian Penyangga………………………………………………. 37

3.2.8 Rangkaian Penyearah Presisi……………………………………….. 38

3.2.9 Hubungan Sinyal Terkondisi dengan ADC0804…………………… 39

BAB IV. HASIL DAN PEMBAHASAN ............................................. 41

4.1 Sensor Tegangan ........................................................................................ 42

4.1.1 Rangkaian Penguat inverting dengan Gain = 1 ................................ 44

4.1.2 Rangkaian Penyearah Presisi ............................................................ 45

4.1.3 Hubungan Sinyal Terkondisi dengan ADC0804............................... 46

xiii

4.2 Sensor Arus ................................................................................................ 47

4.2.1 Sensor Arus pada Skala 5 Ampere.................................................... 49

4.2.2 Sensor Arus pada Skala 0,5 Ampere................................................. 50

4.2.3 Sensor Arus pada Skala 0,05 Ampere............................................... 51

4.3 Rangkaian Penguat Inverting dan Relay sebagai Saklar............................. 52

4.4 Rangkaian Penyearah Presisi...................................................................... 55

4.4.1 Rangkaian Penyearah Presisi dengan Skala 5 Ampere...................... 56

4.4.2 Rangkaian Penyearah Presisi dengan Skala 0,5 Ampere................... 57

4.4.3 Rangkaian Penyearah Presisi dengan Skala 0,05 Ampere................. 58

BAB V. KESIMPULAN DAN SARAN............................................... 60

5.1 Kesimpulan ................................................................................................ 60

5.2 Saran........................................................................................................... 61

DAFTAR PUSTAKA ............................................................................... 62

LAMPIRAN

xiv

DAFTAR GAMBAR

Gambar 2-1. Penempatan Voltmeter pada pengukuran ................................ 9

Gambar 2-2. Penempatan Ampermeter pada pengukuran ............................ 9

Gambar 2-3. Gelombang sinusoidal penuh ................................................... 10

Gambar 2-4. Pulsa sinusoidal ....................................................................... 11

Gambar 2-5. Pulsa kotak .............................................................................. 11

Gambar 2-6. Gelombang segitiga ................................................................. 12

Gambar 2-7. Rangkaian penguat operasional sebagai penguat inverting .... 13

Gambar 2-8. Penyearah presisi gelombang penuh ....................................... 14

Gambar 2-9. Penguat operasional sebagai penyangga tegangan................... 15

Gambar 2-10. Relay ....................................................................................... 16

Gambar 2-11. Rangkaian saklar transistor ...................................................... 16

Gambar 2-12. Karakteristik keluaran transistor ............................................. 17

Gambar 2-13. Transistor sebagai saklar tertutup ........................................... 18

Gambar 2-14. Transistor sebagai saklar terbuka............................................ 18

Gambar 2-15. Rangkaian LED ....................................................................... 19

Gambar 2-16. Rangkaian phototransistor ....................................................... 20

Gambar 2-17. Pembagi tegangan ................................................................... 21

Gambar 2-18. Diagram blok pengubah analog ke digital .............................. 22

Gambar 2-19. Pin ADC0804........................................................................... 25

Gambar 3-1. Diagram blok rancangan secara keseluruhan .......................... 26

Gambar 3-2. Rangkaian sensor Tegangan (a) rangkaian sensor Arus (b)..... 30

Gambar 3-3. Rangkaian penguat inverting dengan gain = 1 ........................ 31

xv

Gambar 3-4. Rangkaian penguat inverting dan relay sebagai saklar untuk

pemilihan gain ......................................................................... 34

Gambar 3-5. Rangkaian optocoplers ............................................................. 35

Gambar 3-6. Transistor sebagai pengaktif relay .......................................... 37

Gambar 3-7. Rangkaian penyangga ............................................................. 37

Gambar 3-8. Rangkaian penyearah presisi ................................................... 39

Gambar 3-9. Hubungan sinyal terkondisi dengan ADC0804 ...................... 40

Gambar 4-1. Gelombang keluaran sensor tegangan ..................................... 44

Gambar 4-2. Keluaran penyearah presisi ..................................................... 45

Gambar 4-3. Input ADC0804 (multimeter) dan keluaran ADC0804 (LED) 47

Gambar 4-4. Kotak merah sbagai rangkaian uji beban peralatan listrik ...... 48

Gambar 4-5. (a) keluaran sensor arus (b) keluaran sensor tegangan dengan

gain 1 kali skala 5 Ampere ...................................................... 49

Gambar 4-6. (a) keluaran sensor arus (b) keluaran sensor tegangan dengan

gain 10 kali skala 0,5 Ampere ................................................. 50

Gambar 4-7. (a) keluaran sensor arus (b) keluaran sensor tegangan dengan

gain 100 kali skala 0,05 Ampere ............................................. 51

Gambar 4-8. Bentuk gelombang penyearah presisi (Vp) pada skala

5 Ampere ................................................................................ 56

Gambar 4-9. Error pada skala 0,5A (Vp) setelah output dari

rangkaian penyearah presisi melewati 5,00Vp ........................ 57

Gambar 4-10. Offset Gain pada skala 0,5A (Vp) ............................................ 57

Gambar 4-11 Offset Gain pada skala 0,05mA (Vp). ...................................... 59

xvi

DAFTAR TABEL

Tabel 4-1. Data pengamatan input output sensor tegangan dan

kesalahan pengukuran tegangan (Vrms) ..................................... 53

Tabel 4-2. Data pengamatan input output rangkaian penguat inverting

dengan gain = 1 .......................................................................... 55

Tabel 4-3. Data pengamatan input output rangkaian penyearah presisi ...... 57

Tabel 4-4. Data pengamatan sensor Arus untuk skala 5 Ampere dengan

pemilih skala I untuk 1 kali ..................................................... 49-50

Tabel 4-5. Data pengamatan sensor Arus untuk skala 0,5 Ampere

dengan pemilih skala II untuk 10 kali ..................................... 50-51

Tabel 4-6. Data pengamatan sensor Arus untuk skala 0,05 Ampere

dengan pemilih skala III untuk 100 kali ..................................... 52

Tabel 4-7. Data pengamatan input output Rangkaian Penguat Inverting

dan relay sebagai saklar untuk pemilih gain 1 kali ................... 53

Tabel 4-8. Data pengamatan input output Rangkaian Penguat Inverting

dan relay sebagai saklar untuk pemilih gain 10 kali ................. 54

Tabel 4-9. Data pengamatan input output Rangkaian Penguat Inverting

dan relay sebagai saklar untuk pemilih gain 100 kali ................ 55

Tabel 4-10. Data pengamatan pada input output Rangkaian penyearah

presis skala 5 Ampere .............................................................. 56-57

Tabel 4-11. Data pengamatan pada input output Rangkaian penyearah

presisi skala 0,5 Ampere ............................................................ 58

xvii

Tabel 4-12. Data pengamatan pada input output Rangkaian penyearah

presisi skala 0,05 Ampere .......................................................... 59

xviii

DAFTAR LAMPIRAN

Datasheet ADC0804 ....................................................................................... L01

Datasheet 4N35 ............................................................................................... L02

Datasheet Relay 5 volt .................................................................................... L03

Datasheet LF 356 ............................................................................................ L04

Datasheet LM 741

xix

BAB I

PENDAHULUAN

1.1 Latar Belakang Masalah

Seiring dengan perubahan kehidupan masyarakat yang semakin beragam,

rasanya tidak mudah untuk terlepas dari perkembangan teknologi yang semakin

pesat pula. Kemajuan dalam bidang elektronika membawa perkembangan dalam

hal peralatan listrik dan peralatan elektronika. Peralatan listrik baik dalam dunia

industri maupun peralatan rumah tangga yang mengarah pada aplikasi elektronika.

dewasa ini telah banyak kemudahan yang telah disumbangkan oleh dunia

teknologi bagi kehidupan manusia, namun semua itu tidaklah menutup

kemungkinan bagi dunia teknologi untuk terus berkembang dan menciptakan

berbagai temuan baru yang bisa menunjang kelancaran kehidupan manusia.

Penggunaan beban peralatan listrik yang non linier, mengakibatkan

bentuk gelombang arus tidak sama dengan bentuk gelombang tegangan pada

komponen elektronika daya peralatan listrik. Bentuk gelombang yang tidak sinus

akan menimbulkan adanya komponen harmonisa selain frekuensi fundamental.

Komponen arus dapat menimbulkan banyak implikasi pada jala-jala daya listrik.

Hal ini menyebabkan timbulnya rugi-rugi daya listrik, selain itu dapat

menginteferensi saluran komunikasi.

Dalam menganalisis komponen frekuensi harmonisa arus beban peralatan

listrik diperlukan peralatan yang mampu merekam bentuk gelombang yang

diperoleh dari sumber agar sesuai dengan kenyataan yang nantinya bentuk

1

2

gelombang dapat terlihat pada unit penampil. Untuk memperoleh bentuk

gelombang arus beban peralatan listrik, sistem menggunakan sensor arus berupa

resistor yang akan diambil besaran tegangan pada saat resistor dialiri arus listrik,

sedangkan sensor tegangan menggunakan resistor sebagai pembagi tegangan dan

dilakukan penguatan tegangan. Sinyal tegangan keluaran penguat dari sensor arus

dan tegangan selanjutnya diolah oleh mikrokontroler II setelah sebelumnya

melalui ADC untuk diketahui nilai Irms dan Vrms sehingga dapat dihitung nilai

Prms. Sinyal tegangan keluaran penguat dari sensor arus kemudian dimasukkan

ke dalam BPF terkendali digital. BPF ditala pada frekuensi tertentu (fundamental

atau harmonisanya), yang dikendalikan oleh mikrokontroler. Tegangan keluaran

filter dimasukkan ke dalam rangkaian yang dapat mengambil nilai puncak

gelombang, yang kemudian dihubungkan ke pengubah tegangan analog menjadi

data digital. Data digital kemudian direkam oleh mikrokontroler I sesuai dengan

komponen frekuensi harmonisa orde tertentu sesuai penalaan BPF. Setiap kali

mengubah frekuensi pusat dari BPF, dilakukan pengukuran terhadap amplitudo

gelombang. Hasil pembacaan amplitudo komponen harmonisa ini dapat langsung

dikirimkan ke PC. Kemudian data diproses lebih untuk menggambarkan grafik

hubungan antara amplitudo arus beban komponen harmonisa sebagai fungsi orde

frekuensi harmonisa listrik jala-jala. Sarana bantu pemrograman menggunakan

Visual Basic.

Pada penelitian yang akan digunakan sensor arus dan tegangan yang

nantinya dapat mengetahui bentuk gelombang tegangan sama dengan bentuk

gelombang arus yang sesunguhnya, selanjutnya akan dibuat pengondisi sinyal

3

yang akan memudahkan pemprosesan sinyal untuk level tegangan dan sebelum

dilewatkan pada bagian mikrokontroler sebagai pengontrol pada system

penganalisis komponen frekuensi harmonisa yang keluaranya berupa nilai rms

terlebih dahulu haruslah dilewatkan pada sebuah pengubah sinyal analog menjadi

data digital yang dikenal dengan nama (ADC).

1.2 Tujuan penelitian

Tujuan dari penelitian ini adalah:

1. Merancang alat ukur berupa sensor arus dan tegangan untuk mengetahui

gelombang dari besaran arus dan tegangan.

2. Merancang dan membuat pengkondisi sinyal yang berfungsi untuk memproses

level tegangan.

3. Menerapkan pengubah tegangan analog menjadi digital (ADC) untuk

mengambil gelombang arus dan tegangan beban.

1.3 Manfaat Penelitian

Adapun manfaat yang akan dicapai dari penelitian ini adalah:

1. Dapat menghasilkan sebuah alat yang dapat mengubah besaran arus menjadi

besaran tegangan, yang akan dianalisis komponen harmonisanya.

2. Mempermudah pengukuran nilai sebuah rms dan komponen harmonisa arus

dan tegangan peralatan listrik.

3. Menambah literature tentang aplikasi mikrokontroler, yaitu alat ukur nilai rms

dari suatu pengukuran arus dan tegangan dari masukan tegangan AC dan

4

penyedia tegangan DC yang mempresentasikan nilai dari rms pengukuran arus

dan tegangan.

1.4 Batasan Masalah

Pada perancangan perangkat terdapat batasan-batasan sebagai berikut :

1. Terdapat tiga skala untuk pengukuran arus maksimum yaitu 5 Ampere; 0,5

Ampere; 0,05 Ampere.

2. Sensor arus yang digunakan adalah resistor yang akan diambil besaran

tegangan pada saat resistor dialiri arus listrik.

3. Sensor tegangan yang digunakan adalah resistor sebagai pembagi tegangan.

4. Mendeteksi tegangan pada nilai 220 v dengan toleransi ± 20 v.

5. Perancangan pengkondisi sinyal untuk pemprosesan nilai tegangan dan arus

dari ADC yang digunakan.

1.5 Metodologi penelitian

Adapun metodologi yang dilakukan oleh penulis dalam penelitian ini

antara lain :

1. Mengumpulkan literatur dan bahan-bahan dari studi kepustakaan.

2. Menyusun literatur, bahan dan referensi yang ada.

3. Perancangan, pembuatan dan pengujian alat, baik perangkat lunak maupun

keras.

4. Penyusunan laporan dan makalah.

5

1.6 Sistematika Penulisan

Sistematika penulisan terdiri dari beberapa bab, yaitu:

BAB 1. Berisi latar belakang penelitian, tujuan dan manfaat penelitian,

batasan masalah, metodologi penelitian, dan sistematika

penulisan.

BAB II. Berisi dasar teori meliputi sensor arus dan tegangan yang

digunakan adalah resistor yang akan diambil besaran tegangan

saat resistor dialiri arus listrik, nilai rms (root-mean-square),

penguat operasional sebagai pengkondisi sinyal, pengubahan

analog menjadi digital (ADC),

BAB III. Berisi perancangan perangkat keras dan perancangan

perangkat lunak.

BAB IV. Berisi data pengamatan dan pembahasan.

BAB V. Berisi kesimpulan dan saran.

BAB II

DASAR TEORI

2.1 Pengukuran

Secara definitif, pengukuran adalah upaya untuk mendapatkan besaran

kuantitatif yang merupakan hasil perbandingan antara suatu yang ingin diketahui

terhadap standarnya.dalam suatu pengukuran diperlukan instrument sebagai suatu

cara fisis untuk menentukan suatu besaran (kuantitas) atau variabel. Dengan

demikian, sebuah instrument dapat didefinisikan sebagai sebuah alat yang

digunakan untuk menentukan nilai dari suatu kuantitas atau variabel sehingga

instrument dapat pula disebut alat ukur.

Dalam pengukuran digunakan istilah-istilah yang menentukan

Karakteristik suatu alat ukur :[1]

• Presisi (ketelitian)

Adalah suatu ukuran kemampuan untuk mendapatkan hasil pengukuran yang

serupa.

• Akurasi (ketepatan)

Merupakan sifat kedekatan pembacaan alat ukur dengan nilai sebenarnya dari

variabel yang diukur.

• Sensitivitas (kepekaan)

Merupakan perubahan terkecil dari masukan yang mempengaruhi keluaran.

6

7

• Resolusi (kemampuan pembacaan skala)

Resolusi diartikan sebagai satuan terkecil dari keluaran.

• Repeability (kemampuan mengulangi)

Adalah sebagai ukuran deviasi dari hasil uji nilai rata-rata.

• Threshold

Adalah nilai minimum perubahan masukan yang tidak dapat diamati atau

dideteksi,bila masukanya berangsur-angsur bertambah dari nol.

• Linearitas

Merupakan kemampuan untuk menghasilkan ukuran alat ukur yang

menghasilkan keluaran yang linier.[1]

2.1.1 Pengukuran Tegangan Dan Pengukuran Arus

Suatu cara yang populer untuk pengukuran tahanan adalah menggunakan

metoda voltmeter ampermeter. Jika tegangan V antara ujung-ujung tahanan dan

arus I melalui tahanan tersebut diukur, tahanan Rx yang tidak diketahui dapat

ditentukan berdasarkan hukum ohm:[2]

IVR x = (2-1)

V = I x R (2-2) x

8

RVI =

(2-3)

Persamaan (2-1) berarti bahwa tahanan ampermeter adalah nol dan

tahanan voltmeter tak terhingga.

Dalam gambar 2-1 arus sebenarnya (true current) yang disalurkan ke

beban diukur oleh ampermeter, tetapi voltmeter lebih tepat mengukur tegangan

sumber dari pada tegangan beban nyata. Untuk mendapatkan tegangan yang

sebenanya pada beban, penurunan tegangan di dalam ampermeter harus

dikurangkan dari penunjukan voltmeter. Voltmeter dihubungkan langsung

diantara ujung-ujung tahanan seperti dalam gambar 2-2, sehingga voltmeter

mengukur tegangan beban yang sebenarnya. Tetapi ampermeter menghasilkan

kesalahan (error) sebesar arus yang melalui voltmeter. Dalam pengukuran pada

gambar 2-1 dan gambar 2-2 pengukuran Rx kesalahan akan selalu terjadi. Cara

yang betul untuk menghubungkan voltmeter bergantung pada nilai Rx berserta

tahanan voltmeter dan ampermeter, umumnya tahanan ampermeter adalah rendah

sedangkan tahanan voltmeter adalah tinggi.[2]

9

Gambar 2-1.Penempatan voltmeter pada pengukuran.

Gambar 2-2.Penempatan Ampermeter pada pengukuran.

2.2 Nilai Rms (root-mean-square)

Nilai rms digunakan untuk menentukan keakuratan penghantaran suatu

alat dan tingkat tegangan suatu alat. Gelombang tegangan yang berupa sinusoidal

yang sederhana atau berbentuk empat persegi panjang yang sederhana sering

menjadi masalah dalam menentukan nilai rms. Nilai rms suatu gelombang dapat

dihitung berdasarkan rumus berikut:[3]

∫=T

rms dtIT

I0

2 .1 (2-4)

10

Dengan T adalah perioda waktu. Secara umum, nilai rms merupakan akar dari

kuadrat rata-rata suatu gelombang. Apabila gelombang menjadi rusak sampai

pada harmonisanya, nilai rms dapat dihitung secara individual. Nilai rms dari

gelombang nyata hasil dari aproksimasi yang memuaskan dengan

mengkombinasikan nilai rms dari setiap harmonisanya. Nilai rms suatu

gelombang dapat dihitung berdasarkan rumus berikut:[3]

2)(

2)2(

2)1(

2 ... nrmsrmsrmsdcrms IIIII ++++= (2-5)

Dengan: Idc adalah tegangan komponen DC, Irms dan Irms adalah nilai rms

dari frekuensi fundamental dan komponen harmonik ke-n, secara individu.

)1( )(n

Berikut ini adalah nilai rms yang berbeda dari bermacam-macam bentuk

gelombang:[3]

• Gelombang sinusoidal penuh

Gambar 2-3. Gelombang sinusoidal penuh.

Nilai rms dari gelombang sinusoidal penuh adalah:

2p

rms

II = (2-6)

11

• Pulsa sinusoidal

Gambar 2-4. Pulsa sinusoidal.

Nilai rms dari pulsa sinusoidal adalah:

T

TII prms 2

0= (2-7)

• Pulsa kotak

Gambar 2-5. Pulsa kotak.

Nilai rms dari pulsa kotak adalah:

TT

II prms0= (2-8)

\

12

• Gelombang segitiga

Gambar 2-6. Gelombang segitiga.

Nilai rms dari gelombang segitiga adalah:

T

TII prms 3

2 0= (2-9)

Nilai puncak (peak) atau nilai maksimum merupakan nilai puncak

gelombang, baik pada bagian positif ataupun negatif. Nilai ini ditunjukkan oleh Ip

pada persamaan 2-5, 2-6, 2-7 dan 2-8.

2.3 Penguat Operasional (op_Amp)

2.3.1 Penguat Operasional sebagai Penguat Inverting

Rangkaian penguat operasional sebagai penguat inverting terdiri atas

sebuah penguat operasional dan dua buah resistor. Rangkaian ini menggunakan

feedback supaya penguatan dari penguat operasional lebih kecil dibandingkan

dengan penguatan large signal voltage gain sebesar 200.000 untuk ic LM741,

seperti yang tertera pada datasheet. Rangkaian penguat operasional sebagai

penguat inverting ditunjukkan pada gambar 2-7.

13

Rf

1k

Vo

+

-

Vi

Ri

Gambar 2-7.Rangkaian penguat operasional sebagai penguat inverting.

Besarnya penguatan dapat dihitung dengan:

RiRf

=Penguatan (2-10)

Rinv = Avinv. Rfinv (2-11)

Besarnya gain dapat dihitung dengan:

Avinv = ViVo (2-12)

2.3.2 Penguat Operasional sebagai Penyearah Presisi Gelombang

penuh

Rangkaian penguat operasional sebagai penyearah presisi gelombang

penuh terdiri atas dua buah penguat operasional, penguat operasional yang

pertama berfungsi sebagai penyearah presisi setengah gelombang dan penguat

operasional yang kedua berfungsi sebagai penjumlah pembalik. Keuntungan

menggunakan penyearah presisi gelombang penuh adalah tegangan keluaran yang

tidak mengalami pengurangan tegangan yang disebabkan oleh tegangan bias maju

14

dioda, sehingga tegangan dibawah tegangan bias maju dioda juga dapat

disearahkan. Untuk mengatur besarnya penguatan, dapat diatur berdasarkan rumus

berikut :

RRf

=Penguatan (2-13)

Rfpp = Avpp . Rpp (2-14)

Besarnya gain dapat dihitung dengan:

Avpp = ViVo (2-15)

Rangkaian penguat operasional sebagai penyearah presisi gelombang

penuh ditunjukkan pada gambar 2-8.

D2

R

+

-

D1

RRfR/2

R

+

-

Vo

Vi

Gambar 2-8. Penyearah presisi gelombang penuh.

15

2.3.3 Penguat Operasional Sebagai Penyangga Tegangan

Penguatan tegangan yang dihasilkan rangkaian penguat operasional

sebagai penyangga tegangan adalah sama dengan satu, sehingga tegangan

keluaran “mengikuti” tegangan masukan. Secara ideal, impedansi inputnya tak

terhingga dan impedansi outputnya sama dengan nol. Dengan demikian,

rangkaian penguat operasional sebagai penyangga tegangan dapat berfungsi

sebagai isolasi antara sumber dan beban sehingga level tegangan sumber dapat

terjaga. Penguat operasional sebagai penyangga mempunyai konfigurasi seperti

ditunjukkan gambar 2-9.

Vo+

-

Vi

Gambar 2-9. Penguat operasional sebagai penyangga tegangan.

2.4 Relay

Relay adalah suatu komponen elektronika yang akan bekerja bila ada arus

yang melalui kumparannya. Sebuah relay terdiri dari kumparan yang dililitkan

pada inti besi dan kontak-kontak penghubung. Apabila kumparan yang melilit inti

besi dilalui arus listrik maka akan menimbulkan induksi medan magnet, dan

induksi ini akan menarik kontak-kontak penghubung relay. Diagram relay

ditunjukkan pada gambar 2-10 berikut ini.

16

Common

Kumparan

35

412

NC

NO

Gambar 2.10 Relay

Kontak penghubung relay terdiri dari dua bagian, yaitu :

1. Kontak NC (Normally Closed)

Kontak penghubung dalam kondisi menutup atau terhubung bila relay tidak

mendapat masukan tegangan pada kumparannya. Tetapi bila diberi tegangan

yang mencukupi pada kumparannya maka kontak penghubung menjadi

terbuka.

2. Kontak NO (Normally Open)

Kontak penghubung dalam kondisi terbuka bila relay tidak mendapat

tegangan pada kumparannya. Tetapi bila diberi tegangan yang mencukupi

pada kumparannya maka kontak penghubung menjadi tertutup.

2.5 Transistor Sebagai Saklar

Rangkaian saklar transistor ditunjukkan oleh gambar 2-11.

Rc

Vcc

QVBB

IB

Ic

Rb

Gambar 2-11 Rangkaian saklar transistor

17

Sedangkan karakteristik keluaran transistor ditunjukkan oleh gambar 2-12

Gambar 2-12 Karakteristik keluaran transistor.

Tansistor berada dalam keadaan saturasi/jenuh saat IB = IB0. Pada keadaan

ini, beda potensial antara kolektor dan emitter (Vce) adalah sangat kecil, yaitu

sama dengan Vce(sat), sedangkan arus kolektor IC yang mengalir hampir sama

dengan Vcc/Rc. Jika arus basis diperbesar menjadi IB1 atau IB2 atau lebih besar lagi,

nilai Vce dan IC tidak mengalami perubahan. Nilai Vce = Vce(sat) dan nilai IC =

Vcc/Rc. Hal inilah yang disebut dengan keadaan saturasi sebab nilai IC dan Vce

tidak berubah walaupun arus basis bertambah besar.

Nilai arus basis tergantung dari tegangan VBB yang digunakan untuk

meng-on-kan /mengaktifkan transistor dan juga pada hambatan Rb yang

dihubungkan seri dengan basis. Arus basis IB diperoleh berdasarkan persamaan :

b

beBBB R

VVI

−= (2-16)

Arus colector Ic diperoleh berdasarkan persamaan :

=cIc

cc

RV

(2-17)

18

Jika arus basis lebih dari 0 atau semakin besar maka transistor menjadi on

sehingga dapat berfungsi sebagai saklar tertutup. Transistor sebagai saklar tertutup

ditunjukkan oleh gambar 2-13.

Rc

Vcc

QVBB

Vcc

IB > 0

IcRc

Rb

Gambar 2-13 Transistor sebagai saklar tertutup

Sedangkan jika arus basis sama dengan 0, maka dapat dikatakan transistor

bekerja di daerah cut-off sehingga transistor menjadi off dan berfungsi sebagai

saklar terbuka. Transistor sebagai saklar tebuka ditunjukkan oleh gambar 2-14.

Vcc

Rb

Rc

QVBB

Ib = 0

Ic Rc

Vcc

Gambar 2-14 Transistor sebagai saklar terbuka

2.6 Dioda Memancarkan Cahaya (Light Emitting Diode)

Pada dioda yang diberi prategangan maju, elektron bebas melintasi

persambungan dan jatuh ke dalam lubang (hole). Pada saat elektron ini jatuh dari

tingkat energi yang lebih tinggi ke tingkat energi yang lebih rendah, ia

19

memancarkan energi. Pada dioda-dioda biasa, energi ini keluar dalam bentuk

panas. Tetapi pada Light Emitting Diode (LED), energi memancar sebagai cahaya.

LED telah menggantikan lampu-lampu pijar dalam beberapa pemakaian karena

tegangannya yang rendah, umurnya yang panjang, dan switch mati-hidupnya yang

cepat.

Gambar 2-15 memperlihatkan lambang skematis untuk LED. Resistor

LED dapat dihitung sebagai berikut :

led

led

IVVccRx −

= (2-18)

Dengan ILED adalah arus yang melalui LED, Vcc adalah tegangan catu daya, VLED

adalah tegangan pada LED, dan Rx adalah resistansi yang diseri dengan LED

Gambar 2-15 Rangkaian LED

20

2.7 Phototransistor

Phototransistor adalah sebuah transistor yang titik kerjanya dipengaruhi

oleh cahaya tertentu, cahaya yang memancar ke transistor tersebut akan

menyebabkan timbulnya arus basis (Ib), sehingga transistor tersebut on. Dalam

phototransistor untai basisnya dibiarkan terbuka sehingga bila tidak ada cahaya,

transistor ini akan off.

Rangkaian phototransistor sebagai sensor cahaya ditunjukkan pada

Gambar 2-16 sebagai berikut.

Vo

Ic

Ie

Rc

QSD123

12

0

VCC 5V

Gambar 2-16 Rangkaian Phototransistor

Arus kolektor yang tepat menimbulkan saturasi adalah:

IC(sat) = C

CC

RV

(2-19)

IcVccRc = (2-20)

Sedangkan,

IE ≅ IC (2-21)

21

Dan,

IC = β IB (2-22)

2.8 Pembagi Tegangan

Rangkaian pembagi tegangan dapat dilihat pada gambar 2-17 berikut ini

Gambar 2-17 Pembagi tegangan

Dari gambar 2-17 diatas, nilai V0 bisa dihitung sebagai berikut:

xVLRR

RVo21

2+

= (2-23)

Sedangkan nilai VL sendiri adalah sebagai berikut:

VL =VR1 + VR2 (2-24)

22

2.9 Pengubahan Analog ke Digital

Pengubahan sinyal analog ke system digital disebut pengkode atau encoder.

Gambar 2-18 memperlihatikan diagram blok pengubah analog ke digital yang

dapat memberikan gambaran kepada kita mengenai pengubahan sinyal analog ke

digital.

MSB LSB

Pengubah analog ke digital

D C B A Masukkan analog

Gambar 2-18. Diagram blok pengubah analog ke digital.

Dari diagram blok gambar 2-18,memperlihatkan masukkan berupa sinyal

listrik analog yang harus diubah menjadi keluaran biner dari bit paling rendah

(LSB) sampai bit yang paling tinggi (MSB).

Pengubah analog ke digital yang digunakan oleh penulis adalah ADC0804

yang dibuat untuk dapat langsung berhubungan dengan mikroprosesor baik Zilog

80, 8080, atau mikroprosesor 8 bit lainnya. IC ini merupakan CMOS 8 bit yang

mendekati pengubah analog ke digital. Sinyal masukkan maupun sinyal keluaran

dari IC ini, sesuai untuk MOS dan TTL. IC ADC0804 mempunyai waktu

pengubahan 100µS terhadap pengubahan masukkan dan mengeluarkan dalam

bentuk biner. Beroperasi pada daya standar +5 volt dan dapat menerima masukkan

23

analog berkisar 0volt sampai 5 volt. Macam-macam pin (kaki) yang dimiliki oleh

IC ADC 0804.

a. CS

Berfungsi sebagai masukkan. Pin ini sebagai chip select dari kontrol

mikroprosesor.

b. RD

Berfungsi sebagai masukkan. Pin ini sebagai kontrol untuk membaca data dari

mikroprosesor.

c. WR

Berfungsi sebagai masukkan. Pin ini sebagai kontrol untuk menulis data ke

mikroprosesor.

d. CLK IN

Berfungsi sebagai masukkan. Pin ini sebagai pengatur detak.

e. INTR

Berfungsi sebagai keluaran. Pin ini sebagai sarana untuk memberikan

interupsi pada masukkan interupsi mikroprosesor.

f. V (+) IN

Berfungsi sebagai masukkan. Pin ini merupakan jalan masuk bagi sinyal

analog masukkan positif.

g. V (-) IN

Berfungsi sebagai masukkan. Pin ini merupakan jalan masuk bagi sinyal

analog masukkan negatif.

24

h. A GND

Berfungsi sebagai masukkan daya. Pin ini sebagai pembulatan analog.

i. V /2 REF

Berfungsi sebagai masukkan. Pin ini merupakan jalan masuk bagi tegangan

acuan yang lain (±).

j. D GND

Berfungsi sebagai keluaran. Pin ini sebagai pembulatan digital.

k. DB7-DB0

Berfungsi sebagai keluaran. Pin ini merupakan jalan keluaran bagi data

keluaran bit7 sampai bit0.

l. CLKR

Berfungsi sebagai masukkan. Pin ini sebagai pengatur detak dengan

menghubungkannya ke resistor eksternal.

m. V CC (Or ref)

Berfungsi sebagai masukkan daya. Pin ini sebagai jalan masuk untuk catu

daya +5 volt dan tegangan acuan primer.

Resolusi ADC dengan jumlah bit (n), dapat dihitung dengan rumus berikut:

12 −

= nmakV

resolusi Volt/step (2-25)

25

ADC0804

67

9111213141516171819

45

123

10

8

20

+IN-IN

VREF/2DB7DB6DB5DB4DB3DB2DB1DB0

CLKR

CLKININTR

CSRDWR

D GND

A GND

VCC

Gambar 2-19. Pin ADC0804.

BAB III

RANCANGAN PENELITIAN

3.1 Diagram Blok

Gambar 3-1 menunjukkan diagram blok perancangan alat pengukuran arus

dan tegangan pada sistem penganalisis komponen frekuensi harmonisa arus beban

peralatan listrik.

Gambar 3-1. Diagram blok rancangan secara keseluruhan.

26

27

Tegangan masukan AC dari keluaran rangkaian sensor arus dan tegangan

terlebih dahulu melewati rangkaian penguat inverting yang dapat diatur

penguatannya dengan relay sebagai pemilihan saklar agar sesuai dengan

jangkauan ADC dan penguat operasional. Keluaran dari penguat inverting akan

melewati penyearah presisi sehingga keluaran dari penyearah presisi selalu

mempunyai nilai positif. Keluaran penyearah presisi diumpankan menuju ADC

yang digunakan agar nilai tegangan masukan ADC bisa diproses oleh

mikrokontroler karena sebelumnya merupakan sinyal analog yang perlu diubah

terlebih dahulu menjadi sinyal digital.

Mikrokontroler mengambil data keluaran dari ADC sebanyak 8 bit dengan

256 kali pencuplikan dengan kecepatan pengambilan data yang konstan. Nilai

tegangan rms hasil pencuplikan akan diperoses dalam mikrokontroler. Nilai rms

sebanyak 8 bit akan diteruskan mikrokontroler menuju LCD sebagai penampil

setelah disesuaikan dengan pemilihan jangkauan level tegangan pada relay

sebagai saklar. Proses penampillan nilai rms ke LCD membutuhkan 10 bit data

dan 3 bit data dibutuhkan untuk pemilihan jangkauan level tegangan pada relay

sebagai saklar .

3.2 Perancangan Perangkat Keras

3.2.1 Rangkaian Sensor Arus

Rangkaian sensor arus diambil dari 10 buah resistor 10 /5w yang

dipasang secara paralel sehingga didapatkan resistor yang nilai resistansinya 1

Ω

Ω /

5w dimana pemilihan resistansi didasari atas pemilihan skala arus pada alat yang

akan dibuat yaitu skala pengukuran 5 Ampere, 0,5 Ampere, dan 0,05 Ampere.

28

Pemilihan skala tersebut haruslah sesuai dengan besarnya tegangan arus yang

dibutuhkan untuk penguatan pada rangkaian penguat inverting dan relay sebagai

saklar untuk pemilihan gain.

Nilai skala pemilihan arus untuk masukan penguat inverting dan relay

sebagai saklar untuk pemilihan gain, ditentukan sebagai berikut.

Nilai skala pada saat I = 5A diperlukan tegangan Ac sebesar 5 v dengan

Rx=1Ω berdasarkan persamaan 2-2, sehingga didapatkan :

Vx = 5A x 1Ω

= 5 volt

Tegangan pada masukan beban listrik akan terbebani sebesar 5v (peak) dari

tegangan masukan jala-jala 220 2 (peak), sehingga penurunan tegangan pada

beban dihitung sebagai berikut:

Vx : 2

5v : 2 = 3,53v

Didapatkan penurunan tegangan 100220

53,3 xvv =1,59% terhadap tegangan jala-jala

listrik 220 v 2 , penurunan tegangan sebesar 1,59% dianggap kecil.

Nilai skala pada saat I = 0,5A diperlukan tegangan Ac sebesar 0,5v dengan

Rx=1Ω berdasarkan persamaan 2-2, sehingga didapatkan :

Vx = 0,5A x 1Ω

= 0,5 volt

29

Tegangan pada masukan beban listrik akan terbebani sebesar 0,5v (peak) dari

tegangan masukan jala-jala 220 2 (peak),penurunan tegangan pada beban

dihitung sebagai berikut:

Vx : 2

0,5v : 2 = 0,35v

Didapatkan penurunan tegangan 100220

35,0 xvv =0,15% terhadap tegangan jala-jala

listrik 220 v 2 , penurunan tegangan sebesar 0,15% dianggap kecil.

Nilai skala pada saat I = 0,05A diperlukan tegangan Ac sebesar 0,05v

dengan Rx=1Ω berdasarkan persamaan 2-2, sehingga didapatkan :

Vx = 0,05A x 1Ω

= 0.0 5 volt

Tegangan pada masukan beban listrik akan terbebani sebesar 0,05v (peak) dari

tegangan masukan jala-jala 220 2 (peak), penurunan tegangan pada beban

dihitung sebagai berikut:

Vx : 2

0,05v : 2 = 0,035v

Didapatkan penurunan tegangan 100220035,0 x

vv = 0,015% terhadap tegangan jala-

jala listrik 220 v 2 , penurunan tegangan sebesar 0,015% dianggap kecil.

30

3.2.2 Rangkaian Sensor Tegangan

Rangkaian sensor tegangan terdiri dari dua buah resistor yaitu R1 dan R2

sebagai pembagi tegangan. Tegangan maksimum dari beban adalah sebesar

2240x (peak) dan keluaran sensor yang dinginkan adalah sebesar 5v(peak).

Dengan menentukan R2=10k maka nilai R1 berdasarkan persamaan (2-22)

ditentukan sebagai berikut :

212RR

RViVo

+=

kRk101

102240

5+

=

R1 + 10k = 678,82k

R1 =668,82k

(a) (b)

Gambar 3-2. Rangkaian sensor tegangan (a) dan sensor arus (b)

31

3.2.3 Rangkaian Penguat inverting dengan Gain = 1

Rangkaian penguat inverting digunakan untuk membatasi nilai tegangan.

Masukan maksimum dari ADC yang digunakan yaitu 5 Vp. Keluaran dari

rangkaian pembagi tegangan sebagai sensor tegangan 5 v nantinya akan dikuatkan

dengan rangkaian penguat inverting.

Nilai gain untuk amplitudo masukan tegangan AC maksimum 5 volt

berdasarkan persamaan (2-11) ditentukan sebagai berikut:

Avinv = 55

Avinv = 1

Dengan pemilihan Rfinv sebesar 100 kΩ maka nilai Rinv berdasarkan persamaan

(2-10) dapat dihitung

Rinv = 1 . 105

Rinv = 100 kΩ

Gambar 3-3. Rangkaian penguat inverting degan gain = 1

32

3.2.4 Rangkaian Penguat Inverting dan Relay sebagai Saklar

untuk Pemilih Gain.

Penguat inverting ini digunakan untuk membatasi nilai tegangan

masukkan maksimal agar sesuai dengan masukkan ADC 0804 yaitu 5 Vp, saat

tegangan masukkan melebihi tegangan masukkan ADC. Sesuai dengan batasan

masalah maka digunakan 3 gain yaitu dengan tegangan masukkan maksimum 5

Ampere, 0,5 Ampere dan 0,05Ampere. Pemilihan Riinv dan Rfinv, didasarkan pada

kebutuhan gain dengan perhitungan sebagai berikut:

Nilai gain untuk amplitudo masukan tegangan AC maksimum 5 volt

berdasarkan persamaan (2-11 ) ditentukan sebagai berikut :

Avinv1 = 55

Avinv1 = 1

Dengan pemilihan Rfinv sebesar 100 kΩ maka nilai Riinv 1 berdasarkan persamaan

(2-10) dapat dihitung:

Riinv 1= 1 . 105

Riinv 1= 100 kΩ

Nilai gain untuk amplitudo masukan tegangan AC maksimum 0,5 volt

berdasarkan persamaan (2-11 ) ditentukan sebagai berikut :

Avinv2 = 5,0

5

Avinv2 = 10

33

Dengan pemilihan Rfinv sebesar 100 kΩ maka nilai Riinv 2 berdasarkan persamaan

(2-10) dapat dihitung:

Riinv2 = 10105

Riinv2 = 10KΩ

Nilai gain untuk amplitudo masukan tegangan AC maksimum 0,05 volt

berdasarkan persamaan (2-11 ) ditentukan sebagai berikut :

Avinv3 = 05,05

Avinv3 = 100

Dengan pemilihan Rfinv sebesar 100 kΩ maka nilai Riinv 3 berdasarkan persamaan

(2-10) dapat dihitung:

Riinv3 = 100105

Riinv3 = 1KΩ

Rangkaian penguat inverting dan relay sebagai saklar untuk pemilihan gain

ditunjukkan gambar 3-4.

34

Gambar 3-4. Rangkaian penguat inverting dan relay sebagai saklar untuk

pemilihan gain.

Dari gambar 3-4, jika penguatan adalah sebesar 1x pada Vo sebagai

rangkaian penguat inverting maka relay1 pada posisi NC, relay1 aktif karena

mendapat masukan pada IN_1 yang berasal dari keluaran mikrokontroler.

Demikian juga untuk relay2 dan relay3 dengan besar penguatan yang berbeda

yaitu 10x dan 100x maka relay2 dan relay3 akan pada posisi NC jika pada IN_2

dan IN_3 mendapat masukan dari mikrokontroler. besarnya penguatan terjadi

karena perbandingan Vo dan Vi, serta besarnya R_inv dan Rf_inv ditentukan

dalam perhitungan.

3.2.5 Optocouplers

Rangkaian optocouplers digunakan sebagai isolator pengaman pada

keluaran ADC dan masukan mikrokontroler. Pada datasheet optocouplers 4N35M

diketahui besarnya Iled 10mA dan Vled 1,1volt sehingga dapat menghitung R. Nilai

Rx dihitung berdasarkan persamaan (2- 17) sebagai berikut:

35

= Ω=− 390

101,15

mAVV

Sesuai datasheet diketahui Ic 0,5mA sehingga Rc dapat dihitung

berdasarkan persamaan (2-19) sebagai berikut:

mAV

5,05

=

=10kΩ

Gambar rangkaian optocouplers sebagai isolator dapat dilihat pada gambar 3-5

Gambar 3-5 Rangkaian optocouplers.

Dari gambar 3-5 jika keluaran pada ADC adalah aktif rendah,

mengakibatkan led aktif, hal ini menyebabkan transistor aktif dan IN

mikrokontroler akan bernilai aktif rendah. Jika nilai ADC aktif tinggi,

mengakibatkan led tidak aktif, sehingga transistor tidak aktif dan nilai IN

mikrokontroler akan bernilai aktif tinggi, sehingga data keluaran dari ADC dapat

diterima oleh mikrokontroler.

36

3.2.6 Transistor Sebagai Pengaktif Relay

Rangkaian Transistor digunakan sebagai pengaktif relay, pada datasheet

diketahui β transistor Fc9012 = 160, dan Rd coil = 125Ω, maka akan didapat nilai

RB melalui perhitungan berdasarkan persamaan (2-16) sebagai berikut :

Ic = Ω125

5V

Ic = 40 mA

mAI

mAI

II

II

B

B

CB

CB

25.0160

40

=

=

=

=

β

β

Berdasarkan persamaan (2-15)maka didapat RB:

RB = B

BEcc

IVV −

RB =mA

vv25.0

7.05 −

RB = 17200 Ω = 17.2kΩ Maka dipilih nilai = 15k agar benar-benar saturasi, gambar rangkaian dari

transistor sebagai pengaktif relay dapat dilihat pada gambar 3-6.

BR

37

Gambar 3-6 transistor sebagai pengaktif relay

3.2.7 Rangkaian Penyangga

Dengan menggunakan rangkaian penyangga, maka tegangan keluaran dari

rangkaian penyangga adalah sama dengan tegangan masukkan dari rangkaian

penyangga baik dalam hal magnitudo maupun polaritasnya.

Rangkaian penyangga juga mempunyai hambatan masukkan yang tinggi sehingga

arus dari tegangan masukkan rangkaian penyangga dapat diabaikan. Rangkaian

penyangga ditunjukkan pada gambar 3-7.

tegangan keluaran pembalik

+

-

U2

LF356

3

26

tegangan keluaran buf f er

Gambar 3-7. Rangkaian penyangga.

38

3.2.8 Rangkaian Penyearah Presisi

Rangkaian penyearah presisi digunakan sebagai penyearah tegangan

keluaran buffer sehingga didapatkan harga mutlak dari tegangan keluaran

rangkaian penguat inverting dengan gain dan relay sebagai saklar. Tegangan

keluaran maksimum dari rangkaian penguat inverting dengan gain dan relay

sebagai saklar telah sesuai dengan tegangan masukan ADC0804 yaitu 5 Volt,

maka penguatan untuk rangkaian penyearah presisi berdasarkan persamaan (2-14)

ditentukan sebagai berikut :

Avpp = 55

Avpp = 1

Dengan mengacu pada gambar 2-8, maka dua buah resistor yang

dibutuhkan adalah sebesar R dan 2R . Resistor yang terdapat dipasaran untuk

memenuhi kedua nilai resistor tersebut tanpa menghubungkan resistor secara seri

maupun paralel, adalah pasangan resistor R sebesar 20 KΩ dan resistor 2R

sebesar 10 KΩ. Dengan pemilihan Rpp sebesar 20 KΩ maka nilai Rfpp berdasarkan

persamaan (2-13) dapat dihitung sebagai berikut:

Rfpp = Avpp . Rpp

Rfpp = 1 . 2.105

Rfpp = 20kΩ

39

Dioda yang digunakan adalah 1N4148 karena gelombang keluarannya bisa

tetap stabil dengan frekuensi tinggi dan mempunyai kecepatan respon yang tinggi.

Rangkaian penyerah presisi ditunjukkan gambar 3-8.

R2 pp

20K

Rf pp

20K

+

-

U3

LF356

3

26

tegangan keluaran pembalikD2 pp

1N4148

R1 pp

20K

R pp/2

10K

D1 pp

1N4148

+

-

U2

LF356

3

26

R3 pp

20K

tegangan keluaran peny earah presisi

Gambar 3-8. Rangkaian penyearah presisi

3.2.9 Hubungan Sinyal Terkondisi dengan ADC0804

Pin start conversion ADC ( SC ) dihubungkan ke ground agar ADC0804

selalu melakukan konversi data. Pin DR pada ADC 0804 juga dihubungkan ke

ground sehingga ADC selalu membaca data dari mikrokontroler. Pin WR

dihubungkan dengan P0.0 pada Mikrokontroler AT89s51 yang bertujuan agar

penulisan data dari ADC0804 menuju mikrokontroler dapat dikendalikan oleh

mikrokontroler.

Tegangan masukan ADC0804 adalah tegangan keluaran penyearah presisi

yang dihubungkan pada pin +IN. Berdasarkan datasheet, untuk mencapai waktu

konversi ADC0804 sebesar 100 µs, dibutuhkan resistor 10 KΩ dan kapasitor 150

pF. Pada rangkaian ini, juga digunakan dioda zener 5,1 Volt sebagai pembatas

40

tegangan agar saat tegangan masukan ADC0804 bernilai sama dengan tegangan

saturasi penguat operasional, tegangan tersebut tidak merusak IC ADC0804.

CAP ADC150pf

D55,1V

R ADC10k

5 Volt

tegangan keluaran peny earah presisi

U4

ADC0804

67

9111213141516171819

45

123

10

8

20

+IN-IN

VREF/2DB7DB6DB5DB4DB3DB2DB1DB0

CLKR

CLKININTR

CSRDWR

D GND

A GND

VCC

Gambar 3-9. Hubungan sinyal terkondisi dengan ADC0804.

Tegangan masukan positif dibatasi sebesar 5,1 Volt sesuai dengan nilai

dioda zener, sedangkan tegangan masukan negatif dibatasi sekitar 0,7 Volt, sesuai

dengan tegangan maju dioda silikon. Hubungan sinyal terkondisi dengan ADC

ditunjukkan pada gambar 3-9.

BAB IV

HASIL DAN PEMBAHASAN

Pada bab ini akan ditampilkan data hasil pengukuran tegangan dan arus

dengan skala yang berbeda-beda. Pengukuran yang dilakukan bertujuan untuk

mengetahui kemampuan, ketelitian dan hasil realisasi rancangan alat. Proses

pengukuran sendiri dilakukan dengan membandingkan nilai rms tegangan dan

arus pada LCD dengan alat ukur referensi, yaitu multimeter digital dengan merek

SANWA CD 800a dan sebuah tang Ampere digital dengan merek CONSTANT

AC600 Terdapat tiga skala untuk pengukuran arus maksimum yaitu 5 Ampere,

0,5 Ampere, 0,05 Ampere, pengukuran tegangan rms juga dilakukan dengan

mendeteksi tegangan pada nilai 220 volt dengan toleransi ± 20 volt.

Tahap pengujian meliputi pengukuran tegangan saja, pengukuran arus saja,

pengukuran tegangan dan arus.

Hasil suatu pengamatan sudah tentu memiliki nilai yang menyimpang dari

nilai yang ditinjukkan oleh alat pembanding. Pada sub bab ini, nilai galat untuk

menunjukkan penyimpangan atau kesalahan pada sistem dihitung untuk tampilan

data tegangan rms (Vrms), arus rms (Irms), dan Penyimpangan yang terjadi antara

nilai hasil pengamatan dengan nilai yang ditunjukkan oleh alat pembanding saat

input digital tertentu dapat dihitung dengan menggunakan % galat, yaitu

menggunakan persamaan :

Galat = 100teorinilai

pengamatan nilai- teorinilai× % (4-1)

41

42

Jika hasil pengamatan dan nilai yang ditunjukkan oleh alat pembanding

dari data tegangan rms (Vrms), arus rms (Irms), yang terdapat pada tabel 4-1

dimasukkan ke persamaan di atas, maka akan diketahui besarnya tingkat

kesalahan yang dihasilkan oleh alat.

4.1 Sensor Tegangan

Data hasil pengukuran tegangan rms untuk percobaan rangkaian diperoleh

dengan memberikan masukan tegangan AC didapatkan dari keluaran trafo yang

divariabel keluarannya agar mendapatkan nilai masukan yang diinginkan.

Secara umum pengukuran tegangan dilakukan dengan cara seperti ditunjukkan

gambar 3-2 (a)

Dari gambar 3-2 (a), pengukuran dilakukan dengan memberi masukan

tertentu, R1 dan R2 sebagai pembagi tegangan. Kemudian pada V (keluaran

sensor tegangan) akan didapatkan nilai keluaran pembagi tegangan yang sesuai

dengan masukan yang diberikan dan diukur menggunakan alat ukur referensi

(multimeter) untuk kemudian dicari selisihnya.

Analisa data tegangan menggunakan data pada tabel 4-1, dapat terlihat

bahwa alat sudah mampu mengukur tegangan dengan jangkauan 195~240 Vrms

dengan tingkat kesalahan rerata kurang dari 2%.

Dari percobaan yang dilakukan diperoleh data pada sensor tegangan

seperti pada tabel 4-1

43

Tabel 4-1

Data pengamatan input output sensor tegangan dan kesalahan pengukuran

tegangan (Vrms)

Sensor Tegangan

Teoritis

Terukur No

VIn sensor

(Rms)

Vin (Rms)

Vout (Vp)

vin (Rms)

Vout (Vp)

LCD

(Vrms)

Galat (Vrms)

persen Galat (%)

1 195 2,58 3,66 2,59 2,60 193 2 1,026 2 201 2,66 3,77 2,67 3,80 201 0 0,000 3 205 2,99 4,24 3,00 3,70 206 1 0,488 4 210 3,08 4,36 3,09 3,80 210 0 0,000 5 217 3,17 4,49 3,18 3,90 220 3 1,382 6 220 3,22 4,56 3,23 3,97 224 4 1,818 7 235 3,44 4,87 3,45 4,20 235 0 0,000 8 237 3,45 4,89 3,46 4,28 239 2 0,844 9 240 3,50 4,96 3,51 4,35 241 1 0,417

mean 217,77 3,12 4,42 3,13 3,84 218,77 1,4444 0,664

Dari table 4-1 Perhitungan teoritis berdasarkan persamaan 2-5, sehingga

didapatkan data pada perbandingan antara teoritis dengan data terukur untuk

sensor tegangan yang hampir mendekati nilai perancangan. Diketahui kesalahan

rata-rata galat sebsar 1,4444 Vrms dan persentase kesalahan rerata galat sebesar

(0,664%) dengan persentase kesalahan maksimum 4 Vrms (1.818%). Sedangkan

gambar bentuk glombang dari keluaran sensor tegangan dapat dilihat pada gambar

4-1 dibawah ini.

44

Gambar 4-1 gelombang keluaran sensor tegangan

4.1.1 Rangkaian Penguat Inverting dengan Gain = 1

Pada sub bab ini dilakukan pengukuran tegangan input output pada

rangkaian penguat inverting dan pada pengamatan data didapatkan antara

masukan yang diberikan pada rangkaian adalah sama dengan data yang dihasilkan

pada keluaran, hal ini dikarenakan oleh sifat rangkaian yaitu tegangan masukan

mengikuti tegangan keluaran. Data pengamatan input output rangkaian penguat

inverting dengan Gain = 1 dapat dilihat pada tabel 4-2 dibawah ini.

Tabel 4-2

Data pengamatan input output rangkaian penguat inverting dengan Gain = 1

Vin Vout No (Vrms) (Vp-p) (Vrms) (Vp-p)

A

1 2,59 5,2 2,59 5,2 1 2 2,67 7,6 2,67 7,6 1 3 2,74 7,4 2,74 7,4 1 4 2,81 7,6 2,81 7,6 1 5 2,9 7,8 2,9 7,8 1 6 2,95 7,94 2,95 7,94 1 7 3,12 8,4 3,12 8,4 1 8 3,17 8,56 3,17 8,56 1 9 3,2 8,7 3,2 8,7 1

45

Dari tabel 4-2 dapat dilihat bahwa besarnya penguatan yang terjadi adalah = 1,

sehingga sudah sesuai dengan perancangan dan seterusnya sinyal yang dihasilkan

akan diberikan pada penyearah presisi untuk diproses lebih lanjut.

4.1.2 Rangkaian Penyearah Presisi

Pada sub bab ini dilakukan pengamatan untuk keluaran penyearah presisi,

masukan dari penyearah presisi didapatkan dari keluaran sensor tegangan,

sehingga didapatkan bentuk setengah gelombang (Vpeak) dari masukan yang

diberikan dan akan dibaca bentuk gelombang secara keseluruhan, bukan peaknya

saja untuk mendapatkan data pengamatan. Gelombang yang dihasilkan oleh

rangkaian penyearah presisi antara ujung puncaknya tidak sama hal ini disebabkan

oleh sinyal masukan yang tidak murni yang dihasilkan oleh keluaran sensor

tegangan sehingga pada keluaran penyearah presisi nampak pada ujungnya seperti

terpotong atau cacat. Bentuk gambar gelombang dari keluaran penyearah presisi

dapat dilihat pada gambar 4-2.

(a) (b)

Gambar 4-2 (a) gambar Masukan dan (b) gambar keluaran penyearah presisi

Dari beberapa pengujian didapatkan data seperti data tabel 4-3, dimana keluaran

dari rangkaian penyearah presisi adalah setengah dari masukannya.

46

Tabel 4-3 Data pengamatan input output rangkaian penyearah presisi

No Vin (Vp-p)

Vout (Vp)

1 5,20 2,60 2 7,60 3,80 3 7,40 3,60 4 7,60 3,80 5 7,80 3,90 6 7,94 4,00 7 8,40 4,20 8 8,56 4,30 9 8,70 4,40

Dari tabel 4-3, data yang diambil untuk setengah gelombang (Vpeak) adalah pada

saat puncak gelombang tertinggi, terlihat pada gambar 4-2, yang seterusnya akan

dilanjutkan ke ADC untuk diproses dengan mikrokontroler.

4.1.3 Hubungan Sinyal Terkondisi dengan ADC0804

ADC (Analog to Digital Converter) dalam penelitian ini adalah mengubah

keluaran dari penyearah presisi berupa sinyal analog menjadi bit-bit digital.

Berdasarkan datasheet, ketelitian ADC0804 dibatasi 1 LSB, sehingga kekurang

ketelitian ADC0804 dapat menyebabkan kesalahan sebesar 19,53 mV. Kesalahan

juga didapat dari proses pembulatan yang terjadi karena pemrosesan data secara

digital sehingga didapat resolusi sebesar 20mV. Sebagai pengujian ADC0804,

diperoleh dari masukan catu daya sebesar 1,017v (berdasarkan multimeter merek

SANWA CD800a) dimasukan ke input ADC. Sebagai pengujian keluaran ADC,

menggunakan LED setiap keluaran dianggap sebagai bit-bit keluaran ADC0804.

Diperoleh keluaran ADC 00110011b sama dengan (51d), seterusnya hasil dari

47

ADC dikalikan dengan kesalahan pengukuran maksimum (51 x 20mV = 1,02V)

dan didapatkan pengujian sudah sesuai dengan perancangan.

Gambar 4-3 input ADC0804 (multimeter) dan keluaran ADC0804 (LED)

Dari data keluaran ADC0804 selanjutnya akan dikirim ke mikrokontroler

untuk diolah dan diteruskan ke penampil LCD.

4.2 Sensor Arus

Tahap pengukuran arus dilakukan dengan gambar 3-2 (b) mengukur arus

yang melewati beban peralatan listrik seperti ditunjukkan gambar 3-2 (b). Pada

tahap ini juga akan diukur nilai tegangan (Vx) pada keluaran sensor arus Rx 1Ω.

Dari gambar 3-2 (b), pengukuran dilakukan dengan mengubah nilai hambatan dari

rangkaian uji beban peralatan listrik dengan kenaikan tertentu sehingga nilai arus I

yang melewati beban Rx juga akan berubah-ubah. Selanjutnya nilai arus pada Rx

akan diambil nilai teganganya, dan akan dimasukan pada pengkondisi sinyal. Alat

ukur referensi akan mengukur nilai arus, kemudian hasilnya akan dibandingkan

dengan keluaran alat pada tampilan LCD.

Pada sub bab ini akan dibahas tentang analisis pengamatan data yang

dihasilkan oleh sensor arus dan rangkaian uji beban peralatan listrik untuk

48

pengamatan data yang dihasilkan pada masing-masing skala yang digunakan.

Gambar 4-4 adalah rangkaian uji untuk sensor arus dimana yang di dalam kotak

merah adalah rangkaian uji peralatan listrik yang bersumber dari sebuah trafo 5

Ampere tegangan 50 volt AC dengan jumlah hambatan (R) yang Variabel

dipasang secara paralel dengan jumlah R dan besarnya hambatan disesuaikan

dengan skala pengukuran arus, dan kotak biru sendiri adalah rangkaian sensor

arusnya.

Gambar 4-4 kotak merah sebagai rangkaian uji beban peralatan listrik

Pada pengamatan ini akan dilihat bentuk gelombang keluaran sensor arus

dari masing-masing skala sehingga didapatkan bentuk gambar gelombang dari

masing-masing keluaran sensor arus dan keluaran sensor arus dengan gain dan

skala yang berbeda. Terlihat pada gambar 4-5, 4-6, 4-7 bahwa jika semakin kecil

skala yang digunakan maka semakin sinus bentuk gelombang yang dihasilkan hal

ini dipengaruhi oleh besarnya nilai kapasitor yang dipasang pada rangkaian dan

besarnya gain pada pemilih skala yang digunakan. Gambar yang ambil adalah

pada saat bentuk gelombang mencapai 5Vpp atau 2,5Vp dan 2 volt/div dari

pemilih skala yang berbeda.

4.2.1 Sensor Arus Pada Skala 5 Ampere

49

(a) (b)

Gambar 4-5 (a) keluaran sensor arus, (b) keluaran sensor arus dengan gain 1 kali,

skala 5 Amperepe.

Pengamatan gambar bentuk glombang untuk tiap skala menggunakan

mode masukan Dc coupling.Untuk mengetahui berapa besarnya nilai arus yang

dihasilkan oleh sensor arus skala 5 Ampere, 0,5 Ampere, 0,05 Ampere, dilakukan

Perhitungan nilai arus (Iout) berdasarkan persamaan (2-3) dengan terlebih dahulu

mengetahui nilai hambatan (R=1Ω/5w), sehingga diketahui besarnya nilai Iout

yang dapat dilihat pada tabel 4-4, 4-5, 4-6 untuk masing-masing skala

pengukuran.

Tabel 4-4 Data pengamatan sensor Arus untuk skala 5 Ampere dengan pemilih skala I untuk gain 1 kali.

No Vin

(Vp-p) vout

(Vp-p) Iout

(Ip-p) 1 1,9 1,9 1,9 2 3,1 3,1 3,1 3 4,2 4,2 4,2 4 5,2 5,2 5,2 5 6,0 6,0 6,0 6 6,8 6,8 6,8 7 7,4 7,4 7,4 8 8,0 8,0 8,0 9 8,2 8,2 8,2 10 8,4 8,4 8,4 11 9,2 9,2 9,2 12 9,3 9,3 9,3

50

13 9,6 9,6 9,6 14 9,8 9,8 9,8 15 10,0 10,0 10,0 16 10,2 10,2 10,2 17 10,0 10,0 10,0 18 10,0 10,0 10,0 19 10,2 10,2 10,2 20 10,4 10,4 10,4 21 10,6 10,6 10,6 22 10,8 10,8 10,8

Dari tabel 4-4, terlihat bahwa rangkaian keluaran dari sensor arus skala 5 Ampere

sudah mampu bekerja dengan baik sesuai dengan perancangan dengan penguatan

= 1 kali, maka didapatkan Vout adalah sama dengan Vin.

4.2.2 Sensor Arus Pada Skala 0,5 Ampere

(a) (b)

Gambar 4-6 (a) keluaran sensor arus, (b) keluaran sensor arus dengan gain 10

kali, skala 0,5 Ampere.

Tabel 4-5

Data pengamatan sensor Arus untuk skala 0,5 Ampere dengan pemilih

skala II untuk gain 10 kali.

No Vin

(Vp-p) Vout

(Vp-p) Iout

(Ip-p) 1 0,14 1,5 1,5 2 0,24 2,2 2,2 3 0,30 2,8 2,8 4 0,38 3,6 3,6 5 0,44 4,2 2,0 6 0,48 4,6 4,6 7 0,52 5,0 5,0 8 0,60 5,6 5,6

51

9 0,64 6,0 6,0 10 0,68 6.6 6.6 11 0,72 7,0 7,0 12 0,76 7,4 7,4 13 0,80 8,0 8,0 14 0,84 8,2 8,2 15 0,88 8,4 8,4 16 0,92 8,8 8,8 17 0,96 9,2 9,2 18 0,98 9,6 9,6 19 1,00 10,0 10,0 20 1,04 10,2 10,2 21 1,06 10,4 10,4

Dari tabel 4-5, terlihat bahwa keluaran yang dihasilkan oleh Vout adalah harus

sama dengan 10 kali Vin, dikarnakan penguatan yang digunakan adalah pemilih

skala II untuk gain 10 kali, dan pada tabel 4-5 data yang di dapatkan sudah

mendekati hasil dari perancangan karna selisih yang dihasilkan antara Vout

dengan Vin tidak terlampau jauh.

4.2.3 Sensor Arus Pada Skala 0,05 Ampere

(a) (b)

Gambar 4-7 (a) keluaran sensor arus, (b) keluaran sensor arus dengan gain 100

kali, skala 0,05 Ampere.

Tabel 4-6 Data pengamatan sensor Arus untuk skala 0,05 Ampere dengan pemilih skala III untuk gain 100 kali.

No Vin Vout Iout

52

(Vp-p) (Vp-p) (Ip-p) 1 0,004 0,4 0,4 2 0,038 4,0 4,0 3 0,066 6,8 6,8 4 0,089 8,8 8,8 5 0,094 10,0 10,0 6 0,110 12,0 12,0

Dari tabel 4-6, terlihat bahwa keluaran yang dihasilkan oleh Vout adalah harus

sama dengan 100 kali Vin, dikarnakan penguatan yang digunakan adalah pemilih

skala III untuk gain 100 kali, dan pada tabel 4-6 data yang di dapatkan sudah

mendekati hasil dari perancangan karna selisih yang dihasilkan antara Vout

dengan Vin tidak terlampau jauh.

4.3 Rangkaian Penguat Inverting dan Relay sebagai Saklar untuk Pemilih

Gain.

Pada sub bab ini akan membahas pemilih gain dan skala dimana transistor

sebagai pengaktif relay pemilih skala untuk menentukan besarnya gain yang

digunakan. Pemilih skala berfungsi untuk pemilihan gain, dalam hal ini adalah

skala 5 Ampere, 0,5 Ampere, 0,05 Ampere yang dipilih oleh mikrokontroler.

Rangkaian ini berupa relay, dalam pengujiannya untuk mengaktifkan pemilih

skala diberi masukan 0 volt atau logika rendah, dan bila diberi masukan 5 volt

atau logika tinggi maka relay tidak aktif. Sebagai contoh, bila menginginkan

keluaran skala 5 Ampere pada pemilih skala1 diberi masukan 0 volt atau logika

rendah maka relay1 untuk pemilih gain sebesar 1 kali akan aktif. Untuk pemilih

skala lainya, digunakan dengan cara yang sama.

Tabel 4-7

53

Data pengamatan input output Rangkaian Penguat Inverting dan relay

sebagai saklar untuk pemilih gain 1 kali.

No Vin (Vp-p)

Vout (Vp-p) A

1 1,9 1,9 1 2 3,1 3,1 1 3 4,2 4,2 1 4 5,2 5,2 1 5 6,0 6,0 1 6 6,8 6,8 1 7 7,4 7,4 1 8 8,0 8,0 1 9 8,2 8,2 1 10 8,4 8,4 1 11 9,2 9,2 1 12 9,3 9,3 1 13 9,6 9,6 1 14 9,8 9,8 1 15 10,0 10,0 1 16 10,2 10,2 1 17 10,0 10,0 1 18 10,0 10,0 1 19 10,2 10,2 1 20 10,4 10,4 1 21 10,6 10,6 1 22 10,8 10,8 1

Pada tabel 4-7 didapatkan bahwa keluaran sensor arus sama dengan keluaran

Rangkaian Penguat Inverting dan relay sebagai saklar untuk pemilih gain 1 kali,

dengan besarnya gain adalah 1 kali yang sesuai dengan skala pemilihan gain.

Tabel 4-8

54

Data pengamatan input output Rangkaian Penguat Inverting dan relay

sebagai saklar untuk pemilih gain 10 kali.

No Vin

(Vp-p) Vout

(Vp-p) A 1 0,14 1,5 10,714 2 0,24 2,2 9,166 3 0,30 2,8 9,333 4 0,38 3,6 9,473 5 0,44 4,2 9,545 6 0,48 4,6 9,583 7 0,52 5,0 9,615 8 0,60 5,6 9,333 9 0,64 6,0 9,375 10 0,68 6.6 9,705 11 0,72 7,0 9,722 12 0,76 7,4 9,736 13 0,80 8,0 10,000 14 0,84 8,2 9,761 15 0,88 8,4 9,545 16 0,92 8,8 9,565 17 0,96 9,2 9,583 18 0,98 9,6 9,795 19 1,00 10,0 10,000 20 1,04 10,2 9,807 21 1,06 10,4 9,811

mean - - 9,674

Dari tabel 4-8, bahwa keluaran sensor arus harus sama dengan 10 kali keluaran

Rangkaian Penguat Inverting dan relay sebagai saklar untuk pemilih gain 10 kali,

tetapi pada kenyataanya gain yang di dapatkan tidak selalu sesuai dengan gain

yang sesunguhnya, hal ini dipengaruhi oleh ketidaktelitian dalam pengambilan

data (terjadinya nois terlihat pada gambar 4-6 (a) keluaran sensor arus ) yang

menyebabkan pembacaan gambar pengambilan data yang tidak jelas. Dari

beberapa pengambilan data pada tabel 4-8 didapatkan rerata gain sebesar 9,674

dari gain yang di inginkan yaitu 10 kali.

Tabel 4-9

55

Data pengamatan input output Rangkaian Penguat Inverting dan relay

sebagai saklar untuk pemilih gain 100 kali.

No Vin

(Vp-p) Vin

(Vp-p) A 1 0,004 0,4 100,00 2 0,038 4,0 105,23 3 0,066 6,8 103,03 4 0,089 8,8 98,87 5 0,094 10,0 106,38 6 0,110 12,0 109,09

mean - - 103,766

Dari tabel 4-9, bahwa keluaran sensor arus harus sama dengan 100 kali keluaran

Rangkaian Penguat Inverting dan relay sebagai saklar untuk pemilih gain 100 kali,

tetapi pada kenyataanya gain yang di dapatkan tidak selalu sama dengan gain

yang sesunguhnya, hal ini dipengaruhi oleh ketidaktelitian dalam pengambilan

data (terjadinya nois terlihat pada gambar 4-7 (a) keluaran sensor arus ) yang

menyebabkan pembacaan gambar pengambilan data yang tidak jelas. Dari

beberapa pengambilan data pada tabel 4-9 didapatkan rerata gain sebesar 103,766

dari gain yang di inginkan yaitu 100 kali.

4.4 Rangkaian Penyearah Presisi

Pada sub bab ini akan membahas bentuk gelombang keluaran dari

penyearah presisi dari pemilih skala yang berbeda dan data yang diperoleh dari

pengamatan. Dari gambar bentuk gelombang yang dihasilkan terlihat bahwa

semakin kecil gain untuk pemilihan skala maka akan terjadi offset terlihat pada

gambar 4-9 dan gambar 4-10 pada keluaran penyearah presisi.

4.4.1 Rangkaian penyearah presisi dengan skala 5 Ampere

56

Pada gambar 4-8 bentuk gelombang keluaran penyearah presisi masih

terlihat baik saat bernilai 5,10Vp (amplitudo masukan 5,10Ampere) pada Irms

3,25Ampere.

Gambar 4-8 Bentuk gelombang masukan dan keluaran penyearah presisi pada skala 5 Ampere

Tabel 4-10 Data pengamatan pada input output Rangkaian penyearah presisi sekala 5 Ampere.

No

I rms Tang

Ampere (A)

Vin (Vp-p)

Vout (Vp)

Amplitudo masukan

ADC (A)

1 0,17 1,9 0,95 0,95 2 0,38 3,1 1,55 1,55 3 0,73 4,2 2,10 2,10 4 1,03 5,2 2,60 2,60 5 1,29 6,0 3,00 3,00 6 1,53 6,8 3,40 3,40 7 1,75 7,4 3,70 3,70 8 1,94 8,0 4,00 4,00 9 2,07 8,2 4,10 4,10 10 2,24 8,4 4,40 4,40 11 2,39 9,2 4,60 4,60 12 2,54 9,3 4,65 4,65 13 2,66 9,6 4,80 4,80 14 2,78 9,8 4,90 4,90 15 2,90 10,0 5,00 5,00 16 3,00 10,2 5,00 5,00 17 3,08 10,0 5,00 5,00 18 3,15 10,0 5,00 5,00 19 3,25 10,2 5,10 5,10

57

20 3,33 10,4 5,20 5,20 21 3,40 10,6 5,30 5,30 22 3,47 10,8 5,400 5,40

4.4.2 Rangkaian penyearah presisi dengan skala 0,5 Ampere

Pada tabel 4-11 keluaran penyearah presisi masih terlihat baik saat bernilai

5,00Vp (amplitudo masukan 500mA) pada Irms 178mA, tapi untuk data selanjutnya

data akan error gambar 4-9 karena sensor hanya mampu berkerja pada jangkauan

5v peak untuk masukan ADC, besarnya error yang terjadi juga disebabkan oleh

Offset Gain pada pengkondisi sinyal sebesar 0,04Vp (0,2Vp x 0,2 Volt/Div)

Gambar 4-9 error pada skala 0,5A (Vp) setelah output dari rangkaian penyearah presisi melewati 5,00Vp.

Gambar 4-10 Offset Gain pada skala 0,5A (Vp)

58

Tabel 4-11 Data pengamatan pada input output Rangkaian penyearah presisi sekala 0,5 Ampere.

No

I rms tang

Ampere (mA)

Vin (Vp-p)

Vout (Vp)

Amplitudo masukan

ADC (mA)

1 8 1,50 0,75 75 2 18 2,20 1,10 110 3 28 2,80 1,40 140 4 38 3,60 1,80 180 5 48 2,00 2,10 210 6 58 4,60 2,30 230 7 67 5,00 2,50 250 8 77 5,60 2,80 280 9 87 6,00 3,00 300 10 96 6.60 3,30 330 11 105 7,00 3,50 350 12 114 7,00 3,70 370 13 123 8,00 4,00 400 14 132 8,20 4,10 410 15 142 8,40 4,20 420 16 151 8,80 4,40 440 17 160 9,20 4,60 460 18 168 9,60 4,80 480 19 178 10,00 5,00 500 20 199 10,20 5,10 510 21 209 10,40 5,20 520

4.4.3 Rangkaian penyearah presisi dengan skala 0,05 Ampere

Pada gambar 4-10 Bentuk gelombang keluaran penyearah presisi masih

terlihat baik saat bernilai 5,60Vp (amplitudo masukan 56mA) pada Irms 9,30mA.

Besarnya error yang terjadi juga disebabkan oleh Offset Gain pada pengkondisi

sinyal sebesar 0,2 Vp (0,2Vp x 1 Volt/Div).

59

Gambar 4-11 Offset Gain pada skala 0,05mA (Vp)

Tabel 4-12 Data pengamatan pada input output Rangkaian penyearah presisi sekala 0,05 Ampere

No

I rms tang

Ampere (mA)

Vin (Vp-p)

Vout (Vp)

Amplitudo masukan

ADC (mA)

1 0,02 0,4 0,20 2 2 2,40 4,0 2,00 20 3 4,70 6,8 3,40 34 4 7,00 8,8 4,40 44 5 9,30 10,0 5,60 56 6 11,63 12,0 6,00 60

Kesalahan pengukuran arus disebabkan oleh:

1. Ketelitian ADC0804 berdasarkan datasheet dibatasi ± 1 LSB, sehingga

kesalahan pengukuran maksimum 0,00196Volt.

2. Offset Gain yang terjadi pada pengkondisi sinyal yang berpengaruh

pada sampling data dan pembulatan yang terjadi akibat pemrosesan

data secara digital.

BAB V

KESIMPULAN DAN SARAN

5.1 Kesimpulan

Berdasarkan hasil analisa dan pengujian, penulis menyimpulkan hal-hal

berikut:

a. Alat dapat mengukur nilai Vrms dengan baik pada jangkauan 195~240 Vrms

karena tingkat rerata kesalahan kurang dari 2%.

b. Sensor arus dapat berkerja dengan baik pada saat skala pemilihan gain

yang besar saja (5 Ampere), sedangkan skala kecil (0,5A dan 0,05 A) akan

terjadi tegangan offset. Tegangan Offset tidak berpengaruh di pengukuran

besar tapi pengukuran yang kecil saja.

c. Alat mampu membaca keluaran dari penyearah presisi dengan amplitudo

masukan 5,10Ampere (5,10Vp) pada skala amplitudo masukan maksimum

5Ampere; amplitudo masukan 510mA (5,10Vp) pada skala amplitudo

masukan maksimum 500mA; amplitudo masukan 56mA (5,60Vp) pada

skala amplitudo masukan maksimum 50mA.

d. Untuk pengukuran Arus terbaik, disarankan agar alat ini digunakan pada

jangkauan masukan maksimal 5Vp(peak Arus).

60

61

5.2 Saran

Untuk pengembangan alat lebih lanjut, penulis menyarankan hal-hal

berikut:

a. Peningkatan ketelitian dan kepresisian alat dengan:

1. Untuk mengurangi tingkat kesalahan yang terjadi, maka pemilihan

nilai komponen, khususnya nilai hambatan pada sensor tegangan dan

arus perlu diperhatikan dengan baik.

b. Menggunakan ADC 10 bit atau ADC 12 bit, sehingga resolusi yang

dihasilkan oleh perangkat semakin baik dan digit tampilan dapat lebih

banyak.

c. Peningkatan perangkat lunak untuk perhitungan arus masukan, dan

menambahkan digit tampilan untuk arus masukan.

DAFTAR PUSTAKA

[1] Wasito S. Teknik Ukur Dan Peranti Ukur Elektronika. PT Elex Media

Komputindo Kelompok Gramedia,Jakarta,1988

[2] William D. Cooper. Instrumentasi Elektronika Dan Pengukuran Edisi ke-2.

Erlangga,Jakarta Pusat,1985

[3] Rashid, Muhamad H. Power Electronic( Circuits, Devices, and Applications)

Electrical And Computer Enginering, University Of Florida,2004

http://www.national.com. Diakses pada Otober 2007

http://www.semiconductor.com. Diakses pada Desember 2007

http://www.centrin.net. Diakses pada Maret 2008

62

LAMPIRAN

tm

4NX

XM

, H11A

XM

Gen

eral Pu

rpo

se 6-Pin

Ph

oto

transisto

r Op

toco

up

lers

March 2007

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com4NXXM, H11AXM Rev. 1.0.0

4N25M, 4N26M, 4N27M, 4N28M, 4N35M, 4N36M, 4N37M, H11A1M, H11A2M, H11A3M, H11A4M, H11A5MGeneral Purpose 6-Pin Phototransistor Optocouplers

Features

UL recognized (File # E90700, Volume 2)

VDE recognized (File # 102497)– Add option V (e.g., 4N25VM)

Applications

Power supply regulators

Digital logic inputs

Microprocessor inputs

Description

The general purpose optocouplers consist of a galliumarsenide infrared emitting diode driving a silicon pho-totransistor in a 6-pin dual in-line package.

Functional Block Diagram

6

1

6

6

1

1

PIN 1. ANODE 2. CATHODE 3. NO CONNECTION 4. EMITTER 5. COLLECTOR 6. BASE

2

1

3 NC

5

6

4

L02

4NX

XM

, H11A

XM

Gen

eral Pu

rpo

se 6-Pin

Ph

oto

transisto

r Op

toco

up

lers

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com4NXXM, H11AXM Rev. 1.0.0 2

Absolute Maximum Ratings

(T

A

= 25°C unless otherwise specified)

Electrical Characteristics

(T

A

= 25°C unless otherwise specified)

Individual Component Characteristics

Isolation Characteristics

*Typical values at T

A

= 25°C

Symbol Parameter Value Units

TOTAL DEVICE

T

STG

Storage Temperature -55 to +150 °C

T

OPR

Operating Temperature -55 to +100 °C

T

SOL

Wave solder temperature (see page 8 for reflow solder profile) 260 for 10 sec °C

P

D

Total Device Power Dissipation @ T

A

= 25°C

Derate above 25°C

250 mW

2.94

EMITTER

I

F

DC/Average Forward Input Current 60 mA

V

R

Reverse Input Voltage 6 V

I

F

(pk) Forward Current – Peak (300µs, 2% Duty Cycle) 3 A

P

D

LED Power Dissipation @ T

A

= 25°C

Derate above 25°C

120 mW

1.41 mW/°C

DETECTOR

V

CEO

Collector-Emitter Voltage 30 V

V

CBO

Collector-Base Voltage 70 V

V

ECO

Emitter-Collector Voltage 7 V

P

D

Detector Power Dissipation @ T

A

= 25°C

Derate above 25°C

150 mW

1.76 mW/°C

Symbol Parameter Test Conditions Min. Typ.* Max. Unit

EMITTER

V

F

Input Forward Voltage I

F

= 10mA 1.18 1.50 V

I

R

Reverse Leakage Current V

R

= 6.0V 0.001 10 µA

DETECTOR

BV

CEO

Collector-Emitter Breakdown Voltage I

C

= 1.0mA, I

F

= 0 30 100 V

BV

CBO

Collector-Base Breakdown Voltage I

C

= 100µA, I

F

= 0 70 120 V

BV

ECO

Emitter-Collector Breakdown Voltage I

E

= 100µA, I

F

= 0 7 10 V

I

CEO

Collector-Emitter Dark Current V

CE

= 10V, I

F

= 0 1 50 nA

I

CBO

Collector-Base Dark Current V

CB

= 10V 20 nA

C

CE

Capacitance V

CE

= 0V, f = 1 MHz 8 pF

Symbol Characteristic Test Conditions Min. Typ.* Max. Units

V

ISO

Input-Output Isolation Voltage f = 60Hz, t = 1 sec 7500 Vac(pk)

R

ISO

Isolation Resistance V

I-O

= 500 VDC 10

11

Ω

C

ISO

Isolation Capacitance V

I-O

= &, f = 1MHz 0.2 2 pF

L02

4NX

XM

, H11A

XM

Gen

eral Pu

rpo

se 6-Pin

Ph

oto

transisto

r Op

toco

up

lers

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com4NXXM, H11AXM Rev. 1.0.0 3

Electrical Characteristics

(Continued)

(T

A

= 25°C unless otherwise specified)

Transfer Characteristics

* Typical values at T

A

= 25°C

Symbol Parameter Test Conditions Device Min. Typ.* Max. Unit

DC CHARACTERISTICS

CTR Current Transfer Ratio,Collector to Emitter

I

F

= 10mA, V

CE

= 10V 4N35M, 4N36M, 4N37M

100 %

H11A1M 50

H11A5M 30

4N25M, 4N26MH11A2M, H11A3M

20

4N27M, 4N28MH11A4M

10

I

F

= 10mA, V

CE

= 10V, T

A

= -55°C4N35M, 4N36M,

4N37M40

I

F

= 10mA, V

CE

= 10V, T

A

= +100°C4N35M, 4N36M,

4N37M40

V

CE (SAT)

Collector-EmitterSaturation Voltage

I

C

= 2mA, I

F

= 50mA 4N25M, 4N26M,4N27M, 4N28M,

0.5 V

I

C

= 0.5mA, I

F

= 10mA 4N35M, 4N36M, 4N37M

0.3

H11A1M, H11A2M, H11A3M, H11A4M,

H11A5M

0.4

AC CHARACTERISTICS

T

ON

Non-SaturatedTurn-on Time

I

F

= 10mA, V

CC

= 10V, R

L

= 100

Ω

(Fig. 11)4N25M, 4N26M, 4N27M, 4N28M,

H11A1M, H11A2M,H11A3M, H11A4,

H11A5M

2 µs

I

C

= 2mA, V

CC

= 10V, R

L

= 100

Ω

(Fig. 11)4N35M, 4N36M,

4N37M2 10 µs

T

OFF

Turn-off Time I

F

= 10mA, V

CC

= 10V, R

L

= 100

Ω

(Fig. 11)4N25M, 4N26M,4N27M, 4N28M,

H11A1M, H11A2M,H11A3M, H11A4M,

H11A5M

2 µs

I

C

= 2mA, V

CC

= 10V, R

L

= 100

Ω

(Fig. 11)4N35M, 4N36M,

4N37M2 10

L02

4NX

XM

, H11A

XM

Gen

eral Pu

rpo

se 6-Pin

Ph

oto

transisto

r Op

toco

up

lers

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com4NXXM, H11AXM Rev. 1.0.0 4

Typical Performance Curves

Fig.2 Normalized CTR vs. Forward Current

IF - FORWARD CURRENT (mA)

0 2 4 6 8 10 12 14 16 18 20

NO

RM

ALI

ZE

D C

TR

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6 VCE = 5.0V TA = 25°C

Normalized toIF = 10 mA

Fig. 3 Normalized CTR vs. Ambient Temperature

TA - AMBIENT TEMPERATURE (°C)

-60 -40 -20 0 20 40 60 80 100

NO

RM

ALI

ZE

D C

TR

0.2

0.4

0.6

0.8

1.0

1.2

1.4

IF = 5 mA

IF = 10 mA

IF = 20 mA

Normalized toIF = 10 mA TA = 25°C

IF - LED FORWARD CURRENT (mA)

VF -

FO

RW

AR

D V

OLT

AG

E (

V)

Fig. 1 LED Forward Voltage vs. Forward Current

1 10 1001.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

TA = 25°C

TA = -55°C

TA = 100°C

Fig. 5 CTR vs. RBE (Saturated)

RBE- BASE RESISTANCE (k Ω)

NO

RM

ALI

ZE

D C

TR

( C

TR

RB

E /

CT

RR

BE

(OP

EN

))

10 100 10000.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

IF = 20 mA

IF = 10 mA

IF = 5 mA

VCE= 0.3 V

Fig. 4 CTR vs. RBE (Unsaturated)

RBE- BASE RESISTANCE (kΩ)

NO

RM

ALI

ZE

D C

TR

( C

TR

RB

E /

CT

RR

BE

(OP

EN

))

10 100 1000

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

VCE= 5.0 V

IF = 20 mA

IF = 10 mA

IF = 5 mA

0.01 0.1 1 100.001

0.01

0.1

1

10

100

IF = 5 mA

IF = 20 mA

IF = 10 mA

Fig. 6 Collector-Emitter Saturation Voltage vs. Collector Current

IC - COLLECTOR CURRENT (mA)

VC

E (

SAT

) - C

OLL

EC

TOR

-EM

ITT

ER

S

ATU

RAT

ION

VO

LTA

GE

(V

)

IF = 2.5 mA

TA = 25˚C

L02

4NX

XM

, H11A

XM

Gen

eral Pu

rpo

se 6-Pin

Ph

oto

transisto

r Op

toco

up

lers

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com4NXXM, H11AXM Rev. 1.0.0 5

NO

RM

ALI

ZE

D t o

n -

(ton

(RB

E) /

t on(

open

))

Fig. 8 Normalized ton vs. RBE

RBE- BASE RESISTANCE (k Ω)

10 100 1000 10000 1000000.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

VCC = 10 VIC = 2 mA

RL = 100 Ω

SW

ITC

HIN

G S

PE

ED

- (

µs)

Fig. 7 Switching Speed vs. Load Resistor

R-LOAD RESISTOR (kΩ)0.1 1 10 100

0.1

1

10

100

1000

Toff

IF = 10 mA VCC = 10 VTA = 25°C

Tr

Ton

Tf

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

VCC = 10 VIC = 2 mA

RL = 100 Ω

NO

RM

ALI

ZE

D t o

ff -

(tof

f(R

BE

) / t o

ff(op

en))

10 100 1000 10000 100000

RBE- BASE RESISTANCE (k Ω)

Fig. 9 Normalized toff vs. RBE Fig. 10 Dark Current vs. Ambient Temperature

TA - AMBIENT TEMPERATURE (°C)

0 20 40 60 80 100

I CE

O -

CO

LLE

CTO

R -E

MIT

TER

DA

RK

CU

RR

EN

T (n

A)

0.001

0.01

0.1

1

10

100

1000

10000

VCE = 10 VTA = 25°C

OUTPUT PULSE

INPUT PULSE

TEST CIRCUIT WAVE FORMS

tr tf

INPUT

IF RL

RBE

VCC = 10V

OUTPUT

ton

10%

90%

toff

Figure 11. Switching Time Test Circuit and Waveforms

IC

Adjust IF to produce IC = 2 mA

L02

4NX

XM

, H11A

XM

Gen

eral Pu

rpo

se 6-Pin

Ph

oto

transisto

r Op

toco

up

lers

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com4NXXM, H11AXM Rev. 1.0.0 6

Package Dimensions

Through Hole Surface Mount

0.4" Lead Spacing Recommended Pad Layout for Surface Mount Leadform

Note:

All dimensions are in inches (millimeters)

0.350 (8.89)0.320 (8.13)

0.260 (6.60)0.240 (6.10)

0.390 (9.90)0.332 (8.43)

0.070 (1.77)0.040 (1.02)

0.014 (0.36)0.010 (0.25)

0.320 (8.13)

0.035 (0.88)0.006 (0.16)

0.012 (0.30)0.008 (0.20)

0.200 (5.08)0.115 (2.93)

0.025 (0.63)0.020 (0.51)

0.020 (0.50)0.016 (0.41)

0.100 [2.54]

PIN 1 ID

SE

AT

ING

PLA

NE

0.350 (8.89)0.320 (8.13)

0.260 (6.60)0.240 (6.10)

0.320 (8.13)

0.070 (1.77)0.040 (1.02)

0.014 (0.36)0.010 (0.25)

0.200 (5.08)0.115 (2.93)

0.100 (2.54)0.015 (0.38)

0.020 (0.50)0.016 (0.41) 0.100 (2.54)

15°

0.012 (0.30)

Pin 1 ID

SE

AT

ING

PLA

NE

0.350 (8.89)

PIN 1 ID

0.320 (8.13)

0.260 (6.60)0.240 (6.10)

0.070 (1.77)

SE

AT

ING

PLA

NE

0.040 (1.02)0.014 (0.36)0.010 (0.25)

0.200 (5.08)0.115 (2.93)

0.020 (0.50)0.016 (0.41)

0.100 [2.54]

0.100 (2.54)0.015 (0.38)

0.012 (0.30)0.008 (0.21)

0.425 (10.80)0.400 (10.16)

0.070 (1.78)

0.060 (1.52)

0.030 (0.76)

0.100 (2.54)

0.305 (7.75)

0.425 (10.79)

L02

4NX

XM

, H11A

XM

Gen

eral Pu

rpo

se 6-Pin

Ph

oto

transisto

r Op

toco

up

lers

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com4NXXM, H11AXM Rev. 1.0.0 7

Ordering Information

Marking Information

OptionOrder Entry Identifier

(Example) Description

No option 4N25M Standard Through Hole Device

S 4N25SM Surface Mount Lead Bend

SR2 4N25SR2M Surface Mount; Tape and Reel

T 4N25TM 0.4" Lead Spacing

V 4N25VM VDE 0884

TV 4N25TVM VDE 0884, 0.4" Lead Spacing

SV 4N25SVM VDE 0884, Surface Mount

SR2V 4N25SR2VM VDE 0884, Surface Mount, Tape and Reel

*Note – Parts that do not have the ‘V’ option (see definition 3 above) that are marked with date code ‘325’ or earlier are marked in portrait format.

Definitions

1 Fairchild logo

2 Device number

3VDE mark (Note: Only appears on parts ordered with VDE option – See order entry table)

4 One digit year code, e.g., ‘7’

5 Two digit work week ranging from ‘01’ to ‘53’

6 Assembly package code

4N25

V X YY Q

1

2

6

43 5

L02

4NX

XM

, H11A

XM

Gen

eral Pu

rpo

se 6-Pin

Ph

oto

transisto

r Op

toco

up

lers

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com4NXXM, H11AXM Rev. 1.0.0 8

Carrier Tape Specification

Reflow Profile

4.0 ± 0.1

Ø1.5 MIN

User Direction of Feed

2.0 ± 0.05

1.75 ± 0.10

11.5 ± 1.0

24.0 ± 0.3

12.0 ± 0.1

0.30 ± 0.05

21.0 ± 0.1

4.5 ± 0.20

0.1 MAX 10.1 ± 0.20

9.1 ± 0.20

Ø1.5 ± 0.1/-0

300280260240220200180160140120100

80604020

0

°C

Time (s)

0 60 180120 270

260°C

>245°C = 42 Sec

Time above 183°C = 90 Sec

360

1.822°C/Sec Ramp up rate

33 Sec

L02

4NX

XM

, H11A

XM

Gen

eral Pu

rpo

se 6-Pin

Ph

oto

transisto

r Op

toco

up

lers

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com4NXXM, H11AXM Rev. 1.0.0 9

TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx®

Across the board. Around the world.ActiveArrayBottomlessBuild it NowCoolFETCROSSVOLTCTL™Current Transfer Logic™ DOMEE2CMOSEcoSPARK®

EnSignaFACT Quiet Series™ FACT®

FAST®

FASTrFPSFRFET®

GlobalOptoisolatorGTO

HiSeCi-LoImpliedDisconnectIntelliMAXISOPLANARMICROCOUPLERMicroPakMICROWIREMSXMSXProOCXOCXProOPTOLOGIC®

OPTOPLANAR®

PACMANPOPPower220®

Power247®

PowerEdgePowerSaverPowerTrench®

Programmable Active DroopQFET®

QSQT OptoelectronicsQuiet SeriesRapidConfigureRapidConnectScalarPumpSMART STARTSPM®

STEALTH™SuperFETSuperSOT -3SuperSOT -6SuperSOT -8SyncFET™ TCMThe Power Franchise®

™

TinyBoostTinyBuck

TinyLogic®

TINYOPTOTinyPowerTinyWireTruTranslation

SerDesUHC®

UniFETVCXWire

DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein: 1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only.

Rev. I24

L02

ADC0801/ADC0802/ADC0803/ADC0804/ADC08058-Bit µP Compatible A/D ConvertersGeneral DescriptionThe ADC0801, ADC0802, ADC0803, ADC0804 andADC0805 are CMOS 8-bit successive approximation A/Dconverters that use a differential potentiometricladder — similar to the 256R products. These converters aredesigned to allow operation with the NSC800 and INS8080Aderivative control bus with TRI-STATE output latches directlydriving the data bus. These A/Ds appear like memory loca-tions or I/O ports to the microprocessor and no interfacinglogic is needed.

Differential analog voltage inputs allow increasing thecommon-mode rejection and offsetting the analog zero inputvoltage value. In addition, the voltage reference input can beadjusted to allow encoding any smaller analog voltage spanto the full 8 bits of resolution.

Featuresn Compatible with 8080 µP derivatives — no interfacing

logic needed - access time - 135 nsn Easy interface to all microprocessors, or operates “stand

alone”

n Differential analog voltage inputsn Logic inputs and outputs meet both MOS and TTL

voltage level specificationsn Works with 2.5V (LM336) voltage referencen On-chip clock generatorn 0V to 5V analog input voltage range with single 5V

supplyn No zero adjust requiredn 0.3" standard width 20-pin DIP packagen 20-pin molded chip carrier or small outline packagen Operates ratiometrically or with 5 VDC, 2.5 VDC, or

analog span adjusted voltage reference

Key Specificationsn Resolution 8 bitsn Total error ±1⁄4 LSB, ±1⁄2 LSB and ±1 LSBn Conversion time 100 µs

Connection Diagram

Ordering Information

TEMP RANGE 0˚C TO 70˚C 0˚C TO 70˚C −40˚C TO +85˚C

±1⁄4 Bit Adjusted ADC0801LCN

ERROR ±1⁄2 Bit Unadjusted ADC0802LCWM ADC0802LCN

±1⁄2 Bit Adjusted ADC0803LCN

±1Bit Unadjusted ADC0804LCWM ADC0804LCN ADC0805LCN/ADC0804LCJ

PACKAGE OUTLINE M20B — SmallOutline

N20A — Molded DIP

Z-80® is a registered trademark of Zilog Corp.

ADC080XDual-In-Line and Small Outline (SO) Packages

DS005671-30

See Ordering Information

November 1999A

DC

0801/AD

C0802/A

DC

0803/AD

C0804/A

DC

08058-B

itµPC

ompatible

A/D

Converters

© 2001 National Semiconductor Corporation DS005671 www.national.com

L01

Typical Applications

Error Specification (Includes Full-Scale,

Zero Error, and Non-Linearity)

Part Full- V REF/2=2.500 VDC VREF/2=No Connection

Number Scale (No Adjustments) (No Adjustments)

Adjusted

ADC0801 ±1⁄4 LSB

ADC0802 ±1⁄2 LSB

ADC0803 ±1⁄2 LSB

ADC0804 ±1 LSB

ADC0805 ±1 LSB

DS005671-1

8080 Interface

DS005671-31

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 2

L01

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (VCC) (Note 3) 6.5VVoltage

Logic Control Inputs −0.3V to +18VAt Other Input and Outputs −0.3V to (VCC+0.3V)

Lead Temp. (Soldering, 10 seconds)Dual-In-Line Package (plastic) 260˚CDual-In-Line Package (ceramic) 300˚CSurface Mount Package

Vapor Phase (60 seconds) 215˚C

Infrared (15 seconds) 220˚CStorage Temperature Range −65˚C to +150˚CPackage Dissipation at TA=25˚C 875 mWESD Susceptibility (Note 10) 800V

Operating Ratings (Notes 1, 2)

Temperature Range TMIN≤TA≤TMAX

ADC0804LCJ −40˚C≤TA≤+85˚CADC0801/02/03/05LCN −40˚C≤TA≤+85˚CADC0804LCN 0˚C≤TA≤+70˚CADC0802/04LCWM 0˚C≤TA≤+70˚C

Range of VCC 4.5 VDC to 6.3 VDC

Electrical CharacteristicsThe following specifications apply for VCC=5 VDC, TMIN≤TA≤TMAX and fCLK=640 kHz unless otherwise specified.

Parameter Conditions Min Typ Max Units

ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj. ±1⁄4 LSB

(See Section 2.5.2)

ADC0802: Total Unadjusted Error (Note 8) VREF/2=2.500 VDC ±1⁄2 LSB

ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj. ±1⁄2 LSB

(See Section 2.5.2)

ADC0804: Total Unadjusted Error (Note 8) VREF/2=2.500 VDC ±1 LSB

ADC0805: Total Unadjusted Error (Note 8) VREF/2-No Connection ±1 LSB

VREF/2 Input Resistance (Pin 9) ADC0801/02/03/05 2.5 8.0 kΩADC0804 (Note 9) 0.75 1.1 kΩ

Analog Input Voltage Range (Note 4) V(+) or V(−) Gnd–0.05 VCC+0.05 VDC

DC Common-Mode Error Over Analog Input Voltage ±1/16 ±1⁄8 LSB

Range

Power Supply Sensitivity VCC=5 VDC ±10% Over ±1/16 ±1⁄8 LSB

Allowed VIN(+) and VIN(−)

Voltage Range (Note 4)

AC Electrical CharacteristicsThe following specifications apply for VCC=5 VDC and TMIN≤TA≤TMAX unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

TC Conversion Time fCLK=640 kHz (Note 6) 103 114 µs

TC Conversion Time (Notes 5, 6) 66 73 1/fCLK

fCLK Clock Frequency VCC=5V, (Note 5) 100 640 1460 kHz

Clock Duty Cycle 40 60 %

CR Conversion Rate in Free-Running INTR tied to WR with 8770 9708 conv/s

Mode CS =0 VDC, fCLK=640 kHz

tW(WR)L Width of WR Input (Start Pulse Width) CS =0 VDC (Note 7) 100 ns

tACC Access Time (Delay from Falling CL=100 pF 135 200 ns

Edge of RD to Output Data Valid)

t1H, t0H TRI-STATE Control (Delay CL=10 pF, RL=10k 125 200 ns

from Rising Edge of RD to (See TRI-STATE Test

Hi-Z State) Circuits)

tWI, tRI Delay from Falling Edge 300 450 ns

of WR or RD to Reset of INTR

CIN Input Capacitance of Logic 5 7.5 pF

Control Inputs

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com3

L01

AC Electrical Characteristics (Continued)

The following specifications apply for VCC=5 VDC and TMIN≤TA≤TMAX unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

COUT TRI-STATE Output 5 7.5 pF

Capacitance (Data Buffers)

CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]

VIN (1) Logical “1” Input Voltage VCC=5.25 VDC 2.0 15 VDC

(Except Pin 4 CLK IN)

VIN (0) Logical “0” Input Voltage VCC=4.75 VDC 0.8 VDC

(Except Pin 4 CLK IN)

IIN (1) Logical “1” Input Current VIN=5 VDC 0.005 1 µADC

(All Inputs)

IIN (0) Logical “0” Input Current VIN=0 VDC −1 −0.005 µADC

(All Inputs)

CLOCK IN AND CLOCK R

VT+ CLK IN (Pin 4) Positive Going 2.7 3.1 3.5 VDC

Threshold Voltage

VT− CLK IN (Pin 4) Negative 1.5 1.8 2.1 VDC

Going Threshold Voltage

VH CLK IN (Pin 4) Hysteresis 0.6 1.3 2.0 VDC

(VT+)−(VT−)

VOUT (0) Logical “0” CLK R Output IO=360 µA 0.4 VDC

Voltage VCC=4.75 VDC

VOUT (1) Logical “1” CLK R Output IO=−360 µA 2.4 VDC

Voltage VCC=4.75 VDC

DATA OUTPUTS AND INTR

VOUT (0) Logical “0” Output Voltage

Data Outputs IOUT=1.6 mA, VCC=4.75 VDC 0.4 VDC

INTR Output IOUT=1.0 mA, VCC=4.75 VDC 0.4 VDC

VOUT (1) Logical “1” Output Voltage IO=−360 µA, VCC=4.75 VDC 2.4 VDC

VOUT (1) Logical “1” Output Voltage IO=−10 µA, VCC=4.75 VDC 4.5 VDC

IOUT TRI-STATE Disabled Output VOUT=0 VDC −3 µADC

Leakage (All Data Buffers) VOUT=5 VDC 3 µADC

ISOURCE VOUT Short to Gnd, TA=25˚C 4.5 6 mADC

ISINK VOUT Short to VCC, TA=25˚C 9.0 16 mADC

POWER SUPPLY

ICC Supply Current (Includes fCLK=640 kHz,

Ladder Current) VREF/2=NC, TA=25˚C

and CS =5V

ADC0801/02/03/04LCJ/05 1.1 1.8 mA

ADC0804LCN/LCWM 1.9 2.5 mA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operatingthe device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.

Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC.

Note 4: For VIN(−)≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conductfor analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as highlevel analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The specallows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code willbe correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations,initial tolerance and loading.

Note 5: Accuracy is guaranteed at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can beextended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.

Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. Thestart request is internally latched, see Figure 4 and section 2.0.

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 4

L01

AC Electrical Characteristics (Continued)

Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will holdthe converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams).

Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 7.

Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, andADC0805, and in the ADC0804LCJ, each resistor is typically 16 kΩ. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kΩ.

Note 10: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

Typical Performance Characteristics

Logic Input Threshold Voltagevs. Supply Voltage

DS005671-38

Delay From Falling Edge ofRD to Output Data Validvs. Load Capacitance

DS005671-39

CLK IN Schmitt Trip Levelsvs. Supply Voltage

DS005671-40

fCLK vs. Clock Capacitor

DS005671-41

Full-Scale Error vsConversion Time

DS005671-42

Effect of Unadjusted Offset Errorvs. VREF/2 Voltage

DS005671-43

Output Current vsTemperature

DS005671-44

Power Supply Currentvs Temperature (Note 9)

DS005671-45

Linearity Error at LowVREF/2 Voltages

DS005671-46

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com5

L01

TRI-STATE Test Circuits and Waveforms

Timing Diagrams (All timing is measured from the 50% voltage points)

t1H

DS005671-47

t1H, CL=10 pF

DS005671-48

tr=20 ns

t0H

DS005671-49

t0H, CL=10 pF

DS005671-50

tr=20 ns

DS005671-51

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 6

L01

Timing Diagrams (All timing is measured from the 50% voltage points) (Continued)

Typical Applications

Output Enable and Reset with INTR

DS005671-52

Note: Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR .

6800 Interface

DS005671-53

Ratiometeric with Full-Scale Adjust

DS005671-54

Note: before using caps at VIN or VREF/2,see section 2.3.2 Input Bypass Capacitors.

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com7

L01

Typical Applications (Continued)

Absolute with a 2.500V Reference

DS005671-55

*For low power, see also LM385–2.5

Absolute with a 5V Reference

DS005671-56

Zero-Shift and Span Adjust: 2V ≤ VIN ≤ 5V

DS005671-57

Span Adjust: 0V ≤ VIN ≤ 3V

DS005671-58

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 8

L01

Typical Applications (Continued)

Directly Converting a Low-Level Signal

DS005671-59

VREF/2=256 mV

A µP Interfaced Comparator

DS005671-60

For:VIN(+)>VIN(−)Output=FFHEXFor:VIN(+)<VIN(−)Output=00HEX

1 mV Resolution with µP Controlled Range

DS005671-61

VREF/2=128 mV1 LSB=1 mVVDAC≤VIN≤(VDAC+256 mV)0 ≤ VDAC < 2.5V

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com9

L01

Typical Applications (Continued)

Digitizing a Current Flow

DS005671-62

Self-Clocking Multiple A/Ds

DS005671-63

* Use a large R valueto reduce loadingat CLK R output.

External Clocking

DS005671-64

100 kHz≤fCLK≤1460 kHz

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 10

L01

Typical Applications (Continued)

Self-Clocking in Free-Running Mode

DS005671-65

*After power-up, a momentary grounding of the WR input is needed toguarantee operation.

µP Interface for Free-Running A/D

DS005671-66

Operating with “Automotive” Ratiometric Transducers

DS005671-67

*VIN(−)=0.15 VCC15% of VCC≤VXDR≤85% of VCC

Ratiometric with V REF/2 Forced

DS005671-68

µP Compatible Differential-Input Comparator with Pre-Set V OS (with or without Hysteresis)

DS005671-69

*See Figure 5 to select R valueDB7=“1” for VIN(+)>VIN(−)+(VREF/2)Omit circuitry within the dotted area ifhysteresis is not needed

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com11

L01

Typical Applications (Continued)

Handling ±10V Analog Inputs

DS005671-70

*Beckman Instruments #694-3-R10K resistor array

Low-Cost, µP Interfaced, Temperature-to-DigitalConverter

DS005671-71

µP Interfaced Temperature-to-Digital Converter

DS005671-72

*Circuit values shown are for 0˚C≤TA≤+128˚C***Can calibrate each sensor to allow easy replacement, then A/D can be calibrated with a pre-set input voltage.

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 12

L01

Typical Applications (Continued)

Handling ±5V Analog Inputs

DS005671-33

*Beckman Instruments #694-3-R10K resistor array

Read-Only Interface

DS005671-34

µP Interfaced Comparator with Hysteresis

DS005671-35

Protecting the Input

DS005671-9

Diodes are 1N914

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com13

L01

Typical Applications (Continued)

Analog Self-Test for a System

DS005671-36

A Low-Cost, 3-Decade Logarithmic Converter

DS005671-37

*LM389 transistorsA, B, C, D = LM324A quad op amp

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 14

L01

Typical Applications (Continued)

3-Decade Logarithmic A/D Converter

DS005671-73

Noise Filtering the Analog Input

DS005671-74

fC=20 HzUses Chebyshev implementation for steeper roll-off unity-gain, 2nd order,low-pass filterAdding a separate filter for each channel increases system response timeif an analog multiplexer is used

Multiplexing Differential Inputs

DS005671-75

Output Buffers with A/D Data Enabled

DS005671-76

*A/D output data is updated 1 CLK period prior to assertion of INTR

Increasing Bus Drive and/or Reducing Time on Bus

DS005671-77

*Allows output data to set-up at falling edge of CS

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com15

L01

Typical Applications (Continued)

Functional Description

1.0 UNDERSTANDING A/D ERROR SPECS

A perfect A/D transfer characteristic (staircase waveform) isshown in Figure 1. The horizontal scale is analog inputvoltage and the particular points labeled are in steps of 1LSB (19.53 mV with 2.5V tied to the VREF/2 pin). The digitaloutput codes that correspond to these inputs are shown as

D−1, D, and D+1. For the perfect A/D, not only willcenter-value (A−1, A, A+1, . . . . ) analog inputs producethe correct output digital codes, but also each riser (thetransitions between adjacent output codes) will be located±1⁄2 LSB away from each center-value. As shown, the risersare ideal and have no width. Correct digital output codes willbe provided for a range of analog input voltages that extend

Sampling an AC Input Signal

DS005671-78

Note 11: Oversample whenever possible [keep fs > 2f(−60)] to eliminate input frequency folding (aliasing) and to allow for the skirt response of the filter.

Note 12: Consider the amplitude errors which are introduced within the passband of the filter.

70% Power Savings by Clock Gating

DS005671-79

(Complete shutdown takes ≈ 30 seconds.)

Power Savings by A/D and V REF Shutdown

DS005671-80

*Use ADC0801, 02, 03 or 05 for lowest power consumption.Note: Logic inputs can be driven to VCC with A/D supply at zero volts.Buffer prevents data bus from overdriving output of A/D when in shutdown mode.

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 16

L01

Functional Description (Continued)

±1⁄2 LSB from the ideal center-values. Each tread (the rangeof analog input voltage that provides the same digital outputcode) is therefore 1 LSB wide.

Figure 2 shows a worst case error plot for the ADC0801. Allcenter-valued inputs are guaranteed to produce the correctoutput codes and the adjacent risers are guaranteed to beno closer to the center-value points than ±1⁄4 LSB. In otherwords, if we apply an analog input equal to the center-value±1⁄4 LSB, we guarantee that the A/D will produce the correctdigital code. The maximum range of the position of the codetransition is indicated by the horizontal arrow and it is guar-anteed to be no more than 1⁄2 LSB.

The error curve of Figure 3 shows a worst case error plot forthe ADC0802. Here we guarantee that if we apply an analoginput equal to the LSB analog voltage center-value the A/Dwill produce the correct digital code.

Next to each transfer function is shown the correspondingerror plot. Many people may be more familiar with error plotsthan transfer functions. The analog input voltage to the A/Dis provided by either a linear ramp or by the discrete outputsteps of a high resolution DAC. Notice that the error iscontinuously displayed and includes the quantization uncer-tainty of the A/D. For example the error at point 1 of Figure 1is +1⁄2 LSB because the digital code appeared 1⁄2 LSB inadvance of the center-value of the tread. The error plotsalways have a constant negative slope and the abrupt up-side steps are always 1 LSB in magnitude.

Transfer Function

DS005671-81

Error Plot

DS005671-82

FIGURE 1. Clarifying the Error Specs of an A/D ConverterAccuracy= ±0 LSB: A Perfect A/D

Transfer Function

DS005671-83

Error Plot

DS005671-84

FIGURE 2. Clarifying the Error Specs of an A/D ConverterAccuracy= ±1⁄4 LSB

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com17

L01

Functional Description (Continued)

2.0 FUNCTIONAL DESCRIPTION

The ADC0801 series contains a circuit equivalent of the256R network. Analog switches are sequenced by succes-sive approximation logic to match the analog difference inputvoltage [VIN(+) − VIN(−)] to a corresponding tap on the Rnetwork. The most significant bit is tested first and after 8comparisons (64 clock cycles) a digital 8-bit binary code(1111 1111 = full-scale) is transferred to an output latch andthen an interrupt is asserted (INTR makes a high-to-lowtransition). A conversion in process can be interrupted byissuing a second start command. The device may be oper-ated in the free-running mode by connecting INTR to the WRinput with CS =0. To ensure start-up under all possibleconditions, an external WR pulse is required during the firstpower-up cycle.

On the high-to-low transition of the WR input the internalSAR latches and the shift register stages are reset. As longas the CS input and WR input remain low, the A/D will remainin a reset state. Conversion will start from 1 to 8 clockperiods after at least one of these inputs makes a low-to-hightransition.

A functional diagram of the A/D converter is shown in Figure4. All of the package pinouts are shown and the major logiccontrol paths are drawn in heavier weight lines.

The converter is started by having CS and WR simulta-neously low. This sets the start flip-flop (F/F) and the result-ing “1” level resets the 8-bit shift register, resets the Interrupt(INTR) F/F and inputs a “1” to the D flop, F/F1, which is at theinput end of the 8-bit shift register. Internal clock signals thentransfer this “1” to the Q output of F/F1. The AND gate, G1,combines this “1” output with a clock signal to provide a resetsignal to the start F/F. If the set signal is no longer present(either WR or CS is a “1”) the start F/F is reset and the 8-bitshift register then can have the “1” clocked in, which startsthe conversion process. If the set signal were to still bepresent, this reset pulse would have no effect (both outputsof the start F/F would momentarily be at a “1” level) and the8-bit shift register would continue to be held in the resetmode. This logic therefore allows for wide CS and WRsignals and the converter will start after at least one of thesesignals returns high and the internal clocks again provide areset signal for the start F/F.

Transfer Function

DS005671-85

Error Plot

DS005671-86

FIGURE 3. Clarifying the Error Specs of an A/D ConverterAccuracy= ±1⁄2 LSB

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 18

L01

Functional Description (Continued)

After the “1” is clocked through the 8-bit shift register (whichcompletes the SAR search) it appears as the input to theD-type latch, LATCH 1. As soon as this “1” is output from theshift register, the AND gate, G2, causes the new digital wordto transfer to the TRI-STATE output latches. When LATCH 1is subsequently enabled, the Q output makes a high-to-lowtransition which causes the INTR F/F to set. An invertingbuffer then supplies the INTR input signal.

Note that this SET control of the INTR F/F remains low for 8of the external clock periods (as the internal clocks run at 1⁄8of the frequency of the external clock). If the data output iscontinuously enabled (CS and RD both held low), the INTRoutput will still signal the end of conversion (by a high-to-lowtransition), because the SET input can control the Q outputof the INTR F/F even though the RESET input is constantlyat a “1” level in this operating mode. This INTR output willtherefore stay low for the duration of the SET signal, which is8 periods of the external clock frequency (assuming the A/Dis not started during this interval).

When operating in the free-running or continuous conversionmode (INTR pin tied to WR and CS wired low — see alsosection 2.8), the START F/F is SET by the high-to-low tran-sition of the INTR signal. This resets the SHIFT REGISTER

which causes the input to the D-type latch, LATCH 1, to golow. As the latch enable input is still present, the Q output willgo high, which then allows the INTR F/F to be RESET. Thisreduces the width of the resulting INTR output pulse to onlya few propagation delays (approximately 300 ns).

When data is to be read, the combination of both CS and RDbeing low will cause the INTR F/F to be reset and theTRI-STATE output latches will be enabled to provide the 8-bitdigital outputs.

2.1 Digital Control Inputs

The digital control inputs (CS, RD, and WR) meet standardT2L logic voltage levels. These signals have been renamedwhen compared to the standard A/D Start and Output Enablelabels. In addition, these inputs are active low to allow aneasy interface to microprocessor control busses. Fornon-microprocessor based applications, the CS input (pin 1)can be grounded and the standard A/D Start function isobtained by an active low pulse applied at the WR input (pin3) and the Output Enable function is caused by an active lowpulse at the RD input (pin 2).

DS005671-13

Note 13: CS shown twice for clarity.

Note 14: SAR = Successive Approximation Register.

FIGURE 4. Block Diagram

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com19

L01

Functional Description (Continued)

2.2 Analog Differential Voltage Inputs andCommon-Mode Rejection

This A/D has additional applications flexibility due to theanalog differential voltage input. The VIN(−) input (pin 7) canbe used to automatically subtract a fixed voltage value fromthe input reading (tare correction). This is also useful in 4mA–20 mA current loop conversion. In addition,common-mode noise can be reduced by use of the differen-tial input.

The time interval between sampling VIN(+) and VIN(−) is 4-1⁄2clock periods. The maximum error voltage due to this slighttime difference between the input voltage samples is givenby:

where:

∆Ve is the error voltage due to sampling delay

VP is the peak value of the common-mode voltage

fcm is the common-mode frequency

As an example, to keep this error to 1⁄4 LSB (∼5 mV) whenoperating with a 60 Hz common-mode frequency, fcm, andusing a 640 kHz A/D clock, fCLK, would allow a peak value ofthe common-mode voltage, VP, which is given by:

or

which gives

VP.1.9V.

The allowed range of analog input voltages usually placesmore severe restrictions on input common-mode noise lev-els.

An analog input voltage with a reduced span and a relativelylarge zero offset can be handled easily by making use of thedifferential input (see section 2.4 Reference Voltage).

2.3 Analog Inputs

2.3 1 Input Current

Normal Mode

Due to the internal switching action, displacement currentswill flow at the analog inputs. This is due to on-chip straycapacitance to ground as shown in Figure 5.

The voltage on this capacitance is switched and will result incurrents entering the VIN(+) input pin and leaving the VIN(−)input which will depend on the analog differential input volt-age levels. These current transients occur at the leadingedge of the internal clocks. They rapidly decay and do notcause errors as the on-chip comparator is strobed at the endof the clock period.

Fault Mode

If the voltage source applied to the VIN(+) or VIN(−) pinexceeds the allowed operating range of VCC+50 mV, largeinput currents can flow through a parasitic diode to the VCC

pin. If these currents can exceed the 1 mA max allowedspec, an external diode (1N914) should be added to bypassthis current to the VCC pin (with the current bypassed withthis diode, the voltage at the VIN(+) pin can exceed the VCC

voltage by the forward voltage of this diode).

2.3.2 Input Bypass Capacitors

Bypass capacitors at the inputs will average these chargesand cause a DC current to flow through the output resis-tances of the analog signal sources. This charge pumpingaction is worse for continuous conversions with the VIN(+)input voltage at full-scale. For continuous conversions with a640 kHz clock frequency with the VIN(+) input at 5V, this DCcurrent is at a maximum of approximately 5 µA. Therefore,bypass capacitors should not be used at the analog inputs orthe VREF/2 pin for high resistance sources (> 1 kΩ). If inputbypass capacitors are necessary for noise filtering and highsource resistance is desirable to minimize capacitor size, thedetrimental effects of the voltage drop across this inputresistance, which is due to the average value of the inputcurrent, can be eliminated with a full-scale adjustment whilethe given source resistor and input bypass capacitor areboth in place. This is possible because the average value ofthe input current is a precise linear function of the differentialinput voltage.

2.3.3 Input Source Resistance

Large values of source resistance where an input bypasscapacitor is not used, will not cause errors as the inputcurrents settle out prior to the comparison time. If a low passfilter is required in the system, use a low valued seriesresistor (≤ 1 kΩ) for a passive RC section or add an op ampRC active low pass filter. For low source resistance applica-tions, (≤ 1 kΩ), a 0.1 µF bypass capacitor at the inputs willprevent noise pickup due to series lead inductance of a long

DS005671-14

rON of SW 1 and SW 2 . 5 kΩr=rON CSTRAY . 5 kΩ x 12 pF = 60 ns

FIGURE 5. Analog Input Impedance

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 20

L01

Functional Description (Continued)

wire. A 100Ω series resistor can be used to isolate thiscapacitor — both the R and C are placed outside the feed-back loop — from the output of an op amp, if used.

2.3.4 Noise

The leads to the analog inputs (pins 6 and 7) should be keptas short as possible to minimize input noise coupling. Bothnoise and undesired digital clock coupling to these inputscan cause system errors. The source resistance for theseinputs should, in general, be kept below 5 kΩ. Larger valuesof source resistance can cause undesired system noisepickup. Input bypass capacitors, placed from the analoginputs to ground, will eliminate system noise pickup but cancreate analog scale errors as these capacitors will averagethe transient input switching currents of the A/D (see section2.3.1.). This scale error depends on both a large sourceresistance and the use of an input bypass capacitor. Thiserror can be eliminated by doing a full-scale adjustment ofthe A/D (adjust VREF/2 for a proper full-scale reading — seesection 2.5.2 on Full-Scale Adjustment) with the source re-sistance and input bypass capacitor in place.

2.4 Reference Voltage

2.4.1 Span Adjust

For maximum applications flexibility, these A/Ds have beendesigned to accommodate a 5 VDC, 2.5 VDC or an adjustedvoltage reference. This has been achieved in the design ofthe IC as shown in Figure 6.

Notice that the reference voltage for the IC is either 1⁄2 of thevoltage applied to the VCC supply pin, or is equal to thevoltage that is externally forced at the VREF/2 pin. This allowsfor a ratiometric voltage reference using the VCC supply, a 5VDC reference voltage can be used for the VCC supply or avoltage less than 2.5 VDC can be applied to the VREF/2 inputfor increased application flexibility. The internal gain to theVREF/2 input is 2, making the full-scale differential inputvoltage twice the voltage at pin 9.

An example of the use of an adjusted reference voltage is toaccommodate a reduced span — or dynamic voltage rangeof the analog input voltage. If the analog input voltage wereto range from 0.5 VDC to 3.5 VDC, instead of 0V to 5 VDC, thespan would be 3V as shown in Figure 7. With 0.5 VDC

applied to the VIN(−) pin to absorb the offset, the referencevoltage can be made equal to 1⁄2 of the 3V span or 1.5 VDC.The A/D now will encode the VIN(+) signal from 0.5V to 3.5 Vwith the 0.5V input corresponding to zero and the 3.5 VDC

input corresponding to full-scale. The full 8 bits of resolutionare therefore applied over this reduced analog input voltagerange.

2.4.2 Reference Accuracy Requirements

The converter can be operated in a ratiometric mode or anabsolute mode. In ratiometric converter applications, themagnitude of the reference voltage is a factor in both theoutput of the source transducer and the output of the A/Dconverter and therefore cancels out in the final digital outputcode. The ADC0805 is specified particularly for use in ratio-metric applications with no adjustments required. In absoluteconversion applications, both the initial value and the tem-perature stability of the reference voltage are important fac-tors in the accuracy of the A/D converter. For VREF/2 volt-ages of 2.4 VDC nominal value, initial errors of ±10 mVDC willcause conversion errors of ±1 LSB due to the gain of 2 of theVREF/2 input. In reduced span applications, the initial valueand the stability of the VREF/2 input voltage become evenmore important. For example, if the span is reduced to 2.5V,the analog input LSB voltage value is correspondingly re-duced from 20 mV (5V span) to 10 mV and 1 LSB at theVREF/2 input becomes 5 mV. As can be seen, this reducesthe allowed initial tolerance of the reference voltage andrequires correspondingly less absolute change with tem-perature variations. Note that spans smaller than 2.5V placeeven tighter requirements on the initial accuracy and stabilityof the reference source.

In general, the magnitude of the reference voltage will re-quire an initial adjustment. Errors due to an improper valueof reference voltage appear as full-scale errors in the A/Dtransfer function. IC voltage regulators may be used forreferences if the ambient temperature changes are not ex-cessive. The LM336B 2.5V IC reference diode (from Na-tional Semiconductor) has a temperature stability of 1.8 mVtyp (6 mV max) over 0˚C≤TA≤+70˚C. Other temperaturerange parts are also available.

DS005671-15

FIGURE 6. The VREFERENCE Design on the IC

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com21

L01

Functional Description (Continued)

2.5 Errors and Reference Voltage Adjustments

2.5.1 Zero Error

The zero of the A/D does not require adjustment. If theminimum analog input voltage value, VIN(MIN), is not ground,a zero offset can be done. The converter can be made tooutput 0000 0000 digital code for this minimum input voltageby biasing the A/D VIN(−) input at this VIN(MIN) value (seeApplications section). This utilizes the differential mode op-eration of the A/D.

The zero error of the A/D converter relates to the location ofthe first riser of the transfer function and can be measured bygrounding the VIN (−) input and applying a small magnitudepositive voltage to the VIN (+) input. Zero error is the differ-ence between the actual DC input voltage that is necessaryto just cause an output digital code transition from 0000 0000to 0000 0001 and the ideal 1⁄2 LSB value (1⁄2 LSB = 9.8 mVfor VREF/2=2.500 VDC).

2.5.2 Full-Scale

The full-scale adjustment can be made by applying a differ-ential input voltage that is 11⁄2 LSB less than the desiredanalog full-scale voltage range and then adjusting the mag-nitude of the VREF/2 input (pin 9 or the VCC supply if pin 9 isnot used) for a digital output code that is just changing from1111 1110 to 1111 1111.

2.5.3 Adjusting for an Arbitrary Analog Input VoltageRange

If the analog zero voltage of the A/D is shifted away fromground (for example, to accommodate an analog input signalthat does not go to ground) this new zero reference shouldbe properly adjusted first. A VIN(+) voltage that equals thisdesired zero reference plus 1⁄2 LSB (where the LSB is cal-culated for the desired analog span, 1 LSB=analog span/

256) is applied to pin 6 and the zero reference voltage at pin7 should then be adjusted to just obtain the 00HEX to 01HEX

code transition.

The full-scale adjustment should then be made (with theproper VIN(−) voltage applied) by forcing a voltage to theVIN(+) input which is given by:

where:

VMAX=The high end of the analog input range

and

VMIN=the low end (the offset zero) of the analog range.(Both are ground referenced.)

The VREF/2 (or VCC) voltage is then adjusted to provide acode change from FEHEX to FFHEX. This completes theadjustment procedure.

2.6 Clocking Option

The clock for the A/D can be derived from the CPU clock oran external RC can be added to provide self-clocking. TheCLK IN (pin 4) makes use of a Schmitt trigger as shown inFigure 8.

DS005671-87

a) Analog Input Signal Example

DS005671-88

*Add if VREF/2 ≤ 1 VDC with LM358 to draw 3 mA to ground.

b) Accommodating an Analog Input from0.5V (Digital Out = 00 HEX) to 3.5V

(Digital Out=FF HEX)

FIGURE 7. Adapting the A/D Analog Input Voltages to Match an Arbitrary Input Signal Range

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 22

L01

Functional Description (Continued)

Heavy capacitive or DC loading of the clock R pin should beavoided as this will disturb normal converter operation.Loads less than 50 pF, such as driving up to 7 A/D converterclock inputs from a single clock R pin of 1 converter, areallowed. For larger clock line loading, a CMOS or low powerTTL buffer or PNP input logic should be used to minimize theloading on the clock R pin (do not use a standard TTLbuffer).

2.7 Restart During a Conversion

If the A/D is restarted (CS and WR go low and return high)during a conversion, the converter is reset and a new con-version is started. The output data latch is not updated if theconversion in process is not allowed to be completed, there-fore the data of the previous conversion remains in this latch.The INTR output simply remains at the “1” level.

2.8 Continuous Conversions

For operation in the free-running mode an initializing pulseshould be used, following power-up, to ensure circuit opera-tion. In this application, the CS input is grounded and the WRinput is tied to the INTR output. This WR and INTR nodeshould be momentarily forced to logic low following apower-up cycle to guarantee operation.

2.9 Driving the Data Bus

This MOS A/D, like MOS microprocessors and memories,will require a bus driver when the total capacitance of thedata bus gets large. Other circuitry, which is tied to the databus, will add to the total capacitive loading, even inTRI-STATE (high impedance mode). Backplane bussingalso greatly adds to the stray capacitance of the data bus.

There are some alternatives available to the designer tohandle this problem. Basically, the capacitive loading of thedata bus slows down the response time, even though DCspecifications are still met. For systems operating with arelatively slow CPU clock frequency, more time is availablein which to establish proper logic levels on the bus andtherefore higher capacitive loads can be driven (see typicalcharacteristics curves).

At higher CPU clock frequencies time can be extended forI/O reads (and/or writes) by inserting wait states (8080) orusing clock extending circuits (6800).

Finally, if time is short and capacitive loading is high, externalbus drivers must be used. These can be TRI-STATE buffers

(low power Schottky such as the DM74LS240 series is rec-ommended) or special higher drive current products whichare designed as bus drivers. High current bipolar bus driverswith PNP inputs are recommended.

2.10 Power Supplies

Noise spikes on the VCC supply line can cause conversionerrors as the comparator will respond to this noise. A lowinductance tantalum filter capacitor should be used close tothe converter VCC pin and values of 1 µF or greater arerecommended. If an unregulated voltage is available in thesystem, a separate LM340LAZ-5.0, TO-92, 5V voltage regu-lator for the converter (and other analog circuitry) will greatlyreduce digital noise on the VCC supply.

2.11 Wiring and Hook-Up Precautions

Standard digital wire wrap sockets are not satisfactory forbreadboarding this A/D converter. Sockets on PC boardscan be used and all logic signal wires and leads should begrouped and kept as far away as possible from the analogsignal leads. Exposed leads to the analog inputs can causeundesired digital noise and hum pickup, therefore shieldedleads may be necessary in many applications.

A single point analog ground that is separate from the logicground points should be used. The power supply bypasscapacitor and the self-clocking capacitor (if used) shouldboth be returned to digital ground. Any VREF/2 bypass ca-pacitors, analog input filter capacitors, or input signal shield-ing should be returned to the analog ground point. A test forproper grounding is to measure the zero error of the A/Dconverter. Zero errors in excess of 1⁄4 LSB can usually betraced to improper board layout and wiring (see section 2.5.1for measuring the zero error).

3.0 TESTING THE A/D CONVERTER

There are many degrees of complexity associated with test-ing an A/D converter. One of the simplest tests is to apply aknown analog input voltage to the converter and use LEDs todisplay the resulting digital output code as shown in Figure 9.

For ease of testing, the VREF/2 (pin 9) should be suppliedwith 2.560 VDC and a VCC supply voltage of 5.12 VDC shouldbe used. This provides an LSB value of 20 mV.

If a full-scale adjustment is to be made, an analog inputvoltage of 5.090 VDC (5.120–11⁄2 LSB) should be applied tothe VIN(+) pin with the VIN(−) pin grounded. The value of theVREF/2 input voltage should then be adjusted until the digitaloutput code is just changing from 1111 1110 to 1111 1111.This value of VREF/2 should then be used for all the tests.

The digital output LED display can be decoded by dividingthe 8 bits into 2 hex characters, the 4 most significant (MS)and the 4 least significant (LS). Table 1 shows the fractionalbinary equivalent of these two 4-bit groups. By adding thevoltages obtained from the “VMS” and “VLS” columns inTable 1, the nominal value of the digital display (whenVREF/2 = 2.560V) can be determined. For example, for anoutput LED display of 1011 0110 or B6 (in hex), the voltagevalues from the table are 3.520 + 0.120 or 3.640 VDC. Thesevoltage values represent the center-values of a perfect A/Dconverter. The effects of quantization error have to be ac-counted for in the interpretation of the test results.

DS005671-17

FIGURE 8. Self-Clocking the A/D

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com23

L01

Functional Description (Continued) For a higher speed test system, or to obtain plotted data, adigital-to-analog converter is needed for the test set-up. Anaccurate 10-bit DAC can serve as the precision voltagesource for the A/D. Errors of the A/D under test can beexpressed as either analog voltages or differences in 2digital words.

A basic A/D tester that uses a DAC and provides the error asan analog output voltage is shown in Figure 8. The 2 opamps can be eliminated if a lab DVM with a numericalsubtraction feature is available to read the difference volt-age, “A–C”, directly. The analog input voltage can be sup-plied by a low frequency ramp generator and an X-Y plottercan be used to provide analog error (Y axis) versus analoginput (X axis).

For operation with a microprocessor or a computer-basedtest system, it is more convenient to present the errorsdigitally. This can be done with the circuit of Figure 11, wherethe output code transitions can be detected as the 10-bitDAC is incremented. This provides 1⁄4 LSB steps for the 8-bitA/D under test. If the results of this test are automaticallyplotted with the analog input on the X axis and the error (inLSB’s) as the Y axis, a useful transfer function of the A/Dunder test results. For acceptance testing, the plot is notnecessary and the testing speed can be increased by estab-lishing internal limits on the allowed error for each code.

4.0 MICROPROCESSOR INTERFACING

To dicuss the interface with 8080A and 6800 microproces-sors, a common sample subroutine structure is used. Themicroprocessor starts the A/D, reads and stores the resultsof 16 successive conversions, then returns to the user’sprogram. The 16 data bytes are stored in 16 successivememory locations. All Data and Addresses will be given inhexadecimal form. Software and hardware details are pro-vided separately for each type of microprocessor.

4.1 Interfacing 8080 Microprocessor Derivatives (8048,8085)

This converter has been designed to directly interface withderivatives of the 8080 microprocessor. The A/D can bemapped into memory space (using standard memory ad-dress decoding for CS and the MEMR and MEMW strobes)or it can be controlled as an I/O device by using the I/O Rand I/O W strobes and decoding the address bits A0 → A7(or address bits A8 → A15 as they will contain the same 8-bitaddress information) to obtain the CS input. Using the I/Ospace provides 256 additional addresses and may allow asimpler 8-bit address decoder but the data can only be inputto the accumulator. To make use of the additional memoryreference instructions, the A/D should be mapped intomemory space. An example of an A/D in I/O space is shownin Figure 12.

DS005671-18

FIGURE 9. Basic A/D Tester

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 24

L01

Functional Description (Continued)

TABLE 1. DECODING THE DIGITAL OUTPUT LEDs

OUTPUT VOLTAGE

FRACTIONAL BINARY VALUE FOR CENTER VALUES

HEX BINARY WITH

VREF/2=2.560 VDC

MS GROUP LS GROUP VMSGROUP(Note 15)

VLSGROUP(Note 15)

F 1 1 1 1 15/16 15/256 4.800 0.300

E 1 1 1 0 7/8 7/128 4.480 0.280

D 1 1 0 1 13/16 13/256 4.160 0.260

C 1 1 0 0 3/4 3/64 3.840 0.240

B 1 0 1 1 11/16 11/256 3.520 0.220

A 1 0 1 0 5/8 5/128 3.200 0.200

9 1 0 0 1 9/16 9/256 2.880 0.180

8 1 0 0 0 1/2 1/32 2.560 0.160

7 0 1 1 1 7/16 7/256 2.240 0.140

6 0 1 1 0 3/8 3/128 1.920 0.120

5 0 1 0 1 5/16 2/256 1.600 0.100

4 0 1 0 0 1/4 1/64 1.280 0.080

3 0 0 1 1 3/16 3/256 0.960 0.060

2 0 0 1 0 1/8 1/128 0.640 0.040

1 0 0 0 1 1/16 1/256 0.320 0.020

0 0 0 0 0 0 0

Note 15: Display Output=VMS Group + VLS Group

DS005671-89

FIGURE 10. A/D Tester with Analog Error Output

DS005671-90

FIGURE 11. Basic “Digital” A/D Tester

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com25

L01

Functional Description (Continued)

DS005671-20

Note 16: *Pin numbers for the DP8228 system controller, others are INS8080A.

Note 17: Pin 23 of the INS8228 must be tied to +12V through a 1 kΩ resistor to generate the RST 7

instruction when an interrupt is acknowledged as required by the accompanying sample program.

FIGURE 12. ADC0801_INS8080A CPU Interface

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 26

L01

Functional Description (Continued)

Note 18: The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack.

Note 19: All address used were arbitrarily chosen.

The standard control bus signals of the 8080 CS, RD andWR) can be directly wired to the digital control inputs of theA/D and the bus timing requirements are met to allow bothstarting the converter and outputting the data onto the databus. A bus driver should be used for larger microprocessorsystems where the data bus leaves the PC board and/ormust drive capacitive loads larger than 100 pF.

4.1.1 Sample 8080A CPU Interfacing Circuitry andProgram

The following sample program and associated hardwareshown in Figure 12 may be used to input data from theconverter to the INS8080A CPU chip set (comprised of theINS8080A microprocessor, the INS8228 system controllerand the INS8224 clock generator). For simplicity, the A/D iscontrolled as an I/O device, specifically an 8-bit bi-directionalport located at an arbitrarily chosen port address, E0. TheTRI-STATE output capability of the A/D eliminates the needfor a peripheral interface device, however address decodingis still required to generate the appropriate CS for the con-verter.

It is important to note that in systems where the A/D con-verter is 1-of-8 or less I/O mapped devices, no addressdecoding circuitry is necessary. Each of the 8 address bits(A0 to A7) can be directly used as CS inputs — one for eachI/O device.

4.1.2 INS8048 Interface

The INS8048 interface technique with the ADC0801 series(see Figure 13) is simpler than the 8080A CPU interface.There are 24 I/O lines and three test input lines in the 8048.With these extra I/O lines available, one of the I/O lines (bit0 of port 1) is used as the chip select signal to the A/D, thuseliminating the use of an external address decoder. Buscontrol signals RD, WR and INT of the 8048 are tied directlyto the A/D. The 16 converted data words are stored aton-chip RAM locations from 20 to 2F (Hex). The RD and WRsignals are generated by reading from and writing into adummy address, respectively. A sample interface program isshown below.

SAMPLE PROGRAM FOR Figure 12 ADC0801–INS8080A CPU INTERFACE

DS005671-99

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com27

L01

Functional Description (Continued)

4.2 Interfacing the Z-80

The Z-80 control bus is slightly different from that of the8080. General RD and WR strobes are provided and sepa-rate memory request, MREQ, and I/O request, IORQ, sig-nals are used which have to be combined with the general-ized strobes to provide the equivalent 8080 signals. Anadvantage of operating the A/D in I/O space with the Z-80 isthat the CPU will automatically insert one wait state (the RDand WR strobes are extended one clock period) to allowmore time for the I/O devices to respond. Logic to map theA/D in I/O space is shown in Figure 14. Additional I/O advantages exist as software DMA routines

are available and use can be made of the output datatransfer which exists on the upper 8 address lines (A8 to

DS005671-21

FIGURE 13. INS8048 Interface

SAMPLE PROGRAM FOR Figure 13 INS8048 INTERFACE

DS005671-A0

DS005671-23

FIGURE 14. Mapping the A/D as an I/O Devicefor Use with the Z-80 CPU

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 28

L01

Functional Description (Continued)

A15) during I/O input instructions. For example, MUX chan-nel selection for the A/D can be accomplished with thisoperating mode.

4.3 Interfacing 6800 Microprocessor Derivatives(6502, etc.)

The control bus for the 6800 microprocessor derivativesdoes not use the RD and WR strobe signals. Instead itemploys a single R/W line and additional timing, if needed,can be derived fom the φ2 clock. All I/O devices are memorymapped in the 6800 system, and a special signal, VMA,indicates that the current address is valid. Figure 15 showsan interface schematic where the A/D is memory mapped inthe 6800 system. For simplicity, the CS decoding is shownusing 1⁄2 DM8092. Note that in many 6800 systems, analready decoded 4/5 line is brought out to the common busat pin 21. This can be tied directly to the CS pin of the A/D,provided that no other devices are addressed at HX ADDR:4XXX or 5XXX.

The following subroutine performs essentially the same func-tion as in the case of the 8080A interface and it can be calledfrom anywhere in the user’s program.

In Figure 16 the ADC0801 series is interfaced to the M6800microprocessor through (the arbitrarily chosen) Port B of theMC6820 or MC6821 Peripheral Interface Adapter, (PIA).Here the CS pin of the A/D is grounded since the PIA is

already memory mapped in the M6800 system and no CSdecoding is necessary. Also notice that the A/D output datalines are connected to the microprocessor bus under pro-gram control through the PIA and therefore the A/D RD pincan be grounded.

A sample interface program equivalent to the previous one isshown below Figure 16. The PIA Data and Control Registersof Port B are located at HEX addresses 8006 and 8007,respectively.

5.0 GENERAL APPLICATIONS

The following applications show some interesting uses forthe A/D. The fact that one particular microprocessor is usedis not meant to be restrictive. Each of these applicationcircuits would have its counterpart using any microprocessorthat is desired.

5.1 Multiple ADC0801 Series to MC6800 CPU Interface

To transfer analog data from several channels to a singlemicroprocessor system, a multiple converter scheme pre-sents several advantages over the conventional multiplexersingle-converter approach. With the ADC0801 series, thedifferential inputs allow individual span adjustment for eachchannel. Furthermore, all analog input channels are sensedsimultaneously, which essentially divides the microproces-sor’s total system servicing time by the number of channels,since all conversions occur simultaneously. This scheme isshown in Figure 17.

DS005671-24

Note 20: Numbers in parentheses refer to MC6800 CPU pin out.

Note 21: Number or letters in brackets refer to standard M6800 system common bus code.

FIGURE 15. ADC0801-MC6800 CPU Interface

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com29

L01

Functional Description (Continued)

Note 22: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program.

SAMPLE PROGRAM FOR Figure 15 ADC0801-MC6800 CPU INTERFACE

DS005671-A1

DS005671-25

FIGURE 16. ADC0801–MC6820 PIA Interface

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 30

L01

Functional Description (Continued)

The following schematic and sample subroutine (DATA IN)may be used to interface (up to) 8 ADC0801’s directly to theMC6800 CPU. This scheme can easily be extended to allowthe interface of more converters. In this configuration theconverters are (arbitrarily) located at HEX address 5000 inthe MC6800 memory space. To save components, the clocksignal is derived from just one RC pair on the first converter.This output drives the other A/Ds.

All the converters are started simultaneously with a STOREinstruction at HEX address 5000. Note that any other HEXaddress of the form 5XXX will be decoded by the circuit,pulling all the CS inputs low. This can easily be avoided byusing a more definitive address decoding scheme. All theinterrupts are ORed together to insure that all A/Ds havecompleted their conversion before the microprocessor isinterrupted.

The subroutine, DATA IN, may be called from anywhere inthe user’s program. Once called, this routine initializes the

CPU, starts all the converters simultaneously and waits forthe interrupt signal. Upon receiving the interrupt, it reads theconverters (from HEX addresses 5000 through 5007) andstores the data successively at (arbitrarily chosen) HEXaddresses 0200 to 0207, before returning to the user’s pro-gram. All CPU registers then recover the original data theyhad before servicing DATA IN.

5.2 Auto-Zeroed Differential Transducer Amplifierand A/D Converter

The differential inputs of the ADC0801 series eliminate theneed to perform a differential to single ended conversion fora differential transducer. Thus, one op amp can be elimi-nated since the differential to single ended conversion isprovided by the differential input of the ADC0801 series. Ingeneral, a transducer preamp is required to take advantageof the full A/D converter input dynamic range.

SAMPLE PROGRAM FOR Figure 16 ADC0801–MC6820 PIA INTERFACE

DS005671-A2

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com31

L01

Functional Description (Continued)

DS005671-26

Note 23: Numbers in parentheses refer to MC6800 CPU pin out.

Note 24: Numbers of letters in brackets refer to standard M6800 system common bus code.

FIGURE 17. Interfacing Multiple A/Ds in an MC6800 System

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 32

L01

Functional Description (Continued)

Note 25: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program.

For amplification of DC input signals, a major system error isthe input offset voltage of the amplifiers used for the preamp.Figure 18 is a gain of 100 differential preamp whose offsetvoltage errors will be cancelled by a zeroing subroutinewhich is performed by the INS8080A microprocessor sys-tem. The total allowable input offset voltage error for thispreamp is only 50 µV for 1⁄4 LSB error. This would obviouslyrequire very precise amplifiers. The expression for the differ-ential output voltage of the preamp is:

where IX is the current through resistor RX. All of the offseterror terms can be cancelled by making ±IXRX= VOS1 +VOS3 − VOS2. This is the principle of this auto-zeroingscheme.

The INS8080A uses the 3 I/O ports of an INS8255 Progra-mable Peripheral Interface (PPI) to control the auto zeroingand input data from the ADC0801 as shown in Figure 19.The PPI is programmed for basic I/O operation (mode 0) withPort A being an input port and Ports B and C being outputports. Two bits of Port C are used to alternately open or closethe 2 switches at the input of the preamp. Switch SW1 isclosed to force the preamp’s differential input to be zeroduring the zeroing subroutine and then opened and SW2 isthen closed for conversion of the actual differential inputsignal. Using 2 switches in this manner eliminates concernfor the ON resistance of the switches as they must conductonly the input bias current of the input amplifiers.

Output Port B is used as a successive approximation regis-ter by the 8080 and the binary scaled resistors in series witheach output bit create a D/A converter. During the zeroingsubroutine, the voltage at Vx increases or decreases asrequired to make the differential output voltage equal to zero.This is accomplished by ensuring that the voltage at theoutput of A1 is approximately 2.5V so that a logic “1” (5V) on

SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A/D’s IN AN MC6800 SYSTEM

DS005671-A3

SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A/D’s IN AN MC6800 SYSTEM

DS005671-A4

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com33

L01

Functional Description (Continued)

any output of Port B will source current into node VX thusraising the voltage at VX and making the output differentialmore negative. Conversely, a logic “0” (0V) will pull currentout of node VX and decrease the voltage, causing the differ-ential output to become more positive. For the resistor val-ues shown, VX can move ±12 mV with a resolution of 50 µV,which will null the offset error term to 1⁄4 LSB of full-scale for

the ADC0801. It is important that the voltage levels that drivethe auto-zero resistors be constant. Also, for symmetry, alogic swing of 0V to 5V is convenient. To achieve this, aCMOS buffer is used for the logic output signals of Port Band this CMOS package is powered with a stable 5V source.Buffer amplifier A1 is necessary so that it can source or sinkthe D/A output current.

DS005671-91

Note 26: R2 = 49.5 R1

Note 27: Switches are LMC13334 CMOS analog switches.

Note 28: The 9 resistors used in the auto-zero section can be ±5% tolerance.

FIGURE 18. Gain of 100 Differential Transducer Preamp

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 34

L01

Functional Description (Continued)

A flow chart for the zeroing subroutine is shown in Figure 20.It must be noted that the ADC0801 series will output an allzero code when it converts a negative input [VIN(−) ≥ VIN(+)].Also, a logic inversion exists as all of the I/O ports arebuffered with inverting gates.

Basically, if the data read is zero, the differential outputvoltage is negative, so a bit in Port B is cleared to pull VX

more negative which will make the output more positive forthe next conversion. If the data read is not zero, the outputvoltage is positive so a bit in Port B is set to make VX morepositive and the output more negative. This continues for 8approximations and the differential output eventually con-verges to within 5 mV of zero.

The actual program is given in Figure 21. All addresses usedare compatible with the BLC 80/10 microcomputer system.In particular:

Port A and the ADC0801 are at port address E4

Port B is at port address E5

Port C is at port address E6

PPI control word port is at port address E7

Program Counter automatically goes to ADDR:3C3D upon

acknowledgement of an interrupt from the ADC0801

5.3 Multiple A/D Converters in a Z-80 InterruptDriven Mode

In data acquisition systems where more than one A/D con-verter (or other peripheral device) will be interrupting pro-gram execution of a microprocessor, there is obviously a

need for the CPU to determine which device requires servic-ing. Figure 22 and the accompanying software is a methodof determining which of 7 ADC0801 converters has com-pleted a conversion (INTR asserted) and is requesting aninterrupt. This circuit allows starting the A/D converters inany sequence, but will input and store valid data from theconverters with a priority sequence of A/D 1 being read first,A/D 2 second, etc., through A/D 7 which would have thelowest priority for data being read. Only the converterswhose INT is asserted will be read.

The key to decoding circuitry is the DM74LS373, 8-bit D typeflip-flop. When the Z-80 acknowledges the interrupt, theprogram is vectored to a data input Z-80 subroutine. Thissubroutine will read a peripheral status word from theDM74LS373 which contains the logic state of the INTRoutputs of all the converters. Each converter which initiatesan interrupt will place a logic “0” in a unique bit position in thestatus word and the subroutine will determine the identity ofthe converter and execute a data read. An identifier word(which indicates which A/D the data came from) is stored inthe next sequential memory location above the location ofthe data so the program can keep track of the identity of thedata entered.

DS005671-92

FIGURE 19. Microprocessor Interface Circuitry for Differential Preamp

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com35

L01

Functional Description (Continued)

DS005671-28

FIGURE 20. Flow Chart for Auto-Zero Routine

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 36

L01

Functional Description (Continued)

5.3 Multiple A/D Converters in a Z-80 Interrupt DrivenMode (Continued)

The following notes apply:

• It is assumed that the CPU automatically performs a RST7 instruction when a valid interrupt is acknowledged(CPU is in interrupt mode 1). Hence, the subroutinestarting address of X0038.

• The address bus from the Z-80 and the data bus to theZ-80 are assumed to be inverted by bus drivers.

• A/D data and identifying words will be stored in sequen-tial memory locations starting at the arbitrarily chosenaddress X 3E00.

• The stack pointer must be dimensioned in the main pro-gram as the RST 7 instruction automatically pushes thePC onto the stack and the subroutine uses an additional6 stack addresses.

• The peripherals of concern are mapped into I/O spacewith the following port assignments:

DS005671-A5

Note 29: All numerical values are hexadecimal representations.

FIGURE 21. Software for Auto-Zeroed Differential A/D

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com37

L01

Functional Description (Continued)

HEX PORT ADDRESS PERIPHERAL

00 MM74C374 8-bit flip-flop

01 A/D 1

02 A/D 2

03 A/D 3

HEX PORT ADDRESS PERIPHERAL

04 A/D 4

05 A/D 5

06 A/D 6

07 A/D 7

This port address also serves as the A/D identifying word inthe program.

DS005671-29

FIGURE 22. Multiple A/Ds with Z-80 Type Microprocessor

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 38

L01

Functional Description (Continued)

DS005671-A6

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

www.national.com39

L01

Physical Dimensions inches (millimeters) unless otherwise noted

SO Package (M)Order Number ADC0802LCWM or ADC0804LCWM

NS Package Number M20B

Molded Dual-In-Line Package (N)Order Number ADC0801LCN, ADC0802LCN,

ADC0803LCN, ADC0804LCN or ADC0805LCNNS Package Number N20A

AD

C08

01/A

DC

0802

/AD

C08

03/A

DC

0804

/AD

C08

05

www.national.com 40

L01

Notes

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.

2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.

National SemiconductorCorporationAmericasEmail: support@nsc.com

National SemiconductorEurope

Fax: +49 (0) 180-530 85 86Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208English Tel: +44 (0) 870 24 0 2171Français Tel: +33 (0) 1 41 91 8790

National SemiconductorAsia Pacific CustomerResponse GroupTel: 65-2544466Fax: 65-2504466Email: ap.support@nsc.com

National SemiconductorJapan Ltd.Tel: 81-3-5639-7560Fax: 81-3-5639-7507

www.national.com

AD

C0801/A

DC

0802/AD

C0803/A

DC

0804/AD

C0805

8-BitµP

Com

patibleA

/DC

onverters

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

L01

LF155/LF156/LF256/LF257/LF355/LF356/LF357JFET Input Operational AmplifiersGeneral DescriptionThese are the first monolithic JFET input operational ampli-fiers to incorporate well matched, high voltage JFETs on thesame chip with standard bipolar transistors (BI-FET™ Tech-nology). These amplifiers feature low input bias and offsetcurrents/low offset voltage and offset voltage drift, coupledwith offset adjust which does not degrade drift orcommon-mode rejection. The devices are also designed forhigh slew rate, wide bandwidth, extremely fast settling time,low voltage and current noise and a low 1/f noise corner.

FeaturesAdvantagesn Replace expensive hybrid and module FET op ampsn Rugged JFETs allow blow-out free handling compared

with MOSFET input devicesn Excellent for low noise applications using either high or

low source impedance — very low 1/f cornern Offset adjust does not degrade drift or common-mode

rejection as in most monolithic amplifiersn New output stage allows use of large capacitive loads

(5,000 pF) without stability problemsn Internal compensation and large differential input voltage

capability

Applicationsn Precision high speed integratorsn Fast D/A and A/D convertersn High impedance buffersn Wideband, low noise, low drift amplifiers

n Logarithmic amplifiersn Photocell amplifiersn Sample and Hold circuits

Common Featuresn Low input bias current: 30pAn Low Input Offset Current: 3pAn High input impedance: 1012Ωn Low input noise current:n High common-mode rejection ratio: 100 dBn Large dc voltage gain: 106 dB

Uncommon FeaturesLF155/LF355

LF156/LF256/LF356

LF257/LF357(AV=5)

Units

j Extremelyfast settlingtime to0.01%

4 1.5 1.5 µs

j Fast slewrate

5 12 50 V/µs

j Wide gainbandwidth

2.5 5 20 MHz

j Low inputnoisevoltage

20 12 12

Simplified Schematic

00564601

*3pF in LF357 series.

BI-FET™, BI-FET II™ are trademarks of National Semiconductor Corporation.

December 2001LF155/LF156/LF256/LF257/LF355/LF356/LF357

JFET

InputOperationalA

mplifiers

© 2001 National Semiconductor Corporation DS005646 www.national.com

L04

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors foravailability and specifications.

LF155/6 LF256/7/LF356B LF355/6/7

Supply Voltage ±22V ±22V ±18V

Differential Input Voltage ±40V ±40V ±30V

Input Voltage Range (Note 2) ±20V ±20V ±16V

Output Short Circuit Duration Continuous Continuous Continuous

TJMAX

H-Package 150˚C 115˚C 115˚C

N-Package 100˚C 100˚C

M-Package 100˚C 100˚C

Power Dissipation at TA = 25˚C (Notes1, 8)

H-Package (Still Air) 560 mW 400 mW 400 mW

H-Package (400 LF/Min Air Flow) 1200 mW 1000 mW 1000 mW

N-Package 670 mW 670 mW

M-Package 380 mW 380 mW

Thermal Resistance (Typical) θJA

H-Package (Still Air) 160˚C/W 160˚C/W 160˚C/W

H-Package (400 LF/Min Air Flow) 65˚C/W 65˚C/W 65˚C/W

N-Package 130˚C/W 130˚C/W

M-Package 195˚C/W 195˚C/W

(Typical) θJC

H-Package 23˚C/W 23˚C/W 23˚C/W

Storage Temperature Range −65˚C to +150˚C −65˚C to +150˚C −65˚C to +150˚C

Soldering Information (Lead Temp.)

Metal Can Package

Soldering (10 sec.) 300˚C 300˚C 300˚C

Dual-In-Line Package

Soldering (10 sec.) 260˚C 260˚C 260˚C

Small Outline Package

Vapor Phase (60 sec.) 215˚C 215˚C

Infrared (15 sec.) 220˚C 220˚C

See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods ofsoldering surface mount devices.

ESD tolerance

(100 pF discharged through 1.5kΩ) 1000V 1000V 1000V

DC Electrical Characteristics(Note 3)

Symbol Parameter ConditionsLF155/6

LF256/7LF356B

LF355/6/7Units

Min Typ Max Min Typ Max Min Typ Max

VOS Input Offset Voltage RS=50Ω, TA=25˚C 3 5 3 5 3 10 mV

Over Temperature 7 6.5 13 mV

∆VOS/∆T Average TC of InputOffset Voltage

RS=50Ω5 5 5 µV/˚C

∆TC/∆VOS Change in Average TCwith VOS Adjust

RS=50Ω, (Note 4)0.5 0.5 0.5

µV/˚Cper mV

IOS Input Offset Current TJ=25˚C, (Notes 3, 5) 3 20 3 20 3 50 pA

TJ≤THIGH 20 1 2 nA

LF15

5/LF

156/

LF25

6/LF

257/

LF35

5/LF

356/

LF35

7

www.national.com 2

L04

DC Electrical Characteristics (Continued)(Note 3)

Symbol Parameter ConditionsLF155/6

LF256/7LF356B

LF355/6/7Units

Min Typ Max Min Typ Max Min Typ Max

IB Input Bias Current TJ=25˚C, (Notes 3, 5) 30 100 30 100 30 200 pA

TJ≤THIGH 50 5 8 nA

RIN Input Resistance TJ=25˚C 1012 1012 1012 ΩAVOL Large Signal Voltage

GainVS=±15V, TA=25˚C 50 200 50 200 25 200 V/mV

VO=±10V, RL=2k

Over Temperature 25 25 15 V/mV

VO Output Voltage Swing VS=±15V, RL=10k ±12 ±13 ±12 ±13 ±12 ±13 V

VS=±15V, RL=2k ±10 ±12 ±10 ±12 ±10 ±12 V

VCM Input Common-ModeVoltage Range

VS=±15V±11

+15.1±11

±15.1+10

+15.1 V

−12 −12 −12 V

CMRR Common-ModeRejection Ratio

85 100 85 100 80 100 dB

PSRR Supply VoltageRejection Ratio

(Note 6)85 100 85 100 80 100 dB

DC Electrical CharacteristicsTA = TJ = 25˚C, VS = ±15V

ParameterLF155 LF355 LF156/256/257/356B LF356 LF357

UnitsTyp Max Typ Max Typ Max Typ Max Typ Max

SupplyCurrent

2 4 2 4 5 7 5 10 5 10 mA

AC Electrical CharacteristicsTA = TJ = 25˚C, VS = ±15V

Symbol Parameter Conditions

LF155/355 LF156/256/356B

LF156/256/356/LF356B

LF257/357

Units

Typ Min Typ Typ

SR Slew Rate LF155/6:AV=1,

5 7.5 12 V/µs

LF357: AV=5 50 V/µs

GBW Gain Bandwidth Product 2.5 5 20 MHz

ts Settling Time to 0.01% (Note 7) 4 1.5 1.5 µs

en Equivalent Input NoiseVoltage

RS=100Ωf=100 Hz 25 15 15

f=1000 Hz 20 12 12

in Equivalent Input CurrentNoise

f=100 Hz 0.01 0.01 0.01

f=1000 Hz 0.01 0.01 0.01

CIN Input Capacitance 3 3 3 pF

Notes for Electrical CharacteristicsNote 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,TA. The maximum available power dissipation at any temperature is PD=(TJMAX−TA)/θJA or the 25˚C PdMAX, whichever is less.

Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

Note 3: Unless otherwise stated, these test conditions apply:

LF155/LF156/LF256/LF257/LF355/LF356/LF357

www.national.com3

L04

Notes for Electrical Characteristics (Continued)

LF155/156 LF256/257 LF356B LF355/6/7

Supply Voltage, VS ±15V ≤ VS ≤ ±20V ±15V ≤ VS ≤ ±20V ±15V ≤ VS ±20V VS= ±15V

TA −55˚C ≤ TA ≤ +125˚C −25˚C ≤ TA ≤ +85˚C 0˚C ≤ TA ≤ +70˚C 0˚C ≤ TA ≤ +70˚C

THIGH +125˚C +85˚C +70˚C +70˚C

and VOS, IB and IOS are measured at VCM = 0.

Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5µV/˚C typically) for each mV of adjustment from its originalunadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment.

Note 5: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, TJ. Due to limitedproduction test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambienttemperature as a result of internal power dissipation, Pd. TJ = TA + θJA Pd where θJA is the thermal resistance from junction to ambient. Use of a heat sink isrecommended if input bias current is to be kept to a minimum.

Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.

Note 7: Settling time is defined here, for a unity gain inverter connection using 2 kΩ resistors for the LF155/6. It is the time required for the error voltage (the voltageat the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the inverter. For the LF357, AV = −5,the feedback resistor from output to input is 2kΩ and the output step is 10V (See Settling Time Test Circuit).

Note 8: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outsideguaranteed limits.

Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwisespecified.

Input Bias Current Input Bias Current

00564637 00564638

Input Bias Current Voltage Swing

00564639 00564640

LF15

5/LF

156/

LF25

6/LF

257/

LF35

5/LF

356/

LF35

7

www.national.com 4

L04

Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwisespecified. (Continued)

Supply Current Supply Current

00564641 00564642

Negative Current Limit Positive Current Limit

00564643 00564644

Positive Common-ModeInput Voltage Limit

Negative Common-ModeInput Voltage Limit

00564645

00564646

LF155/LF156/LF256/LF257/LF355/LF356/LF357

www.national.com5

L04

Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwisespecified. (Continued)

Open Loop Voltage Gain Output Voltage Swing

00564647 00564648

Typical AC Performance CharacteristicsGain Bandwidth Gain Bandwidth

0056464900564650

Normalized Slew Rate Output Impedance

0056465100564652

LF15

5/LF

156/

LF25

6/LF

257/

LF35

5/LF

356/

LF35

7

www.national.com 6

L04

Typical AC Performance Characteristics (Continued)

Output Impedance LF155 Small Signal Pulse Response, A V = +1

00564653

00564605

LF156 Small Signal Pulse Response, A V = +1 LF155 Large Signal Pulse Response, A V = +1

00564606 00564608

LF156 Large Signal PulsResponse, A V = +1 Inverter Settling Time

00564609

00564655

LF155/LF156/LF256/LF257/LF355/LF356/LF357

www.national.com7

L04

Typical AC Performance Characteristics (Continued)

Inverter Settling Time Open Loop Frequency Response

00564656 00564657

Bode Plot Bode Plot

00564658 00564659

Bode Plot Common-Mode Rejection Ratio

00564660 00564661

LF15

5/LF

156/

LF25

6/LF

257/

LF35

5/LF

356/

LF35

7

www.national.com 8

L04

Typical AC Performance Characteristics (Continued)

Power Supply Rejection Ratio Power Supply Rejection Ratio

00564662 00564663

Undistorted Output Voltage Swing Equivalent Input Noise Voltage

00564664

00564665

Equivalent Input NoiseVoltage (Expanded Scale)

00564666

LF155/LF156/LF256/LF257/LF355/LF356/LF357

www.national.com9

L04

Detailed Schematic

00564613

*C = 3pF in LF357 series.

Connection Diagrams (Top Views)

Metal Can Package (H)

00564614

Order Number LF155H, LF156H, LF256H, LF257H,LF356BH, LF356H, or LF357H

See NS Package Number H08C*Available per JM38510/11401 or JM38510/11402

Dual-In-Line Package (M and N)

00564629

Order Number LF356M, LF356MX, LF355N, or LF356NSee NS Package Number M08A or N08E

Application HintsThese are op amps with JFET input devices. These JFETshave large reverse breakdown voltages from gate to sourceand drain eliminating the need for clamps across the inputs.Therefore large differential input voltages can easily be ac-commodated without a large increase in input current. Themaximum differential input voltage is independent of thesupply voltages. However, neither of the input voltagesshould be allowed to exceed the negative supply as this willcause large currents to flow which can result in a destroyedunit.

Exceeding the negative common-mode limit on either inputwill force the output to a high state, potentially causing a

LF15

5/LF

156/

LF25

6/LF

257/

LF35

5/LF

356/

LF35

7

www.national.com 10

L04

Application Hints (Continued)

reversal of phase to the output. Exceeding the negativecommon-mode limit on both inputs will force the amplifieroutput to a high state. In neither case does a latch occursince raising the input back within the common-mode rangeagain puts the input stage and thus the amplifier in a normaloperating mode.

Exceeding the positive common-mode limit on a single inputwill not change the phase of the output however, if bothinputs exceed the limit, the output of the amplifier will beforced to a high state.

These amplifiers will operate with the common-mode inputvoltage equal to the positive supply. In fact, thecommon-mode voltage can exceed the positive supply byapproximately 100 mV independent of supply voltage andover the full operating temperature range. The positive sup-ply can therefore be used as a reference on an input as, forexample, in a supply current monitor and/or limiter.

Precautions should be taken to ensure that the power supplyfor the integrated circuit never becomes reversed in polarityor that the unit is not inadvertently installed backwards in asocket as an unlimited current surge through the resultingforward diode within the IC could cause fusing of the internalconductors and result in a destroyed unit.

All of the bias currents in these amplifiers are set by FETcurrent sources. The drain currents for the amplifiers aretherefore essentially independent of supply voltage.

As with most amplifiers, care should be taken with leaddress, component placement and supply decoupling in orderto ensure stability. For example, resistors from the output toan input should be placed with the body close to the input tominimize “pickup” and maximize the frequency of the feed-back pole by minimizing the capacitance from the input toground.

A feedback pole is created when the feedback around anyamplifier is resistive. The parallel resistance and capacitancefrom the input of the device (usually the inverting input) to ACground set the frequency of the pole. In many instances thefrequency of this pole is much greater than the expected 3dBfrequency of the closed loop gain and consequently there isnegligible effect on stability margin. However, if the feedbackpole is less than approximately six times the expected 3 dBfrequency a lead capacitor should be placed from the outputto the input of the op amp. The value of the added capacitorshould be such that the RC time constant of this capacitorand the resistance it parallels is greater than or equal to theoriginal feedback pole time constant.

Typical Circuit ConnectionsVOS Adjustment

00564667

• VOS is adjusted with a 25k potentiometer

• The potentiometer wiper is connected to V+

• For potentiometers with temperature coefficient of 100ppm/˚C or less the additional drift with adjust is ≈ 0.5µV/˚C/mV of adjustment

• Typical overall drift: 5µV/˚C ±(0.5µV/˚C/mV of adj.)

Driving Capacitive Loads

00564668

* LF155/6 R = 5k

LF357 R = 1.25k

Due to a unique output stage design, these amplifiershave the ability to drive large capacitive loads and stillmaintain stability. CL(MAX) . 0.01µF.

Overshoot ≤ 20%

Settling time (ts) . 5µs

LF357. A Large Power BW Amplifier

00564615

For distortion ≤ 1% and a 20 Vp-p VOUT swing, power bandwidth is:500kHz.

LF155/LF156/LF256/LF257/LF355/LF356/LF357

www.national.com11

L04

Typical ApplicationsSettling Time Test Circuit

00564616

• Settling time is tested with the LF155/6 connected as unity gain inverter and LF357 connected for AV = −5

• FET used to isolate the probe capacitance

• Output = 10V step

• AV = −5 for LF357

Large Signal Inverter Output, V OUT (from Settling Time Circuit)

LF355

00564617

LF356

00564618

LF357

00564619

LF15

5/LF

156/

LF25

6/LF

257/

LF35

5/LF

356/

LF35

7

www.national.com 12

L04

Typical Applications (Continued)

Low Drift Adjustable Voltage Reference

00564620

• ∆ VOUT/∆T = ±0.002%/˚C

• All resistors and potentiometers should be wire-wound

• P1: drift adjust

• P2: VOUT adjust

• Use LF155 for

j Low IBj Low drift

j Low supply current

Fast Logarithmic Converter

00564621

• Dynamic range: 100µA ≤ Ii ≤ 1mA (5 decades), |VO| = 1V/decade

• Transient response: 3µs for ∆Ii = 1 decade

• C1, C2, R2, R3: added dynamic compensation

• VOS adjust the LF156 to minimize quiescent error

• RT: Tel Labs type Q81 + 0.3%/˚C

LF155/LF156/LF256/LF257/LF355/LF356/LF357

www.national.com13

L04

Typical Applications (Continued)

Precision Current Monitor

00564631

• VO = 5 R1/R2 (V/mA of IS)

• R1, R2, R3: 0.1% resistors

• Use LF155 for

j Common-mode range to supply range

j Low IBj Low VOS

j Low Supply Current

8-Bit D/A Converter with Symmetrical Offset Binary Operation

00564632

• R1, R2 should be matched within ±0.05%

• Full-scale response time: 3µs

EO B1 B2 B3 B4 B5 B6 B7 B8 Comments

+9.920 1 1 1 1 1 1 1 1 Positive Full-Scale

+0.040 1 0 0 0 0 0 0 0 (+) Zero-Scale

−0.040 0 1 1 1 1 1 1 1 (−) Zero-Scale

−9.920 0 0 0 0 0 0 0 0 Negative Full-Scale

LF15

5/LF

156/

LF25

6/LF

257/

LF35

5/LF

356/

LF35

7

www.national.com 14

L04

Typical Applications (Continued)

Wide BW Low Noise, Low Drift Amplifier

00564670

• Parasitic input capacitance C1 . (3pF for LF155, LF156 and LF357 plus any additional layout capacitance) interacts withfeedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 . R1 C1.

Boosting the LF156 with a Current Amplifier

00564673

• IOUT(MAX).150mA (will drive RL≥ 100Ω)

• No additional phase shift added by the current amplifier

LF155/LF156/LF256/LF257/LF355/LF356/LF357

www.national.com15

L04

Typical Applications (Continued)

3 Decades VCO

00564624

R1, R4 matched. Linearity 0.1% over 2 decades.

Isolating Large Capacitive Loads

00564622

• Overshoot 6%

• ts 10µs

• When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX):

LF15

5/LF

156/

LF25

6/LF

257/

LF35

5/LF

356/

LF35

7

www.national.com 16

L04

Typical Applications (Continued)

Low Drift Peak Detector

00564623

• By adding D1 and Rf, VD1=0 during hold mode. Leakage of D2 provided by feedback path through Rf.

• Leakage of circuit is essentially Ib (LF155, LF156) plus capacitor leakage of Cp.

• Diode D3 clamps VOUT (A1) to VIN−VD3 to improve speed and to limit reverse bias of D2.

• Maximum input frequency should be << 1⁄2πRfCD2 where CD2 is the shunt capacitance of D2.

Non-Inverting Unity Gain Operation for LF157

00564675

Inverting Unity Gain for LF157

00564625

LF155/LF156/LF256/LF257/LF355/LF356/LF357

www.national.com17

L04

Typical Applications (Continued)

High Impedance, Low Drift Instrumentation Amplifier

00564626

• System VOS adjusted via A2 VOS adjust

• Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift

LF15

5/LF

156/

LF25

6/LF

257/

LF35

5/LF

356/

LF35

7

www.national.com 18

L04

Typical Applications (Continued)

Fast Sample and Hold

00564633

• Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible)

• Acquisition time TA, estimated by:

• LF156 develops full Sr output capability for VIN ≥ 1V

• Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop

• Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2

LF155/LF156/LF256/LF257/LF355/LF356/LF357

www.national.com19

L04

Typical Applications (Continued)

High Accuracy Sample and Hold

00564627

• By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1.

No VOS adjust required for A2.

• TA can be estimated by same considerations as previously but, because of the added

propagation delay in the feedback loop (A2) the overshoot is not negligible.

• Overall system slower than fast sample and hold

• R1, CC: additional compensation

• Use LF156 for

j Fast settling time

j Low VOS

High Q Band Pass Filter

00564628

• By adding positive feedback (R2)

• Q increases to 40

• fBP = 100 kHz

• Clean layout recommended

• Response to a 1Vp-p tone burst: 300µs

LF15

5/LF

156/

LF25

6/LF

257/

LF35

5/LF

356/

LF35

7

www.national.com 20

L04

Typical Applications (Continued)

High Q Notch Filter

00564634

• 2R1 = R = 10MΩ2C = C1 = 300pF

• Capacitors should be matched to obtain high Q

• fNOTCH = 120 Hz, notch = −55 dB, Q > 100

• Use LF155 for

j Low IBj Low supply current

LF155/LF156/LF256/LF257/LF355/LF356/LF357

www.national.com21

L04

Physical Dimensions inches (millimeters) unless otherwise noted

Metal Can Package (H)Order Number LF155H, LF156H, LF256H, LF257H, LF356BH, LF356H or LF357H

NS Package Number H08C

Small Outline Package (M)Order Number LF356M or LF356MX

NS Package Number M08A

LF15

5/LF

156/

LF25

6/LF

257/

LF35

5/LF

356/

LF35

7

www.national.com 22

L04

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)Order Number LF356N

NS Package Number N08E

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.

2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.

National SemiconductorCorporationAmericasEmail: support@nsc.com

National SemiconductorEurope

Fax: +49 (0) 180-530 85 86Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208English Tel: +44 (0) 870 24 0 2171Français Tel: +33 (0) 1 41 91 8790

National SemiconductorAsia Pacific CustomerResponse GroupTel: 65-2544466Fax: 65-2504466Email: ap.support@nsc.com

National SemiconductorJapan Ltd.Tel: 81-3-5639-7560Fax: 81-3-5639-7507

www.national.com

LF155/LF156/LF256/LF257/LF355/LF356/LF357JFE

TInputO

perationalAm

plifiers

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

L04

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.

L04

LM741Operational AmplifierGeneral DescriptionThe LM741 series are general purpose operational amplifi-ers which feature improved performance over industry stan-dards like the LM709. They are direct, plug-in replacementsfor the 709C, LM201, MC1439 and 748 in most applications.

The amplifiers offer many features which make their appli-cation nearly foolproof: overload protection on the input and

output, no latch-up when the common mode range is ex-ceeded, as well as freedom from oscillations.

The LM741C is identical to the LM741/LM741A except thatthe LM741C has their performance guaranteed over a 0˚C to+70˚C temperature range, instead of −55˚C to +125˚C.

Features

Connection Diagrams

Metal Can Package Dual-In-Line or S.O. Package

00934102

Note 1: LM741H is available per JM38510/10101

Order Number LM741H, LM741H/883 (Note 1),LM741AH/883 or LM741CH

See NS Package Number H08C

00934103

Order Number LM741J, LM741J/883, LM741CNSee NS Package Number J08A, M08A or N08E

Ceramic Flatpak

00934106

Order Number LM741W/883See NS Package Number W10A

Typical Application

Offset Nulling Circuit

00934107

August 2000LM

741O

perationalAm

plifier

© 2004 National Semiconductor Corporation DS009341 www.national.com

L05

Absolute Maximum Ratings (Note 2)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

(Note 7)

LM741A LM741 LM741C

Supply Voltage ±22V ±22V ±18V

Power Dissipation (Note 3) 500 mW 500 mW 500 mW

Differential Input Voltage ±30V ±30V ±30V

Input Voltage (Note 4) ±15V ±15V ±15V

Output Short Circuit Duration Continuous Continuous Continuous

Operating Temperature Range −55˚C to +125˚C −55˚C to +125˚C 0˚C to +70˚C

Storage Temperature Range −65˚C to +150˚C −65˚C to +150˚C −65˚C to +150˚C

Junction Temperature 150˚C 150˚C 100˚C

Soldering Information

N-Package (10 seconds) 260˚C 260˚C 260˚C

J- or H-Package (10 seconds) 300˚C 300˚C 300˚C

M-Package

Vapor Phase (60 seconds) 215˚C 215˚C 215˚C

Infrared (15 seconds) 215˚C 215˚C 215˚C

See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods ofsoldering

surface mount devices.

ESD Tolerance (Note 8) 400V 400V 400V

Electrical Characteristics (Note 5)

Parameter Conditions LM741A LM741 LM741C Units

Min Typ Max Min Typ Max Min Typ Max

Input Offset Voltage TA = 25˚C

RS ≤ 10 kΩ 1.0 5.0 2.0 6.0 mV

RS ≤ 50Ω 0.8 3.0 mV

TAMIN ≤ TA ≤ TAMAX

RS ≤ 50Ω 4.0 mV

RS ≤ 10 kΩ 6.0 7.5 mV

Average Input Offset 15 µV/˚C

Voltage Drift

Input Offset Voltage TA = 25˚C, VS = ±20V ±10 ±15 ±15 mV

Adjustment Range

Input Offset Current TA = 25˚C 3.0 30 20 200 20 200 nA

TAMIN ≤ TA ≤ TAMAX 70 85 500 300 nA

Average Input Offset 0.5 nA/˚C

Current Drift

Input Bias Current TA = 25˚C 30 80 80 500 80 500 nA

TAMIN ≤ TA ≤ TAMAX 0.210 1.5 0.8 µA

Input Resistance TA = 25˚C, VS = ±20V 1.0 6.0 0.3 2.0 0.3 2.0 MΩTAMIN ≤ TA ≤ TAMAX, 0.5 MΩVS = ±20V

Input Voltage Range TA = 25˚C ±12 ±13 V

TAMIN ≤ TA ≤ TAMAX ±12 ±13 V

LM74

1

www.national.com 2

L05

Electrical Characteristics (Note 5) (Continued)

Parameter Conditions LM741A LM741 LM741C Units

Min Typ Max Min Typ Max Min Typ Max

Large Signal Voltage Gain TA = 25˚C, RL ≥ 2 kΩVS = ±20V, VO = ±15V 50 V/mV

VS = ±15V, VO = ±10V 50 200 20 200 V/mV

TAMIN ≤ TA ≤ TAMAX,

RL ≥ 2 kΩ,

VS = ±20V, VO = ±15V 32 V/mV

VS = ±15V, VO = ±10V 25 15 V/mV

VS = ±5V, VO = ±2V 10 V/mV

Output Voltage Swing VS = ±20V

RL ≥ 10 kΩ ±16 V

RL ≥ 2 kΩ ±15 V

VS = ±15V

RL ≥ 10 kΩ ±12 ±14 ±12 ±14 V

RL ≥ 2 kΩ ±10 ±13 ±10 ±13 V

Output Short Circuit TA = 25˚C 10 25 35 25 25 mA

Current TAMIN ≤ TA ≤ TAMAX 10 40 mA

Common-Mode TAMIN ≤ TA ≤ TAMAX

Rejection Ratio RS ≤ 10 kΩ, VCM = ±12V 70 90 70 90 dB

RS ≤ 50Ω, VCM = ±12V 80 95 dB

Supply Voltage Rejection TAMIN ≤ TA ≤ TAMAX,

Ratio VS = ±20V to VS = ±5V

RS ≤ 50Ω 86 96 dB

RS ≤ 10 kΩ 77 96 77 96 dB

Transient Response TA = 25˚C, Unity Gain

Rise Time 0.25 0.8 0.3 0.3 µs

Overshoot 6.0 20 5 5 %

Bandwidth (Note 6) TA = 25˚C 0.437 1.5 MHz

Slew Rate TA = 25˚C, Unity Gain 0.3 0.7 0.5 0.5 V/µs

Supply Current TA = 25˚C 1.7 2.8 1.7 2.8 mA

Power Consumption TA = 25˚C

VS = ±20V 80 150 mW

VS = ±15V 50 85 50 85 mW

LM741A VS = ±20V

TA = TAMIN 165 mW

TA = TAMAX 135 mW

LM741 VS = ±15V

TA = TAMIN 60 100 mW

TA = TAMAX 45 75 mW

Note 2: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device isfunctional, but do not guarantee specific performance limits.

LM741

www.national.com3

L05

Electrical Characteristics (Note 5) (Continued)Note 3: For operation at elevated temperatures, these devices must be derated based on thermal resistance, and Tj max. (listed under “Absolute MaximumRatings”). Tj = TA + (θjA PD).

Thermal Resistance Cerdip (J) DIP (N) HO8 (H) SO-8 (M)

θjA (Junction to Ambient) 100˚C/W 100˚C/W 170˚C/W 195˚C/W

θjC (Junction to Case) N/A N/A 25˚C/W N/A

Note 4: For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.

Note 5: Unless otherwise specified, these specifications apply for VS = ±15V, −55˚C ≤ TA ≤ +125˚C (LM741/LM741A). For the LM741C/LM741E, thesespecifications are limited to 0˚C ≤ TA ≤ +70˚C.

Note 6: Calculated value from: BW (MHz) = 0.35/Rise Time(µs).

Note 7: For military specifications see RETS741X for LM741 and RETS741AX for LM741A.

Note 8: Human body model, 1.5 kΩ in series with 100 pF.

Schematic Diagram

00934101

LM74

1

www.national.com 4

L05

Physical Dimensions inches (millimeters)unless otherwise noted

Metal Can Package (H)Order Number LM741H, LM741H/883, LM741AH/883, LM741AH-MIL or LM741CH

NS Package Number H08C

LM741

www.national.com5

L05

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Ceramic Dual-In-Line Package (J)Order Number LM741J/883NS Package Number J08A

Dual-In-Line Package (N)Order Number LM741CN

NS Package Number N08E

LM74

1

www.national.com 6

L05

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

10-Lead Ceramic Flatpak (W)Order Number LM741W/883, LM741WG-MPR or LM741WG/883

NS Package Number W10A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reservesthe right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMSWITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTORCORPORATION. As used herein:

1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body, or(b) support or sustain life, and whose failure to perform whenproperly used in accordance with instructions for useprovided in the labeling, can be reasonably expected to resultin a significant injury to the user.

2. A critical component is any component of a life supportdevice or system whose failure to perform can be reasonablyexpected to cause the failure of the life support device orsystem, or to affect its safety or effectiveness.

BANNED SUBSTANCE COMPLIANCE

National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products StewardshipSpecification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘BannedSubstances’’ as defined in CSP-9-111S2.

National SemiconductorAmericas CustomerSupport CenterEmail: new.feedback@nsc.comTel: 1-800-272-9959

National SemiconductorEurope Customer Support Center

Fax: +49 (0) 180-530 85 86Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208English Tel: +44 (0) 870 24 0 2171Français Tel: +33 (0) 1 41 91 8790

National SemiconductorAsia Pacific CustomerSupport CenterEmail: ap.support@nsc.com

National SemiconductorJapan Customer Support CenterFax: 81-3-5639-7507Email: jpn.feedback@nsc.comTel: 81-3-5639-7560

www.national.com

LM741

OperationalA

mplifier

L05

239

DK-RELAYS

MINIATURE POWER RELAY

VDE

1a 1a1b

mm inch

12.5.492

10.394

20.787 15

.591

10.394

20.787

FEATURES

• Large capacity in small size: 10 A 250 V AC (1a)• High sensitivity: 200 mW nominal operating power• High breakdown voltage 4,000 Vrms between contacts and

coil 1,000 Vrms between open contacts Meeting FCC Part 68• Sealed construction• Latching types available

SPECIFICATIONS

Contact

Coil

Remarks

* Specifications will vary with foreign standards certification ratings.*

1

Measurement at same location as "Initial breakdown voltage" section*

2

Detection current: 10 mA*

3

Wave is standard shock voltage of

±

1.2

×

50

µ

s according to JEC-212-1981*

4

Excluding contact bounce time*

5

Half-wave pulse of sine wave: 11ms; detection time: 10

µ

s*

6

Half-wave pulse of sine wave: 6ms*

7

Detection time: 10

µ

s*

8

Refer to 5. Conditions for operation, transport and storage mentioned in AMBIENT ENVIRONMENT (Page 61).

Characteristics

Arrangement 1 Form A2 Form A, 1 Form A 1 Form B

Initial contact resistance, max. (By voltage drop 6 V DC 1A) 30 m

Ω

Contact material Gold flash over silver alloy

Rating (resistive)

Nominal switching capacity

10 A 250 V AC10 A 30 V DC

8 A 250 V AC8 A 30 V DC

Max. switching power 300 W, 2,500 VA 240 W, 2,000 VA

Max. switching voltage

250 V AC, 30 V DC

250 V AC, 30 V DC

Max. switching current 10 A 8 A

Expected life (min. operations)

Mechanical 5

×

10

7

Electrical (resistive)

10

5

(10 A 250 V AC, 10 A 30 V DC)

10

5

(8 A 250 V AC, 8 A 30 V DC)

Nominal operating power 200 mW

Max. operating speed 20 cpm (at rated load)

Initial insulation resistance*

1

Min. 1,000 m

Ω

(at 500 V DC)

Initial breakdown voltage*

2

Between open contacts 1,000 Vrms

Between contacts and coil 4,000 Vrms

Surge voltage between coil and contact*

3

Min. 10,000 V

Operate time*

4

(at nominal voltage) Max. 10 ms (Approx. 5 ms)

Release time (without diode)*

4

(at nominal voltage) Max. 8 ms (Approx. 3 ms)

Temperature rise (at nominal voltage)

Max. 40

°

C with nominal coil voltage and at 10 A switching current

Shock resistance

Functional*

5

Min. 98 m/s

2

10 G

Destructive*

6

Min. 980 m/s

2

100 G

Vibration resistance

Functional*

7

88.2 m/s

2

9 G, 10 to 55 Hz at double amplitude of 1.5 mm

Destructive 176.4 m/s

2

18 G, 10 to 55 Hz at double amplitude of 3.0 mm

Conditions for oper-ation, transport and storange*

8

(Not freezing and condensing at low temperature)

Ambient temp.

–40

°

C to +65

°

C–40

°

F to +149

°

F

Humidity 5 to 85% R.H.

Unit weight

1 Form A Approx. 5.6 g .20 oz

1 Form A 1 Form B, 2 Form A Approx. 6 g .21 oz

TYPICAL APPLICATIONS

• Switching power supply• Power switching for various

OA equipment• Control or driving relays for industrial

machines (robotics, numerical control machines, etc.)

• Output relays for programmable logic controllers, temperature controllers, timers and so on.

• Home appliances

ORDERING INFORMATION

Ex. DK

Note: Standard packing Carton: 50 pcs.; Case: 500 pcs.UL/CSA, TÜV approved type is standard.

1a L2 12V

Contact arrangement

1a: 1 Form A2a: 2 Form A1a1b: 1 Form A 1 Form B

Nil: Single side stableL2: 2 coil latching

3, 5, 6, 9, 12, 24V

Operating function Coil voltage

L03

DK

240

TYPES AND COIL DATA (at 20

°

C 68

°

F)

Single side stable

2 coil latching

Part No.Nominal voltage, V DC

Pick-up voltage,

V DC (max.)

Drop-out voltage,

V DC (min.)

Nominal operating current,

mA (

±

10%)

Coil resistance,

Ω

(

±

10%)

Nominal operating

power, mW

Maximum allowable voltage,

V DC (at 65

°

C 149°F)

1 Form A

DK1a-3V 3 2.1 0.3 66.6 45 200 3.9

DK1a-5V 5 3.5 0.5 40 125 200 6.5

DK1a-6V 6 4.2 0.6 33.3 180 200 7.8

DK1a-9V 9 6.3 0.9 22.2 405 200 11.7

DK1a-12V 12 8.4 1.2 16.6 720 200 15.6

DK1a-24V 24 16.8 2.4 8.3 2,880 200 31.2

1 Form A1 Form B

DK1a1b-3V 3 2.1 0.3 66.6 45 200 3.9

DK1a1b-5V 5 3.5 0.5 40 125 200 6.5

DK1a1b-6V 6 4.2 0.6 33.3 180 200 7.8

DK1a1b-9V 9 6.3 0.9 22.2 405 200 11.7

DK1a1b-12V 12 8.4 1.2 16.6 720 200 15.6

DK1a1b-24V 24 16.8 2.4 8.3 2,880 200 31.2

2 Form A

DK2a-3V 3 2.1 0.3 66.6 45 200 3.9

DK2a-5V 5 3.5 0.5 40 125 200 6.5

DK2a-6V 6 4.2 0.6 33.3 180 200 7.8

DK2a-9V 9 6.3 0.9 22.2 405 200 11.7

DK2a-12V 12 8.4 1.2 16.6 720 200 15.6

DK2a-24V 24 16.8 2.4 8.3 2,880 200 31.2

Part No.Nominal voltage, V DC

Set voltage, V DC (max.)

Reset voltage, V DC (max.)

Nominal operating current,

mA (

±

10%)

Coil resistance,

Ω

(

±

10%)

Nominal operating

power, mW

Maximum allowable voltage,

V DC (at 65

°

C 149°F)Set Reset Set Reset Set Reset

1 Form A

DK1a-L2-3V 3 2.1 2.1 66.6 66.6 45 45 200 200 3.9

DK1a-L2-5V 5 3.5 3.5 40 40 125 125 200 200 6.5

DK1a-L2-6V 6 4.2 4.2 33.3 33.3 180 180 200 200 7.8

DK1a-L2-9V 9 6.3 6.3 22.2 22.2 405 405 200 200 11.7

DK1a-L2-12V 12 8.4 8.4 16.6 16.6 720 720 200 200 15.6

DK1a-L2-24V 24 16.8 16.8 8.3 8.3 2,880 2,880 200 200 31.2

1 Form A1 Form B

DK1a1b-L2-3V 3 2.1 2.1 66.6 66.6 45 45 200 200 3.9

DK1a1b-L2-5V 5 3.5 3.5 40 40 125 125 200 200 6.5

DK1a1b-L2-6V 6 4.2 4.2 33.3 33.3 180 180 200 200 7.8

DK1a1b-L2-9V 9 6.3 6.3 22.2 22.2 405 405 200 200 11.7

DK1a1b-L2-12V 12 8.4 8.4 16.6 16.6 720 720 200 200 15.6

DK1a1b-L2-24V 24 16.8 16.8 8.3 8.3 2,880 2,880 200 200 31.2

2 Form A

DK2a-L2-3V 3 2.1 2.1 66.6 66.6 45 45 200 200 3.9

DK2a-L2-5V 5 3.5 3.5 40 40 125 125 200 200 6.5

DK2a-L2-6V 6 4.2 4.2 33.3 33.3 180 180 200 200 7.8

DK2a-L2-9V 9 6.3 6.3 22.2 22.2 405 405 200 200 11.7

DK2a-L2-12V 12 8.4 8.4 16.6 16.6 720 720 200 200 15.6

DK2a-L2-24V 24 16.8 16.8 8.3 8.3 2,880 2,880 200 200 31.2

L03

DK

241

REFERENCE DATA

1. 1 Form A type

1. Maximum operating power 2. Life curve 3. Operate/Release time

Sample: DK1a-24V, 5 pcs.

AC resistive load

DC resistive load

DC inductive load (L/R = 7 ms)

AC inductive load (cosϕ = 0.4)

Contact voltage, V

Con

tact

cur

rent

, A

10 100 1,0000.1

1

10

100

0 1 2 3 4 5 6 7 8 9 10

10

100

1,000

1

Life

, ×10

4

Contact voltage, V

250 V AC resistive load30 V DC resistive load

250 V AC inductive load (cosϕ = 0.4)30 V DC inductive load (L/R = 7 ms)

80 90 10 110 120 130 1400

1

2

3

4

5

6

7

8

9

Coil applied voltage,%V

Ope

rate

/rel

ease

tim

e, m

s

Release time(with diode)

Operate time

Release time

x

xMax.

Min.

Max.

Max.

Min.

Min.

x

4. Coil temperature rise (at 30

°

C 68

°

F)

Sample: DK1a-12V, 5 pcs.

5. Ambient temperature characteristics

Sample: DK1a-24V, 6 pcsAmbient temperature: -40

°

C to +80

°

C –40

°

F to +176

°

F

6. Operate/Release time (at 20

°

C 68

°

F)

Sample: DK1a-24V (50 pcs.)

7 A5 A

10 A

0 A

80 90 100 110 120 1300

10

20

30

40

50

Coi

l tem

pera

ture

ris

e, °

C

Coil applied voltage,%V

10020

130

120

110

90

80

70

40 60 800–20–40Ambienttemperature,°C

Var

iatio

n ra

tio, %

Drop-outvoltage

Pick-upvoltage

0

10

20

30

Operate/release time, msD

istr

ibut

ion

freq

uenc

y

1 2 3 4 5 6

Operate timeRelease time

7. Contact resistance (at 20

°

C 68

°

F)

Sample: DK1a-24V (50 pcs.)

1.52.0

2.53.0

3.54.0

4.55.0

02468

101214161820222426

Contact resistance, mΩ

Dis

trib

utio

n fr

eque

ncy

2. 1 Form A 1 Form B type, 2 Form A type

1. Maximum operating power 2. Life curve 3. Operate/Release time (at 20

°

C 68

°

F)

Sample: DK1a1b-12V, 5 pcs.

Contact voltage, V

Con

tact

cur

rent

, A AC resistive load

DC inductive load (L/R = 7 ms) DC resistive

load

AC inductive load (cosϕ = 0.4)

0.1

1

5

10

10 100 1,000 0 1 2 3 4 5 6 7 8 9 10

10

100

1,000

1

Life

, ×10

4

Contact current, A

250 V AC resistive load30 V DC resistive load

250 V AC inductive load (cosϕ = 0.4)30 V DC inductive load (L/R = 7 ms)

80 90 10 110 120 130 1400

1

2

3

4

5

6

7

8

9

Coil applied voltage,%V

Ope

rate

/rel

ease

tim

e, m

s

Min.

Max.x

Max.

Max.

Min.

Min.

Release time(with diode)

Operate time

Release time

x

x

L03

DK

242

4. Coil temperature rise

Sample: DK1a1b-12V, 5 pcs.Ambient temperature: 20

°

C 68

°

F

5. Ambient temperature characteristics

80 90 100 110 120 1300

10

20

30

40

50

Coi

l tem

pera

ture

ris

e, °

C

Coil applied voltage,%V

8 A5 A0 A

100

20 Ambienttemperature,°C

Var

iatio

n ra

tio, % Pick-up

voltage

Drop-outvoltage

130

120

110

90

80

70

40 60 800–20–40

DIMENSIONS

1. 1 Form A type

mm inch

Single side stable type

2 coil latching type

General tolerance:

±

0.3

±

.012

20.787

12.5.492

7.62.300

10.16.400

0.8.031

0.4.016

0.4.016

3.5.138

1.2.047

0.8.031

1.11.044

9.7.382

0.3.012

10.16.400

20.787

12.5.492

7.62.300

7.62.300

2.54.100

0.8.031

0.4.016

0.4.016

0.4.016

3.5.138

1.2.047

0.8.031

1.11.044

9.7.382

0.3.012

10.16.400

PC board pattern (Copper-side view)

10.16.400

7.62.300

2.54.100

7.62.300

1.1 dia..043 dia.

10.16.400

7.62.300

2.54.100

7.62.300

1.1 dia..043 dia.

The above shows 2 coil latching type. No.5 terminal is eliminated on single side stable type.

Tolerance:

±

0.1

±

.004

Schematic (Bottom view)

Single side stable (Deenergized condition)

2 coil latching (Reset condition)

1 3 4

6

-

+

1 3 4

6 5

-

+ +

Since this is a polarized relay, the connection to the coil should be done according to the above schematic.

2. 1 Form A 1 Form B type, 2 Form A type

Single side stable type

2 coil latching type

Note:

Relay out-line and PC board pattern are common for both 1 Form A 1 Form B type and 2 Form A type.

General tolerance:

±

0.3

±

.012

20.787

15.591

7.62.300

10.16.400

0.8.031

0.4.016

0.4.0162.42

.095

3.5.1380.8

.031

1.11.044

9.7.382

0.3.012

10.16.400

15.591

0.4.0162.42

.095

3.5.138

10.16.400

20.787

7.62.300

7.62.300

2.54.100

0.8.031

0.4.016

0.6.024

0.8.031

1.11.044

9.7.382

0.3.012

PC board pattern (Copper-side view)

Tolerance:

±

0.1

±

.004

10.16.400

10.16.400

7.62.300

1.1 dia..043 dia.

10.16.400

7.62.300

7.62.300

2.54.100

1.1 dia..043 dia.

Schematic (Bottom view)<1 Form A 1 Form B type>

Single side stable (Deenergized condition)

2 coil latching (Reset condition)

1 3 4

8 6 5

-

+

1 3 4

8 6 5

-

+

7

+

<2 Form A>

Single side stable (Deenergized condition)

2 coil latching (Reset condition)

1 3 4

8 6 5

-

+

1 3 4

8 6 5

-

+

7

+

Since this is a polarized relay, the connection to the coil should be done according to the above schematic.

L03

DK

243

DK relay socket TYPES AND RELAY COMPATIBILITYSocket 1 Form A 1 Form A 1 Form B, 2 Form A

RelaySingle side stable type

2 coil latching type

Single side stable type

2 coil latching type

1 Form ASingle side stable type DK1a-PS DK1a-PSL2 — —

2 coil latching type — DK1a-PSL2 — —

1 Form A 1 Form B2 Form A

Single side stable type — — DK2a-PS DK2a-PSL2

2 coil latching type — — — DK2a-PSL2

SPECIFICATIONS

Remarks*1 Detection current: 10 mA

Breakdown voltage*1 4,000 Vrms (Except the portion between coil terminals)

Insulation resistance Min. 1,000 mΩ (at 500 V DC)

Heat resistance 150°C (for 1 hour)

Max. continuous current 10 A (DK1a-PS, DK1a-PSL2), 8 A (DK2a-PS, DK2a-PSL2)

DIMENSIONS

23±0.6.906±.024

15±0.6.591±.024

1 Form A type

23±0.6.906±.024

15±0.6.591±.024

1 Form A 1 Form B type, 2 Form A type

0.8.031

13.7±0.6.539±.024

6±0.3.236±.012

3.4±0.3.134±.012

17±0.6.669±.024

0.25.010

0.3±0.1.012±.0042.54±0.1.100±.004 7.62±0.3

.300±.0127.62±0.3.300±.012

13.7±0.6.539±.024

3.4±0.3.134±.012

17±0.6.669±.024

0.3±0.1.012±.004

10.16±0.3.400±.012

7.62±0.3.300±.012

10.16±0.3.400±.012

10.16±0.3.400±.012

6±0.3.236±.012

General tolerance: ±0.3 ±.012

mm inch

PC board pattern (Copper-side view)1 Form A

1 Form A 1 Form B

The above shows 2 coil latching type. No.2 and 5 terminal are eliminated on single side stable type.

2.54.100

2.54.100

1.2 dia..047 dia.1 2

6 5

43

2.54.100

2.54.100

1 2

6 58 7

431.2 dia.

.047 dia.

Tolerance: ±0.1 ±.004

FIXING AND REMOVAL METHOD1. Match the direction of relay and socket.

2. Both ends of the relay are to be secured firmly so that the socket hooks on the top sur-face of the relay.

3. Remove the relay, applying force in the direction shown below.

4. In case there is not enough space to grasp relay with fin-gers, use screwdrivers in the way shown below.

GOOD NO GOOD

NOTES1. Phase synchronization of AC-load switchingIn case of switching the contact synchro-nized with phase of load voltage, the life of contact might be shorter or contact failure might be caused. Please confirm this matter in the actual system in this case. If necessary, the phase control would be recommended.

Vin

Vin

Loadvoltage

Loadvoltage

RyLoad 2. Soldering should be done under the fol-

lowing conditions:250°C 482°F within 10s300°C 572°F within 5s350°C 662°F within 3s

For Cautions for Use, see Relay Technical Information (Page 48 to 76).9/1/2000 All Rights Reserved, © Copyright Matsushita Electric Works, Ltd.

Go To Online Catalog

L03