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Pass Transistor Logic • We want to transfer a logic 1 using the circuit below. • Assume V in = V DD , V g makes a transition from 0V to V DD and at t=0 V x = 0V. • Pass transistor starts to conduct when the clock V g makes the transition. • The pass transistor T p operates in saturation since V gs = V ds and V ds >V gs -V tn • Pass transistor operating in saturation region starts to charge up capacitor C x . • Using the equation for the pass transistor in saturation we have that the change in voltage at node x with respect to time is given by: • The threshold voltage is subject to substrate bias effect and thus depends on the voltage level V x . • We can simplify the analysis by neglecting the V sb factor. V in V x C x V g 2 2 tn x DD x x V V V dt dV C n

Pass Transistor Logic

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We want to transfer a logic 1 using the circuit below. Assume V in = V DD , V g makes a transition from 0V to V DD and at t=0 V x = 0V. Pass transistor starts to conduct when the clock V g makes the transition. - PowerPoint PPT Presentation

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Page 1: Pass Transistor Logic

Pass Transistor Logic

• We want to transfer a logic 1 using the circuit below.

• Assume Vin = VDD, Vg makes a transition from 0V to VDD and at t=0 Vx = 0V.

• Pass transistor starts to conduct when the clock Vg makes the transition.

• The pass transistor Tp operates in saturation since Vgs = Vds and Vds>Vgs-Vtn

• Pass transistor operating in saturation region starts to charge up capacitor Cx.

• Using the equation for the pass transistor in saturation we have that the change in voltage at node x with respect to time is given by:

• The threshold voltage is subject to substrate bias effect and thus depends on the voltage level Vx.

• We can simplify the analysis by neglecting the Vsb factor.

Vin Vx

Cx

Vg

2

2 tnxDDx

x VVVdt

dVC n

Page 2: Pass Transistor Logic

Pass Transistor Logic

• If we integrate the expression describing Cx we can solve for Vx.

t

C

VV

tC

VV

VVtV

tV

VVVVV

Ct

VVV

C

VVV

dVCdt

x

tnDD

x

tnDD

tnDDx

x

tnDDtnxDD

x

V V

tnxDD

x

tnxDD

xxt x

x

21

2)(

:get to)( solvecan wefor time expression above theFrom

112

|122

0 020

Page 3: Pass Transistor Logic

Pass Transistor Logic

• The variation of the node voltage Vx as a function of time shows that if the voltage at node x cannot exceed a maximum of

• The above expression assumes that VSB is at logic 0. What would be the expression assuming a changing VSB since the source/drain voltage changes?

• The pass transistor turns off when Vx=Vmax since at this point the gate-to-source voltage is equal to the transistor’s threshold voltage. We need VGS>Vtn for ON.

• There are several possible states the terminals could be in: VG=0=Vin=Vx, VG=VDD with Vin =Vx=0, VG=VDD=Vin, with Vx=0 etc.

t

tnDDtx VVVV |max

Vin

VG

Vx

Page 4: Pass Transistor Logic

Pass Transistor Logic

• The nMOS device therefore passes good 0s and poor 1s since the source cannot be pulled to a value above VDD-Vtn (the threshold drop).

• When the source voltage rises VSB is not equal to zero any more an body effects occur.

• The threshold drop tends to violate noise margins.

• The pMOS device passes good 1s and poor 0s.

• Vx of the pMOS drops to below |Vtp| and the transistor cuts off.

• pMOS devices thus pull down to only |Vtp| above ground (GND).

• Why isn’t, Vmax4 VDD-Vtn1-Vtn2-Vtn3-Vtn4?

• What would happen if we configured the series devices above to have each drain/source drive the next device’s gate?

VDD

VDD

V1 V2 V3

Vmax3=VDD-Vtn4


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