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Overview
Why VLSI? Moore’s Law. Why FPGAs? Circuit Component The system design process
Why VLSI?
Integration improves the design– lower parasitics = higher speed– lower power– physically smaller
Integration reduces– Manufacturing cost-(almost)– No manual assembly.
VLSI and you
Microprocessors– personal computers– Microcontrollers
DRAM/SRAM/flash. Audio/video and other consumer systems Telecommunications.
Moore’s Law
Gordon Moore– co-founder of Intel.
Predicted that– Number of transistors per chip would grow
exponentially– (double every 18 months)
Exponential improvement in technology is a natural trend– Example : steam engines, dynamos(電動機 ),
automobiles.
Moore’s Law plot
The cost of fabrication
Current cost– $2-3 billion.
Typical fab line– Occupies about 1 city block– Employs a few hundred people
New fabrication processes– Require 6-8 month turnaround
Cost factors in ICs
For large-volume ICs– packaging is largest cost– testing is second-largest cost
For low-volume ICs– design costs may swamp all manufacturing
costs– $10 million-$20 million
Mask cost vs. line width
0100,000200,000300,000400,000500,000600,000700,000800,000900,000
1,000,000
.25 micron .18 micron .13 micron .09 micron
mask cost ($)
Field-programmable gate arrays
FPGAs are programmable logic devices– Logic elements + interconnect.– Provide multi-level logic.
LE
LE
LE
Interconnectnetwork
LE
LE
LE
FPGA design
FPGA manufacturer– Creates an FPGA fabric
System designer– Uses the fabric
FPGA fabric design issues– Study sample user designs– Select interconnect topology– Create logic element structures– Design circuits, layout
FPGAs and VLSI
FPGAs are standard parts– Pre-manufactured– Don’t worry (much) about physical design
VLSI (Custom silicon)– Tailored to your application– Generally lower power consumption and higher
speed
FPGA vs. VLSI
FPGA Pros– Have shorter design cycle– Have no manufacturing delay– Reduce inventory
FPGA Cons– Slower– Larger– More power-hungry.
Circuit Component
Using Component– Hierarchical name
– Instantiating
Representation– Net lists
– Layout
– Stick diagram
– Transistor schematic
– Mixed schematic
Hierarchical name
Interior view of a component– Components and wires that make it up
Exterior view of a component– type– body– pins Full
addera
bcin
sum
cout
Component hierarchy
top
i1 xxx i2
Hierarchical names
Typical hierarchical name:– top/i1.foo
component pin
Instantiating component types
Each instance has its own name– add1 (type full adder)– add2 (type full adder)
Each instance is a separate copy of the type:
Add1(Fulladder)
a
bcin
sum
cout
Add2(Fulladder)
a
bcin
sumAdd1.a Add2.a
Net lists and component lists
Net list:net1: top.in1 in1.in
net2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out
Component listtop: in1=net1 n1=topin1
n2=topin2 n3=topine out=outnet
i1: in=net1 out=net2
xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3
i2: in=net3 out=outnet
Layout and its abstractions
Layout for dynamic latch:
Stick diagram
Transistor schematic
Mixed schematic
inverter
System design
Dealing with complexity Top-down vs. bottom-up design Levels of abstraction
The system design process
May be part of larger product design. Major levels of abstraction
– specification;– architecture;– logic design;– circuit design;– layout.
FPGA-based system design
Dealing with complexity
Divide-and-conquer– Limit the number of components you deal with at
any one time. Group several components into larger
components– transistors form gates– gates form functional units– functional units form processing elements– etc.
Top-down vs. bottom-up design
Top-down design– Adds functional detail.– Create lower levels of abstraction from upper
levels. Bottom-up design
– creates abstractions from low-level behavior. Good design
– Needs both top-down and bottom-up efforts
Design abstractions
specification
behavior
register-transfer
logic
circuit
layout
English
Executableprogram
Sequentialmachines
Logic gates
transistors
rectangles
Throughput,design time
Function units,clock cycles
Literals, logic depth
nanoseconds
microns
function cost
Levels of abstraction
Specification– function, cost, etc
Architecture– large blocks
Logic– gates + registers
Circuits– transistor sizes for speed, power
Layout– determines parasitics
Circuit abstraction
Continuous voltages and time
Logic (Digital) abstraction
Discrete levels, discrete time
Register-transfer abstraction
Abstract components, abstract data types:
+
+
0010
0001
0100
0011
Layout Abstraction
Why do we care about layout?– Layout determines
» Logic delay
» Interconnect delay
» Energy consumption
– For FPGA » We want to understand
• FPGA characteristics