Moore’s Law in Microprocessors

Moore’s Law in Microprocessors

1000

P610

100(M

T)

2X growth in 1.96 years!

286386

486Pentium® proc

P6

0 1

1

nsi

sto

rs

80088080

8085 8086286

0.01

0.1

Tran

40048008

0.001

1970 1980 1990 2000 2010YCourtesy Intel YearCourtesy, Intel

Transistors on Lead Microprocessors double every 2 years

Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens

Productivity Trendsy

10,000,000 100,000,00010,000(M)

100,000

100,000

1,000,000

1,000,000

10,000,000Logic Tr./ChipTr./Staff Month.

1,000

100

r p

er C

hip

1,000

10,000

ty f -M

o.

xity

1,000

10,000

10,000

100,00058%/Yr. compoundedComplexity growth rate

10

1

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nsi

sto

r

10

100

Pro

du

ctiv

itTr

ans.

/Sta

ff

Co

mp

lex

10

100

100

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21%/Yr. compoundProductivity growth rate

x0.1

0.01

0 001

Lo

gic

0 01

0.1

1

P(K

) T

1

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

100.001 0.01

S S t hCourtesy ITRS Roadmap Source: Sematech

Complexity outpaces design productivity

Courtesy, ITRS Roadmap


Abstraction Drives Design Productivityg y

SimulationSource Implementation

Algorithmic C++Algorithmic C++Algorithmic C++Algorithmic C++ 10,000x (1 min) 20x (2 days!!)Functional

Untimed TLM SystemCUntimed TLM SystemCUntimed TLM SystemCUntimed TLM SystemC 1,000xStructural

Timed TLM SystemCTimed TLM SystemCTimed TLM SystemCTimed TLM SystemC 100xTransaction

Cycle Accurate SystemCCycle Accurate SystemCCycle Accurate SystemCCycle Accurate SystemC 10x 2x (2 weeks)Cycle

RTLRTLRTLRTL 1x (7 days) 1x (5 weeks)RTL


Design Languages & Tasksg g g

R i tR i t Text / UMLText / UMLRequirementsRequirements

AlgorithmAlgorithmExplorationExploration

Text / UMLText / UML

ExplorationExploration

Architecture Architecture AnalysisAnalysis TransactionTransaction

LevelLevel

C/C++C/C++UntimedUntimedSystemCSystemC

VerificationVerification

LevelLevelSystemCSystemCBlueSpecBlueSpec

BlueSpecBlueSpecSystemSystem

RTL D iRTL D i

VHDLVHDLVerilogVerilog

AssertionsAssertionsPSL/SVAPSL/SVA

SystemSystemVerilogVerilog

LanguageLanguageTaskTask

RTL DesignRTL Design


LanguageLanguageTaskTask

Gajski’s & Khun’s Y-chartj


VHDL

VHDL is a language for describing digital hardware used by industry worldwide

–VHDL is an acronym for VHSIC (Very High Speed y ( y g p

Integrated Circuit) Hardware Description Language


Advantages of VHDLg

Technology/vendor independent

P t bl Portable

Reusable Reusable


Genesis of VHDL

State of art circa 1980

– Multiple design entry methods and h d d i ti l i

State of art circa 1980

hardware description languages in use– No or limited portability of designs b t CAD t l f diff t dbetween CAD tools from different vendors

– Objective: shortening the time from a design concept to implementation fromconcept to implementation from18 months to 6 months


History of VHDLy

June 1981: Woods Hole WorkshopJune 1981: Woods Hole Workshop July 1983: contract awarded to develop VHDL

Intermetrics– Intermetrics– IBM

T I t t– Texas Instruments

August 1985: VHDL Version 7.2 released December 1987:

VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard


VHDL Standards

P1076 Standard VHDL Language Reference Manual (VASG)

VHDL 87 VHDL 93 VHDL 01 VHDL 08VHDL-87, VHDL-93, VHDL-01, VHDL-08 P1076.1 Standard VHDL Analog and Mixed-Signal

Extensions (VHDL AMS)Extensions (VHDL-AMS) P1076.1.1 Standard VHDL Analog and Mixed-Signal

Extensions - Packages for Multiple Energy DomainExtensions - Packages for Multiple Energy Domain Support (StdPkgs) - this group is now part of 1076.1

P1076.2 IEEE Standard VHDL Mathematical PackagesP1076.2 IEEE Standard VHDL Mathematical Packages (math)


VHDL Standards

P1076.3 Standard VHDL Synthesis Packages (vhdlsynth)P1076 4 St d d VITAL ASIC (A li ti S ifi P1076.4 Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification (VITAL) - This group is now part of 1076group is now part of 1076.

P1164 Standard Multivalue Logic System for VHDL Model Interoperability (Std logic 1164) (vhdl-std-logic) ode e ope ab y (S d_ og c_ 6 ) ( d s d og c)


VHDL vs Verilogg

Government Commercially Developed Developed

Ada based C basedAda based C based

St l T C t Mildl T C tStrongly Type Cast Mildly Type Cast

Difficult to learn Easier to Learn

More Powerful Less Powerful


VHDL Subsets

VHDL for Specification

VHDL for Simulation

VHDL for SynthesisVHDL for Synthesis


Design Flowg

SpecificationDesign and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..

VHDL description

Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity RC5_core isport(

clock, reset, encr_decr: in std_logic;d t i t i td l i t (31 d t 0)

Functional simulationdata_input: in std_logic_vector(31 downto 0);data_output: out std_logic_vector(31 downto 0);out_full: in std_logic;key_input: in std_logic_vector(31 downto 0);key_read: out std_logic;

);end AES_core;

Synthesis Post-synthesis simulationSynthesis


Design Flowg

Implementation(M i Pl i & R i )(Mapping, Placing & Routing)

Timing simulation

Configuration

On chip testingOn chip testing


EDA Tools

ModelSim – www.model.com, www.mentor.com

ModelSim Xilinx Edition – www.xilinx.com

Leonardo Spectrum – www.mentor.com

Xilinx ISE – www.xilinx.com


Translating Code into Circuitsg

VHDL description Circuit netlistarchitecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;signal B1:STD LOGIC;

C cu t et st

signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

beginA1<=A when (NEG_A='0') else

not A;B1<=B when (NEG_B='0') else

not B;Y<=Y1 when (NEG_Y='0') else

not Y1;

MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;

with (L1 & L0) selectwith (L1 & L0) selectY1<=MUX_0 when "00",

MUX_1 when "01",MUX_2 when "10",MUX_3 when others;


end MLU_DATAFLOW;

VHDL Design Stylesg y

VHDL DesignVHDL Design Styles

structuraldataflow behavioral

Components andi t t

structuraldataflow

Concurrent

behavioral

Sequential statementsinterconnectsstatements • Registers

• State machines• Test benchesTest benches

Subset most suitable for synthesisMicroprocessors & Digital Systems Laboratory

© 2009 National Technical University of Athens

Subset most suitable for synthesis

Dataflow Description

Describes how data moves through the system and the various processing steps. D t Fl i f t t t t t Data Flow uses series of concurrent statements to realize logic. Concurrent statements are evaluated at the same time; thus order of these statements doesn’tsame time; thus, order of these statements doesn t matter.

Data Flow is most useful style when series of Boolean a a o s os use u s y e e se es o oo eaequations can represent a logic.

Data Flow describes best combinational logic. g


Structural Description

Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functionssimple building blocks to compose logic functions.

Components are interconnected in a hierarchical mannermanner.

Structural descriptions may connect simple gates or complex, abstract components.co p e , abs ac co po e s

Structural style is useful when expressing a design that is naturally composed of sub-blocks.y p


Behavioral Description

It accurately models what happens on the inputs and outputs of the black box (no matter what is inside and how it works)how it works).

This style uses PROCESS and sequential statements to realize logic which are executed one after the other likerealize logic, which are executed one after the other, like in most programming languages.

Behavioral descriptions describe best sequential logic.e a o a desc p o s desc be bes seque a og c


Naming and Labelingg g

VHDL is not case sensitiveExample:

Names or labelsdatabus

Databus

DataBus

DATABUS

are all equivalent


Naming and Labelingg g

General rules of thumb (according to VHDL-( g87)

1 All names should start with an alphabet character (a-z1. All names should start with an alphabet character (a z or A-Z)

2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)

3. Do not use any punctuation or reserved characters within a name (! ? & + etc )within a name (!, ?, ., &, +, -, etc.)

4. Do not use two or more consecutive underscore characters ( ) within a name (e.g., Sel A is invalid)characters (__) within a name (e.g., Sel__A is invalid)

5. All names and labels in a given entity and architecture must be unique


Free Format

VHDL is a “free format” languageVHDL is a free format languageNo formatting conventions, such as spacing or

indentation imposed by VHDL compilers Spaceindentation imposed by VHDL compilers. Space and carriage return treated the same way.Example:Example:

if (a=b) then

orif (a=b) then

orif (if (a =

b) then

are all equivalent


q

Comments

Comments in VHDL are indicated with a “double dash”, i.e., “--”

Comment indicator can be placed anywhere in the liline

Any text that follows in the same line is treated asa commenta comment Carriage return terminates a comment No method for commenting a block extending over No method for commenting a block extending over

a couple of linesExamples:p-- main subcircuitData_in <= Data_bus; -- reading data from the input FIFO


Design Entityg y

design entity

Design Entity most basicentity declaration Design Entity - most basic building block of a design.

entity declaration

One entity can have architecture 1

many different architectures.architecture 2

architecture 3


Entity Declarationy

Entity Declaration describes the interface of th t i i t d t t tthe component, i.e. input and output ports.

Entity name Port names Port typeSemicolon

ENTITY nand_gate ISPORT(

a : IN STD_LOGIC;b : IN STD LOGIC; No Semicolonb : IN STD_LOGIC;z : OUT STD_LOGIC

);END nand_gate;

No Semicolon

Reserved words Port modes (data flow directions)


Entity Declaration - Syntaxy y

ENTITY entity name ISENTITY entity_name ISPORT (

port_name : signal_mode signal_type;port_name : signal_mode signal_type;………….

t i l d i l t )port_name : signal_mode signal_type);END entity_name;


Architecture

Describes an implementation of a design entity. esc bes a p e e tat o o a des g e t ty Architecture example:

ARCHITECTURE model OF nand gate ISARCHITECTURE model OF nand_gate ISBEGIN

z <= a NAND b;z <= a NAND b;END model;


Architecture - Syntaxy

ARCHITECTURE architecture name OF entity name ISARCHITECTURE architecture_name OF entity_name IS[ declarations ]

BEGINBEGINcode

END architecture_name;


Entity Declaration & Architecturey

nand_gate.vhd

LIBRARY ieee;USE ieee.std_logic_1164.all;


a : IN STD_LOGIC;b : IN STD_LOGIC;_z : OUT STD_LOGIC);

END nand_gate;

ARCHITECTURE model OF nand_gate ISBEGIN

z <= a NAND b;END model;


Port Mode In

EntityPort signal

a

Driver residesoutside the entity


Port Mode Out

Entityy

Port signal

z

Can’t read out within an entityc

Driver resides

y

<inside the entity

c <= z


Port Mode Out with Signalg

Entity

Port signal

y

x z

cSignal X can beread inside the entity

Driver resides z <= x

y

inside the entity c <= x


Port Mode Inout

EntityyPort signal

Signal can bea

gread inside the entity

Driver may resideboth inside and outside

f th titMicroprocessors & Digital Systems Laboratory


of the entity

Port Mode Buffer

Entityy

Port signal

z

Port signal Z can beread inside the entityc

Driver resides

y

c <= zinside the entity

c


Port Modes

The Port Mode of the interface describes the direction in which data travels with respect to the component

– In: Data comes in this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment.

– Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signalcannot be read. It can only appear on the left side of a signal assignment.

Inout: The value of a bi directional port can be read and updated within– Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.

B ff U d f i l th t i t t f tit Th l f– Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides

f th < t


of the <= operator

Library Declarationy

Use all definitions from the packagestd logic 1164

Library declarationstd_logic_1164

LIBRARY ieee;;USE ieee.std_logic_1164.all;


a : IN STD_LOGIC;b : IN STD_LOGIC;z : OUT STD_LOGIC);

END nand_gate;


z <= a NAND b;END model;END model;


Library Declaration - Syntaxy y

LIBRARY library_name;USE lib k k tUSE library_name.package_name.package_parts;


Parts of a Libraryy

LIBRARYLIBRARY

PACKAGE 1 PACKAGE 2

TYPES TYPESCONSTANTSFUNCTIONS

PROCEDURES

CONSTANTSFUNCTIONS

PROCEDURESPROCEDURESCOMPONENTS

PROCEDURESCOMPONENTS


ECE 545 Introduction to VHDL

Common Libraries

ieeeNeed to be explicitlydeclared

Specifies multi-level logic system,including STD_LOGIC, and STD LOGIC VECTOR d t tSTD_LOGIC_VECTOR data types.

stdSpecifies pre-defined data types(BIT, BOOLEAN, INTEGER, REAL, SIGNED UNSIGNED etc ) arithmetic

std

Visible by defaultSIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc.

C t d i ft il ti

work


Current designs after compilation.

STD_LOGIC



a : IN STD_LOGIC;b : IN STD_LOGIC;z : OUT STD_LOGIC);

END d tEND nand_gate;


z <= a NAND b;z <= a NAND b;END model;

What is STD_LOGIC you ask?


STD_LOGIC Typey

Value MeaningValue Meaning

‘X’ Forcing (Strong driven) Unknown

‘0’ Forcing (Strong driven) 00 Forcing (Strong driven) 0

‘1’ Forcing (Strong driven) 1

‘Z’ High Impedance

‘W’ Weak (Weakly driven) Unknown

‘L’Weak (Weakly driven) 0.Models a pull down.

‘H’Weak (Weakly driven) 1. Models a p ll pModels a pull up.

‘-’ Don't Care


STD_LOGIC Meaningg

‘1’1‘X’

X

‘0’

Contention on the bus


STD_LOGIC Meaningg


STD_LOGIC Meaningg

VDDVDD

VDD

‘H’‘1’

‘0’

‘1’

‘L’


STD_LOGIC Meaningg

‘ ’‘-’

•Do not care.•Can be assigned to outputs for the case of invalid inputs(may produce significant improvement ininputs(may produce significant improvement in resource utilization after synthesis).•Use with caution‘1’ = ‘-’ give FALSEg


Resolving Logic Levelsg g

X 0 1 Z W L H -X 0 1 Z W L H

X X X X X X X X X0 X 0 X 0 0 0 0 X1 X X 1 1 1 1 1 XZ X 0 1 Z W L H XZ X 0 1 Z W L H XW X 0 1 W W W W XL X 0 1 L W L W XL X 0 1 L W L W XH X 0 1 H W W H X- X X X X X X X X


Wires and Buses

SIGNAL a : STD_LOGIC;_

a

wire

a

1

SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);

b

bus8


Standard Logic Vectorsg

SIGNAL a: STD_LOGIC;_ ;SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL d: STD LOGIC VECTOR(7 DOWNTO 0);SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);SIGNAL f: STD LOGIC VECTOR(8 DOWNTO 0);_ _ ( );

……….a <= ‘1’;b < ”0000” Bi b d b d f ltb <= ”0000”; -- Binary base assumed by defaultc <= B”0000”; -- Binary base explicitly specifiedd <= ”0110 0111”; -- You can use ‘ ’ to increase readabilityd 0110_0111 ; You can use _ to increase readabilitye <= X”AF67”; -- Hexadecimal basef <= O”723”; -- Octal base


Concatenation

SIGNAL a: STD LOGIC VECTOR(3 DOWNTO 0);_ _ ( )SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= ”0000”; b <= ”1111”; c <= a & b; -- c = ”00001111”;

d <= ‘0’ & ”0001111”; -- d <= ”00001111”

e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &‘1’ & ‘1’;

-- e <= ”00001111”e < 00001111


XOR3 Example


Entity xor3y

ENTITY xor3 ISENTITY xor3 IS

PORT(

A : IN STD LOGIC;A : IN STD_LOGIC;

B : IN STD_LOGIC;

C : IN STD LOGIC;C : IN STD_LOGIC;

Result : OUT STD_LOGIC

););

end xor3;


Dataflow Architecture

ARCHITECTURE dataflow OF xor3 ISSIGNAL U1_out: STD_LOGIC;BEGIN

U1 t A XOR BU1_out <=A XOR B;Result <=U1_out XOR C;

END dataflow;END dataflow;

U1 tU1_out


Structural Architecture

ARCHITECTURE structural OF xor3 ISSIGNAL U1_OUT: STD_LOGIC;

I1I2

Y

XOR2

COMPONENT xor2 ISPORT(

I1 : IN STD LOGIC;I1 : IN STD_LOGIC;I2 : IN STD_LOGIC;Y : OUT STD_LOGIC

);END COMPONENT

AB ResultXOR3END COMPONENT;

BEGINU1: xor2 PORT MAP (I1 => A,

BC

ResultXOR3

I2 => B,Y => U1_OUT);

U2: xor2 PORT MAP (I1 => U1 OUT

AB

CRESULT

U1_OUT

XOR3

U2: xor2 PORT MAP (I1 => U1_OUT,I2 => C,Y => Result);

END structural;


Component Instantiation

Named association connectivitya ed assoc at o co ect ty(recommended)

COMPONENT xor2 ISPORT(

I1 : IN STD LOGIC;I1 : IN STD_LOGIC;I2 : IN STD_LOGIC;Y : OUT STD_LOGIC));

END COMPONENT;

U1: xor2 PORT MAP (I1 > AU1: xor2 PORT MAP (I1 => A,I2 => B,Y => U1_OUT);


Component Instantiation

Positional association connectivity os t o a assoc at o co ect ty(not recommended)

COMPONENT xor2 ISPORT((

I1 : IN STD_LOGIC;I2 : IN STD_LOGIC;Y : OUT STD LOGICY : OUT STD_LOGIC);

END COMPONENT;

U1: xor2 PORT MAP (A, B, U1_OUT);


Behavioral Architecture

ARCHITECTURE behavioral OF xor3 ISBEGINxor3_behave: PROCESS (A,B,C)BEGIN

IF ((A XOR B XOR C) = '1') THENResult <= '1';

ELSEResult <= '0';

END IF;END PROCESS xor3_behave;END behavioral;


QuestionsQuestions


Dataflow VHDL

Major instructionsjConcurrent statements

• concurrent signal assignment ()

di i l i l i• conditional concurrent signal assignment(when-else)

l d i l i• selected concurrent signal assignment(with-select-when)

t h f ti• generate scheme for equations (for-generate)


MLU Block Diagramg

A A1

MUX_0

NEG_AIN0

IN1

IN2

IN3 OUTPUT Y

Y1MUX_1

MUX_2

IN3 OUTPUT

SEL1

SEL0

NEG Y

Y

B1B MUX_4_1

NEG_YB1

MUX_3

NEG_B

L0L1


MLU Entity Declarationy


ENTITY mlu ISPORT(

NEG_A : IN STD_LOGIC;NEG B : IN STD LOGIC;NEG_B : IN STD_LOGIC;NEG_Y : IN STD_LOGIC;A : IN STD_LOGIC;B : IN STD LOGIC;B : IN STD_LOGIC;L1 : IN STD_LOGIC;L0 : IN STD_LOGIC;Y : OUT STD LOGICY : OUT STD_LOGIC

);END mlu;


MLU Architecture: Declarations

ARCHITECTURE mlu_dataflow OF mlu IS

SIGNAL A1 : STD_LOGIC;SIGNAL B1 : STD LOGIC;SIGNAL B1 : STD_LOGIC;SIGNAL Y1 : STD_LOGIC;SIGNAL MUX_0 : STD_LOGIC;SIGNAL MUX_1 : STD_LOGIC;SIGNAL MUX_2 : STD_LOGIC;SIGNAL MUX 3 : STD LOGIC;SIGNAL MUX_3 : STD_LOGIC;SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);


MLU Architecture: BodyyBEGIN

A1<= NOT A WHEN (NEG_A='1') ELSEAA;

B1<= NOT B WHEN (NEG_B='1') ELSE B;

Y <= NOT Y1 WHEN (NEG Y='1') ELSE( _ )Y1;

MUX_0 <= A1 AND B1;MUX 1 <= A1 OR B1;MUX_1 < A1 OR B1;MUX_2 <= A1 XOR B1;MUX_3 <= A1 XNOR B1;

L <= L1 & L0;L < L1 & L0;

with (L) selectY1 <= MUX_0 WHEN "00",

MUX_1 WHEN "01",MUX_2 WHEN "10",MUX_3 WHEN OTHERS;


END mlu_dataflow;

FOR … GENERATE

F G tFor - Generate

label: FOR identifier IN range GENERATEBEGIN{Concurrent Statements}

END GENERATE;


PARITY Example


PARITY: Entity Declarationy


ENTITY parity ISPORT(

it i IN STD LOGIC VECTOR(7 DOWNTO 0)parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);parity_out : OUT STD_LOGIC

);END parity;


PARITY: Block Diagramg

xor_out(1)xor_out(2)

xor_out(3) xor_out(4)xor out(5)xor_out(5) xor_out(6)


PARITY: Architecture

ARCHITECTURE parity_dataflow OF parity IS

SIGNAL xor_out: std_logic_vector (6 downto 1);

BEGIN

t(1) it i (0) XOR it i (1)xor_out(1) <= parity_in(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor out(6) <= xor out(5) XOR parity in(6);_ ( ) _ ( ) p y_ ( );parity_out <= xor_out(6) XOR parity_in(7);

END parity dataflow;Microprocessors & Digital Systems Laboratory


END parity_dataflow;

PARITY: Block Diagram 2g

xor_out(1)xor_out(2)

xor_out(3) xor_out(4)xor out(5)

xor_out(0)

xor_out(5) xor_out(6)xor_out(7)


PARITY: Architecture 2


SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0);

BEGINBEGIN

xor_out(0) <= parity_in(0);xor_out(1) <= xor_out(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);

t(4) < t(3) XOR it i (4)xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor_out(6) <= xor_out(5) XOR parity_in(6);xor out(7) <= xor out(6) XOR parity in(7);xor_out(7) <= xor_out(6) XOR parity_in(7);parity_out <= xor_out(7);

END parity dataflow;



PARITY: Architecture 3


SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

xor out(0) <= parity in(0);_ ( ) p y_ ( );

G2: FOR i IN 1 TO 7 GENERATExor out(i) <= xor out(i-1) XOR parity in(i);xor_out(i) < xor_out(i 1) XOR parity_in(i);

end generate G2;

parity out <= xor out(7);parity_out <= xor_out(7);



Simple Rules

For combinational logic,For combinational logic,use only concurrent statements

• concurrent signal assignment ()• conditional concurrent signal assignment• conditional concurrent signal assignment

(when-else)• selected concurrent signal assignment• selected concurrent signal assignment

(with-select-when)• generate scheme for equations• generate scheme for equations

(for-generate)


Simple Rules

F i it d fFor circuits composed of - simple logic operations (logic gates)- simple arithmetic operations (addition,subtraction, multiplication)subt act o , u t p cat o )

- shifts/rotations by a constantuseuse

• concurrent signal assignment ()


Simple Rules

For circuits composed of - multiplexers- decoders, encodersdecoders, encoders- tri-state buffers

useuse

diti l t i l i t• conditional concurrent signal assignment(when-else)

l t d t i l i t• selected concurrent signal assignment(with-select-when)


Left vs Right Side of Assignmentsg g

<=Left side Right side<= when-elsewith-select <=

g

with select <

Expressions including:• Internal signals (defined

in a given architecture)• Ports of the mode

Expressions including:• Internal signals (defined

in a given architecture)• Ports of the mode

- out- inout

• Ports of the mode- in

inoutinout- buffer

- inout- buffer


Arithmetic Operators

Synthesizable arithmetic operations:Sy t es ab e a t et c ope at o s Addition, + Subtraction, -Subtraction, Comparisons, >, >=, <, <= Multiplication *Multiplication, Division by a power of 2, /2**6

(equivalent to right shift)( q g ) Shifts by a constant, SHL, SHR


Arithmetic Operators

The result of synthesis of an arithmeticoperation is a- combinational circuitcombinational circuit- without pipelining.

The exact internal architecture used (and thus delay and area of the circuit)(and thus delay and area of the circuit)may depend on the timing constraints specifiedd i th i ( th t d iduring synthesis (e.g., the requested maximumclock frequency).


QuestionsQuestions


Anatomy of a Processy

OPTIONALOPTIONAL

[label:] process [(sensitivity list)][declaration part]

begingstatement part

end process [label];end process [label];


Statement Part

Contains Sequential Statements to be Executed Each Time the Process Is Activated

Analogous to Conventional Programming Languages


What is a Process

A process is a sequence of instructions referred to as sequential statements

A process can be given a unique name using an optional LABEL TESTING: process

sequential statements.The Keyword PROCESS

using an optional LABEL

This is followed by the keyword PROCESS

pbegin

TEST_VECTOR<=“00”;wait for 10 ns;TEST VECTOR<=“01”;

The keyword BEGIN is used to indicate the start of the process

TEST_VECTOR<= 01 ;wait for 10 ns;TEST_VECTOR<=“10”;wait for 10 ns;TEST VECTOR “11” All statements within the process are

executed SEQUENTIALLY. Hence, order of statements is important.

TEST_VECTOR<=“11”;wait for 10 ns;

end process;

A process must end with the keywords END PROCESS.


Execution of Statements

Testing: PROCESS

The execution of statements

BEGINtest_vector<=“00”;WAIT FOR 10 ns; The execution of statements

continues sequentially till the last statement in the process.

After execution of the last r of

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WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;

After execution of the last statement, the control is again passed to the beginning of the process

Ord

er test_vector<=“10”;WAIT FOR 10 ns;test vector<=“11”;process. test_vector< 11 ;WAIT FOR 10 ns;

END PROCESS;

Program control is passed to the first statement after BEGIN


BEGIN

WAIT Statement

The last statement in the Testing: PROCESSPROCESS is a WAIT instead of WAIT FOR 10 ns.

This will cause the PROCESS

BEGINtest_vector<=“00”;WAIT FOR 10 ns;

to suspend indefinitely when the WAIT statement is executed.

WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;

r of

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This form of WAIT can be used in a process included in a testbench when all possible

test_vector<=“10”;WAIT FOR 10 ns;test vector<=“11”;

Ord

er

combinations of inputs have been tested or a non-periodical signal has to be generated.

test_vector< 11 ;WAIT;

END PROCESS;

Program execution stops here


here

WAIT FOR vs WAIT

WAIT FOR: waveform will keep repeating p p gitself forever

0 1 2 3 0 1 2 3 …

WAIT : waveform will keep its state after theWAIT : waveform will keep its state after the last wait instruction.

…Microprocessors & Digital Systems Laboratory


Sensitivity Listy

List of signals to which the gprocess is sensitive.

Whenever there is an t f thevent on any of the

signals in the sensitivity list, the process fires.

label: process (sensitivity list)declaration part , p

Every time the process fires, it will run in its

ti t

beginstatement part

entirety. WAIT statements are

NOT ALLOWED in a

end process;

NOT ALLOWED in a processes with SENSITIVITY LIST.


IF Statement: Example

SELECTOR: processbegin

WAIT UNTIL Cl k'EVENT AND Cl k '1'WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF Sel = “00” THEN

f <= x1;f <= x1;ELSIF Sel = “10” THEN

f <= x2;;ELSE

f <= x3;END IFEND IF;

end process;


Thank you for your attentionThank you for your attention

QuestionsQuestions


Documents

Moore’s Law in Microprocessors