Optical Packet Switch Architectures: A Comparative Analysis for Bursty Traffic and Optical Cost

Fiber and Integrated Optics, 26:321–334, 2007

Copyright © Taylor & Francis Group, LLC

ISSN: 0146-8030 print/1096-4681 online

DOI: 10.1080/01468030701595597

Optical Packet Switch Architectures:

A Comparative Analysis for Bursty Trafficand Optical Cost

RAJAT KUMAR SINGH

Department of Electrical Engineering

Indian Institute of Technology Kanpur

Kanpur, India

RAJIV SRIVASTAVA



Kanpur, India

YATINDRA NATH SINGH



Kanpur, India

Abstract In this article, we present the comparative analysis of various opticalpacket switch architectures. The comparison is done on the basis of bursty traffic

arrival and the optical cost of various optical components used to build that switch.The architectures chosen for the analysis were previously proposed by us and their

performance was evaluated only for the uniform random traffic arrival. Hence, thisarticle can be considered as the cumulative and effective extension of the previous

works. The computer simulations are performed to obtain the packet loss probabilityand average delay in presence of bursty traffic.

Keywords bursty traffic, loop buffer memory, optical cost, optical packet switching

1. Introduction

All-optical packet switching is one of those optical technologies that have a major impact

over electronic domain for transmission of high-speed data. Here, the data remain in the

optical form throughout the transmission while the control operation is done electronically

[1–3]. This switching is classified in terms of node architecture, scalability, arriving traffic,

component costs, and control complexity.

In this article, we have compared four architectures in terms of optical cost and

realistic traffic (bursty). The analysis is done in view of architectural similarity and

Received 12 March 2007; accepted 25 June 2007.Address correspondence to Rajat Kumar Singh, ACES 301B, Electrical Engineering Depart-

ment, IIT Kanpur, Kanpur 208016, India. E-mail: [email protected]

321

322 R. K. Singh et al.

buffering technique. We have chosen the staggering switch [4], its modified version [5],

feed-forward shared buffer switch [6], and feedback shared buffer switch architecture

[7] for comparison, and these are named as A1, A2, A3, and A4. All are examples

of “almost-all” optical packet switches incorporating fiber delay lines for contention

resolution. In almost-all optical packet switches, the control of switching operation is

done electronically while the data path is fully optical. These architectures extract the

header information from the packets, process it electronically, and route the packets

according to their destination by following the scheduling algorithm defined for the

respective architecture. The architectures A2, A3, and A4 are already proposed by us,

but their performance was analyzed considering uniform random traffic to verify the

existence and proper functioning of these switches. This article can be viewed as the

cumulative extension of the works done in past.

The arriving traffic is considered as the realistic one, also known as the bursty traffic.

For this analysis, we have considered a two states Markov chain model to describe the

behavior of bursty data. In order to verify the switch performance, we have assumed the

condition of uniformly distributed packets for the sake of simplicity. In this condition,

packets are equiprobable to select any of the destination ports. In skewed traffic distribu-

tion, few destinations may dominate others. This will flood the switch with packets for

the same destination within a few slots. It is expected that more buffers will be required

in such a case. If buffering capacity is kept the same, the packet loss probability will

become very high for skewed traffic.

It has been assumed that the packets used in all of the compared architectures are of

fixed size and are equal to one slot. The main issue involved in the case of fixed/variable

length packets is synchronization because if the packets are of fixed length and equal to

one slot duration, then the controller can easily identify the arrival/departure of all the

packets in the same time slot. Further, the longer packet can be fragmented into smaller

ones equal to one slot duration at the ingress nodes. Thus, our study will remain valid

in such a scenario. If the packets are not of fixed length, the switch will require higher

control complexity. Also, the longer length packets will tend to dominate short length

packets in bandwidth usage, thus making the system unfair.

The architectures are simulated and analyzed for bursty traffic arrival to obtain packet

loss probability and average delay. The cost estimation for any switch architecture com-

prises optical cost as well as electronic cost [8]. The optical cost estimation deals with the

count of optical components used to build that architecture, whereas the electronic cost

is obtained by counting the number of optical-electronic-optical (OEO) conversion cir-

cuits used for header reading. The architectures considered here use various techniques

to resolve the contention among the packets and hence they incorporate different sets

of optical components. In this article we compare only their optical cost because the

extraction process of header information is considered the same for each one.

The organization of the rest of the article is as follows. The description and working

of the architectures are described briefly in section 2. Bursty traffic analysis is done in

section 3 and the overall optical cost is calculated in section 4. Conclusions are given in

section 5.

2. Brief Description of the Switch Architectures

2.1. Staggering Switch Architecture (A1)

The architecture A1 (Figure 1) consists of two stages: the scheduling stage .N �S/ and the

switching stage .S�N / where S � N . The scheduling stage is connected to the switching

Optical Packet Switch Architectures: A Comparison 323

Figure 1. Staggering switch architecture (A1).

stage by S delay lines. The delay line di provides a delay of i slots .1 � i � S/. Each

stage may be implemented as a reconfigurable and rearrangeable nonblocking switch [4].

The scheduling is done by using a well-defined scheduling algorithm. This algorithm

tries to allocate each incoming packet into the appropriate delay line and thus avoids the

packet contention at the input of switching stage. The scheduling algorithm considers

two conditions: (1) no previous packet was inserted in the delay line in same time slot

and (2) no other packet to the same destination exists in the column in which the packet

is to be inserted.

2.2. Modified Staggering Switch Architecture (A2)

In the modified architecture A2 (Figure 2), we have increased the dimension of scheduling

switch to .N C R/� .S C R/ by adding extra delay lines (R) from output to input at the

scheduling stage [5]. Each extra line provides one packet (slot) delay; i.e., for each value

of R these extra lines will provide maximum of one packet delay. These extra delay

lines are used to carry those packets, which are going to be lost in the current slot due

to nonavailability of suitable direct delay line (S ). In the next slot, priority for choosing

the appropriate line will be given to the packet stored in these extra delay lines.

Figure 2. Modified architecture for staggering switch (A2).


Figure 3. Feed-forward shared buffer switch architecture (A3).

2.3. Feed-Forward Shared Buffer Architecture (A3)

The basic building block of the architecture A3 (Figure 3) consists of three sections:

(i) scheduling section, (ii) combined section for routing the packet through either M

direct paths or m buffer modules, and (iii) switching section [6]. The size of scheduling

and switching stage are N � K and K � N , respectively, where K D M C m � D. Here,

D is the number of input/output ports assigned to each loop buffer module (Figure 4).

The capacity of each buffer module, indexed 1 to m (Figure 3), is equal to B (�D)

where B is the number of different wavelengths at which the packets are stored in the

buffer [9, 10]. The packets to be buffered are converted to the wavelengths available in

the buffer; if the buffer is full, then packets are dropped. When a packet is forwarded

for buffering, the respective tunable wavelength converters (TWC) at the input of the

available buffer module is tuned to any one of the loop buffer wavelengths, which is

free to accept the packet. As long as a packet circulates in buffer, the TWC inside that

module corresponding to the used wavelength will remain transparent. For reading out

a packet when output contention is resolved, the corresponding TWC is tuned to the

free wavelength port of demultiplexer (DEMUX). Then these packets can be directed

Figure 4. Loop buffer module.


to the destined output port through the space switch fabric. The buffer wavelengths

are automatically cleared from the loop buffer as soon as the buffered packet leaves

the loop.

2.4. Feedback Shared Buffer Architecture (A4)

This architecture A4 (Figure 5) is similar to the A3 with the difference that the loop

buffer is utilized in feedback configuration. The size of the core switch (space switch

fabric) is 2N � 2N . The lower N ports of the space switch are used as actual inputs

and outputs. The upper N ports are used for buffering of the packets in the optical loop

buffer modules [7]. Thus, the maximum number of allowed buffer modules is m D N=D.

The loop buffer module indexed 1 to m (Figure 5) is the same as that used in the case

of architecture A3 (Figure 4). Thus, the process of storing in as well as reading out a

packet from the buffer is same as that for A3.

3. Bursty Traffic Analysis

The brief detail of bursty traffic is given in this section along with the bursty traffic

analysis of the above-mentioned architectures. Here, we present the two state model of

Markov chain, and the simplified form of the three state model was given by Hass [4].

3.1. Model of Bursty Traffic

As a function of time, the traffic will be composed of bursts of packets destined to the

same output port. These bursts are followed by an idle period that can be of length zero,

where a new burst will be adjacent to the older one (Figure 6). The bursty traffic is

characterized by two parameters:

1. average offered traffic load �, and

2. average burst length, BL.

Figure 5. Feedback shared buffer switch architecture (A4).


Figure 6. Packet sequencing for bursty traffic.

Time correlation of traffic on each input can be modeled as the Markov chain shown

in Figure 7. The chain is composed of two states: idle state (0) or burst state (j ). The

system will be in the idle state (0) when no packet arrives in the current slot. Also, if

no packet will arrive in the next slot with probability Pa , then a new burst will begin

with probability 1 � Pa and the system will be transferred to the burst state j . In this

state, one of the values of output destinations is chosen with equal probability. Being in

this bursty state, the next arrival will be either the part of same burst with probability Pb

(i.e., destined to the same output port) or the burst will terminate. The termination of a

burst can occur in two ways with certain probability:

1. A new burst will start for another destination. This transfers the system to a state

other than the current one. The choice of another destination is equiprobable. The

probability of this state will be .1 � Pb/ � .1 � Pa/.

2. Or the burst will become idle, with probability .1 � Pb/ � Pa .

The steady-state equation for this Markov chain can be written in terms of steady-

state probabilities as

�

Pa .1 � Pb/Pa

.1 � Pa/ .1 � Pa/.1 � Pb/ C Pb

� �

�0

�

�

D

�

�0

�

�

(1)

Figure 7. Markov chain model for bursty traffic.


Here, � is the steady-state probability of the system being in any one of state j ; i.e.,

� D †�j and 1 � j � N . Further using the property that summation of all the state

probabilities is equal to unity,

�0 C � D 1 (2)

Solving (1) and (2), we will get the steady-state probabilities in terms of Pa and Pb .

�0 DPa.1 � Pb/

1 � PaPb

and � D.1 � Pa/

1 � PaPb

(3)

The average offered traffic load (�) will be a fraction of time the system is not in

the idle state; i.e.,

� D 1 � �0 D1 � Pa

1 � PaPb

(4)

The probability of a burst of length k is

Pr.k/ D .1 � Pb/P k�1b ; k � 1 (5)

Hence the average burst length is

BL D

1X

kD1

k Pr.k/ D1

1 � Pb

(6)

Considering some fix value of � and BL in (4) and (6) respectively, the values

of Pa and Pb can be calculated and will be used to simulate the performance of the

above-mentioned switch architectures under bursty traffic conditions.

3.2. Results and Discussion

The loss probability and average delay for bursty traffic arrival are shown graphically

in Figures 8a and 8b respectively, for the switch architecture A1 and A3. We have

considered the same size switch .N D 16/ for all the architectures and the comparison

is done under the same loading condition. The buffering capacity for A1 at S D 16

is 136 ŒD S � .S C 1/=2�, whereas it is 80 .D m � B/ for A3 at m D 4, B D 20,

D D 4, and M D 0. We have chosen M D 0 in architecture A3 to make it comparable

with A1 and A2. The value m D 4 is chosen for A3 because all the ports of scheduling

and switching stages are fully utilized with it (i.e., m � D D N ). The value B D 20

provides comparable packet loss probability for A3 compared to A1. Under lower loading

conditions (i.e., � � 0:6) and for smaller burst length (BL � 5), the loss probability and

average delay for A3 are slightly better than A1 (Figures 8a and 8b) but under the higher

loads and larger burst length, the results for A1 will be better than that for A3.

The results with different number of extra delay lines (R) for A2 are shown in

Figure 9 at � D 0:7. For smaller burst length, the loss probability is much better for A2

(Figure 10a) compared to A3 (Figure 8a) but at the expense of much higher and constant

delay (Figures 8b and 10b). Also, there is not enough advantage of using extra delay

lines for larger burst length as loss probability for A2 is nearly equal to that of A3 but

with increasing delay.


(a)

(b)

Figure 8. (a) Loss probability for staggering switch (A1) and feed-forward switch (A3).

(b) Average delay for staggering switch (A1) and feed-forward switch (A3).


(a)

(b)

Figure 9. (a) Loss probability for feed-forward switch (A3) and feedback switch (A4). (b) Average

delay for feed-forward switch (A3) and feedback switch (A4).


(a)

(b)

Figure 10. (a) Loss probability for modified staggering switch (A2). (b) Average delay for modified

staggering switch (A2).


The bursty traffic analysis for A3 and A4 is done for same buffering capacity with

N D 16, m D 4, B D 8, and M D 16. We have considered M D 16 for A3 as it is

equivalent to the lower N output ports of A4 for direct transfer. The loss probabilities

(Figure 9a) and the average delay (Figure 9b) are better for A4 compared to A3 but,

usually, the average delay increases when loss probability is reduced. Hence, the above

observation implies that A3 is not effectively utilizing the available buffering capacity

while A4 is utilizing the same.

4. Optical Cost Analysis

The optical cost of any switch architecture is calculated by adding the cost of each optical

component used in that architecture. The cost of the optical components is obtained by

counting the number of fiber-to-chip couplings (FCCs) [8]. The FCC is the number of

interconnections to the outer world through that component. The counting of optical

components in the switch architecture is started from the switch input. The number of

each component is multiplied by the respective optical cost as given in Table 1, and thus

the optical cost of whole switch is obtained.

4.1. Optical Cost for Architecture A1 and A2

The optical cost for the staggering switch architecture (A1) is calculated in terms of

FCCs as

CA1 D CScheduling Stage.N; S/ C CSwitching Stage.S; N /

Since we are using the switch A1 with N D 16 and S D 16, applying the parametric

values from Table 1

CA1 D .N C S/ C .S C N / D 2N C 2S D 64

Similarly, the optical cost for A2 is obtained with R D 4

CA2 D .N C R C S C R/ C .S C N / D 2N C 2R C 2S D 72

Table 1

Optical cost function of the components

Function Description Number of FCC

CD.W / Demultiplexer (W channels) W C 1

CT .W / TWC (W wavelength) W C 1

CCom.W / Combiner .W � 1/ W C 1

CSwitch.I; O/ Switch (I/O input/output ports) I C O

CAmp Amplifier 2

CISO Isolator 2

C3dB 3 dB Coupler 4


4.2. Optical Cost for Architecture A3

We use the switch A3 of N D 16 input with m D 4, D D 4, and M D 16 to compare it

with A4 and since K D M Cm�D; i.e., K D 32. Hence, the effective size of scheduling

and switching stages of A3 will be N � K and K � N , respectively, which is used in

the following equation for calculating the optical cost:

CA3 D CSwitch.N; K/ C m � ŒD � CT .B/ C CCom.D/ C C3dB C CD.B/ C B � CT .D/

C CCom.B/ C CAmp C CISO C CD.D/� C CSwitch.K; N /

CA3 D .N C K/ C m � ŒD � .B C 1/ C .D C 1/ C 4 C .B C 1/ C B � .D C 1/

C .B C 1/ C 2 C 2 C .D C 1/� C .K C N /

D 2N C 2K C m � Œ2BD C 3D C 3B C 12� D 544

4.3. Optical Cost for Architecture A4

The optical cost for the shared buffer feedback switch architecture is calculated as

CA4 D CSwitch.2N; 2N / C m � ŒD � CT .B/ C CCom.D/ C C3dB C CD.B/

C B � CT .D/ C CCom.B/ C CAmp C CISO C CD.D/�

CA4 D .2N C 2N / C m � ŒD � .B C 1/ C .D C 1/ C 4 C .B C 1/

C B � .D C 1/ C .B C 1/ C 2 C 2 C .D C 1/�

D 4N C m � Œ2BD C 3D C 3B C 12� D 512

5. Conclusions

The switch A3 effectively uses the principle of staggering switch (A1) but, in addition,

it applies the WDM technique to store the packets in recirculating loop. Thus, A3 is

compared with A1 and A2 on the basis of bursty traffic arrival only and not in terms of

optical cost, since it is architecturally not equivalent to A1 an A2. The FIFO discipline is

not maintained by A1 and A2, while A3 maintains the FIFO. Also, A3 is scalable in terms

of the buffering capacity, i.e., we can increase its buffering capacity without changing

the switch configuration. This comparative study implies that under bursty traffic, the

feed-forward architecture is much better than the staggering switch due to the additional

advantage of WDM application in buffering. The modified staggering switch has some

advantages over feed-forward architecture in terms of loss probability but only for smaller

burst length, while it also increases the size of scheduling stage. So, it is preferred over

the staggering switch and not over feed-forward switch.

Since the architecture A4 utilizes WDM recirculation loop buffer in feedback config-

uration for data storage and maintains FIFO, it is compared only with A3 for both bursty

traffic arrival pattern and optical cost estimation. The feedback switch is advantageous

over feed-forward in term of loss probability and average delay under bursty traffic due


to more effective use of buffers. The optical cost of the feedback switch is also much

higher but still comparatively less than the feed-forward switch.

The optical cost of architectures A1 and A2 is very low because they do not incor-

porate WDM loop buffer module and hence they are not compared with A3 and A4 in

terms of optical cost. Hence, we can conclude that the feedback configuration is the best

option among all of the compared architectures.

References

1. Tucker, R. S., and Zhong, W. D. 1999. Photonic packet switching: An overview. IEICE—

Transactions on Communications E82(B):254.

2. Dittmann, L., Develder, C., Chiaroni, D., Neri, F., Callegati, F., Koerber, W., Stavdas, A.,

Renaud, M., Rafel, A., Sole-Pareta, J., Cerroni, W., Leligou, N., Dembeck, L., Mortensen, B.,

Pickavet, M., Le Sauze, N., Mahony, M., Berde, B., and Eilenberger, G. 2003. The European

IST project DAVID: A viable approach toward optical packet switching. IEEE Journal on

Selected Areas in Communications 21(7):1026.

3. Singh, R. K., and Singh, Y. N. 2006. An overview of photonic packet switching architectures.

IETE Technical Review 23(1):15.

4. Hass, Z. 1993. The staggering switch: An electronically controlled optical packet switch.

Journal of Lightwave Technology 11(5):925.

5. Singh, R. K., and Singh, Y. N. 2005. A modified architecture for the staggering switch. NCC

2005 1(1):186.

6. Singh, R. K., Srivastava, R., Mangal, V., and Singh, Y. N. 2006. Wavelength routed shared

buffer based feed-forward architectures for optical packet switching. IEEE INDICON 2006.

Annual India Conference, 2006, September, pp. 1–6. Available at IEEE Xplore.

7. Singh, R. K., Srivastava, R., and Singh, Y. N. 2007. Wavelength division multiplexed loop

buffer memory based optical packet switch. Optical and Quantum Electronics 39(1):15.

8. Caenegem, R. V., Colle, D., Pickavet, M., Demeester, P., Martinez, J. M., Ramos, F., and

Marti, J. 2006. From IP over WDM to all-optical packet switching: Economical view. Journal

of Lightwave Technology 24(4):1638.

9. Verma, N., Srivastava, R., and Singh, Y. N. 2002. Novel design modification proposal for all

optical fiber loop buffer switch. Photonics 2002 1(1):181.

10. Shukla, S., Srivastava, R., and Singh, Y. N. 2004. Modeling of fiber loop buffer based switch.

Photonics 2004 1(1):248.

Biographies

Rajat Kumar Singh was born in Jaunpur (UP), India, on December 18, 1975. He re-

ceived a B.Tech. degree in electronics and instrumentation engineering from Bundelkhand

Institute of Engineering & Technology, Jhansi (UP) in 1999 and an M.E. in communica-

tion engineering from Birla Institute of Technology & Science, Pilani (Raj.) in December

2001. Currently he is pursuing his Ph.D. from the Indian Institute of Technology, Kanpur.

His research interests are in the field of photonic packet switching, telecom networking,

and optical networks.

Rajiv Srivastava was born in Kanpur (UP), India, on February 18, 1976. He re-

ceived an M.Sc. degree in physics (solid state) from CSJM University, Kanpur (UP), in

1997, and an M.Tech. degree in laser technology from Indian Institute of Technology,

Kanpur, in December 2003. Currently he is pursuing his Ph.D. from the Indian Institute

of Technology, Kanpur. His research interests are in the field of photonic packet switching

and solitons-based optical networks.


Yatindra Nath Singh was born in Delhi, India, on August 26, 1969. He obtained

a B.Tech. in electrical engineering from Regional Engineering College, Hamirpur, Hi-

machal Pradesh, in July 1991; an M.Tech. in optoelectronics and optical communications

from the Indian Institute of Technology, Delhi, in December 1992; and a Ph.D. from the

Department of Electrical Engineering, Indian Institute of Technology, Delhi, in 1997.

He was with the Department of Electronics and Computer Engineering, IIT Roorkee,

India, as faculty from February 1997 to July 1997. He is currently working as faculty in

the Department of Electrical Engineering, Indian Institute of Technology, Kanpur. He was

awarded the AICTE Young Teacher Award in 2002. He is a fellow of the Institution of

Electronics and Telecommunication Engineers (IETE), India, and senior member of the

Institution of Electrical and Electronics Engineers, Inc. (IEEE). His academic interests

include optical networks, photonic packet switching, optical communications, telecom

networks, network managements, e-learning systems, and open-source software develop-

ment. He is actively involved in development of open source e-learning platform tools

code named Brihaspati.

Documents

Optical Packet Switch Architectures: A Comparative Analysis for Bursty Traffic and Optical Cost