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Mr. V. VAITHIANATHAN, M.Tech (PhD)Assistant Professor, ECE Department
EC1254 Linear Integrated Circuits
Unit – I: Part - I
Operational Amplifier Internal Circuit
Objectives of this presentation• To learn about
–The pin configuration and the complete schematic circuit diagram for 741.
–Analysis of Differential Amplifiers –Circuits for improving CMRR. –Various types of current sources/mirrors.– Input Resistance–Active Load – Level Translator–Output Stage
OPAMP 741• 741 op-amp has become. an industry standard
today. • The pin configuration and the complete schematic
circuit diagram for 741 is shown in figures.
OPAMP 741
OPAMP 741• The input stage diff-amp consists of transistors Q1
- Q3 and Q2- Q4.
• Transistors Q16 and Q17 provide the second stage voltage gain.
• Transistors Q1Q3 and Q2Q4 are in cascode (CE-CB) configuration.
• Two transistors in series (Q1 feeds Q3) provide high gain per stage needed to achieve the adequate open-loop gain in a two stage amplifier.
• The transistors Q5,Q6 and Q7 form the active load for Q3 and Q4.
OPAMP 741• Transistors Q5 and Q6 also function as a
differential amplifier for the external offset nulling signal.
• The emitter current of transistors Q5 and Q6 can be controlled by varying a 10 kΩ potentiometer that is externally connected between offset null terminals, as shown by dotted line in fig.
• Bias currents for the input stage are provided by a complicated arrangement of current mirror pairs.
• Q12 generates a current in Q11. This current is reflected over to Q10(though reduced because of the emitter feedback due to R4).
OPAMP 741• This, in turn, generates a series current in Q9
which is reflected across another mirror pair to Qs. • The bias current of Q3 and Q4 is effectively driven
by the mirror pair Q10 and Q11. • The output of the first diff-amp is taken at the
junction of Q4 and Q6 (point X) which acts as a complementary symmetry amplifier.
• The output at this point is proportional to the differential input signal.
• The output is now amplified by the second stage consisting of transistor Q16 and Q17 in Darlington connection.
OPAMP 741
• The output of common-collector-amplifier formed by Q16 and R9 drives the CE-amplifier composed of Q17, Rs and a constant current load Q13.
• The output of CE-amplifier is a bias source for transistors Q18 and Q19.
• Transistors Q12 and Q13 form a current mirror and supply current to transistors Q17, Q18 and Q19.
• The network consisting of transistors Q18,Q19 and R10 is a fixed voltage level shifter shifting the voltage output of Q17 by a fixed amount on its way to the output complementary stage formed by Q14and Q20.
OPAMP 741• The level shifter network is designed to bias the
output stage in the linear region. • The transistors Q18 and Q19 also separate the bases
of Q14 and Q20 by two diode drops and thus temperature compensate currents in Q14and Q20.
• Transistor Q22 performs two functions. It serves as a buffer between Q17 and Q20 and also provides a negative feedback to Q16.
• The final output is taken at the junction of R6 and R7. • The output complementary pair operates so that
depending upon the sign of the output, only one of the transistors Q14 or Q20 is conducting at any time.
OPAMP 741• With no input signal, both devices are turned off,
resulting in a low quiescent current drain in the output stage.
• Transistors Q15, Q21 and Q23 protect the circuit by limiting current to the output complementary stage.
• If the output (load) current exceeds the safe limit, the voltage drop across R6 and R7 increases.
• This turns on Q15 and Q21 which in turn makes Q23on.
• This however shorts out, that is turns off the amplifier Q16-Q17.
OPAMP 741
• This reduces the emitter current in Q22 and in turn current in Q18 and Q19.
• The reduction in the currents of Q18 and Q19 lowers the currents in Q14 and Q20.
• The diode-connected transistor Q24 is a temperature compensating diode for transistor Q23.
• Finally, the internal 30nF capacitor provides the high frequency roll-off to stabilize the circuit.
Block Diagram
Differential Amplifier
Differential Amplifier
Buffer & Level
Translator
Output Driver
Vout
V2 --
V1 +
Block Diagram • Commercial IC op-amps usually consists of four
cascaded blocks as shown in fig.• The first two stages are cascaded differential
amplifiers used to provide high gain and high input resistance.
• The third stage acts as a buffer as well as a level shifter.
• The buffer is usually an emitter follower whose input impedance is very high so that it prevents loading of the high gain stage.
• The level shifter adjusts the dc voltages so that output voltage is zero for zero inputs.
• The adjustment of dc level is required as the gain stages are direct coupled.
Block Diagram • As it is not possible to fabricate large value of
capacitors, all IC's are direct coupled usually.• The output stage is designed to provide a low
output impedance as demanded by the ideal op-amp characteristics.
• The output voltage should swing symmetrically with respect to ground.
• To allow such symmetrical swing, the amplifier is provided with both positive and negative supply voltages.
• Power supply voltages of ±15V are common. • Additionally, an op-amp generally incorporates
circuitry to provide drift compensation and frequency compensation.
Differential Amplifier • The main purpose of the differential amplifier
stage is to provide high gain to the difference mode signal and cancel the common-mode signal.
• Thus, it is able to suppress any undesired noise which is common to both of the input terminals.
• The relative sensitivity of an op-amp to a difference signal as compared to common-mode signal is called common-mode rejection ratio (CMRR) and gives the figure of merit of the differential amplifier.
Differential Amplifier • The higher the value of CMRR, better is the op-
amp. • Another requisite of a good op-amp is that it
should have high input impedance. • A cascaded dc amplifier can provide high gain
down to zero frequency as it has no coupling capacitor.
• However, such an amplifier suffers from the major problem of drift of the operating point due to temperature dependency of lCO, VBE and hFE of the transistor.
• This problem can be eliminated by using a balanced or differential amplifier as shown in fig.
Differential Amplifier
• Basic differential amplifier
Differential Amplifier • It is essentially an emitter-coupled differential
amplifier. • This circuit has low drift on account of symmetrical
construction. • It can be designed to give high input resistance.
• It has two input terminals and it may be seen easily that terminal B2 is the inverting input terminal since transistor Q2 provides a phase shift of 180° for the output taken at the collector of Q2.
• Obviously, B1 is the non-inverting input terminal. • So, a differential amplifier is well suited to obtain
the ideal characteristics of an op-amp.
Differential Amplifier • A differential amplifier can be used in four
different configurations depending upon the number of input signals used and the way output is taken. These four configurations are:– Differential-input, differential-output or Dual-
input balanced-output – Differential-input, single ended-output – Single-input, differential-output – Single-input, single ended-output.
• If signal is applied to both the inputs, then it is differential input or dual input and the difference of signals applied to the two inputs gets amplified.
Differential Amplifier • In many applications a single input is only used
• Similarly, if output voltage is measured between two collectors then it is a differential output. This is also referred to as a balanced output, as both collectors are at the same dc potential.
• To understand the working of a differential amplifier first consider the case when both the
• bases B1 & B2 are joined together and connected to a voltage VCM called the common-mode voltage.
• Thus in fig. V1 = V2= VCM.
Differential Amplifier Differential pair with a common-mode input signal VCM
Differential Amplifier • As both the transistors Q1 and Q2 are forward-
biased and matched, due to symmetry of the circuit, the current IQ divides equally through transistors Q1 and Q2, that is, iE1 = iE2= IQ/2.
• The collector currents iC1 and iC2 through the resistors Rc is αF IQ/2.
• The voltage at each of the collectors will be
• Therefore the difference of the voltage between the two collectors (VO1- VO2)will be zero.
Differential Amplifier • Now, even if the value of VCM is changed, the
voltage across the collectors will not change.
• Thus, the differential pair does not respond to (or rejects) the common-mode input signals.
• Now, consider the case when the voltage V2 is made zero and voltage V1 =1 V (say) as shown in fig.
• It can be seen that the transistor Q1 will conduct and transistor Q2 will be off.
• The entire current IQ will now flow through Q1.
• Since Q1 is on, the voltage at its emitter will be 0.3 V.
Differential Amplifier • Differential pair with large differential input signal.
Differential Amplifier • This will make emitter-base junction of Q2 reverse-
biased and thus Q2 will be off. • The collector voltages will be Vo1 = Vcc - αF IQRC and
Vo2 = Vcc.• If, however, V1 = -1V and V2 = 0V, it can be seen
that Q1 will be off and the entire current IQ will flow through Q2.
• The voltage at the common emitter point 'E will now be - 0.7V which makes Q1 off and Q2 on.
• The collector voltages will be Vo1 = Vcc and Vo2= Vcc - αF IQRc.
• The differential pair responds only to the difference mode signals and rejects common-mode signals.
Differential Amplifier Transfer Characteristics
Differential Amplifier • The collector currents iC1 and iC2 for transistors Q1
and Q2 biased in the forward active mode may be given by (neglecting reverse saturation currents of the collector base junction)
• Here, IES is the reverse saturation current of emitter-base junction and VT is volts equivalent of temperature.
• We may write
Differential Amplifier • We may also write KVL for the loop containing two
emitter-base junctions as
where, Vd is the difference of two input voltages.
• Solving for iC1 and iC2, gives
Differential Amplifier Low Frequency Small Signal Analysis
• An ideal dual-input balanced-output differential amplifier should amplify only the differential signal at the two inputs and reject the signal common to these inputs.
• As transistors Q1 and Q2 are a matched pair of transistors, thus any unwanted signal, such as noise or hum pick up which is common to both the inputs would get rejected.
• However in a practical case transistors Q1 and Q2are not equally matched and output does appear even when same voltage is applied to the two input terminals.
Differential Amplifier • In this section, we will discuss how to compute the
small signal differential mode gain, ADM and common-mode gain ACM.
• These expressions help in finding the figure of merit CMRR of the differential amplifier and hence the ways to improve it.
Differential-mode gain, ADM
• For V1 = V2 the current IQ divides equally into the two transistors Q1 and Q2 because of the symmetry of the circuit.
Differential Amplifier • However, if V1 is now increased by an incremental
voltage (small signal) Vd/2 and V2 is decreased by Vd/2, it can be seen that the differential amplifier is being fed by differential small signal Vd.
• The common mode small signal is naturally zero.
• The collector current iC1 will now increase by an incremental current iC and iC2will decrease by an equal amount.
• The sum of total currents in transistors Q1 and Q2
however remains constant as constrained by the constant current IQ.
Differential Amplifier • As there is no change of current through RE, the
voltage VE at the common emitter point 'E' remains constant.
• Thus, for small signal analysis, the common emitter point 'E' can be considered to be at ground potential.
• The fig. shows the small signal equivalent circuit of the differential amplifier under the differential input signal conditions described above.
Differential Amplifier Using hybrid-n Model
• Since the performance of two sides of the differential amplifier is identical, we need to
• analyze only one side of the differential amplifier called differential-half circuit.
• The fig. shows a single
stage CE transistor
amplifier fed by a
small signal voltage Vi2.
Differential Amplifier • It 's ac. equivalent circuit using hybrid-π model is
shown in fig.
• From fig, we may write as,
• Similarly, it can be seen that
Differential Amplifier • The output voltage signal of a differential amplifier
can be taken either differentially (i.e. between the two collectors) or single-ended (i.e. between one collector and ground).
• If the output is taken differentially, then the differential-mode gain, ADM is given by
Differential Amplifier • On the other hand, if output is single-ended, (say
between collector of transistor Q1 and ground),
then the differential-mode gain ADM is given by
• In the above analysis, we have not included the transistor model parameter ro. If ro is included,
Differential Amplifier Using 'h' parameters
• The ac equivalent circuit using approximate h-parameter model is shown in fig.
• From fig, we can write
Differential Amplifier • Therefore, differential mode gain, ADM is given by
• Similarly, we may write
• If the output is taken differentially between the two collectors, then
• In the above analysis, the source resistance Rs has not been taken into account.
Differential Amplifier Common-mode gain, ACM
• Now, consider the case when V1 and V2 both are increased by an incremental voltage VC.
• The differential signal Vd now is zero and common-mode signal is VC.
• Both the collector currents iC1 and iC2 will increase by an incremental current iC.
• The current through RE now increases by 2iC. • The voltage, VE at emitter node is now increased
by 2iCRE and no longer constant.
Differential Amplifier • In order to draw the common mode half circuit,
replace resistance RE by 2RE as shown in fig.
• The common-mode gain, ACM is calculated from the small-signal hybrid-π equivalent model shown in fig.
Differential Amplifier• The equations are
• It can be seen that, if the output is taken differentially, then the output voltage VO1 -VO2,will be zero and the common-mode gain will be zero.
• In this analysis, we have assumed that the circuit is perfectly symmetrical.
Differential Amplifier• However, in practical circuits, it will not be so,
and the differential output voltage will not be exactly zero.
• If the output is taken single ended, the common-mode gain will be finite.
• The common mode gain, ACM, using h-parameter model can be easily computed as
Differential Amplifier• The common-mode rejection ratio (CMRR) is
defined as
• For differential-input, differential-output,
Circuits for Improving CMRR• For CMRR to be large, ACM should be as small as
possible. For ACM ≈ 0, RE ≈∞. • There are, however, practical limitations on the
magnitude of RE because of the quiescent dc voltage across it.
• If RE is made large, the emitter supply VEE will also have to be increased in order to maintain the proper quiescent current.
• If the operating currents of the transistors are allowed to decrease, then hie will decrease , thereby decreasing hfe too.
• This too will decrease the common mode rejection ratio.
Circuits for Improving CMRR
Circuits for Improving CMRR• The use of a constant current bias in place of RE is
found to be a practical solution. This is shown in fig.
• So, RE is replaced by a constant current transistor circuit in which R1, R2 and R3 can be adjusted to give the same quiescent conditions for the transistors Q1 and Q2 as in the original circuit.
• The modified circuit presents a very high effective emitter resistance RE even for very small values of R3,
• Typically, RE is hundreds of kΩ even if R3 is as small as 1 kΩ.
Circuits for Improving CMRR• Let us calculate the current lQ and verify that the
emitter circuit really behaves as a constant current source.
• Writing KVL for the base circuit of Q3, we get
• Here VD represents the drop across the diode D. If the base current is neglected, then
Circuits for Improving CMRR• By proper choice of resistors R1 and R2, it is
possible to set,
• So, it can be seen that the current IQ will be essentially constant as it does not depend upon signal voltages V1 and V2.
• The diode D makes IQ independent of temperature.
Constant Current Source (Current Mirror)
• A constant current source makes use of the fact that for a transistor in the active mode of operation, the collector current is relatively independent of the collector voltage
• In the basic circuit shown in fig. the transistors Q1and Q2 are matched as the circuit is fabricated using IC technology.
• It may be noted that bases and emitter of Q1 and Q2 are tied together and thus have the same VBE.
• In addition, transistor Q1 is connected as a diode by shorting its collector to base.
Constant Current Source (Current Mirror)
Constant Current Source (Current Mirror)
• The input current Iref flows through the diode connected transistor Q1 and thus establishes a voltage across Q1.
• This voltage in turn appears between the base and emitter of Q2.
• Since Q2 is identical to Q1 the emitter current of Q2will be equal to emitter current of Q1 which is approximately equal to Iref.
• Thus, we can say that as long as Q2 is maintained in the active region, its collector current Ic2 =IOwill be approximately equal to Iref.
Constant Current Source (Current Mirror)
• Since the output current IO is a reflection or mirror of the reference current Iref the circuit is often referred to as a current mirror.
• This mirror effect is however, valid only for large values of β.
• To study the effect of β on the operation of the current mirror circuit, we analyze it further.
• The collector currents IC1 and IC2 for transistors Q1and Q2 can be approximately expressed as
Constant Current Source (Current Mirror)
• Since VBE1 = VBE2,we obtain IC2 = IC1 = IC = IO. • Also since both the transistors are identical, β1=β2= β.
• KCL at the collector of Q1 gives
• Solving for IC, we get
Widlar Current Source• The basic current mirror has a limitation.• Whenever, we need low value current source, the
value of the resistance R1 required is sufficiently high and can not be fabricated economically in IC circuits.
• The fig shows a widlar current source which is particularly suitable for low value of currents.
• The circuit differs from the basic current mirror only in the resistance RE that is included in the emitter lead of Q2.
• It can be seen that due to RE, the base-emitter voltage VBE2 is less than VBE1 and consequently current IO is smaller than lC1.
Widlar Current Source
Widlar Current Source• The ratio of collector currents lC1 and lC2 using is
given by
• Taking natural logarithm of both sides, we get
• Writing KVL for the emitter base loop
Widlar Current Source• A relation between lC1 and the reference current
lref is obtained by writing KCL at the collector point of Q1 (note 'a')
• In the Widlar current source IC2«IC1, therefore the term IC2/β may be neglected.
(Assuming β2=β1=β for identical transistors)
Widlar Current Source• Sometimes, it is convenient to use emitter
resistance's in both the transistors Q1 and Q2 as shown in fig.
Widlar Current Source• If R1=R2, the currents IC1 =IC2. • The same circuit can also be used to provide
different currents in Q1 and Q2.
• Writing KVL in the base-emitter loop
Current Repeaters• The basic current mirror can be used to source
current to more than one load.• Such a circuit is called current repeater and is
shown in fig,
• If all the transistors are identical, then the current
Current Repeaters• It can be seen from at node 'a'
• It is possible to achieve different value of IC1, IC2, ... ... ICN by scaling the emitter area of transistors Q1, Q2, ...,... QN.
• The same can also be achieved by using emitter resistance as in the Widlar current source.
(Assuming identical transistors)
Improved Current Source Circuits
• A good current source must meet two requirements.
• The first is that the output current, IO should not be dependent upon β and secondly the output resistance of the current source should be very high.
• The need for high output resistance current source can be seen because the common-mode gain of the differential amplifier (used as basic building block in op-amps) can only be reduced by using high resistance current sources.
Improved Current Source Circuits
• Also, all differential amplifiers invariably use current source as a load.
• Thus to obtain high voltage gain a large output• resistance load is required. • Now, we discuss two circuits that exhibit reduced
dependence on β or increased output resistance.
Current Source with Gain• The circuit shown in fig. includes a transistor Q3
whose emitter current supplies the base currents of Q1 and Q2.
Current Source with Gain• The expression for the source current IO =lC2 can
be derived by writing KCL at node 'a'
Current Source with Gain• Here, the output current is essentially independent
of β.
• The output resistance of the current source is only ro.
• It can however be increased by using emitter resistances in Q1 and Q2 as is done in the modified Widlar source circuit.
• The two emitter resistors can also be used to make IO different from lref.
Wilson Current Source• The current source shown in fig provides an
output current 10, which is very nearly equal to lref
and also exhibits a very high output resistance.
Wilson Current Source
• At node ‘b’
Wilson Current Source• At node ‘a’
• The output resistance of a Wilson current mirror is substantially greater than simple current mirror or Widlar current mirror.
Input Resistance • The resistance offered by the differential amplifier
to the differential input signal (V1 - V2) is called differential input resistance Rid.
• The emitters of Q1 and Q2 are floating as RE is replaced by a constant current source, therefore Rid ≈ hie1 + hie2 = 2 hie.
• If input 2 is grounded, then input 1 is loaded by 2 hie.
• The value of hie can be increased by reducing the biasing currents for Q1 and Q2 and input resistance of the order of 500kΩ can be obtained.
Input Resistance • Higher values of input resistance can be obtained
by using a Darlington pair in place of transistor Q1 and Q2.
Input Resistance • One drawback of the Darlington differential
amplifier is the higher offset voltage Vas, (due to cascaded stages) which is about 2 times larger than - the ordinary two transistor differential amplifier.
• The most important feature of the Darrington pair differential amplifier is its extraordinary large current gain.
Active Load • The open circuit voltage gain of an op-amp should
be as large as possible and this is achieved by cascading gain stages.
• However, this increases the phase shift too and amplifier becomes more susceptible to breaking out into oscillations.
• One can think of increasing gain by using large collector resistance values as gain is proportional to load resistor RC.
Active Load • However, there are limitations to the maximum
value of RC to be used due to the following two reasons:
– A large value of resistance requires a large chip area.
– For large RC, quiescent drop across it increases and hence a large power supply will be required to maintain a given quiescent collector current. These difficulties are circumvented by using a current source as load in the place of RC.
Active Load • The current mirror discussed earlier has a dc
resistance of the order of few kilo ohms, as the quiescent voltage across it is a fraction of the supply voltage and the current is in milli amperes.
• However, since it acts as a constant current source, its dynamic resistance (ac) is very high.
• Hence, a current mirror can also be used as an active load for an amplifier to obtain a very large voltage gain.
• The figure 2.29 (a) shows a diff-amp with an active load.
Active Load
Active Load • The current mirror uses pnp transistors Q3 and Q4.
• The constant current IQ may also be obtained from a current mirror.
• The operation of the circuit is as follows:
• Under the quiescent conditions, V1=V2=0.
• From symmetry of Q1 and Q2, I1=I2=IQ/2 where base currents are assumed to be neglected.
• Since Q3 and Q4 form a current mirror, I=I1=I2.
• The load current IL entering the next stage is IL=I - I2=0.
Active Load • However, when V1 is increased over V2, I1
increases whereas I2 decreases, since I1+I2=IQ(constant).
• Also the current I always remains equal to I1 due to the current mirror.
• The load current is given by IL = I – I2 = I1 - I2
= gmV1 - gmV2
= gm(V1 - V2)= gm Vd
• The circuit thus behaves as a transconductance amplifier.
Level Translator • There are two good reasons for using a level
shifter in an IC op-amp. • As we want an op-amp to operate down to dc, no
coupling capacitor is used. • Because of direct coupling, the de level rises from
stage to stage. • The increase in de level tends to shift the
operating point of the next stage. • This, in turn, limits the output voltage swing and
may even distort the output signal. • It, therefore, becomes essential that the quiescent
voltage of one stage is shifted before it is applied to the next stage.
Level Translator • Another requirement to be satisfied is that the
output should have quiescent voltage level of 0V for zero input signal.
• The simplest type of a level shifter is shown in fig. • It may be noted that this is
basically an emitter follower. • Hence the level shifter also acts
as a buffer to isolate the high gainstages from the output stagegain stages from the output stage.
• The amount of shift obtained
Level Translator • If this shift is insufficient, the
output can be taken at the junction of two resistors R1 and R2, as shown in fig.
• The voltage shift is now increased by the drop across R1.
• However, this arrangement has the disadvantage that signal voltage also gets attenuated by R2/(R1 + R2).
Level Translator • This can be easily circumvented
if R2 is replaced by a current
mirror I as shown in fig
• The shift in level now is
• There is no ac
attenuation due to
high resistance of the
current source.
Level Translator • Another voltage source
commonly used in µA741
op-amp is shown in fig.
• It can be seen that if base
current is negligible compared
to the current in R3 and R4,
then the circuit behaves
as a VBE multiplier as,
Output Stage • The function of the last stage, i.e., the output
stage in an op-amp is to supply the load current and provide a low impedance output.
• A simple output stage is an emitter follower with complementary transistors as shown in fig.
• It can be seen that for Vi positive, transistor Q1 is on and supplies current to load RL.
• If Vi is negative, Q1 is cut off and Q2 acts as a sink to remove current from the load RL.
• There is, however, a limitation in this circuit.
• The output voltage Vo remains zero until the input Vi exceeds VBE(cut in)=0.5 V.
Output Stage
• This is called cross-over distortion.
• It can be eliminated by applying a bias voltage V slightly greater than 2 VBE(cutin) = 1 V between the two bases, so that a small current flows in the transistors even in the quiescent state.
Output Stage
• This is called cross-over distortion.
• It can be eliminated by applying a bias voltage V slightly greater than 2 VBE(cutin) = 1 V between the two bases, so that a small current flows in the transistors even in the quiescent state.
Output Stage • The output stage of IlA 741
op-amp is shown in • The block marked V is the
VBE multiplier of the type shown in fig.
• It is designed to supply a voltage of about 1V between the bases of the complementary pair of transistors Q14 and Q15.
• The small emitter resistors (250) stabilize the quiescent base current.
Conclusion • In this session we have discussed about
– The pin configuration and the complete schematic circuit diagram for 741.
– Analysis of Differential Amplifiers – Circuits for improving CMRR. – Various types of current sources/mirrors.– Input Resistance– Active Load – Level Translator– Output Stage
