741 Op-Amp IC

By :

Mr. Himanshu Diwakar

Assistant Professor

JETGI

JETGI 1Himanshu Diwakar

Introduction

• With respect to operational amplifiers, a typical configuration is shown in block diagram form

JETGI 2Himanshu Diwakar

Bias Circuitry

• The reference bias current for the entire 741 circuit is generated in the

branch containing the diode-connected transistors Q11 and Q12 and the

resistor R5.

• The bias current for the first stage is generated in the collector of Q10 from

the Widlar current source composed of Q10, Q11 and R4.

• The current mirror formed by transistors Q8 and Q9 provide the bias current

(IEE) of the differential amplifier formed by Q1, Q2, Q3 and Q4.

JETGI 3Himanshu Diwakar

JETGI 4Himanshu Diwakar

The 741 Op-Amp

JETGI 5Himanshu Diwakar

Cont’d

• The 741 is internally compensated by means of an on-chip resistor-capacitor (RC) network.

• We’re going to talk about frequency response, compensation and stability in future sections, but for now we’re just going to define the internal compensation of the 741 as the means by which the op-amp maintains stability while still having a high gain and large operational frequency range (i.e., bandwidth).

JETGI 6Himanshu Diwakar

Short Circuit Protection Circuitry

• The 741 circuit contains several transistors that are normally off and that turn on (conduct) only when a large current exists at the output. In the circuit above, the short circuit protection is provided by Q15, Q21, Q22, Q24, R6 and R7.

• The function of this network is to limit the current in the output transistors – all to prevent overheating and possible burnout of the IC (i.e., it keeps from letting the smoke out).

• Refer to the figure above for the following analysis of the short circuit protection circuitry.

JETGI 7Himanshu Diwakar

Cont’d

• The transistor Q15 is the normally off state. If the current in the emitter leg of Q14 becomes too large, the voltage drop across R6 will become large enough to turn Q15 on.

• Once Q15 is turned on, its collector will bleed off some of the current supplied by Q13, thereby reducing the base current to Q14 and the emitter current of Q14.

• This limits the maximum current that the op-amp can source, or supply from the output terminal in the outward direction.

JETGI 8Himanshu Diwakar

Cont’d• The current through Q20 is limited in a similar fashion, where the

relevant components are Q21, Q22, Q24, and R7.

• If the current through Q20 becomes too large, the voltage drop across R7 turns Q21 on. Once Q21 is turned on, its collector will bleed off some of the current supplied by the current mirror formed by Q22 and Q24, reducing the base current (and therefore the emitter current) of Q20.

• This mechanism limits the maximum current that the op-amp can sink, or draw from the output terminal in the inward direction.

JETGI 9Himanshu Diwakar

Input stage

JETGI 10Himanshu Diwakar

JETGI 11Himanshu Diwakar

The load circuit of the input stage fed by the two complementary current signals generated by Q1 through Q4 in Fig. shown on previous slide Circled numbers indicate the order of the analysis steps.

JETGI 12Himanshu Diwakar

JETGI 13Himanshu Diwakar

Figure Simplified circuits for finding the two components of the output resistance Ro1 of the first stage.

JETGI 14Himanshu Diwakar

• Output resistance (R01) of the input stage is the resistance seen looking back onto the collector of transistor Q6 .

• From the figure shown on slide 64, we can say that, R01 is equal to the parallel combination of the output resistance of the current source ie and the output resistance of Q6 .

• Assume that the base of Q4 is virtual ground.

JETGI 15Himanshu Diwakar

Second stage

Figure The 741 second stage prepared for small-signal analysisJETGI 16Himanshu Diwakar

• This is used to determine the values of the parameters of the equivalent circuit.

• Input Resistance: The resistance Ri2 is given by

• Trans conductance: from the small-signal equivalent circuit model of the second stage, we can observe that,

JETGI 17Himanshu Diwakar

JETGI 18Himanshu Diwakar

OUTPUT STAGE

JETGI 19Himanshu Diwakar

FREQUENCY RESPONSE

JETGI 20Himanshu Diwakar

Cont’d

• Frequency response of the op-amp is the plot of its open loop gain versus frequency.

• The open loop gain changes with frequency.

• To plot the frequency response we need to refer high frequency model of OP-AMP.

• After a certain frequency the rolloff decreases after certain frequency.

• The capacitor is due to BJT used in the 741.

• The BJTs has parasitic capacitances so the capacitances is too small.

• So in order to reduces the effect of this parasitic capacitances the compensated capacitor is used in 741.

JETGI 21Himanshu Diwakar

JETGI 22Himanshu Diwakar

SLEW RATE

JETGI 23Himanshu Diwakar

• Consider the unity-gain follower shown on previous slide.

• 10 volt step is applied at the input.

• The entire value of the step signal will appear as a differential signal between the two input terminals.

JETGI 24Himanshu Diwakar

Cont’d

• From the circuit shown on previous slide, wee see that, output voltage ramp with a slope of 2I/CC .

• So the slew rate is given by:

For 741 SR = 0.63 V/µs.

JETGI 25Himanshu Diwakar

ALL THE BEST FOR EXAMS

JETGI 26Himanshu Diwakar