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On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim [email protected]

On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim [email protected]

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Page 1: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

On-Chip Inductance Extraction

- Concept & Formulae –

2002. 3

Hyungsuk Kim

[email protected]

Page 2: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

OutLine

Introduction – On-Chip Inductance Loop Inductance and Partial Inductance Closed Forms of Inductance Formulae

Self Inductance Formulae- Hoer, FastHenry, Ruehli, Grover

Mutual Inductance Formulae- Hoer (FastHenry), Ruehli, Grover

Computational Results Conclusion

Page 3: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Introduction – On-Chip Inductance

As the clock frequency grows fast, the reactance becomes larger for on-chip interconnections

Z = R + jwL w is determined not by clock frequency itself but by clock

edge

w ~ 1/(rising time)

More layers are applied, wider conductors are used Wide conductor => low resistance

Multiple layer interconnections make complex return loops Inductance is defined in the closed loop in EM

Page 4: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Loop Inductance

jkifIforI

L kj

ijij 0

i a

iiiji

ij

i

dadlAa

1

Loop inductance is defined as the induced magnetic flux in the loop by the unit current in other loop

where, represents the magnetic flux

in loop i due to a current Ij in loop j

ijLoop i Loop j

Ij

ij

The average magnetic flux can be calculated by magnetic vector potential Aij

ij

where, ai represents a cross section of loop i

Page 5: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Loop Inductance (cont’d)

j a ij

jj

j

jij

jr

dadl

a

IA

4

jconductorofareacrossa

jconductorofelementdl

rrrwhere

j

j

jiij

:

:

,

i a j a

jiij

ji

jiij

i j

dadar

dldl

aaL

1

4

The magnetic vector potential A, defined by B = A, has an integral form

So, loop inductance is

Page 6: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Partial Inductance

Problems of loop inductance The loops (called return paths) are

hardly defined explicitly in VLSI In most cases, the return paths

are multiple

Partial inductance proposed by A. Ruehli The return path is assumed at infinite

for each conductor segment It can be directly appliable to circuit simulator like SPICE

1

2

3

4

5

Page 7: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Partial Inductance (cont’d)

K

k

c

bi

k

k1

K

k

M

m a a

c

b

c

b

mkkm

mk

mkij

k m

k

k

m

m

dadar

dldl

aaL

1 1

1

4

M

m

c

bj

m

m1

(assume loop i consists of K segments and loop j does M segments)So, loop inductance is

i a j a

jiij

ji

jiij

i j

dadar

dldl

aaL

1

4

Loop inductance between loop i and j is

Page 8: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Partial Inductance (cont’d)

k m

k

k

m

m

km

a a

c

b

c

b

mkkm

mk

mkP dada

r

dldl

aaL

||1

4

K

k

M

mPkmij km

LSL1 1

Definition of partial inductance

The sign of partial inductance is not considered So, partial inductance is solely dependent of conductor geometry

Sign rule for partial inductance

where, Skm = +1 or –1

The sign depends on the direction of current flow in the conductors

Page 9: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Geometry and Formulae

Conductor Geometry

Inductance Formulae Self Inductance : Grover(1962), Hoer(1965), Ruehli(1972),

FastHenry(1994) Mutual Inductance : Grover(1962), Hoer(FastHenry)(1965),

Ruehli(1972)

x z

Dx

Dy

Dz

y

Conductor 1 Conductor 2

T

W

l

(a) Single Conductor (b) Two Parallel Conductors

Page 10: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Self Inductance

Grover’s Formula

e

TW

l

l

Le

i

ii log2

12ln002.0

l

TW

TW

l

l

L

i

ii )(2235.0

2

12ln002.0

T/W logee T/W logee T/W logee T/W logee

0 0 0.2 0.00249 0.5 0.00211 0.8 0.00181

0.05 0.00146 0.3 0.00244 0.6 0.00197 0.9 0.00178

0.1 0.00210 0.4 0.00228 0.7 0.00187 1.0 0.00177

Grover 2(without table)

Page 11: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Self Inductance (cont’d)

Hoer’s Formula

)()()(tan6

tan6

tan6

33360

1ln

24244

ln24244

ln24244

008.0

000

222

13

222

13

222

13

222222222444

22

2224422

22

2224422

22

2224422

22

zyxzyxx

yzyzx

zyxy

xzzxy

zyxz

xyxyz

zyxxzzyyxzyxyx

zyxzz

yxyx

xz

zyxyy

zxxz

zy

zyxxx

zyzy

TWL

lTW

ii

2

1

2

1

2

1

1 ),,()1()()()(),,(1

2

1

2

1

2i j k

kjikji

s

s

r

r

qq srqfzyxzyxfwhere

Page 12: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Self Inductance (cont’d)

Ruehli’s Formula

3142

3

63

3

51

2

3

4314222412712

4

17

4

16

4

12

542

2

2

73

2

34

2

6252

2

60ln

24

1ln

242060

11

60

1

20ln

24

1

tan6

1

4tan

64tan

6420

1

60ln

2460ln

24

11ln

24

2

AuAAu

Au

Au

Au

AuAA

uAA

uA

uAA

uAAu

A

uA

A

uA

u

uA

uA

uAA

u

Au

AAu

AAu

AAu

AA

ul

L

i

ii

2

47

1

46

3

45

224

223

22

21

lnln1

ln1

11

A

AuA

A

AA

A

AAuA

uAAuAW

T

W

lu

.1

111

ln31

1ln36

2

3

3

2

3

4

222

uu

uuu

uuuu

l

L

i

ii

where

If T/W < 0.01

Page 13: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Self Inductance (cont’d)

FastHenry’s Formula

aratarawarraratatawawar

atawar

arawawwwrrar

wawwrar

aratatttrrar

tattrar

arw

t

t

w

art

w

w

t

ar

tw

tw

arataw

wt

wtarawat

tw

twarawrw

t

t

w

aratrt

w

w

t

arraww

t

t

w

arratt

w

w

t

raw

t

tat

w

wLii

111

20

1

))(1)(1)((

)1(

))()()((

)(

))()()((

)(

60

1tantantan

1

6

1

)(sinh

1

)(sinh

1

)(sinh

)(sinh

)(sinh

)(sinh

24

11sinhsinh

1sinh

1

4

12

2

2111

21

2

21

2

21

2

221

2

2

12

12

111

111 2222

22

twartatwaw

twrl

Tt

l

Wwwhere

Page 14: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu
Page 15: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu
Page 16: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu
Page 17: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Comparisons of Self Inductance

Formula Short Conductor(l/W < 10)

Medium Conductor

(10 < l/W < 1000)

Long Conductor(l/W > 1000)

Hoer O O X

FastHenry O O O

Ruehli X O X

Ruehli (T=0) O (30% larger)

(T/W < 0.01)

O(T/W < 0.01)

O(T/W < 0.01)

Grover X O O

Grover2 X O O

Page 18: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Mutual Inductance

Ruehli’s Formula

Grover’s Formula (single filament)

4

1

22221 ln14 m

mmmmm

i

ij rgrgggl

L

22222222

1111 sinhsinhsinhsinh001.0

dddd

ddddLij

where pgvpgvpgpgl

DyDxr

l

Dzp

l

lv

iii

j

4321

22

11

mlmlxxx 1lnsinh 21where

Page 19: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Mutual Inductance (cont’d)

Hoer’s Formula (multiple filaments)

)()()(tan6

tan6

tan6

33360

1ln

24244

ln24244

ln24244

001.0

21

12

21

12

21

12

,

,

,

,

,

,

222

13

222

13

222

13

222222222444

22

2224422

22

2224422

22

2224422

2121

zyxzyxx

yzyzx

zyxy

xzzxy

zyxz

xyxyz

zyxxzzyyxzyxyx

zyxzz

yxyx

xz

zyxyy

zxxz

zy

zyxxx

zyzy

TTWWL

lDlD

DllD

TDTD

DTTD

WDWD

DWWD

ij

zz

zz

xx

xx

yy

yy

where

4

1

4

1

4

1

1,

,

,

,

,, ),,()1()()()(),,(

31

42

31

42

31

42i j k

kjikji

ss

ss

rr

rr

qqqq srqfzyxzyxf

Page 20: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu
Page 21: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu
Page 22: On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

Conclusion

On-Chip inductance becomes a troublemaker in high-performance VLSI design Higher clock frequency, wide interconnections, complex

return paths The concept of partial inductance is useful in VLSI area

Not related to the return path Only dependent of geometry

Several inductance formulae are in hand but they have Different computational complexities Different applicable ranges according to the geometry