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Numeric Components

September 2004

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Contents1 Numeric Advanced Communications Components

Introduction............................................................................................................... 1-1AddGuard ................................................................................................................. 1-2ConvolutionalCoder .................................................................................................. 1-7CRC_Coder .............................................................................................................. 1-10CRC_Decoder .......................................................................................................... 1-12Deinterleaver802 ...................................................................................................... 1-14Demapper................................................................................................................. 1-17Interleaver802........................................................................................................... 1-23LoadIFFTBuff802...................................................................................................... 1-26Mapper ..................................................................................................................... 1-30MuxOFDMSym802 ................................................................................................... 1-36RMSE ....................................................................................................................... 1-41ViterbiDecoder.......................................................................................................... 1-43

2 Numeric Communications ComponentsIntroduction............................................................................................................... 2-1ADPCM_Coder......................................................................................................... 2-2ADPCM_Decoder ..................................................................................................... 2-4ADPCM_FromBits .................................................................................................... 2-6ADPCM_ToBits......................................................................................................... 2-7AWGN_Channel ....................................................................................................... 2-8BlockPredictor .......................................................................................................... 2-10CoderRS................................................................................................................... 2-12DecoderRS............................................................................................................... 2-15DeScrambler............................................................................................................. 2-21DeSpreader .............................................................................................................. 2-23FreqPhase ................................................................................................................ 2-24HilbertSplit ................................................................................................................ 2-26InterleaveDeinterleave.............................................................................................. 2-28NoiseChannel ........................................................................................................... 2-30NonlinearDistortion................................................................................................... 2-31PAM2Rec.................................................................................................................. 2-32PAM2Xmit ................................................................................................................. 2-33PAM4Rec.................................................................................................................. 2-35PAM4Xmit ................................................................................................................. 2-36PCM_BitCoder.......................................................................................................... 2-38PCM_BitDecoder...................................................................................................... 2-39PhaseShift ................................................................................................................ 2-40PSK2Rec .................................................................................................................. 2-41

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PSK2Xmit ................................................................................................................. 2-43QAM16 ..................................................................................................................... 2-45QAM16Decode ......................................................................................................... 2-46QAM16Slicer ............................................................................................................ 2-47QAM4 ....................................................................................................................... 2-48QAM4Slicer .............................................................................................................. 2-50QAM64 ..................................................................................................................... 2-51QAM64Decode ......................................................................................................... 2-52QAM64Slicer ............................................................................................................ 2-53RaisedCosine ........................................................................................................... 2-54RaisedCosineCx....................................................................................................... 2-57RecSpread................................................................................................................ 2-59Scrambler ................................................................................................................. 2-60Spread ...................................................................................................................... 2-64TelephoneChannel.................................................................................................... 2-65WalshCoder .............................................................................................................. 2-67XmitSpread............................................................................................................... 2-70

3 Numeric Control ComponentsIntroduction............................................................................................................... 3-1ActivatePath.............................................................................................................. 3-2ActivatePath2............................................................................................................ 3-4AsyncCommutator .................................................................................................... 3-6AsyncDistributor ....................................................................................................... 3-8Bus ........................................................................................................................... 3-10BusMerge2 ............................................................................................................... 3-11BusMerge3 ............................................................................................................... 3-12BusMerge4 ............................................................................................................... 3-13BusMerge5 ............................................................................................................... 3-14BusMerge6 ............................................................................................................... 3-16BusMerge7 ............................................................................................................... 3-18BusMerge8 ............................................................................................................... 3-20BusMerge9 ............................................................................................................... 3-22BusSplit2 .................................................................................................................. 3-24BusSplit3 .................................................................................................................. 3-25BusSplit4 .................................................................................................................. 3-27BusSplit5 .................................................................................................................. 3-29BusSplit6 .................................................................................................................. 3-31BusSplit7 .................................................................................................................. 3-33BusSplit8 .................................................................................................................. 3-35BusSplit9 .................................................................................................................. 3-37Chop ......................................................................................................................... 3-39

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ChopVarOffset .......................................................................................................... 3-42Commutator.............................................................................................................. 3-43Commutator2............................................................................................................ 3-44Commutator3............................................................................................................ 3-45Commutator4............................................................................................................ 3-47Delay ........................................................................................................................ 3-49DeMux ...................................................................................................................... 3-50DeMux2 .................................................................................................................... 3-52Distributor ................................................................................................................. 3-53Distributor2 ............................................................................................................... 3-55Distributor3 ............................................................................................................... 3-56Distributor4 ............................................................................................................... 3-58DownSample ............................................................................................................ 3-60EnableUDSample ..................................................................................................... 3-62Fork .......................................................................................................................... 3-64Fork2 ........................................................................................................................ 3-66Fork3 ........................................................................................................................ 3-68Fork4 ........................................................................................................................ 3-70Fork5 ........................................................................................................................ 3-72Fork6 ........................................................................................................................ 3-74Fork7 ........................................................................................................................ 3-76Fork8 ........................................................................................................................ 3-78Fork9 ........................................................................................................................ 3-80IfElse......................................................................................................................... 3-82InitDelay.................................................................................................................... 3-86Mux........................................................................................................................... 3-87Mux2......................................................................................................................... 3-89Repeat ...................................................................................................................... 3-91Reverse .................................................................................................................... 3-92Trainer....................................................................................................................... 3-93Transpose ................................................................................................................. 3-95UpSample................................................................................................................. 3-96

4 Numeric Logic ComponentsIntroduction............................................................................................................... 4-1DFF........................................................................................................................... 4-2DivByN...................................................................................................................... 4-5JKFF......................................................................................................................... 4-8LFSR ........................................................................................................................ 4-11Logic ......................................................................................................................... 4-19LogicAND ................................................................................................................. 4-20LogicAND2 ............................................................................................................... 4-21

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LogicInverter............................................................................................................. 4-22LogicLatch ................................................................................................................ 4-23LogicNAND............................................................................................................... 4-25LogicNAND2............................................................................................................. 4-26LogicNOR................................................................................................................. 4-27LogicNOR2............................................................................................................... 4-28LogicOR.................................................................................................................... 4-29LogicOR2.................................................................................................................. 4-30LogicXNOR............................................................................................................... 4-31LogicXNOR2............................................................................................................. 4-32LogicXOR ................................................................................................................. 4-33LogicXOR2 ............................................................................................................... 4-34Multiple ..................................................................................................................... 4-35Test ........................................................................................................................... 4-36TestEQ...................................................................................................................... 4-38TestGE...................................................................................................................... 4-39TestGT ...................................................................................................................... 4-40TestLE....................................................................................................................... 4-42TestLT ....................................................................................................................... 4-44TestNE ...................................................................................................................... 4-46

5 Numeric Math ComponentsIntroduction............................................................................................................... 5-1Abs ........................................................................................................................... 5-2Add ........................................................................................................................... 5-3Add2 ......................................................................................................................... 5-4AddCx....................................................................................................................... 5-5AddCx2..................................................................................................................... 5-6AddFix ...................................................................................................................... 5-7AddFix2 .................................................................................................................... 5-9AddInt ....................................................................................................................... 5-11AddInt2 ..................................................................................................................... 5-12Average .................................................................................................................... 5-13AverageCx ................................................................................................................ 5-14Cos ........................................................................................................................... 5-15DB............................................................................................................................. 5-16DivByInt .................................................................................................................... 5-18Exp ........................................................................................................................... 5-19Floor ......................................................................................................................... 5-20Gain .......................................................................................................................... 5-21GainCx...................................................................................................................... 5-22GainFix ..................................................................................................................... 5-23

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GainInt ...................................................................................................................... 5-25Integrate ................................................................................................................... 5-26Ln.............................................................................................................................. 5-28Math.......................................................................................................................... 5-29MathCx ..................................................................................................................... 5-31MaxMin ..................................................................................................................... 5-33Modulo...................................................................................................................... 5-35ModuloInt.................................................................................................................. 5-36Mpy........................................................................................................................... 5-37Mpy2......................................................................................................................... 5-38MpyCx ...................................................................................................................... 5-39MpyCx2 .................................................................................................................... 5-40MpyFix ...................................................................................................................... 5-41MpyFix2 .................................................................................................................... 5-43MpyInt ....................................................................................................................... 5-45MpyInt2..................................................................................................................... 5-46Reciprocal................................................................................................................. 5-47SDC1........................................................................................................................ 5-49SDC2........................................................................................................................ 5-50SDC3........................................................................................................................ 5-51SDC4........................................................................................................................ 5-52SDCCx1.................................................................................................................... 5-54SDCCx2.................................................................................................................... 5-55SDCCx3.................................................................................................................... 5-56SDCCx4.................................................................................................................... 5-58Sgn ........................................................................................................................... 5-60Sin ............................................................................................................................ 5-61Sinc........................................................................................................................... 5-62Sqrt........................................................................................................................... 5-63Sub ........................................................................................................................... 5-64SubCx....................................................................................................................... 5-65SubFix ...................................................................................................................... 5-66SubInt ....................................................................................................................... 5-68Trig............................................................................................................................ 5-69TrigCx ....................................................................................................................... 5-70Variance.................................................................................................................... 5-71

6 Numeric Matrix ComponentsIntroduction............................................................................................................... 6-1Abs_M ...................................................................................................................... 6-2Add_M ...................................................................................................................... 6-3Add2_M .................................................................................................................... 6-4

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AddCx_M.................................................................................................................. 6-5AddCx2_M................................................................................................................ 6-6AddFix_M ................................................................................................................. 6-7AddFix2_M ............................................................................................................... 6-9AddInt_M .................................................................................................................. 6-11AddInt2_M ................................................................................................................ 6-12AvgSqrErr_M ............................................................................................................ 6-13Conjugate_M ............................................................................................................ 6-15Delay_M ................................................................................................................... 6-16Gain_M..................................................................................................................... 6-17GainCx_M................................................................................................................. 6-18GainFix_M ................................................................................................................ 6-19GainInt_M................................................................................................................. 6-21Hermitian_M ............................................................................................................. 6-22Inverse_M................................................................................................................. 6-23InverseCx_M............................................................................................................. 6-24InverseFix_M ............................................................................................................ 6-25InverseInt_M............................................................................................................. 6-27Kalman_M ................................................................................................................ 6-28Matlab_M.................................................................................................................. 6-30MatlabCx_M ............................................................................................................. 6-32MatlabF_M................................................................................................................ 6-34MatlabFCx_M ........................................................................................................... 6-36MatlabLibLink ........................................................................................................... 6-38MatlabLibLinkCx ....................................................................................................... 6-40MatlabSink................................................................................................................ 6-42MatlabSinkF.............................................................................................................. 6-44Mpy_M...................................................................................................................... 6-46MpyCx_M ................................................................................................................. 6-47MpyFix_M ................................................................................................................. 6-49MpyInt_M.................................................................................................................. 6-51MpyScalar_M............................................................................................................ 6-52MpyScalarCx_M ....................................................................................................... 6-53MpyScalarFix_M....................................................................................................... 6-54MpyScalarInt_M........................................................................................................ 6-56MxCom_M ................................................................................................................ 6-57MxDecom_M ............................................................................................................ 6-59Pack_M..................................................................................................................... 6-61PackCx_M ................................................................................................................ 6-62PackFix_M................................................................................................................ 6-63PackInt_M................................................................................................................. 6-65SampleMean_M ....................................................................................................... 6-66

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Sub_M ...................................................................................................................... 6-67SubCx_M.................................................................................................................. 6-68SubFix_M ................................................................................................................. 6-69SubInt_M .................................................................................................................. 6-71SubMx_M ................................................................................................................. 6-72SubMxCx_M............................................................................................................. 6-74SubMxFix_M............................................................................................................. 6-76SubMxInt_M ............................................................................................................. 6-78SVD_M ..................................................................................................................... 6-80Table_M .................................................................................................................... 6-82TableCx_M................................................................................................................ 6-84TableInt_M ................................................................................................................ 6-86Toeplitz_M ................................................................................................................ 6-88ToeplitzCx_M ............................................................................................................ 6-90ToeplitzFix_M............................................................................................................ 6-92ToeplitzInt_M ............................................................................................................ 6-95Transpose_M ............................................................................................................ 6-97TransposeCx_M........................................................................................................ 6-98TransposeFix_M ....................................................................................................... 6-99TransposeInt_M ........................................................................................................ 6-100UnPk_M.................................................................................................................... 6-101UnPkCx_M ............................................................................................................... 6-102UnPkFix_M............................................................................................................... 6-103UnPkInt_M................................................................................................................ 6-105

7 Numeric Signal Processing ComponentsIntroduction............................................................................................................... 7-1Autocor ..................................................................................................................... 7-2Biquad ...................................................................................................................... 7-4BiquadCascade ........................................................................................................ 7-6BlockAllPole.............................................................................................................. 7-8BlockFIR ................................................................................................................... 7-10BlockLattice .............................................................................................................. 7-12BlockRLattice............................................................................................................ 7-14Burg .......................................................................................................................... 7-16Convolve................................................................................................................... 7-18ConvolCx .................................................................................................................. 7-20CrossCorr ................................................................................................................. 7-22DTFT ........................................................................................................................ 7-25FFT_Cx..................................................................................................................... 7-27FIR............................................................................................................................ 7-29FIR_Cx ..................................................................................................................... 7-32

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FIR_Fix ..................................................................................................................... 7-35Hilbert ....................................................................................................................... 7-39IIR ............................................................................................................................. 7-41IIR_Cx....................................................................................................................... 7-44IIR_Fix ...................................................................................................................... 7-46Lattice ....................................................................................................................... 7-49LevDur ...................................................................................................................... 7-52LMS .......................................................................................................................... 7-54LMS_Cx.................................................................................................................... 7-56LMS_Leak ................................................................................................................ 7-59LMS_OscDet ............................................................................................................ 7-61PattMatch.................................................................................................................. 7-64RLattice .................................................................................................................... 7-66SlidWinAvg ............................................................................................................... 7-69

8 Numeric SourcesIntroduction............................................................................................................... 8-1Bits............................................................................................................................ 8-2ComplexExp ............................................................................................................. 8-5Const ........................................................................................................................ 8-6ConstCx.................................................................................................................... 8-7ConstFix ................................................................................................................... 8-8ConstInt .................................................................................................................... 8-10Cx_M ........................................................................................................................ 8-11DataPattern .............................................................................................................. 8-13Diagonal_M .............................................................................................................. 8-15DiagonalCx_M.......................................................................................................... 8-16DiagonalFix_M.......................................................................................................... 8-17DiagonalInt_M .......................................................................................................... 8-19Fix_M........................................................................................................................ 8-20Float_M..................................................................................................................... 8-22IID_Gaussian............................................................................................................ 8-24IID_Uniform .............................................................................................................. 8-25Identity_M................................................................................................................. 8-26IdentityCx_M............................................................................................................. 8-27IdentityFix_M ............................................................................................................ 8-28IdentityInt_M............................................................................................................. 8-30ImpulseFloat ............................................................................................................. 8-31Int_M......................................................................................................................... 8-32NumericExpression .................................................................................................. 8-34NumericSource......................................................................................................... 8-35RampFix ................................................................................................................... 8-37

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RampFloat ................................................................................................................ 8-40RampInt .................................................................................................................... 8-41ReadFile ................................................................................................................... 8-42ReadFilePreProc ...................................................................................................... 8-43Rect .......................................................................................................................... 8-45RectCx...................................................................................................................... 8-46RectCxDoppler ......................................................................................................... 8-47RectFix ..................................................................................................................... 8-49SineGen.................................................................................................................... 8-51WaveForm ................................................................................................................ 8-52WaveFormCx............................................................................................................ 8-54Window..................................................................................................................... 8-56

9 Numeric Special FunctionsIntroduction............................................................................................................... 9-1AdaptLinQuant.......................................................................................................... 9-2Compress ................................................................................................................. 9-4DeadZone................................................................................................................. 9-7Dirichlet..................................................................................................................... 9-9Expand ..................................................................................................................... 9-11LatchClocked............................................................................................................ 9-14Limit .......................................................................................................................... 9-16LinQuantIdx .............................................................................................................. 9-19MuLaw ...................................................................................................................... 9-21OrderTwoInt .............................................................................................................. 9-23PcwzLinear ............................................................................................................... 9-25Polynomial ................................................................................................................ 9-27Quant........................................................................................................................ 9-28QuantIdx ................................................................................................................... 9-30Quantizer .................................................................................................................. 9-32Quantizer2D ............................................................................................................. 9-34SchmittTrig................................................................................................................ 9-38Table ......................................................................................................................... 9-40TableCx..................................................................................................................... 9-42TableInt ..................................................................................................................... 9-44Toggle ....................................................................................................................... 9-46Unwrap ..................................................................................................................... 9-48

10 Numeric Synthesizable DSP ComponentsIntroduction............................................................................................................... 10-1AbsSyn ..................................................................................................................... 10-3AddSyn ..................................................................................................................... 10-5AndSyn ..................................................................................................................... 10-7

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And2Syn ................................................................................................................... 10-9BPSKSyn.................................................................................................................. 10-10BarShiftSyn............................................................................................................... 10-12BitFillSyn................................................................................................................... 10-14BufferSyn.................................................................................................................. 10-15Bus8MergeSyn ......................................................................................................... 10-17Bus8RipSyn.............................................................................................................. 10-19BusMergeSyn ........................................................................................................... 10-21BusRipSyn................................................................................................................ 10-23CastSyn .................................................................................................................... 10-25CombFiltSyn ............................................................................................................. 10-27CompSyn.................................................................................................................. 10-29Comp6Syn................................................................................................................ 10-31ConstSyn .................................................................................................................. 10-33CountCombSyn ........................................................................................................ 10-34CounterSyn............................................................................................................... 10-36DPRamSyn............................................................................................................... 10-38DPSKSyn.................................................................................................................. 10-40Div2ClockSyn ........................................................................................................... 10-42FSMSyn.................................................................................................................... 10-43FixToFloatSyn........................................................................................................... 10-46FloatToFixSyn........................................................................................................... 10-47GainSyn.................................................................................................................... 10-49LCounterSyn............................................................................................................. 10-51MultSyn..................................................................................................................... 10-53MuxSyn..................................................................................................................... 10-55Mux2Syn................................................................................................................... 10-57Mux3Syn................................................................................................................... 10-58Mux4Syn................................................................................................................... 10-60Nand2Syn................................................................................................................. 10-62Nor2Syn.................................................................................................................... 10-63NotSyn...................................................................................................................... 10-64OQPSKSyn............................................................................................................... 10-65Or2Syn ..................................................................................................................... 10-67OrSyn ....................................................................................................................... 10-68PI4DQPSKSyn ......................................................................................................... 10-70PSK8Syn .................................................................................................................. 10-72QPSKSyn ................................................................................................................. 10-74RamSyn.................................................................................................................... 10-76RegSyn..................................................................................................................... 10-78RomSyn.................................................................................................................... 10-80ShiftRegPPSyn......................................................................................................... 10-82

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ShiftRegPSSyn......................................................................................................... 10-84ShiftRegSPSyn......................................................................................................... 10-86SineCosineSyn ......................................................................................................... 10-88SinkRespSyn ............................................................................................................ 10-90SinkStimSyn ............................................................................................................. 10-91XorSyn...................................................................................................................... 10-92Xor2Syn.................................................................................................................... 10-94ZeroInterpSyn........................................................................................................... 10-95

11 Numeric Synthesizable DSP Xilinx ComponentsIntroduction............................................................................................................... 11-1AccumSyn ................................................................................................................ 11-2AddRegSyn .............................................................................................................. 11-5CombFiltSyn ............................................................................................................. 11-7DPRamRegSyn ........................................................................................................ 11-9DualNCOSyn ............................................................................................................ 11-12FIRSyn...................................................................................................................... 11-15FixedGainSyn ........................................................................................................... 11-19IntegratorSyn ............................................................................................................ 11-21MultRegSyn .............................................................................................................. 11-24Mux2Syn................................................................................................................... 11-26Mux3Syn................................................................................................................... 11-27Mux4Syn................................................................................................................... 11-29NCOSyn ................................................................................................................... 11-31RamRegSyn ............................................................................................................. 11-34RomRegSyn ............................................................................................................. 11-37SerialFIRSyn ............................................................................................................ 11-40SineCosineSyn ......................................................................................................... 11-43SubRegSyn .............................................................................................................. 11-45SymFIRSyn .............................................................................................................. 11-47

12 Obsolete Numeric ComponentsCoderConvolution ..................................................................................................... 12-2DecoderViterbi.......................................................................................................... 12-10

A WMAN Example DesignsIntroduction............................................................................................................... A-1Agilent Instrument Compatibility ............................................................................... A-1WMAN IEEE 802.16 Specifications.......................................................................... A-2WMAN System Designs ........................................................................................... A-3

Signal Sources ................................................................................................... A-3Basic Components ............................................................................................. A-6Multiplexing for Frame Structure......................................................................... A-7

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Channel Coding Components ............................................................................ A-7Preambles .......................................................................................................... A-12FCH Structure .................................................................................................... A-14Downlink Burst Generation................................................................................. A-16OFDM Modulation .............................................................................................. A-17Measurements.................................................................................................... A-19

WMAN Design Example Descriptions ...................................................................... A-21Fully-Coded Signal Generation .......................................................................... A-21Transmission Test ............................................................................................... A-25Signal Downloading to ESGc ............................................................................. A-30Key Parameters .................................................................................................. A-31

References ............................................................................................................... A-32Index

xiv

Chapter 1: Numeric AdvancedCommunications Components

IntroductionNumeric Advanced Communications components provide functions for simulation ofadvanced communication systems based on the latest communication technologiesincluding wireless metropolitan access networks (WMAN), wireless local accessnetworks (WLAN), and wireless personal access networks (WPAN).

The MuxOFDMSym802, LoadIFFTBuff802, and AddGuard components provideorthogonal frequency division multiplexing (OFDM) modulation. These componentscan be used for OFDM modulation based on IEEE.802.11a/g, IEEE 802.153a, andIEEE 802.16d standards.

The Mapper and Demapper components provide basic modulation/demodulation andmapping/demapping types BPSK, QPSK, 8PSK, 16QAM, 64QAM, 128QAM, and256QAM.

The ConvolutionalCoder and ViterbiDecoder components provide convolutionalencoding and decoding.

The CRC_Coder and CRC_Decoder components provide code error checking.

The Interleaver802 and Deinterleaver802 components provideinterleaving/deinterleaving functionality based on IEEE 802 standards.

The RMSE component provides EVM calculations for users who want to createsubnet measurements.

ADS examples (accessed from the ADS Main window: File > Example Project >Com_Sys > WMAN_802_16d_TX_prj) demonstrate the use of these components forsimulation as well as WLAN and WMAN system testing. Appendix A, WMANExample Designs discusses designs in this project.

Introduction 1-1

Numeric Advanced Communications Components

AddGuard

Description Guard insertion of OFDM symbolLibrary Numeric, Advanced CommClass SDFAddGuard

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component is used to add a guard interval to IFFT signals, which forms anOFDM symbol. Pre- and post-guard intervals are implemented; all OFDMsystems are supported.

2. IFFTSize specifies the input IFFT signal length.

PreGuard specifies the pre-guard length; PostGuard specifies the post-guardlength. If PreGuard is set to zero, there is no pre-guard; if PostGuard is set tozero, there is no post-guard.

Name Description Default Type Range

IFFTSize IFFT size 64 int [1, ∞)

PreGuard Pre-guard length 16 int [0, IFFTSize]

PostGuard Post-guard length 0 int [0, IFFTSize]

Intersection Guard intersection length 0 int [0, IFFTSize]

Pin Name Description Signal Type

1 In Transmitted signal after IFFT complex

2 Window Window function real


3 Out OFDM output data complex

1-2 AddGuard

Intersection specifies the intersect length of two consecutive OFDM symbols. IfIntersection=0, there is no intersect between symbols. To protect the IFFTsignals, Intersection cannot exceed PreGuard+PostGuard.

IEEE 802 series (802.11a, 802.11g, 802.15.3a, 802.16a, 802.16d) and DVB-Tstandards do not include post-guard and intersection.

3. Each firing IFFTSize tokens are input from pin In.

PreGuard+IFFTSize+PostGuard tokens are input from pin Window.

PreGuard+IFFTSize+PostGuard-Intersection tokens are output.

Pin In is the IFFT signal input, pre-guard and post-guard are addedaccordingly, which forms an OFDM symbol.

Pin Window is used to add a window function to the current OFDM symbol;length is PreGuard+IFFTSize+PostGuard. Users can specify the window valuesand input to this pin. The input of this pin can also be set as a constant value.

• If an intersect does not exist, the OFDM symbol multiplies the window, thenoutputs at pin Out.

• If an intersect does exist, the OFDM symbol multiplies the window; resultsare output after adding the intersecting parts of the previous OFDM symbol.The intersecting parts of the OFDM symbol are then stored as intersectingparts for the next OFDM symbol.

4. An OFDM symbol is formed as described here.

Inverse-Fourier-transforming creates the IFFT signal; time duration is Tb. Acopy of the last time duration Tg of the useful symbol period is added before theIFFT signal (this pre-guard is also called cyclic prefix). A copy of the last timeduration Tc of the useful symbol period is added after the IFFT signal (thispost-guard is also called cyclic postfix). The combined duration is referred to assymbol time Ts. Figure 1-1 illustrates this sequence.

AddGuard 1-3


Figure 1-1. OFDM Symbol Time with Guard Interval

5. Intersection, PreGuard and PostGuard values form consecutive OFDMsymbols.

• Case 1: Intersection>PreGuard, Intersection>PostGuard

Figure 1-2. Intersection > PreGuard, Intersection > PostGuard

For the IFFT signal of the second OFDM symbol, pre-guard, and post-guardare added. Thus, the second OFDM symbol are formed and multiplied bywindow.

The points with Intersection length of the first and second OFDM symbolsare then summed and output first. The points of the second OFDM symbolwith length of PreGuard+IFFTSize+PostGuard-Intersection are then output.The points with Intersection length of the second OFDM symbol are stored asintersecting parts for the next OFDM symbol, as described next.

Let the input be 0, 1, 2, 3, 4, 5 and 6, 7, 8, 9, 10, 11, window is 1,IFFTSize=6, PreGuard=2, PostGuard=2, Intersection=3. With calculationsteps above, the output of the first and second OFDM symbol are 4, 5, 0, 1, 2,3, 4 and 15, 11, 7, 7, 8, 9, 10, respectively. Figure 1-3 illustrates thecalculation.

1-4 AddGuard

Figure 1-3. Case 1: Calculation for Output

• Case 2: Intersection≤ PreGuard, Intersection≤ PostGuard

Figure 1-4. Intersection≤ PreGuard, Intersection≤ PostGuard

This calculation is similar to Case 1. Let the input be 0, 1, 2, 3, 4, 5 and 6,7, 8, 9, 10, 11, window is 1, IFFTSize=6, PreGuard=3, PostGuard=3,Intersection=2. The output of the first and second OFDM symbols are 3, 4, 5,0, 1, 2, 3, 4, 5, 0 and 10, 12, 11, 6, 7, 8, 9, 10, 11, 6, respectively. Figure 1-5illustrates the calculation.

Figure 1-5. Case 2: Calculation for Output

References

[1] IEEE Standard 802.11a-1999, “Part 11: Wireless LAN Medium Access Control(MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer inthe 5 GHz Band,” 1999.

[2] ETSI TS 101 475 v1.1.1, “Broadband Radio Access Networks (BRAN);HIPERLAN Type 2; Physical (PHY) layer,” April, 2000.

[3] ARIB-JAPAN, Terrestrial Integrated Services Digital Broadcasting (ISDB-T);Specification of Channel Coding, Frame Structure and Modulation, Sept.1998.

AddGuard 1-5


[4] ETSI, Digital Video Broadcasting (DVB); Framing structure, channel codingand modulation for digital terrestrial television. EN300 744 v1.2.1, EuropeanTelecommunication Standard, July 1999.

[5] IEEE P802.15-03/268r1, “Multi-band OFDM Physical Layer Proposal for IEEE802.15 Task Group 3a,” September 2003.

[6] IEEE P802.16-REVd/D2-2003, “Draft IEEE Standard for Local andmetropolitan area networks Part 16: Air Interface for Fixed Broadband WirelessAccess Systems,” 2003.

1-6 AddGuard

ConvolutionalCoder

Description Convolutional coderLibrary Numeric, Advanced CommClass SDFConvolutionalCoderDerived From ConvolutionalCodeBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component is used to convolute the input information sequence bit-by-bit.

Name Description Default Sym Type Range

CodingRate Coding rate: rate_1_2,rate_1_3, rate_1_4,rate_1_5, rate_1_6,rate_1_7, rate_1_8

rate_1_2 R enum

ConstraintLength Constraint length 7 K int [3, 14]

Polynomial Generator polynomial 0133, 0171 int array 2^(K-1)+2*n-1,n=1,2,3,...2^(K-2).

ZeroTail Zero tail used to convertconvolutional code to blockcode: NO, YES

NO enum

BitSequenceLength Length of bit squence notincluding tail bits, validwhen ZeroTail=YES

88 N int [1, 65535]


1 In input int


2 Out output int

ConvolutionalCoder 1-7


Each firing, 1/CodingRate Out tokens are produced when 1 In token isconsumed.

A convolutional code is generated by passing the information sequence to betransmitted through a linear finite-state shift register. The shift registergenerally consists of K(k-bit) stages and n linear algebraic function generators.Input data to the encoder (assumed to be binary) is shifted into (and along) theshift register k bits at a time. The number of output bits for each k-bit inputsequence is n bits. Therefore, the code rate is defined as Rc = k/n, which isconsistent with the code rate definition for a block code. The K parameter iscalled the constraint length of the convolutional code.

2. CodingRate (Rc) is the ratio of input bit (k) and output bits (n).ConvolutionalCoder supports the 1/n coding rate only, which implements anRc=1/n rate(n =2,3,4,5,6,7,8) convolution for input data.

Convolutional codes with k/n (k>1) are not supported by this componentbecause: coding and decoding will be more complex; and, even convolutionalcodes with a k/n (k>1) coding rate are used that are typically implemented bypuncturing the convolutional code with a 1/n coding rate.

3. ConstraintLength (K) represents shift register stages.

4. Polynomial is the generator function of the convolutional code. In general, thegenerator matrix for a convolutional code is semi-infinite since the inputsequence is semi-infinite. As an alternative to specifying the generator matrix,a functionally equivalent representation is used in which a set of n vectors isspecified, one vector for each n modulo-2 adder. 1 in the ith position of the vectorindicates that the corresponding stage in the shift register is connected to themodulo-2 adder; 0 in a given position indicates that no connection existsbetween that stage and the modulo-2 adder.

For example, consider the binary convolutional encoder with constraint lengthK=7, k=1, and n=2; refer to Figure 1-6. The connection for y0 is (1, 0, 1, 1, 0, 1,1) from Outputs to Input; the connection for y1 is (1, 1, 1, 1, 1, 0, 1). Thegenerators for this code are more conveniently given in octal form as (0133,0175). So, when k=1, n generators, each of dimension K specify the encoder.

1-8 ConvolutionalCoder

Figure 1-6. Convolutional Code CC(2,1,7)

5. ZeroTail specifies the character of encoder input sequence. If ZeroTail is YES,the input sequence of encoder is divided into blocks. The length of the block isBitSequenceLength. After each block, K-1 zeros are appended as tail bits. Thatis, the total block length of encoder is (BitSequenceLength + K - 1). Theinformation will be used in the decoder to obtain better performance.

6. BitSequenceLength (valid only if ZeroTail is set to YES) is used to specify theinformation bit length, which indicates the length of uncoded bits. Thisparameter can be used to set the same value for the encoder and the decoder.

References

[1]John G. Proakis, Digital Communications (Third edition), Publishing House ofElectronics Industry, Beijing, 1998.

ConvolutionalCoder 1-9


CRC_Coder

Description CRC generatorLibrary Numeric, Advanced CommClass SDFCRC_CoderDerived From CRC_Base

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component is used to add CRC bits to the input information.


ParityPosition Parity bits position: Tail,Head

Tail enum

ReverseData reverse the data sequenceor not: NO, YES

NO enum

ReverseParity reverse the parity bits ornot: NO, YES

NO enum

ComplementParity complement parity bits ornot: NO, YES

NO enum

MessageLength input message length 172 int [1, ∞)

InitialState initial state of encoder 0x0 int [0, ∞)

Polynomial generator polynomial 0x1f13 int [3, ∞)


1 In input data int


2 Out output data int

1-10 CRC_Coder

Each firing, (MessageLength + CRCLength) tokens are produced whenMessageLength tokens are consumed. CRCLength is the length of CRC bitsthat is determined by Polynomial, where 2CRCLength ≤ Polynomial ≤2CRCLength+1.

2. CRC bits can be added to the head or the tail of the information bits by settingParityPosition. The order of CRC bits and the order of information bits can bereversed by setting ReverseData and ReverseParity.

3. Figure 1-7 is an example of a CRC encoder in CDMA2000, where g(x) = x6 + x2 +x + 1, and Polynomial is hex 0x47. The CRC bits are added after the informationbits; the order of the CRC and information bits are not reversed.

• Initially, all shift register elements are set to the InitialState and theswitches are set in the up position.

• The register is clocked the number of times equal to MessageLength.

• Switches are then set in the down position so that the output is a modulo-2addition with a 0 and the successive shift register inputs are 0.

• The register is clocked an additional number of times equal to CRCLengthand the CRC bits are output.

Figure 1-7. CRC Bit Calculation

References

[1]TIA/EIA/IS-2000.2 (PN-4428), Physical Layer Standard for cdma2000 SpreadSpectrum Systems, July 1999.

CRC_Coder 1-11


CRC_Decoder

Description CRC DecoderLibrary Numeric, Advanced CommClass SDFCRC_DecoderDerived From CRC_Base

Parameters

Pin Inputs

Pin Outputs

Notes/Equations


ParityPosition Parity bits position: Tail,Head

Tail enum

ReverseData reverse the data sequenceor not: NO, YES

NO enum

ReverseParity reverse the parity bits ornot: NO, YES

NO enum

ComplementParity complement parity bits ornot: NO, YES

NO enum

MessageLength input message length 172 int [1, ∞)

InitialState initial state of encoder 0x0 int [0, ∞)

Polynomial generator polynomial 0x1f13 int [3, ∞)


1 In input data int


2 Out output data int

3 Parity Parity check int

1-12 CRC_Decoder

1. This component is used to check the CRC bits for CRC frame errors.

Each firing, (MessageLength + CRCLength) tokens are consumed whenMessageLength tokens and one parity token are produced. CRCLength is theCRC bit length determined by Polynomial, where 2CRCLength ≤ Polynomial ≤2CRCLength+1.

2. The message part of the input data is sent to a CRC encoder that has the samePolynomial value as the encoder (CRC_Coder). The CRC bits are then comparedwith the CRC bits in the input data. If they are the same, the CRC check ispassed.

CRC_Decoder 1-13


Deinterleaver802

Description Deinterleave the input dataLibrary Numeric, Advanced CommClass SDFDeinterleaver802

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Deinterleaver802 performs deinterleaving based on IEEE 802 standards. Thiscomponent deinterleaves (the inverse of Interleaver802) input bits with a blocksize corresponding to the number of bits in a single OFDM symbol NCBPS.

Each firing, NCBPS tokens are consumed and NCBPS tokens are produced.

2. Deinterleaving is defined by a two-step permutation; j is used to denote theindex of the original received bit before the first permutation; i is used to denote


s modular factor ofinterleaving

1 int [1, ∞)

l divisor factor of interleaving 16 int [1, ∞)

NCBPS Number of coded bits perOFDM symbol

48 int [1, ∞)

† The configuration of parameters s,l and NCBPS should be considered carefully or unexpected result will occur.


1 In Input real


2 Out Output real

1-14 Deinterleaver802

the index after the first (and before the second) permutation; k is used to denotethe index after the second permutation, before delivering the coded bits to theconvolutional (Viterbi) decoder.

The first permutation is defined by

i = s × floor(j/s) + (j + floor(l × j/ NCBPS )) mod s j = 0, 1, … NCBPS – 1

The function floor (.) denotes the largest integer not exceeding the parameter

The second permutation is defined by

k = l × i – (NCBPS – 1)floor(l × i/NCBPS ) i = 0, 1, … NCBPS – 1

In the equations, s is the modular factor and l is the divisor factor; they arevariable parameters and their values depend on which standard the model isused for.

If this model is used for IEEE 802.11 and HIPERLAN/2

s = max (NBPSC/2, 1), l = 16

where

NBPSC and NCBPS are determined by data rates given in Table 1-1.

If this model is used for IEEE 802.16

s = NBPSC/2, 1) l = 12

where NBPSC and NCBPS are determined by block sizes given in Table 1-2.

Table 1-1. IEEE 802.11 and HIPERLAN/2 Rate-Dependent Values

Data Rate (Mbps) ModulationCodingRate (R)

Coded Bits perSubcarrier

(NBPSC)

Coded Bits perOFDM Symbol

(NCBPS)

Data Bits perOFDM Symbol

(NDBPS)

6 BPSK 1/2 1 48 24

9 BPSK 3/4 1 48 36

12 QPSK 1/2 2 96 48

18 QPSK 3/4 2 96 72

24 (IEEE 802.11a) 16-QAM 1/2 4 192 96

27 (HIPERLAN/2) 16-QAM 9/16 4 192 108

36 16-QAM 3/4 4 192 144

48 (IEEE 802.11a) 64-QAM 2/3 6 288 192

54 64-QAM 3/4 6 288 216

Deinterleaver802 1-15


References



[3] IEEE P802.16-REVd/D2-2003,” Part 16 Air Interface for Fixed BroadcastWireless Access Systems”.

Table 1-2. IEEE 802.16 Bit Interleaver Block Sizes (NCBPS / NBPSC)

Modulation16 Subchannels(Default) 8 Subchannels 4 Subchannels 2 Subchannels 1 Subchannel

QPSK 384/2 192/2 96/2 48/2 24/2

16-QAM 768/4 384/4 192/4 96/4 48/4

64-QAM 1152/6 576/6 288/6 144/6 72/6

1-16 Deinterleaver802

Demapper

Description Demodulator for BPSK, QPSK, 8PSK, 16QAM, 32QAM, 64QAM,128QAM, and 256QAM or demapping according to user defined table.Library Numeric, Advanced CommClass SDFDemapper

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component is used for BPSK, QPSK, 8-PSK, 16-QAM, 32-QAM, 64-QAM,128-QAM and 256-QAM symbol demodulation or for demapping bits accordingto the mapping table.

2. The input signal is assumed to be modulated using the Mapper component. ForQAM modulations, the input signal amplitude must be normalized before inputto the model according to the constellations.

Name Description Default Type

ModType Modulation type: BPSK,QPSK, PSK8, QAM16,QAM32, QAM64,QAM128, QAM256,User_Defined

QPSK enum

MappingTable Constellation table complexarray


1 In input symbol sequence complex


2 Out output bit sequence int

Demapper 1-17


Each firing, when one In token is consumed:

• 1 Out token is produced for BPSK

• 2 Out tokens are produced for QPSK

• 3 Out tokens are produced for 8-PSK

• 4 Out tokens are produced for 16-QAM





For the user-defined mapping table, assuming the size of the array is A, log2(A)Out tokens are produced when one In token is consumed.

3. For BPSK, bit 0 is mapped to 1 and bit 1 is mapped to -1.

4. The QPSK constellation is illustrated in Figure 1-8. The 8-PSK constellation isillustrated in Figure 1-9.

Figure 1-8. QPSK Modulation Constellation

1-18 Demapper

Figure 1-9. 8-PSK Modulation Constellation

5. For 16-QAM, 32-QAM, 64-QAM, 128-QAM and 256-QAM, the constellationpoints in quadrant 1 are converted to quadrants 2, 3 and 4 by changing the twomost significant bits (Ik and Qk) and by rotating the q least significant bitsaccording to Table 1-3.

Constellation diagrams are illustrated in Figure 1-10 through Figure 1-13.

6. For user-defined mapping, the input binary bit sequence is mapped to aconstellation point with the corresponding decimal index specified in theMappingTable parameter.

Table 1-3. Conversion of Constellation Points

Quadrant Most Significant Bit Least Significant Bit Rotation

1 00

2 10 π/2

3 11 π4 01 3π/2

Demapper 1-19


Figure 1-10. 16- and 32-QAM Constellations

Figure 1-11. 64-QAM Constellation

1-20 Demapper



Demapper 1-21


References

[1]EN 300 429, “Digital Video Broadcasting (DVB); Framing structure, channelcoding and modulation for cable systems,” V1.2.1, 1998-04.

1-22 Demapper

Interleaver802

Description Interleave the input bitsLibrary Numeric, Advanced CommClass SDFInterleaver802

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Interleaver802 performs interleaving based on IEEE 802 standards. Encodeddata bits are interleaved by this block interleaver with a block sizecorresponding to the number of bits in a single OFDM symbol NCBPS.

Each firing, NCBPS tokens are consumed and NCBPS tokens are produced.

2. Interleaving is defined by a two-step permutation. The first permutationensures that adjacent coded bits are mapped onto nonadjacent subcarriers. The


s modular factor ofinterleaving

1 int [1, ∞)

l divisor factor of interleaving 16 int [1, ∞)

NCBPS Number of coded bits perOFDM symbol

48 int [1, ∞)

† The configuration of parameters s,l and NCBPS should be considered carefully or unexpected result will occur.


1 In Input int


2 Out Output int

Interleaver802 1-23


second permutation ensures that adjacent coded bits are mapped alternatelyonto less and more significant bits of the constellation, thereby avoiding longruns of low reliability bits.

In the following, k denotes the index of the coded bit before the firstpermutation; i denotes the index after the first and before the secondpermutation; j denotes the index after the second permutation, just prior tomodulation mapping.

The first permutation is defined by

i = (NCBPS /l) (k mod l) + floor(k/l) k = 0, 1, …, NCBPS – 1

The function floor (.) denotes the largest integer not exceeding the parameter.

The second permutation is defined by

j = s × floor(i/s) + (i + NCBPS – floor(l × i/NCBPS )) mod s i = 0, 1, … NCBPS – 1

In the equations, s is the modular factor and l is the divisor factor; they arevariable parameters and their values depend on which standard the model isused for.

If this model is used in IEEE 802.11 and HIPERLAN/2,

s = max (NBPSC /2, 1), l = 16;

where NBPSC and NCBPS are determined by data rates given in Table 1-4.

If this model is used in IEEE 802.16,

s = NBPSC /2, l = 12;

where NBPSC and NCBPS are determined by block sizes given in Table 1-5.

Table 1-4. IEEE 802.11 and HIPERLAN/2 Rate-Dependent Values



(NBPSC)


(NCBPS)


(NDBPS)

6 BPSK 1/2 1 48 24

9 BPSK 3/4 1 48 36

12 QPSK 1/2 2 96 48

18 QPSK 3/4 2 96 72

24 (IEEE 802.11a) 16-QAM 1/2 4 192 96

27 (HIPERLAN/2) 16-QAM 9/16 4 192 108

1-24 Interleaver802

References

[1] IEEE Standard 802.11a-1999, Part 11: Wireless LAN Medium Access Control(MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer inthe 5 GHz Band, 1999.

[2] ETSI TS 101 475 v1.1.1, Broadband Radio Access Networks (BRAN);HIPERLAN Type 2; Physical (PHY) layer, April, 2000.

[3] IEEE P802.16-REVd/D2-2003, Part 16 Air Interface for Fixed BroadcastWireless Access Systems.

36 16-QAM 3/4 4 192 144

48 (IEEE 802.11a) 64-QAM 2/3 6 288 192

54 64-QAM 3/4 6 288 216

Table 1-5. IEEE 802.16 Bit Interleaver Block Sizes (NCBPS /NBPSC)

Modulation16 Subchannels(Default) 8 Subchannels 4 Subchannels 2 Subchannels 1 Subchannel

QPSK 384/2 192/2 96/2 48/2 24/2

16-QAM 768/4 384/4 192/4 96/4 48/4

64-QAM 1152/6 576/6 288/6 144/6 72/6

Table 1-4. IEEE 802.11 and HIPERLAN/2 Rate-Dependent Values (continued)



(NBPSC)


(NCBPS)


(NDBPS)

Interleaver802 1-25


LoadIFFTBuff802

Description Subcarriers loader into IFFT bufferLibrary Numeric, Advanced CommClass SDFLoadIFFTBuff802

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component is used to load transmission data into the IFFT buffer. Eachfiring, Carriers tokens are consumed and 2Order tokens are generated. Forexample, if Carriers=52, Order=7, 52 tokens are consumed and 128 tokens aregenerated.


Carriers Number of subcarriers perOFDM symbol

52 int [1, 8192]

DCCarrier DC carrier: OFF, ON OFF enum

DCPilotValue DC Pilot Value 1.333333+j*0.0 complex

FullSubcarriers Active all sub-carriers: NO,YES

YES enum

SubcarrierList Sub-carrier list -21, -7, 7, 21 int array

Order IFFT points in 2^Order 7 int [(logCarriers/log

2), ∞)


1 In Transmitted signal before IFFT complex


2 Out IFFT input signal, zero padded complex

1-26 LoadIFFTBuff802

2. Data loading is performed as follows.

Assume x(0), x(1), ... , x(N-1) are the inputs that generally represent activesubcarriers defined by users, where N=Carriers. y(0), y(1), ... , y(M-1) are theoutputs, M = 2Order.

when N is even

when N is odd

For example, if Order=4 and Carriers=7, the input carriers are x(0), x(1), x(2),x(3),x(4),x(5),x(6), and the output carrier sequence would be:

0 , x(3) , x(4) , x(5) , x(6) , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , x(0) , x(1) , x(2)

which will be loaded into the IFFT model for the IFFT transformation.

3. DCCarrier and DCPilotValue specify whether DC carrier is used; ifDCCarrier=ON, the DC carrier value is set by DCPilotValue.

In the example provided in note 2, DCCarrier=OFF.

While DCCarrier=ON and DCPilotValue=4/3, the output carriers sequencewould be:

4/3, x(3), x(4), x(5), x(6), 0, 0, 0, 0, 0, 0, 0, 0, x(0), x(1), x(2)in which the first carrier is 4/3 instead of 0.

y i( ) x N2----- i 1–+

i 1 … N2-----, ,==

y i( ) 0 i 0 N2----- 1 … M N

2-----– 1–, ,+,==

y i( ) x i M– N2-----+

i M N2-----– … M 1–, ,==

y i( ) x N 1–2

-------------- i 1–+ i 1 … N 1+

2--------------, ,==

y i( ) 0 i 0 N 1+2

-------------- 1 … M N 1+2

--------------–, ,+,==

y i( ) x i M– N 1–2

--------------– i M N 1–

2--------------– … M 1–, ,==

LoadIFFTBuff802 1-27


4. If FullSubcarriers=YES, all input carriers will be used. If FullSubcarriers=NO,some of the input carriers will be used; SubcarrierList specifies which inputcarriers will be used.

5. SubcarrierList (valid when FullSubcarriers=NO) specifies the positions of theinput carriers to be used as active subcarriers (all subcarriers are zero exceptthose carriers specified).

Assume x(0), x(1), ... , x(N-1) are the input signals that generally representactive subcarriers defined by users, where N=Carriers. y(0), y(1), ... , y(M-1) arethe output of the model, M = 2Order. The corresponding indices of x(0), x(1), ... ,x(N-1) are int(-Carriers/2), int(-Carriers/2)+1, ..., -1, 1, ... , int(Carriers/2)-1,int(Carriers/2).

The active subcarrier loading procedure is performed as follows; assume indexis an element of int(-Carriers/2), int(-Carriers/2)+1, ... , -1, 1, ... ,int(Carriers/2)-1, int(Carriers/2):

when N is even

when N is odd

For example, SubcarrierList=-2, -1, 2, 3, and input carriers are x(0), x(1), x(2),x(3),x(4),x(5),x(6). Indices of the input carriers are -3, -2, -1, 1, 2, 3, 4.

Elements in SubcarrierList must be integer and in (-Carriers/2, Carriers/2), inwhich Carriers is the number of carriers of input, here, it is 7 and index shouldbe in [-3, 3]. In this case, the carrier with index is -2, -1, 2, 3 is used, they arex(1), x(2), x(4), x(5). The output subcarriers are then:

4/3, 0, x(4), x(5), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x(1), x(2).

y index( ) x N2----- index 1–+

index 0>=

y M index+( ) x index N2-----+

index 0<=

y index( ) x N 1–2

-------------- index 1–+ index 0>=

y M index+( ) x index N 1–2

--------------+ index 0<=

1-28 LoadIFFTBuff802

References







LoadIFFTBuff802 1-29


Mapper

Description Modulator for BPSK, QPSK, 8PSK, 16QAM, 32QAM, 64QAM, 128QAM,and 256QAM or mapping according to user defined table.Library Numeric, Advanced CommClass SDFMapper

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component is used to generate BPSK, QPSK, 8-PSK, 16-QAM, 32-QAM,64-QAM, 128-QAM and 256-QAM modulation symbols or bit mappingaccording to the mapping table.

Each firing, one Out token is produced when:

• 1 In token is consumed for BPSK

• 2 In tokens are consumed for QPSK


ModType Modulation type: BPSK,QPSK, PSK8, QAM16,QAM32, QAM64,QAM128, QAM256,User_Defined

QPSK enum

MappingTable Constellation table complexarray


1 In input bit sequence int


2 Out output symbol sequence complex

1-30 Mapper

• 3 In tokens are consumed for 8-PSK

• 4 In tokens are consumed for 16-QAM





For user-defined mapping table, assuming the size of the array is A, one Outtoken is produced when log2(A) In tokens are consumed. For more than oneinput token the input sequence is LSB first and MSB last.

2. For BPSK, bit 0 is mapped to 1; bit 1 is mapped to -1.

3. For QPSK, the constellation diagram is illustrated in Figure 1-14.

4. For 8-PSK, the constellation diagram is given in Figure 1-15.

5. For 16-QAM, 32-QAM, 64-QAM, 128-QAM and 256-QAM, the constellationpoints in quadrant 1 are converted to quadrants 2, 3 and 4 by changing the twomost significant bits (Ik and Qk) and by rotating the q least significant bitsaccording to Table 1-6.

16-QAM, 32-QAM, 64-QAM, 128-QAM and 256-QAM constellation diagramsare illustrated in Figure 1-16 through Figure 1-19.

6. For user-defined mapping, the input binary bit sequence is mapped to aconstellation point with corresponding decimal index in the MappingTable.

Table 1-6. Conversion of Constellation Points

Quadrant Most Significant Bit Least Significant Bit Rotation

1 00

2 10 π/2

3 11 π4 01 3π/2

Mapper 1-31


Figure 1-14. QPSK Constellation

Figure 1-15. 8-PSK Constellation

1-32 Mapper

Figure 1-16. 16- and 32-QAM Constellation


Mapper 1-33




1-34 Mapper

References

[1]EN 300 429, “Digital Video Broadcasting (DVB); Framing structure, channelcoding and modulation for cable systems,” V1.2.1, 1998-04.

Mapper 1-35


MuxOFDMSym802

Description generic OFDM symbol multiplexerLibrary Numeric, Advanced CommClass SDFMuxOFDMSym802

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component is used to multiplex data and pilot subcarriers into the OFDMsymbol for IEEE 802 standards 802.11a, 802.11g, 802.15.3a, 802.16a, and802.16d.


Carriers Number of subcarriers perOFDM symbol

52 int [1, 8192]

DataCarriers Number of data subcarriersper OFDM symbol

48 int [1, 8192]

PilotPosition Standard pilots positions -21, -7, 7, 21 int array

PilotValue Standard pilots values 1.0, 1.0, 1.0,-1.0

complexarray

GuardCarrierPosition Guard carriers positions int array

GuardCarrierValue Guard carriers values complexarray


1 Data data subcarriers input complex

2 Pilot continual pilot value complex


3 Out OFDM symbol output complex

1-36 MuxOFDMSym802

Note OFDM symbols generally consist of continual pilots (CP) and scatteredpilots (SP). Current IEEE 802 standards use CP only. Even though some DAB,DVB-T, and ISDB-T OFDM systems may use both CP and SP,MuxOFDMSym802 supports CP only.

2. The basic OFDM symbol structure is introduced in the frequency domain. Thesymbol (illustrated in Figure 1-20) consists of subcarriers that determine thesize of the FFT. There are several subcarrier types:

• Data subcarriers for data transmission

• Pilot subcarriers for estimations

• Null subcarriers for no transmission, for guard bands and DC subcarrier.

Guard bands in most OFDM systems (DVB-T, ISDB-T, 802.11a, 802.11g,802.16a, and 802.16d) are inserted zeros.

IEEE 802.15.3a has additional guard carriers defined between data subcarriersand guard bands. The guard subcarriers can be used for various purposes,including relaxing the specification on transmit and receive filters. Themagnitude level of the guard tones is not specified, so reduced power levels forthese subcarriers can be used. The all-zeros guard bands allow the signal tonaturally decay and create the FFT brick wall shaping.

Figure 1-20. OFDM Symbol

This component multiplexes data and pilot subcarriers into one OFDM symbolaccording to the positions of data and pilot subcarriers defined in the standards.The null subcarriers (guard bands and DC subcarrier) are inserted into anOFDM symbol by the LoadIFFTBuff802 component. (Both MuxOFDMSym802and LoadIFFTBuff802 components implement an OFDM symbol in thefrequency domain.)

MuxOFDMSym802 1-37


3. MuxOFDMSym802 parameter settings enable users to generate a variety ofOFDM symbol formats, in accordance with IEEE standards or not.

Carriers specifies the number of active subcarriers (data subcarriers, pilotsubcarriers and guard subcarriers) in one OFDM symbol.

Note Carriers = DataCarriers+ PilotPosition+ GuardCarrierPosition.

DataCarriers specifies the number of data subcarriers in one OFDM symbol.

PilotPosition specifies continual pilot positions; PilotPosition is the number ofpilot subcarriers in one OFDM symbol.

PilotValue specifies values for continual pilot positions.

GuardCarrierPosition specifies guard carriers positions (default = NULL);GuardCarrierPosition is the number of guard carrier subcarriers in one OFDMsymbol.

GuardCarrierValue specifies values for guard carrier positions (default =NULL).

4. Each firing, one Pilot token and DataCarriers tokens are consumed andCarriers tokens are output.

The complex Data input signal is directly multiplexed into the OFDM symbol.

The continual pilots are multiplexed into OFDM symbols as follows:

pk is the input in Pilot pin for kth OFDM symbol (or kth firing)a0, a1, ... , an are n+1 pilot values defined by PilotValue

The actual pilot values of kth OFDM symbol are pk × a0, pk × a1, ... , pk × an. Thecontinual pilot subcarrier values are multiplexed into the OFDM symbolaccording to PilotPosition.

The guard carriers are multiplexed into the OFDM symbol like continual pilotas follows:

b0, b1, ... , bm are m+1 guard carriers values specified by GuardCarrierValue.

The actual guard carrier values of kth OFDM symbol are pk × b0, pk × b1, ... , pk× bm.

1-38 MuxOFDMSym802

These guard carrier subcarriers values are multiplexed into the OFDM symbolaccording to GuardCarrierPosition.

5. The MuxOFDMSym802 output includes all active data, pilot, and guardcarriers subcarriers indexed in the frequency domain:

[-(Carriers)/2, -(Carriers)/2+1, ... , -1, 1, ... , (Carriers + 1)/2-1, (Carriers+1)/2]

LoadIFFTBuff802 loads these output signals from MuxOFDMSym802 into theIFFT buffer and inserts zeros into the NULL and DC subcarriers. Figure 1-21illustrates the 802.11a IFFT input and output. An OFDM symbol is input in thefrequency domain after LoadIFFTBuff802; an OFDM symbol is output in thetime domain after IFFT.

Figure 1-21. IFFT Input and Output (802.11a Specification)

References





MuxOFDMSym802 1-39




1-40 MuxOFDMSym802

RMSE

Description Root Mean Square ErrorLibrary Numeric, Advanced CommClass SDFRMSE

Parameters

Pin Inputs

Notes/Equations

1. This component is used to calculate the root mean square error of the inputdata.

Each firing, one token is consumed; after(FramesToAverage+StartFrame) × FrameLength tokens are consumed, theRMSE of the input signal is sinked.

2. The root mean square error is calculated according to the equation


StartFrame Start frame 0 int [0, ∞)

FramesToAverage Number of frames for theaverage RMSE

1 int [1, ∞)

FrameLength Frame length 4096 int [1, ∞)

DisplayOption Display option: RMS, dB RMS enum


1 InRef Input reference signal complex

2 InTest Input test signal complex

RMSE 1N f-------- 1

Lf------- I1 i j,( ) I2 i j,( )–( )2 Q1 i j,( ) Q2 i j,( )–( )2

+( )j

Lf

∑i 1=

N f

∑=

RMSE 1-41


where,

Nf is the number of frames to average

Lf is the frame length

I1(i, j), Q1 (i, j) and I2 (i, j), Q2 (i, j) are the in-phase and quadrature parts,respectively, of the input signals

1-42 RMSE

ViterbiDecoder

Description Viterbi decoder for convolutional codeLibrary Numeric, Advanced CommClass SDFViterbiDecoderDerived From ViterbiDecoderBase

Parameters

Pin Inputs


CodingRate Coding rate: rate_1_2,rate_1_3, rate_1_4,rate_1_5, rate_1_6,rate_1_7, rate_1_8

rate_1_2 R enum

ConstraintLength Constraint length 7 K int [3, 14]

Polynomial Generator polynomial 0133, 0171 int array 2^(K-1)+2*n-1,n=1,2,3,...2^(K-2).

ZeroTail Zero tail used to convertconvolutional code to blockcode: NO, YES

NO enum

BitSequenceLength Length of bit squence notincluding tail bits, validwhen ZeroTail=YES

88 N int [1, 65535]

MaxSurvivorLength Maximum length ofsurvivor, in bits

35 int [5*K, 20*K]

Polarity Mapping mode from NRZto logic signal: Negative tologic 1, Negative to logic 0

Negative to logic1

enum

InitialState Initial state of convolutionalencoder: Zero state,Non-zero state

Zero state enum

IgnoreNumber Number of data points tobe ignored

0 int [0, 65535]


1 In input real

ViterbiDecoder 1-43


Pin Outputs

Notes/Equations

1. This component is used for convolutional code decoding with a Viterbialgorithm.

Generally, there are two ways to implement convolutional code incommunications system: code a semi-infinite bit sequence length where theinitial encoder state could be zero- or non-zero with any final state; or, codeblock-by-block by appending zero tails after bit blocks so that the initial and thefinal encoder states are both zero. The ZeroTail parameter specifies thisimplementation; if ZeroTail =YES, then zero tails must be appended beforeinput to this component.

Each firing, if ZeroTail=YES, (N+K-1) Out tokens are produced, when(N+K-1)/R In tokens are consumed; If ZeroTail = NO, 1 Out token is producedfor 1/R In tokens consumed.

For example, in CDMA access channel, CC(3,1,9) with zero tail is used in whichthe convolutional code rate R is 1/3 and the bit sequence length is 88.CodingRate is set to rate 1/3, ZeroTail=YES and BitSequenceLength=88.Eachfiring, 96 Out tokens are produced when 288 In tokens are consumed.

ViterbiDecoder supports the 1/n coding rate only. Convolutional codes with k/n(k>1) are not supported by this component because: the coding and decodingwill be more complex (this is also the reason why convolutional codes with a k/n(k>1) coding rate are seldom used in real communication systems); and, evenconvolutional codes with a k/n (k>1) coding rate are used that are typicallyimplemented by puncturing the convolutional code with a 1/n coding rate.

2. Polynomial is the convolutional code generator function. The generator matrixfor a convolutional code is generally semi-infinite because the input sequence issemi-infinite. As an alternative to specifying the generator matrix, afunctionally equivalent representation is used in which a set of n vectors isspecified, one vector for each of the n modulo-2 adder. 1 in the ith position of thevector indicates that the corresponding stage in the shift register is connectedto the modulo-2 adder; 0 in a given position indicates that no connection existsbetween that stage and the modulo-2 adder.


2 Out output int

1-44 ViterbiDecoder

For example, consider the binary convolutional encoder with constraint lengthK=7, k=1, and n=2, illustrated in Figure 1-22. The connection for y0 is (1, 0, 1, 1,0, 1, 1) from Outputs to Input, while the connection for y1 is (1, 1, 1, 1, 1, 0, 1).Generators for this code are conveniently given in octal form as (0133, 0175).So, when k=1, n generators (each of dimension K) are required to specify theencoder.

Figure 1-22. Convolutional Code CC(2,1,7)

3. ZeroTail is used to specify the encoder input sequence character. IfZeroTail=YES, the encoder input sequence is divided into blocks; block length isN. After each block, K-1 zeros are appended as tail bits. The total block length ofthe encoder is (N + K - 1). In the decoder, known information can be used toobtain better performance.

4. BitSequenceLength (valid only when ZeroTail=YES) is used to specify theinformation bit length, which indicates the length of uncoded bits. Thisparameter can be set to the same value in the encoder and the decoder.

5. MaxSurvivorLength is the maximum length of the survivor that is stored inmemory.

The delay in decoding a long information sequence that has beenconvolutionally encoded is usually too long for most practical applications;moreover, memory required to store the entire length of surviving sequences islarge and expensive. A solution for this is to modify the Viterbi algorithm insuch a way that results in a fixed decoding delay without significantly affectingthe optimal performance of the algorithm.

The modification is to retain at any given time t only the most recent δ decodedinformations bits in each surviving sequence. As each new information bit isreceived, a final decision is made on the bit received δ branches back in thetrellis, by comparing the metrics in the surviving sequences and determining infavor of the bit in the sequence having the largest metric. If the δ chosen issufficiently large, all surviving sequences will contain the identical decoded bit

ViterbiDecoder 1-45


δ branches back in time. That is, with high probability, all surviving sequencesat time t stem from the same one as t−δ. Experimental simulation hasdetermined that a delay δ ≥ 5K results in a negligible degradation in theperformance relative to the optimum Viterbi algorithm.

6. Polarity is used to specify the mapping mode from bit (0, 1) to the NRZ signallevel. Generally, bit 0 is mapped to level 1 and bit 1 is mapped level -1. Analternative is to map bit 0 to level -1 and bit 1 to level 1.

7. InitialState is used to specify the coded sequence character. If the initial state ofencoder is zero-state, the known information can be used to obtain betterperformance. If the initial state is not known to be zero, InitialState must be setto a non-zero state.

8. IgnoreNumber is used to specify how much data will be ignored by thiscomponent. Delays in communications systems can be caused by devices ortransmission. And, the delay may be inserted between the encoder and decoderin the form of meaningless data, so the information must be set inIgnoreNumber.

• If ZeroTail = YES, the value of IgnoreNumber is n × (N + K - 1)/R (n is aninteger and n ≥ 0), and no extra delay will be introduced because it isassumed the sequence is frame synchronized before input to ViterbiDecoder.

• If ZeroTail = NO, the delay is an integer number n; this means the symbolsynchronization is achieved before ViterbiDecoder. If n/R is also an integer,then the delay of output bit sequence will be n/R bits. Otherwise, the delaywill be the minimum integer larger than n/R.

Input sequence requirements are:

If ZeroTail = YES

• The input sequence must be frame synchronized; that is, IgnoreNumbermust be n × N/R (n is an integer and n ≥ 0) and the first valid data must bethe first symbol of the first codeword in that frame.

• The input sequence must be encoded from blocks, each having K-1 zero tailsso that the initial state and final state are all zero-state.

If ZeroTail = NO

• The input sequence must be bit synchronized; that is, the first valid datamust be the first symbol of a codeword.

1-46 ViterbiDecoder

• If InitialState is set to Zero state, the first valid symbol must be encoded withzero initial state.

9. The Viterbi algorithm is an optimal method of decoding convolutional codes.Optimal decoding decisions cannot be made on a symbol-by-symbol basis;instead, the entire received sequence must be compared with all possibletransmitted sequences. The number of possible transmitted sequencesincreases exponentially with time, so an efficient method of comparingsequences is necessary.

The Viterbi algorithm is computationally efficient, but its complexity increasesexponentially with the constraint length of the code. The Viterbi decodermeasures how similar the received sequence is to a transmitted sequence bycalculating a number called path metric (path metric of a sequence is calculatedby adding numbers known as symbol metric, which is a measure of how close areceived symbol is to each of the possible transmitted symbols). Thetransmitted sequence corresponding to the smallest path metric is declared tobe the most likely sequence.

The Viterbi algorithm for a CC(n,k,K) code is described in the followingparagraphs.

Branch Metric Calculation

The branch metric m(α)j , at the Jth instant of the α path through the trellis is

defined as the logarithm of the joint probability of the received n-bit symbol rj1,

rj2 ... , rjn conditioned on the estimated transmitted n-bit symbol cj1(α), cj2

(α) ... ,

cjn(α) for the α path. That is,

If Rake receiver is regarded as a part of the channel, for the Viterbi decoder thechannel can be considered to be an AWGN channel. Therefore,

Path Metric Calculation

m α( )j P r ji c ji

α( )( )i 1=

n

∏

ln

P r ji c jiα( )( ).ln

i 1=

n

∑=

=

m α( )j r jic ji

i 1=

n

∑=

ViterbiDecoder 1-47


The path metric M(α) for the α path at the Jth instant is the sum of the branchmetrics belonging to the α path from the first instant to the Jth instant.Therefore,

Information Sequence Update

There are 2k merging paths at each node in the trellis and the decoder selectsfrom paths α1, α2, ... , α2k the one having the largest metric, namely:

This path is known as the survivor.

Decoder Output

When the two survivors have been determined at the Jth instant, the decoderoutputs from memory the (J-L)th information symbol survivor with the largestmetric.

10. ViterbiDecoder Component Validation

Table 1-7 lists BER measurements for a rate 1/2 code (g0=171, g1=133) and amemoryless additive white Gaussian channel. Simulations were made withhard decision decoding (binary quantization) and soft decision decoding (noquantization). Simulation results are listed along with results published inQUALCOMM Technical Data Sheet Q0256; note that the published data andsimulation results agree.

Table 1-7. BER Measurements

Eb/No(dB)

Hard Decision Soft Decision

Simulated BER QUALCOMM BER Simulated BERQUALCOMM BER(3 bits)

3.0 3.62e-04 8.00e-04

3.5 7.56e-05 2.00e-04

4.0 5.01e-03 6.50e-03 1.11e-05 3.50e-05

4.5 1.79e-03 1.80e-03 2.12e-06 7.00e-06

5.0 5.71e-04 5.50e-04

5.5 1.25e-04 9.00e-05

6.0 2.81e-05 4.00e-05

M α( ) m α( )j

j 1=

J

∑=

max Mα1( )

Mα2( )

... Mα

2k( )

, , ,( )

1-48 ViterbiDecoder

References

[1]S. Lin and D. J. Costello, Jr., Error Control Coding Fundamentals andApplications, Prentice Hall, Englewood Cliffs NJ, 1983.

[2] J. G. Proakis, Digital Communications (Third edition), Publishing House ofElectronics Industry, Beijing, 1998.

ViterbiDecoder 1-49


1-50 ViterbiDecoder

Chapter 2: Numeric CommunicationsComponents

Introduction

The numeric communications components provide basic communication functions onsingle data points or arrays of data that are integer, double precision floating point(real), fixed-point (fixed), or complex values. Each component accepts a specific classof signal and outputs a resultant signal.

If a component receives another class of signal, the received signal is automaticallyconverted to the signal class specified as the input of the component. Auto conversionfrom a higher to a lower precision signal class may result in loss of information.These components do not accept any matrix class of signal. The auto conversion fromtimed, complex or floating-point (real) signals to a fixed signal uses a default bitwidth of 32 bits with the minimum number of integer bits needed to represent thevalue. For example, the auto conversion of the real value of 1.0 creates a fixed-pointvalue with precision of 2.30, and a value of 0.5 would create one of precision of 1.31.For signal conversion rules, refer to “Conversion of Data Types” in the ADS PtolemySimulation manual.

Some components accept parameter values that are arrays of data. The syntax forreferencing arrays of data as parameter values includes an explicit list of values, areference to a file that contains those values, or a combination of explicit values alongwith file references. For details on using arrays of data for parameter values, refer to“Understanding Parameters” in the ADS Ptolemy Simulation manual.

Introduction 2-1

Numeric Communications Components

ADPCM_Coder

Description Adaptive Differential Pulse-Code Modulation EncoderLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. ADPCM_Coder is an adaptive differential pulse-code modulation encoder thatquantizes to 4-bit (24 levels). The adaptive prediction is done with an LMS(least-mean square) adaptive filter.

2. The number of taps in the InitialLMS_Taps parameter sets the order of theLMS filter. The InitialLMS_Taps default value (1.0 0.0 [15]) specifies 16 taps;therefore, the order of the prediction filter is also 16.


StepSize Step size of adaptive LMSprediction filter

1.0e-12 real (-∞, ∞)

InitialLMS_Taps initial taps of adaptive LMSprediction filter

1.0 0.0 [15] real array

Range range of PCM signal level 800 int (0, ∞)


1 input analog input signal real


2 d unquantized ADPCM prediction error signal real

3 u quantized ADPCM prediction error signal real

2-2 ADPCM_Coder

3. ADPCM_Coder works with ADPCM_Decoder and ADPCM_ToBits; the Rangeparameter must be set to the same value in each ADPCM component used.

4. Also see: ADPCM_Decoder, ADPCM_FromBits, ADPCM_ToBits, and LMS.

5. For general information regarding numeric communications components, referto the “Introduction” on page 2-1.

ADPCM_Coder 2-3


ADPCM_Decoder

Description Adaptive Differential Pulse-Code Modulation DecoderLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. ADPCM_Decoder is an adaptive differential pulse-code modulation decoder.The adaptive prediction is done with an LMS (least-mean square) adaptivefilter.

2. The number of taps in the InitialLMS_Taps parameter sets the order of theLMS filter. The InitialLMS_Taps default value 1.0 0.0 [15] specifies 16 taps;therefore, the order of the prediction filter is also 16.

3. The predicted error signal is internally limited to the range −12000 to +12000.This prevents the LMS algorithm from overflowing the floating-point (real)


StepSize step size of adaptive LMSprediction filter

1.0e-12 real (-∞, ∞)

InitialLMS_Taps initial taps of adaptive LMSprediction filter

1.0 0.0 [15] real array


1 input quantized ADPCM prediction error signal real


2 output decoded signal real

2-4 ADPCM_Decoder

range in the event the algorithm becomes unstable. Instability will still beobservable, however, as the output will approach infinity.

4. ADPCM_Decoder works with ADPCM_Coder and ADPCM_FromBits.

5. Also see: ADPCM_Coder, ADPCM_FromBits, ADPCM_ToBits, and LMS.

6. For information regarding numeric communications component signals, refer tothe “Introduction” on page 2-1.

ADPCM_Decoder 2-5


ADPCM_FromBits

Description Adaptive Differential Pulse-Code Modulation Error Signal DecoderLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. ADPCM_FromBits decodes a previously encoded quantized ADPCM errorsignal. For each set of four input bits received, a single quantized ADPCM errorsignal value is produced.

2. ADPCM_FromBits works with ADPCM_ToBits and ADPCM_Decoder; theRange parameter must be set to the same value in each ADPCM componentused.

3. Also see: ADPCM_Coder, ADPCM_Decoder, ADPCM_ToBits.





1 input 4-bit encoded ADPCM error signal int


2 output quantized ADPCM error signal real

2-6 ADPCM_FromBits

ADPCM_ToBits

Description 4-Bit Adaptive Differential Pulse-Code Modulation Error SignalDecoderLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. ADPCM_ToBits encodes a previously quantized ADPCM error signal into a setof 4 bits. For each input value received, four 1-bit outputs are produced.

2. ADPCM_ToBits works with ADPCM_FromBits and ADPCM_Coder; the Rangeparameter must be set to the same value in each ADPCM component used.

3. Also see: ADPCM_Coder, ADPCM_Decoder, ADPCM_FromBits.





1 input quantized ADPCM error signal real


2 output 4-bit code for the received ADPCM error signal value int

ADPCM_ToBits 2-7


AWGN_Channel

Description Additive White Gaussian Noise ChannelLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations/References

1. AWGN_Channel simulates a channel with white Gaussian noise and optionallinear distortion. To simulate linear distortion, the input signal is filteredthrough an FIR filter and fed back through a second FIR filter. White Gaussiannoise with zero mean and variance NoisePwr is then added to the signal. Thedefault values of FwdTaps and FdbkTaps cause the signal to be passed throughwithout distortion.


FwdTaps forward FIR filter tap tomodel linear distortion

1 real array

FdbkTaps feedback FIR filter tap tomodel linear distortion

0 real array

NoisePwr variance of the additivewhite Gaussian noise

0.5 real [0.0, ∞)


1 input input signal real


2 output output signal real

2-8 AWGN_Channel

2. AWGN_Channel can be represented as Y = X + G, where G is a zero meanGaussian random variable with variance σ2 and X=xK, k=0,1, ... q−1. For a

given X, it follows that Y is Gaussian with mean xK and variance σ2 . That is,

For any given input sequence, Xi, i-1, 2 ... , n, there is a corresponding outputsequence Yi = Xi + Gi, i = 1, 2, ... n.

3. Also see: NoiseChannel.


References

[1]J. G. Proakis, Digital Communications, McGraw-Hill, 1989.

P Y X xK=⁄( ) 1

2π σ---------------- e

Y xK–( )2 2σ2⁄–=

AWGN_Channel 2-9


BlockPredictor

Description Block Linear PredictorLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. BlockPredictor consists of Burg’s algorithm to estimate the linear predictorcoefficients of an input random process and a block lattice to implement forwardlattice filter with reflection coefficients that are periodically updated from theoutput of Burg’s algorithm.

2. The BlockSize parameter tells how often the updates occur. This parameterspecifies how many input samples are to be processed using each set ofreflection coefficients from the output of Burg’s algorithm.


Order order of the regression(also number of reflectioncoefficients to generate)

1 int (0, ∞)

BlockSize number of input that useeach reflection coefficientset

64 int (0, ∞)


1 input input random process real



2-10 BlockPredictor

3. The Order parameter tells how many reflection coefficients there are. The orderof the autoregressive model (all-pole signal model) in Burg's algorithm is alsogiven by the Order parameter.

4. The coefficients of autoregressive modeling in the BlockPredictor are theestimated coefficients of the all-pole filter that could have produced theobservations (input data) given a white noise input.The definition of reflectioncoefficients varies in the literature.

5. The reflection coefficients are the negative of the ones generated by Burg'salgorithm in the BlockPredictor, which correspond to the definition in mostother texts, and to the definition of partial-correlation (PARCOR) coefficients inthe statistics literature.

6. See also: Burg, BlockLattice, BlockAllPole


References

[1]J. Makhoul, “Linear Prediction: A Tutorial Review,” Proc. IEEE, Vol. 63, pp.561-580, Apr. 1975.

[2] S. M. Kay, Modern Spectral Estimation: Theory & Application, Prentice-Hall,Englewood Cliffs, NJ, 1988.

[3] S. Haykin, Modern Filters, MacMillan Publishing Company, New York, 1989.

BlockPredictor 2-11


CoderRS

Description Reed Solomon EncoderLibrary Numeric, CommunicationsClass SDFCoderRS

Parameters

Pin Inputs

Pin Outputs

Notes/Equations


GF Define a Galois Field(2^GF)

8 m int [2, 30]

CodeLength Length of output codeword 255 n int[3, 2m -1]

MessageLength Length of input messagesymbols

223 k int [1,CodeLength-2]

PrimPoly Coefficients of PrimitivePolynonial

1 0 1 1 1 0 0 0 1 p(x) int array †

Root The first root of generatorpolynomial

1 m0 int[0, 2m -1 - (n -k) ]

† PrimPoly must be the coefficients of the m order of polynomial


1 in information symbol int


2 out systematical code int

2-12 CoderRS

1. This model is used to perform Reed-Solomon (RS) encoding. RS codes are a classof block codes that operate on non-binary symbols. The symbols are formed fromm bits of a binary data stream. A code block is then formed with n = 2m - 1symbols. In each block, k symbols are formed from the encoder input and (n-k)parity symbols are added. The code is thus a systematic code. The rate of thecode is k/n, and the code is able to correct up to t = (n-k-1)/2 or (n-k)/2 symbolerrors in a block, depending on whether n-k is odd or even. For example, thecode used in the WCDMA [1] data transmission system is a (36,32) codeshortened from RS code (255,251) defined on Galois Field (28). A shortened codecan be formed by taking 32 input symbols, padding them out with 219 all zerosymbols to form 251 symbols, and then encoding with a RS code (255,251). The219 fixed symbols are then discarded prior to transmission. The input pinconsumes k tokens and the output pin produces n tokens for each firing.

2. Implementation

The code format is: RS code (n, k), defined on Galois Field (2m).

Galois Field Generator

Galois Fields are set up according to the number of bits per symbol and thenumber of symbols per block.

Generate GF (2m ) from the irreducible primitive polynomial. It is defined as thepolynomial of least degree, with coefficients in GF(2) and a highest degreecoefficient equal to 1. The polynomial is always of degree m.

The elements of Galois Field can have two representations: exponent orpolynomial. Let α represent the root of the primitive polynomial p(x). Then inGF(2m), for any 0 ≤ i ≤ 2m - 2

where the binary vector (bi(0), bi(1),..., bi(m-1)) is the representation of the

integer polynomial[i]. Now exponent[i] is the element whose polynomialrepresentation is (bi(0), bi(1),..., bi(m-1)), and exponent[polynomial[i]]=i.

Polynomial representation is convenient for addition, exponent representationfor multiplication.

RS Encoder

The RS generator polynomial is generally defined as

αi bi 0( ) bi 1( )α bi 2( )α2 … bi m 1–( )αm 1–+ + + +=

CoderRS 2-13


where t is the correctable error number. It can be reduced to a 2t order ofpolynomial

Encoding is done by using a feedback shift register with appropriateconnections specified by the element gi . The encoded symbol is then

where in(x) is the polynomial representation of the input data, parity(x) is thepolynomial of the parity symbol.

The RS encoder diagram is illustrated in Figure 2-1.

Figure 2-1. Reed Solomon Encoder


References

[1]NTT Mobile Communications Network Inc. “Specifications for W-CDMA MobileCommunication System Experiment”, October 9, 1997.

[2] S. Lin, D. J. Costello, Error Control Coding Fundamentals and Applications,1983.

g x( ) x am0–( ) x a

m0 1+–( )… x a

m0 2t 1–+–( )=

g x( ) x2t g2t 1– x2t 1– … g0+ + +=

in x( ) x n k–( )× parity x( )+

Input symbol

Output RS code

g0 g1 g2 g3

+ + +

x x x x

+Gate1

Gate2

Gate3

2-14 CoderRS

DecoderRS

Description Reed Solomon DecoderLibrary Numeric, CommunicationsClass SDFDecoderRS

Parameters

Pin Inputs

Pin Outputs


GF Define a Galois Field(2^GF)

8 m int [2, 30]

CodeLength Length of input codewords 255 n int[3, 2m -1]

MessageLength Length of output messagesymbols

223 k int [1,CodeLength-2]

PrimPoly Coefficients of primitivepolynomial

1 0 1 1 1 0 0 0 1 p(x) int array †

Root First root of generatorpolynomial

1 m0 int[0, 2m -1 - (n -k)]

† PrimPoly must be the coefficients of the m order of polynomial


1 in received symbol int


2 out decoded symbol int

DecoderRS 2-15


Notes/Equations

1. This model is used to perform RS decoding via the Berlekamp iterativealgorithm [2].

2. The Berlekamp iterative algorithm locates the error in RS code and generatesan error location polynomial. By finding the root of the error locationpolynomial, the error position can be determined. If decoding is successful, theinformation symbols are output; otherwise, the received data is unaltered. Theinput pin consumes n tokens and the output pin produces k tokens.

3. Decoding routines are described here.

For the shortened code, the same number of symbols 0 is inserted into the sameposition as CoderRS and a Reed Solomon decoder is used to decode the block.After decoding, the padded symbols are discarded, leaving the desiredinformation symbols.

Syndromes indicate erroneous situations. When the generator polynomial g(x)and the received codeword represented by r(x) are given, one or more errorshave occurred during transmission of an encoded block.

Let

where v(x) is the polynomial representation of the transmitted symbol.

where r(x) is the polynomial representation of the received symbol.

Then

where e(x) denotes the error patterns.

If ri - vi, then ei = 0; else ei = 1.

Remember that

v(x) = g(x)Q(x)

where Q(x) is the quotient.

So if αi is the root of g(x), then v(αi) = 0 and r(αi) = e (αi).

v x( ) v0 v1x v2x2 … vn 1– xn 1–+ + + +=

r x( ) r0 r1x r2x2 … rn 1– xn 1–+ + + +=

r x( ) v x( ) e x( )+=

2-16 DecoderRS

Now there is a simple procedure for checking the occurrence of errors at thereceiver:

Calculate syndromes s(i), the syndromes are decided by the error patterns:

.

If one or more of the syndromes are not equal to zero, one or more symbol errorsoccur in the received data. For example, if

are roots of g(x), then

.

.

.

.

Syndromes are used to find the error location polynomial.

Given the syndromes s(i), the decoding algorithm will synthesize an errorlocation polynomial. The roots of the polynomial indicate the error positions.

Assuming the received symbols have v symbol errors, the syndromes arerepresented as:

.

.

.

where the error location is

s i( ) e αm0 i+

( )=

αm0 α

m0 1+… α

m0 2t 1–

+, , ,

s 1( ) r αm0( )=

s 1( ) r αm0 1+

( )=

s 2t( ) r αm0 2t 1–+

( )=

s 1( ) β1m0 β2

m0 … βνm0+ + +=

s 2( ) β1m0 1+

β2m0 1+

…βνm0 1+

+ +=

s 2t( ) β1m0 2t 1–+

β2m0 2t 1–+

…βvm0 2t 1–+

+ +=

DecoderRS 2-17


and

Now the error location polynomial is defined as

The Berlekamp iterative algorithm is used to construct this polynomial, whichis the key to RS decoding.

The algorithm is described here without proof; for more information, see Ref.[1].

An iterative table will be filled.

where

is the iterative step numberis the µth step iterative difference

is the order of .

If

then

Table 2-1. Berklekamp Iterative Table

-1 1 1 0 -1

0 1 s1 0 0

1

2 ... , 2t

βl ail=

ail 1 l v≤ ≤( )

Ω x( ) 1 β1m0x+

1 β2m0x+

… 1 βvm0x+

Ω0 Ω1x Ω2x2 … Ωvxv+ + + +

=

=

µ Ω u( ) x( ) dµ lµ µ lµ–

µdµ

lµ Ω µ( ) x( )

dµ 0=

2-18 DecoderRS

and

If

search for lines in the table to find step p in which dp ≠ 0 and the value of p - lpis the maximum, then

and

For the two conditions

Iterate until the last line of the table Ω(2t) (x) is calculated. If the order of thepolynomial is greater than t (which means the received codeword block hasmore than t errors) the error cannot be corrected.

For non-binary codes, the error values must be known.

The minimum order polynomial is iteratively solved to obtain the least numberof roots (error location number). The inverse element of the root indicates theerror location.

The error value is calculated based on the Ref. [2] equation

where

Ω µ 1+( ) x( ) Ωµµ( )

= x( )

lµ 1+ lµ=

dµ 0≠

Ω µ 1+( ) x( ) Ω µ( ) x( ) dµdρ1– x µ ρ–( )Ω ρ( ) x( )–=

lµ 1+ max lµ lρ µ ρ–+,( )=

dµ 1+ sµ 2+ Ω1µ 1+( )sµ 1+ … Ωlµ 1+

µ 1+( )sµ 2 lµ 1+–++ + +=

e jl βl1 m0–( ) z βl

1–( )

1 βiβl1–

+( )i 1=

i l≠

v

∏-----------------------------------------=

DecoderRS 2-19


Then,

References

[1]E.R. Berlekamp, Algebraic Coding Theory, McGraw-Hill, New York, 1968.

[2] S. Lin, D. J. Costello, Error Control Coding Fundamentals and Applications,1983.

z x( ) 1 s1 Ω1+( )x s2 Ω1s1 Ω2+ +( )x2

… sv Ω1sv 1– Ω2sv 2– … Ωv+ + + +( )xv+ + +

+

=

out x( ) r x( ) e x( )–=

2-20 DecoderRS

DeScrambler

Description Input bit sequence descramblerLibrary Numeric, CommunicationsClass SDFDeScramblerC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component descrambles the input bit sequence using a feedback shiftregister. The taps of the feedback shift register are given by the Polynomialparameter.


Polynomial generator polynomial forthe shift register - decimal,octal, or hex integer

0440001 int (0, ∞)

ShiftReg initial state of the shiftregister - decimal, octal, orhex integer

1 int (-∞, ∞)


1 input input bit sequence (zero or nonzero) int


2 output output bit sequence (zero or one) int

DeScrambler 2-21


This is a self-synchronizing descrambler that will exactly reverse the operationof the Scrambler component if the corresponding parameter values ofScrambler and DeScrambler are the same.

A self-synchronized descrambler is shown in Figure 2-2.

Figure 2-2. Self-Synchronized Descrambler

2. Also see: Scrambler.

References

[1]E. A. Lee and D. G. Messerschmitt, Digital Communication, Second Edition,Kluwer Academic Publishers, 1994, pp. 595-603.

D D

Shift-registerInput Ck

Received InputSignal bk

h1 hn-1 hn

2-22 DeScrambler

DeSpreader

Description Frame Synchronized Direct-Sequence Spread Spectrum DemodulatorLibrary Numeric, Communications

Pin Inputs

Pin Outputs

Notes/Equations

1. DeSpreader is a frame synchronized direct-sequence spread spectrumdemodulator. Each input sample is demodulated with a 31-bit pseudo-noisespreading code. This despreads the signal.

2. See also Spread, and RecSpread.

References

[1]S. Hakin, Digital Communications, John Wiley & Sons, 1988, chapter 9.


1 in input spread spectrum signal real


2 out demodulated signal real

DeSpreader 2-23


FreqPhase

Description Frequency Offset or Phase Jitter SamplerLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. FreqPhase can be used to impose a frequency offset or phase jitter, or both, on asignal in order to model channels (such as telephone channels) that suffer theseimpairments.

2. Very low- and very high-frequency signals (near the Nyquist frequency) will bedistorted due to the Hilbert filter.


SampleRate input signal sample rate 2 * PI real [0, ∞)

PhaseJitterFrequencyHz frequency of phase jitterdistortion to add to signal

0.0 real [0.0, ∞)

FrequencyOffsetHz frequency offset distorionto add to signal

0.0 real [0.0, ∞)

PhaseJitterAmplitudeDeg phase jitter peakamplitude, in degrees

0.0 real (-∞, ∞)


1 in input signal real


2 out output signal real

2-24 FreqPhase

3. See Also: PhaseShift.

FreqPhase 2-25


HilbertSplit

Description Real to Analytic Signal ConverterLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. HilbertSplit converts the real input signal into an analytic signal using a phasesplitter. The Delay parameter determines the length and, therefore, theaccuracy of the Hilbert filter used. The Hilbert filter has (2 × Delay+1) taps. Alarger value for delay gives a more accurate filter, but increases the processingtime and the delay through the system. The component scales the input signalso that input and output signals have the same rms value.

2. See Also: Hilbert.

References


Delay processing delay of thisblock

32 int [0, ∞)


1 in real input signal real


2 out analytic output signal complex

2-26 HilbertSplit

[1]A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing,Prentice-Hall: Englewood Cliffs, NJ, 1989.

HilbertSplit 2-27


InterleaveDeinterleave

Description Interleaver / DeinterleaverLibrary Numeric, CommunicationsClass SDFInterleaveDeinterleaveDerived From TransposeC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component is a general purpose interleaver/de-interleaver. Every time itfires it reads (Rows×Columns) samples from its input and writes them to itsoutput in a different order. Its operation is equivalent to writing the samplesread from its input in a Rows × Columns matrix row-wise, then reading thematrix elements column-wise and writing them to the output.


Rows number of rows of theinterleave/deinterleavematrix

8 int (0, ∞)

Columns number of columns of theinterleave/deinterleavematrix

8 int (0, ∞)


1 input anytype


2 output anytype

2-28 InterleaveDeinterleave

Alternatively, the Transpose component in the Numeric Control library can beused.

InterleaveDeinterleave 2-29


NoiseChannel

Description Channel Modeling with Additive White Gaussian NoiseLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. NoiseChannel models a channel with additive white Gaussian noise.

If x(t) is a band-limited input signal to a channel and y(t) is the correspondingoutput signal then, for the additive white Gaussian noise waveform channel,the real output is

y(t) = x(t) + n(t)

where n(t) is a sample function of the additive noise process.

2. See also: AWGN_Channel.


NoiseVariance maximum settable valuefor noise variance

1.0 real [0, ∞)




2 out input signal plus Gaussian noise real

2-30 NoiseChannel

NonlinearDistortion

Description Second and Third Harmonic DistortionLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. With NonlinearDistortion, second- and third-order harmonic distortion isgenerated by squaring and cubing the input signal and adding the results incontrolled proportions to the original signal.

output = input + SecondHarmonic × (input)2 + ThirdHarmonic × (input)3


SecondHarmonic proportion of secondharmonic of input to add tooriginal signal

0.0 real (-∞, ∞)

ThirdHarmonic proportion of thirdharmonic of input to add tooriginal signal

0.0 real (-∞, ∞)





NonlinearDistortion 2-31


PAM2Rec

Description 2-Level Pulse Amplitude Modulation Input Signal ReceiverLibrary Numeric, Communications

Pin Inputs

Pin Outputs

Notes/Equations

1. PAM2Rec receives a 2-level pulse amplitude modulation (PAM) signal andextracts the transmitted bits. It is assumed that the received PAM signal is anonreturn-to-zero polar format with a symbol interval of 16. PAM2Rec willreceive signals generated by the PAM2Xmit component.

2. Once the transmitted bits are extracted, they are descrambled before being sentto the output. The descrambling polynomial matches that of the PAM2Xmitcomponent scrambler.

3. See also: Descrambler, DownSample, PAM2Xmit, and Scrambler.

References



1 in received PAM signal real


2 out bit that corresponds to the received PAM pulse int

2-32 PAM2Rec

PAM2Xmit

Description 2-Level Pulse Amplitude Modulation TransmitterLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. PAM2Xmit uses 2-level pulse amplitude modulation to convert the input bitsinto a transmission signal. The PAM signal is a nonreturn-to-zero polar formatwith square root raised-cosine pulses. The excess bandwidth and length of thesquare root raised-cosine pulses are set by the ExcessBW and FilterLengthparameters. The PAM levels are +2 and −2; the symbol interval is 16; therefore,for each input bit received a 16-sample output pulse is produced.


ExcessBW excess bandwidth of thesquare root raised-cosinepulses used to transmitdata

1.0 real [0, 1]

FilterLength length of square rootraised-cosine pulses usedto transmit data

32 real (0, ∞)


1 in input bits to be transmitted int


2 out square root raised-cosine pulses that correspond tothe input bits

real

PAM2Xmit 2-33


Note that the input bits are scrambled before transmitting. The bits must bedescrambled after they are received.

2. See also: DeScrambler, PAM2Rec, Scrambler.

References


2-34 PAM2Xmit

PAM4Rec

Description 4-Level Pulse Amplitude Modulation Input Signal ReceiverLibrary Numeric, Communications

Pin Inputs

Pin Outputs

Notes/Equations/References

1. PAM4Rec receives a 4-level pulse amplitude modulation signal and extracts thetransmitted bits. The four levels should be −3, −1, +1, and +1. It is assumedthat the received PAM format has a symbol interval of 16. PAM4Rec will receivesignals generated by PAM4Xmit.

Once the transmitted bits are extracted, they are descrambled before being sentto the output. The descrambling polynomial matches the PAM4Xmit componentscrambler.

2. See also: Descrambler, DownSampler, PAM4Xmit.

References

[1]For more information about pulse amplitude modulation, see: S. Hakin, DigitalCommunications, John Wiley & Sons, 1988, chapter 6.


1 in received PAM signal real


2 out bit that corresponds to received PAM pulse int

PAM4Rec 2-35


PAM4Xmit

Description 4-Level Pulse Amplitude Modulation TransmitterLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. PAM4Xmit uses 4-level pulse amplitude modulation to convert pairs of inputbits into a transmission signal. The input bits are first scrambled beforetransmitting. The bits must be descrambled after they are received.

The PAM format used is a nonreturn-to-zero polar format with square rootraised-cosine pulses. The excess bandwidth and length of the square rootraised-cosine pulses are set by the ExcessBW and FilterLength parameters.


ExcessBW excess bandwidth ofsquare root raised-cosinepulses used to transmitdata

1.0 real [0, 1]

FilterLength length of square rootraised-cosine pulses usedto transmit data

32 real (0, ∞)


1 in input bits to be transmitted int


2 out square root raised-cosine pulses that correspond tothe input bits

real

2-36 PAM4Xmit

The PAM levels are +3, +1, −1, and −3. The symbol interval is 16; therefore, foreach two input bits received a 16-sample output pulse is produced.

2. See also: DeScrambler, PAM4Rec, Scrambler.

References


PAM4Xmit 2-37


PCM_BitCoder

Description Pulse-Code Modulation EncoderLibrary Numeric, Communications

Pin Inputs

Pin Outputs

Notes/Equations

1. PCM_BitCoder is a 64-kbits-per-second pulse-code modulation encoder. Eachinput value is companded and quantized to 8 bits that are then sent to theoutput.

2. The encoding follows the CCITT Recommendation G.711.

3. PCM_BitCoder works with PCM_BitDecoder, which performs the reverseoperation.


1 in analog input signal with values from -4000 to 4000 real


2 out PCM encoded bits int

2-38 PCM_BitCoder

PCM_BitDecoder

Description Pulse-Code Modulation DecoderLibrary Numeric, Communications

Pin Inputs

Pin Outputs

Notes/Equations

1. PCM_BitDecoder is a 64-kbits-per-second pulse-code modulation decoder. Eachset of 8 input bits is mapped to its decoded analog value that is then sent to theoutput.

2. The decoding follows the CCITT Recommendation G.711.

3. PCM_BitDecoder works with the PCM_BitCoder component, which performsthe reverse operation.


1 in PCM encoded bits int


2 out corresponding analog signal value real

PCM_BitDecoder 2-39


PhaseShift

Description Phase Shift DistortionLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. PhaseShift adds phase shift distortion found in channels such as telephonechannels. The output is the input signal with the phase of the input signalshifted by the value of the shift input.

2. Very low- and very high-frequency signals (near the Nyquist frequency) will bedistorted due to the Hilbert filter. This can be partially overcome by setting theHilbertFilterLength parameter for a longer, more accurate filter. The defaultHilbert filter is acceptable for most applications.

3. See Also: FreqPhase.


HilbertFilterLength Hilbert filter length 64 int (0, ∞)



2 shift phase shift in radians real



2-40 PhaseShift

PSK2Rec

Description Binary Phase-Shift Keying DemodulatorLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component accepts a BPSK modulated wave and outputs the recoveredbinary data stream.

2. The input sequence is first demodulated by multiplication with a cosine wavesequence. The demodulated sequence is filtered with a square root ofraised-cosine filter and scaled with an appropriate factor so that the outputlevel of the downsampler that follows is independent of the filter length (whichdepends on the sampling and carrier frequencies given by the user). Conversionto bits is done by downsampling, taking the sign of the downsampled values and


CarrierFrequency cosine carier wavefrequency

2000 real (0, ∞)

SamplingRate carrier wave sampling rate 8000 real (0, ∞)


1 in received binary phase-shift keyed transmissionsignal

real


2 out binary wave of the received data (-N,+N) real

PSK2Rec 2-41


mapping 1 and −1 to 1 and 0, respectively. Note that if a BPSK transmitter(PSK2Xmit) and receiver (PSK2Rec) are concatenated, the output bit streamwill be delayed by one bit with respect to the input bit stream; this is due to thedelay introduced by the filters.

3. See also: PSK2Xmit.

References


2-42 PSK2Rec

PSK2Xmit

Description Binary Phase-Shift Keying ModulatorLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component accepts a binary bit stream and outputs a BPSK modulatedwave.

2. The input bit stream is first converted to an NRZ waveform that is then filteredby a square root of raised-cosine filter. The interpolation factor of the filter ischosen so that the rate at the output of the filter matches the sampling rate.The filtered sequence is scaled with an appropriate factor so that the amplitudelevel at the output of the transmitter is independent of the filter length (whichdepends on the sampling and carrier frequencies given by the user). The


CarrierFrequency cosine carrier wavefrequency

2000 real (0, ∞)

SamplingRate carrier wave sampling rate 8000 real (0, ∞)


1 in binary wave (polar from) to be modulated real


2 out binary phase shift keyed transmission signal real

PSK2Xmit 2-43


sequence is then multiplied by a cosine wave resulting in a BPSK modulatedwave.

3. See also: PSK2Rec.

References


2-44 PSK2Xmit

QAM16

Description 16-State Quadrature Amplitude ModulatorLibrary Numeric, Communications

Pin Inputs

Pin Outputs

Notes/Equations

1. QAM16 performs a 16-point quadrature amplitude modulation on the input bitstream, producing a complex output signal. The component consumes 4 bitsfrom the input for each complex valued output it produces. The first 2 bits areGray and differentially encoded and are used to select the quadrant of theoutput point. The last 2 bits are used to select the point inside the quadrantselected by the first 2 bits. Mapping of the last 2 bits to the 4 points in eachquadrant uses Gray encoding. Mapping is also invariant to phase rotations thatare multiples of 90 degrees.

2. There are many ways to map sets of 4 bits into a 16-point grid; therefore, thereare many different variations of 16-QAM encoding. This component implementsone of them.

3. Also see: QAM16Decode, QAM16Slicer.

References

[1]S. Hakin, Digital Communications, John Wiley & Sons, 1988, pages 318-322.


1 in input bit sequence int


2 out output symbol sequence complex

QAM16 2-45


QAM16Decode

Description 16-State Quadrature Amplitude Modulator DecoderLibrary Numeric, Communications

Pin Inputs

Pin Outputs

Notes/Equations

1. QAM16Decode decodes the 16-QAM input signal into an output bit stream. It isassumed that the input 16-QAM signal was encoded using the QAM16component. For each value of the input, 4 bits are written at the output.

2. Also see: QAM16, QAM16Slicer.


1 in input signal complex


2 out output bit sequence int

2-46 QAM16Decode

QAM16Slicer

Description 16-State Quadrature Amplitude Modulator SlicerLibrary Numeric, Communications

Pin Inputs

Pin Outputs

Notes/Equations

1. The component outputs the 16-QAM grid point that is geometrically closest tothe input point.

2. The quadrature amplitude modulation grid is assumed to be:

3. QAM16Slicer works with QAM16; refer to QAM16 for details of 16-QAMencoding.




2 out output 16-QAM signal at exact grid points complex

(-3, 3) (-1, 3) (1, 3) (3, 3)(-3, 1) (-1, 1) (1, 1) (3, 1)(-3, -1) (-1, -1) (1, -1) (3, -1)(-3, -3) (-1, -3) (1, -3) (3, -3)

QAM16Slicer 2-47


QAM4


Pin Inputs

Pin Outputs

Notes/Equations

1. QAM4 performs a 4-point quadrature amplitude modulation on the input bitstream, producing a complex output signal. The component consumes 2 bitsfrom the input for each complex valued output it produces. Mapping of the 2bits to the 4 points uses Gray encoding, that is:






InputBits -->

OutputPoint

0, 1 --> (−1, 1)

0, 0 --> (1, 1)

1, 1 --> (−1, −1)

1, 0 --> (1, −1)

2-48 QAM4

3. Also see: QAM4Slicer.

References


QAM4 2-49


QAM4Slicer


Pin Inputs

Pin Outputs

Notes/Equations

1. This component outputs the 4-QAM grid point that is geometrically closest tothe input point.


3. QAM4Slicer works with QAM4; refer to QAM4 for details of 4-QAM encoding.





(-1, 1) (1, 1)(-1, -1) (1, -1)

2-50 QAM4Slicer

QAM64


Pin Inputs

Pin Outputs

Notes/Equations

1. QAM64 performs a 64-point quadrature amplitude modulation on the input bitstream, producing a complex output signal. The component consumes 6 bitsfrom the input for each complex valued output it produces. The first 2 bits areGray and differentially encoded and used to select the quadrant of the outputpoint. The last 4 bits are used to select the point inside the quadrant selected bythe first 2 bits. Mapping of the last 4 bits to the 16 points in each quadrant usesGray encoding. Mapping is also invariant to phase rotations that are multiplesof 90 degrees.


3. Also see: QAM64Decode, QAM64Slicer.

References






QAM64 2-51


QAM64Decode

Description 64-State Quadrature Amplitude Modulator DecoderLibrary Numeric, Communications

Pin Inputs

Pin Outputs

Notes/Equations

1. QAM64Decode decodes the 64-QAM input signal into an output bit stream. It isassumed that the input 64-QAM signal was encoded using the QAM64component. For each value at the input, 6 bits are written at the output.

2. Also see: QAM64, QAM64Slicer.




2 out output bit sequence int

2-52 QAM64Decode

QAM64Slicer


Pin Inputs

Pin Outputs

Notes/Equations

1. This component outputs the 64-QAM grid point that is geometrically closest tothe input point.


3. QAM64Slicer works with QAM64. Refer to QAM64 for details of 64-QAMencoding.





(-7, 7) (-5, 7) (-3, 7) (-1, 7) (1, 7) (3, 7) (5, 7) (7, 7)(-7, 5) (-5, 5) (-3, 5) (-1, 5) (1, 5) (3, 5) (5, 5) (7, 5)(-7, 3) (-5, 3) (-3, 3) (-1, 3) (1, 3) (3, 3) (5, 3) (7, 3)(-7, 1) (-5, 1) (-3, 1) (-1, 1) (1, 1) (3, 1) (5, 1) (7, 1)(-7, -1) (-5, -1) (-3, -1) (-1, -1) (1, -1) (3, -1) (5, -1) (7, -1)(-7, -3) (-5, -3) (-3, -3) (-1, -3) (1, -3) (3, -3) (5, -3) (7, -3)(-7, -5) (-5, -5) (-3, -5) (-1, -5) (1, -5) (3, -5) (5, -5) (7, -5)(-7, -7) (-5, -7) (-3, -7) (-1, -7) (1, -7) (3, -7) (5, -7) (7, -7)

QAM64Slicer 2-53


RaisedCosine

Description Raised-cosine filterLibrary Numeric, CommunicationsClass SDFRaisedCosineDerived From FIRC++ Code

Parameters

Pin Inputs

Pin Outputs


Decimation decimation ratio 1 D int [1, ∞)

DecimationPhase decimation phase 0 int [0,Decimation-1]

Interpolation interpolation ratio 16 I int [1, ∞)

Length number of taps 64 L int [1, ∞)

SymbolInterval distance from center to firstzero crossing

16 T int [1, ∞)

ExcessBW excess bandwidth 1.0 real [0, 1]

SquareRoot square root raised-cosinepulse: NO, YES

NO enum


1 signalIn real


2 signalOut real

2-54 RaisedCosine

Notes/Equations

1. RaisedCosine implements a finite-impulse response filter with a raised-cosineor square root raised-cosine frequency response. Excess bandwidth is given byExcessBW, symbol interval (in number of samples) of the application is given bySymbolInterval, length of filter (number of taps) is given by Length.

This filter is derived from the FIR filter that uses an internal polyphasestructure. This algorithm efficiently implements the rational sample ratechanges with decimation and interpolation. For more information on multi-rateconcepts, refer to FIR component documentation.

2. For the ordinary raised-cosine response, ideally the impulse response of thefilter would be

However, this ideal pulse is centered at 0, but we can only implement causalfilters. Therefore, the impulse response is actually

where

The impulse response is simply truncated outside this range, so the impulseresponse will generally not be symmetric if L is even because it will have onemore sample to the left than to the right of center. Unless this extra sample is 0,the filter will not have linear phase if L is even. For the ordinary raised-cosineresponse, the distance (in number of samples) from the center to the first zerocrossing is given by T.

3. The output sample rate is I times the input. The Interpolation default is set to16 because this pulse is used in digital communication systems for the linecoding of symbols, and upsampling is necessary. In this case, 16 outputs will be

h n( )π n

T----

sin

π nT----

---------------------

απ n

T----

cos

1 2α nT----

2–

-----------------------------

=

g n( ) h n M–( )=

M L2---- if L is even=

M L 1+2

------------- if L is odd=

RaisedCosine 2-55


produced for each input. Typically, the value of Interpolation is the same asSymbolInterval.

4. When SquareRoot is selected for the raised-cosine filter with and withoutinterpolation, some interesting facts can be observed:

• The output of two-cascaded square root raised-cosine filter is approximatelyequal to the output of raised-cosine filter without square root when using thesame input signal. In other words: h(n) is a raised-cosine filter and H(z) is acorresponding frequency response for h(n); h1(n) is a square-rootedraised-cosine filter and H1 (z) is a frequency response for h1(n). We shouldhave h(n) = h1(n)*h1(n) or H(z) =H1(z)H1(z).

• The output of the raised-cosine filter with interpolation rate I should equalthe output of an UpSample component with its Factor parameter set to Ifollowed by two cascaded square-root raised-cosine filters when using thesame input signal.

• The amplitude output value of square root raised-cosine filter should showresults similar to the amplitude output value of square root raised-cosinefilter with interpolation rate I when using the same input signal. However, itcan be seen that the difference is more output amplitude data from thesquare root raised-cosine filter with interpolation rate I compared to squareroot raised-cosine filter without interpolation rate. This is because every twoinput-sampled data, I zeros are introduced during upsampling.

5. Also see: RaisedCosineCx.

References

[1]E. A. Lee and D. G. Messerchmitt, Digital Communication, Kluwer AcademicPublishers, Boston, 1988.

[2] I. Korn, Digital Communications, Van Nostrand Reinhold, New York, 1985.

2-56 RaisedCosine

RaisedCosineCx

Description Complex Raised-Cosine FilterLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations


Decimation decimation ratio 1 int [1, ∞)


Interpolation interpolation ratio 16 real [1, ∞)

Length number of taps 64 int [1, ∞)

SymbolInterval distance from center to firstzero crossing

16 int [1, ∞)

ExcessBW excess bandwidth,between 0 and 1

1.0 real [0, 1]

SquareRoot square root raised-cosinepulse: NO, YES

NO enum


1 input input signal complex


2 output output signal complex

RaisedCosineCx 2-57


1. RaisedCosineCx implements a pair of FIR filters with a raised-cosine or squareroot raised-cosine frequency response. The real part of the complex input goesthrough one filter to become the real part of the output signal. Similarly, theimaginary part of the input goes through the other filter to become theimaginary part of the output signal.

2. The excess bandwidth for both filters is given by ExcessBW; the symbol interval(in number of samples) of the application is given by SymbolInterval; and thelength of the filters (the number of taps) is given by Length. By default, thiscomponent upsamples by a factor of 16, so 16 outputs will be produced for eachinput unless the Interpolation parameter is changed.

3. For raised-cosine algorithm details, refer to the RaisedCosine component.

2-58 RaisedCosineCx

RecSpread

Description Spread Spectrum ReceiverLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. RecSpread is a direct-sequence spread spectrum receiver. The received signal isfirst downsampled to remove any signal repetition due to the PulseDuration.The received signal is then modulated with the same 31-bit pseudo-noisespreading code used in the XmitSpread component. The demodulated signal isthen correlated and quantized to determine if the received signal is 1 or 0.

2. See also DeSpreader, Spread, XmitSpread.

References

[1]For more information about spread spectrum modulation, see: S. Hakin, DigitalCommunications, John Wiley & Sons, 1988, chapter 9.


PulseDuration number of times to repeateach transmitted sample

1 int (0, ∞)


1 in received direct-sequence spread spectrum signal real


2 out received data real

RecSpread 2-59


Scrambler

Description Input bit sequence scramblerLibrary Numeric, CommunicationsClass SDFScramblerC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component scrambles the input bit sequence using a feedback shiftregister, as shown in Figure 2-3. The taps of the feedback shift register aregiven by the Polynomial parameter, which should be a positive integer. The nthbit of this integer indicates whether the nth tap of the delay line is fed back.The low-order bit is called the 0th bit, and must be set. The next low-order bit


Polynomial generator polynomial forthe shift register - decimal,octal, or hex integer

0440001 int

ShiftReg initial state of the shiftregister - decimal, octal, orhex integer

1 int


1 input input bit sequence (zero or nonzero) int


2 output output bit sequence (zero or one) int

2-60 Scrambler

indicates whether the output of the first delay should be fed back, and so on.The default Polynomial is an octal number defining the V.22bis scrambler.

2. In scramblers based on feedback shift registers, all the bits to be fed back areexclusive-ORed together (their parity is calculated), and the result isexclusive-ORed with the input bit. This result is produced at the output andshifted into the delay line. With proper choice of polynomial, the resultingoutput appears highly random even if the input is highly non-random (forexample, all 0s or all 1s).

Figure 2-3. Feedback Shift Register

3. If the polynomial is a primitive polynomial, then the feedback shift register is aso-called maximal length feedback shift register. This means that with aconstant input, the output will be sequence with period 2N −1 where N is theorder of the polynomial (the length of the shift register). This is the longestpossible sequence. Moreover, within this period the sequence will appear to bewhite, in that a calculated autocorrelation will be very nearly an impulse.Therefore, the scrambler with a constant input can be very effectively used togenerate a pseudo-random bit sequence.

The maximal-length feedback shift register with constant input will passthrough 2N −1 states before returning to a state it has been in before. This isone short of the 2N states that a register with N bits can take on. This onemissing state, in fact, is a lock-up state, in that if the input is an appropriateconstant, the scrambler will cease to produce random-looking output, and willoutput a constant. For example, if the input is all zeros, and the initial state ofthe scrambler is zero, then the outputs will be all zero, hardly random. This iseasily avoided by initializing the scrambler to some non-0 state. That is why thedefault value for the ShiftReg parameter is set to 1.

4. The Polynomial parameter must be carefully chosen. It must represent aprimitive polynomial, which is one that cannot be factored into two (nontrivial)polynomials with binary coefficients. For details, refer to [1].

D

Ck Shift-register Output

hn-1 hn

D

h1

InputSignalbk

Scrambler 2-61


5. Table 2-2 lists primitive polynomials (expressed as octal numbers so that theyare easily translated into taps on shift register); these will result inmaximal-length pseudo-random sequences if the input is constant and lockup isavoided.

The leading 0 in the polynomials indicates an octal number. Note also thatreversing the order of the bits in any of these numbers will also result in aprimitive polynomial. Therefore, the default value for the Polynomialparameter is 0440001 in octal, or "100 100 000 000 000 001" in binary.Reversing these bits we get "100 000 000 000 001 001" in binary, or 0400011 inoctal. This latter number is listed in the table as the primitive polynomial oforder 17. The order is the index of the highest-order non-0 bit in the polynomial,where the low-order bit has index 0.

Because the polynomial and the feedback shift register are both implementedusing type int, the order of the polynomial is limited by the size of the int datatype. For simplicity and portability, the polynomial is also not allowed to beinterpreted as a negative integer, so the sign bit cannot be used. Therefore, if intis a 32-bit word, then the highest order polynomial allowed is 30 (recall thatindexing for the order starts at 0, and we cannot use the sign bit). The primitivepolynomials in the table are up to order 30 because of 32-bit integer machines.

Both the Polynomial and ShiftReg parameters can be set to a decimal, octal, orhex value. To enter an octal or hex value, prefix it with 0 or 0x, respectively. Forexample, in order to use the primitive polynomial of order 11, set Polynomial to04005, 0x805, or 2053.

Table 2-2.

Order Polynomial Order Polynomial Order Polynomial

11 04005 21 010000005

2 07 12 010123 22 020000003

3 013 13 020033 23 040000041

4 023 14 042103 24 0100000207

5 045 15 0100003 25 0200000011

6 0103 16 0210013 26 0400000107

7 0211 17 0400011 27 01000000047

8 0435 18 01000201 28 02000000011

9 01021 19 02000047 29 04000000005

10 02011 20 04000011 30 010040000007

2-62 Scrambler

6. Also see: DeScrambler.

References

[1]Lee and Messerschmitt, Digital Communication, Second Edition, KluwerAcademic Publishers, 1994, pp. 595-603.

Scrambler 2-63


Spread

Description Spread Spectrum ModulatorLibrary Numeric, Communications

Pin Inputs

Pin Outputs

Notes/Equations

1. Spread is a direct-sequence spread spectrum modulator. Each input sample ismodulated with a 31-bit pseudo-noise spreading code.

2. See also DeSpreader, XmitSpread.

References





2 out input signal modulated by a 31-bit pseudo-noisespreading code

real

2-64 Spread

TelephoneChannel

Description Telephone Channel Distortion ModelLibrary Numeric, Communications

Parameters

Pin Inputs


LinearDistortionTaps taps values of the FIR filterthat models lineardistortion

1.0 real array

Noise additive white Gaussiannoise distortion gain

0 real (-∞, ∞)

PhaseJitterFrequencyHz frequency of the phasejitter distortion to add tosignal, in Hertz

0.0 real [0.0, ∞)

PhaseJitterAmplitudeDeg phase jitter peakamplitude, in degrees

0.0 real (-∞, ∞)

FrequencyOffsetHz frequency offset distortionto add to the signal, inHertz

0.0 real [0.0, ∞)

SecondHarmonic proportion of the secondharmonic of the input thatis added to the originalsignal

0.0 real (-∞, ∞)

ThirdHarmonic proportion of the thirdharmonic of the input thatis added to the originalsignal

0.0 real (-∞, ∞)



TelephoneChannel 2-65


Pin Outputs

Notes/Equations

1. TelephoneChannel models the many types of distortion present in a telephonechannel (such as amplitude distortion and phase distortion). The sampling rateof the channel is 8000 samples per second.

2. To model linear distortion, such as intersymbol interference, the input signal ispassed through an FIR filter with the taps set by LinearDistortionTaps. Phasejitter and frequency offset distortions are then added to the signal.

Phase jitter is a consequence of the sensitivity of oscillators used for carriergeneration in single-sideband systems to fluctuations in power supply voltages.Whereas frequency offset is peculiar to telephone channels and channels withDoppler shift.

3. Nonlinear distortion is modeled by adding the second and third harmonics tothe signal. Nonlinear distortion is due to imperfections in amplifiers and totracking errors between A/D and D/A converters.

4. Gaussian noise with zero mean and a variance set by Noise is added. Primarily,there are four noise sources: quantization noise, thermal noise, impulse noise,and crosstalk.

5. See Also: AWGN_Channel, NoiseChannel, NonlinearDistortion.

References

[1]E. A. Lee and D. G. Messerschmitt, Digital Communication, Second Edition,Kluwer Academic Publishers, 1994, pp. 595-603.



2-66 TelephoneChannel

WalshCoder

Description Walsh code generatorLibrary Numeric, CommunicationsClass SDFWalshCoder

Parameters

Pin Outputs

Notes/Equations

1. This component is used to generate variable-length Walsh codes. Each firing, 1token is produced.

2. If Type=Walsh, the walsh codes are determined by:

N is the index of the walsh code, [0, Length-1]N = nJ-1nJ-2...n1n0K is the index of the chip in a walsh code, [0, Length-1]K = kJ-1kJ-2...k1k0J = log2Length


Type Walsh code type: Walsh,Hadamard, OVSF_3GPP

Walsh enum

Length Code length 8 int [1, 8192] †

Index Code index 0 int [0, Length-1]

† The length used must be integer power of 2.


1 Out Output int

hNK 1–( )

ri n( )ki

i 0=

J 1–

∑=

WalshCoder 2-67


r0(n) = nJ-1r1(n) = nJ-1+nJ-2r2(n) = nJ-2+nJ-3...

rJ-1(n) = n1+n0

If Type= Hadamard, the walsh codes are determined by:

.

.

.

If Type= OVSF_3GPP, the walsh codes are determined by:

H21 1

1 1–=

H4

H2 H2

H2 H– 2

=

H2m

H2m H

2m

H2m H–

2m

=

C0 0( ) 1=

C1 0( )

C1 1( )1 1

1 1–=

Cn 1+ 0( )

Cn 1+ 1( )

Cn 1+ 2( )

Cn 1+ 3( )

Cn 1+ 2n 1+

2–( )

Cn 1+ 2n 1+

1–( )

Cn 0( ) Cn 0( )

Cn 0( ) Cn 0( )–

Cn 1( ) Cn 1( )

Cn 1( ) Cn 1( )–

Cn 2n

1–( ) Cn 2n

1–( )

Cn 2n

1–( ) Cn 2n

1–( )

=

2-68 WalshCoder

References

[1]3GPP Technical Specification TS 25.213 V3.0.0 “Spreading and modulation(FDD),” October 1999.

WalshCoder 2-69


XmitSpread

Description Spread Spectrum TransmitterLibrary Numeric, Communications

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. XmitSpread is a direct-sequence spread spectrum transmitter. Each inputsample to be transmitted is modulated with a 31-bit pseudo-noise spreadingcode.

2. The PulseDuration parameter determines how many times each transmittedsample is repeated. Every input sample will result in 31 × PulseDurationtransmitted samples.

3. See also DeSpreader, RecSpread, Spread.

References



PulseDuration number of times to repeateach transmitted bit

1 int (0, ∞)


1 in input signal to transmit int


2 out transmitted signal int

2-70 XmitSpread

Numeric Control Components

Chapter 3: Numeric Control Components

IntroductionThe Numeric Control components library contains components that control signalflow in a data flow graph. These include signal bus merge, signal bus split, signalfork, signal distributor, signal commutator, and more. All of these components acceptas inputs any signal class and output signals of the same class after the signal controloperation is performed.

3-1


ActivatePath

Description Activate or remove succeeding blocksLibrary Numeric, Control

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. ActivatePath is used to activate or remove the succeeding blocks in a schematicdesign.

2. ActivatePath operates at the graph level. When the Activate parameter is set toNO, the succeeding block will be completely removed from the graph before thesimulation starts.

3. The Activate parameter cannot be swept.

4. ActivatePath does not match impedances for timed signals.


Activate "YES" to activatesucceeding blocks: NO,YES

YES enum


1 input multiple anytype


2 output multiple anytype

3-2 ActivatePath

5. For general information regarding numeric control components, refer to the“Introduction” on page 3-1.

ActivatePath 3-3


ActivatePath2

Description Activate or remove succeeding blocksLibrary Numeric, Control

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. ActivatePath2 is used to activate or remove the succeeding blocks in aschematic design.

2. ActivatePath2 operates at the graph level. When the Activate parameter is setto NO, the succeeding block will be completely removed from the graph beforethe simulation starts.

3. When activated (Activate=YES), output1 is connected to input1, output2 isconnected to input2.


Activate "YES" to activatesucceeding blocks: NO,YES

YES enum


1 input1 multiple anytype

2 input2 multiple anytype


3 output1 multiple anytype

4 output2 multiple anytype

3-4 ActivatePath2

4. The Activate parameter cannot be swept.

5. ActivatePath2 does not match impedances for timed signals.


ActivatePath2 3-5


AsyncCommutator

Description Asynchronous Data CommutatorLibrary Numeric, ControlClass SDFAsyncCommutatorC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. AsyncCommutator takes N input streams, where N is the input bus width, andasynchronously combines them into one output stream. It consumes Bi inputparticles from input #i (i=1, ... , N), where Bi are the elements of the BlockSizesparameter. It produces B1+B2+ ... + BN particles on the output. The first B1particles on the output come from the first input, the next B2 particles comefrom the second input, and so on.


BlockSizes block sizes read from eachinput

1 int array [1, ∞)†

† for each array element; number of elements in BlockSizes array must equal input bus width




2 output anytype

3-6 AsyncCommutator


AsyncCommutator 3-7


AsyncDistributor

Description Asynchronous Data DistributorLibrary Numeric, ControlClass SDFAsyncDistributorC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. AsyncDistributor takes one input stream and asynchronously splits it into Noutput streams, where N is the output bus width. It consumes B1+B2+ ... + BNparticles from the input, where Bi (i=1, ... , N) are the elements of theBlockSizes parameter. It produces Bi output particles on output#i (i= 1, ... , N).The particles on the first output are the first B1 particles of the input, theparticles on the second output are the next B2 particles of the input, and so on.


BlockSizes block sizes written to eachoutput

1 int array [1, ∞)†

† for each array element; number of elements in BlockSizes array must equal output bus width


1 input anytype



3-8 AsyncDistributor


AsyncDistributor 3-9


Bus

Description Bus Expander to specified bus widthLibrary Numeric, ControlClass HOFBusDerived From Nop

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The Bus component is used between two multiports and expands the input busto the output bus width specified.



BusWidth BusWidth 1 int [2, ∞)





3-10 Bus

BusMerge2

Description Merge 2 inputs to form a bus of width 2.Library Numeric, ControlClass HOFNop

Pin Inputs

Pin Outputs

Notes/Equations

1. The BusMerge2 component merges the top and bottom input busses into asingle bus. If the input bus widths are M1 and M2 and the output bus width isN, then N=M1+M2 is required. The first M1 outputs come from the first inputbus, while the next M2 outputs come from the second input bus. Both inputsignals must be of the same type.


3. An example that shows how this component is used can be accessed from theADS Main window: File > Example Project > PtolemyDocExamples >Numeric_Control_prj; from the Schematic window, choose File > Open Design,BusMerge2_example.dsn.


1 input#1 anytype

2 input#2 anytype



BusMerge2 3-11


BusMerge3


Pin Inputs

Pin Outputs

Notes/Equations

1. BusMerge3 merges all 3 input busses into a single bus. If the input bus widthsare M1, M2, and M3 and the output bus width is N, then N=M1+M2 +M3 isrequired. The first M1 outputs come from the first input bus, while the next M2outputs come from the second input bus, and so on. All signal inputs must be ofthe same type.


3. An example that shows how this component is used can be accessed from theADS Main window: File > Example Project > PtolemyDocExamples >Numeric_Control_prj; from the Schematic window, choose File > Open Design,BusMerge3_example.dsn.


1 input#1 anytype

2 input#2 anytype

3 input#3 anytype



3-12 BusMerge3

BusMerge4


Pin Inputs

Pin Outputs

Notes/Equations

1. BusMerge4 merges all 4 input busses into a single bus. If the input bus widthsare M1, M2, M3, and M4 and the output bus width is N, thenN=M1+M2+M3+M4 is required. The first M1 outputs come from the first inputbus, while the next M2 outputs come from the second input bus, and so on. Allsignal inputs must be of the same type.


3. An example that shows how a BusMerge component is used can be accessedfrom the ADS Main window: File > Example Project > PtolemyDocExamples >Numeric_Control_prj; from the Schematic window, choose File > Open Design,BusMerge2_example.dsn, BusMerge3_example.dsn, or BusMerge5_example.dsn.


1 input#1 anytype

2 input#2 anytype

3 input#3 anytype

4 input#4 anytype



BusMerge4 3-13


BusMerge5


Pin Inputs

Pin Outputs

Notes/Equations

1. BusMerge5 merges all 5 input busses into a single bus. If the input bus widthsare M1, M2, M3, M4, and M5 and the output bus width is N, thenN=M1+M2+M3+M4+M5 is required. The first M1 outputs come from the firstinput bus, while the next M2 outputs come from the second input bus, and soon. All signal inputs must be of the same type.


3. An example that shows how this component is used can be accessed from theADS Main window: File > Example Project > PtolemyDocExamples >


1 input#1 anytype

2 input#2 anytype

3 input#3 anytype

4 input#4 anytype

5 input#5 anytype



3-14 BusMerge5

Numeric_Control_prj; from the Schematic window, choose File > Open Design,BusMerge5_example.dsn.

BusMerge5 3-15


BusMerge6


Pin Inputs

Pin Outputs

Notes/Equations

1. BusMerge6 merges all 6 input busses into a single bus. If the input bus widthsare M1, M2, ... , M6 and the output bus width is N, then N=M1+M2 ... +M6 isrequired. The first M1 outputs come from the first input bus, while the next M2outputs come from the second input bus, and so on. All signal inputs must be ofthe same type.


3. An example that shows how a BusMerge component is used can be accessedfrom the ADS Main window: File > Example Project > PtolemyDocExamples >


1 input#1 anytype

2 input#2 anytype

3 input#3 anytype

4 input#4 anytype

5 input#5 anytype

6 input#6 anytype



3-16 BusMerge6

Numeric_Control_prj; from the Schematic window, choose File > Open Design,BusMerge2_example.dsn, BusMerge3_example.dsn, or BusMerge5_example.dsn.

BusMerge6 3-17


BusMerge7


Pin Inputs

Pin Outputs

Notes/Equations

1. BusMerge7 merges all 7 input busses into a single bus. If the input bus widthsare M1, M2, ... , M7 and the output bus width is N, then N=M1+M2 ... +M7 isrequired. The first M1 outputs come from the first input bus, while the next M2outputs come from the second input bus, and so on.

All signal inputs must be of the same type.



1 input#1 anytype

2 input#2 anytype

3 input#3 anytype

4 input#4 anytype

5 input#5 anytype

6 input#6 anytype

7 input#7 anytype



3-18 BusMerge7


BusMerge7 3-19


BusMerge8


Pin Inputs

Pin Outputs

Notes/Equations

1. BusMerge8 merges all 8 input busses into a single bus. If the input bus widthsare M1, M2, ... , M8 and the output bus width is N, then N=M1+M2+ ... +M8 isrequired. The first M1 outputs come from the first input bus, while the next M2outputs come from the second input bus, and so on.




1 input#1 anytype

2 input#2 anytype

3 input#3 anytype

4 input#4 anytype

5 input#5 anytype

6 input#6 anytype

7 input#7 anytype

8 input#8 anytype



3-20 BusMerge8


BusMerge8 3-21


BusMerge9


Pin Inputs

Pin Outputs

Notes/Equations

1. BusMerge9 merges all 9 input busses into a single bus. If the input bus widthsare M1, M2, ... , M9 and the output bus width is N, then N=M1+M2+, ... , +M9 isrequired. The first M1 outputs come from the first input bus, while the next M2outputs come from the second input bus, and so on.



1 input#1 anytype

2 input#2 anytype

3 input#3 anytype

4 input#4 anytype

5 input#5 anytype

6 input#6 anytype

7 input#7 anytype

8 input#8 anytype

9 input#9 anytype



3-22 BusMerge9



BusMerge9 3-23


BusSplit2

Description Split input bus to 2 output buses.Library Numeric, ControlClass HOFNop

Pin Inputs

Pin Outputs

Notes/Equations

1. BusSplit2 splits an input bus into two busses. If the input bus width is N, andthe output bus widths are M1 and M2, then N=M1+M2 is required. The first M1inputs go to the first output bus, while the next M2 inputs go to the secondoutput bus.

2. BusSplit2 splits the constituent signals of the input bus. It produces 2 singlesignal outputs, both of the same type as the input.


4. An example that shows how this component is used can be accessed from theADS Main window: File > Example Project > PtolemyDocExamples >Numeric_Control_prj; from the Schematic window, choose File > Open Design,BusSplit2_example.dsn.




2 output#1 anytype

3 output#2 anytype

3-24 BusSplit2

BusSplit3


Pin Inputs

Pin Outputs

Notes/Equations

1. BusSplit3 component splits an input bus into 3 busses. If the input bus width isN, and the output bus widths are M1, M2, and M3 then N=M1+M2+M3 isrequired. The first M1 inputs go to the first output bus, while the next M2inputs go to the second output bus and so on.

2. BusSplit3 splits the constituent signals of the input bus. It produces 3 singlesignal outputs, all of the same type as the input.


4. An example that shows how this component is used can be accessed from theADS Main window: File > Example Project > PtolemyDocExamples >




2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

BusSplit3 3-25


Numeric_Control_prj; from the Schematic window, choose File > Open Design,BusSplit3_example.dsn.

3-26 BusSplit3

BusSplit4


Pin Inputs

Pin Outputs

Notes/Equations

1. BusSplit4 splits an input bus into 4 busses. If the input bus width is N, and theoutput bus widths are M1, M2, M3 and M4, then N=M1+M2+M3+M4 isrequired. The first M1 inputs go to the first output bus, while the next M2inputs go to the second output bus, and so on.



4. An example that shows how a BusSplit component is used can be accessed fromthe ADS Main window: File > Example Project > PtolemyDocExamples >




2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

BusSplit4 3-27


Numeric_Control_prj; from the Schematic window, choose File > Open Design,BusSplit2_example.dsn, BusSplit3_example.dsn, BusSplit5_example.dsn, orBusSplit7_example.dsn.

3-28 BusSplit4

BusSplit5


Pin Inputs

Pin Outputs

Notes/Equations

1. BusSplit5 splits an input bus into 5 busses. If the input bus width is N, and theoutput bus widths are M1, M2, M3, M4, and M5, then N=M1+M2+M3+M4+M5is required. The first M1 inputs go to the first output bus, while the next M2inputs go to the second output bus, and so on.






2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

6 output#5 anytype

BusSplit5 3-29



3-30 BusSplit5

BusSplit6


Pin Inputs

Pin Outputs

Notes/Equations

1. BusSplit6 splits an input bus into 6 busses. If the input bus width is N, and theoutput bus widths are M1, M2, M3, M4, M5, and M6, thenN=M1+M2+M3+M4+M5+M6 is required. The first M1 inputs go to the firstoutput bus, while the next M2 inputs go to the second output bus, and so on.






2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

6 output#5 anytype

7 output#6 anytype

BusSplit6 3-31


4. An example that shows how a BusSplit component is used can be accessed fromthe ADS Main window: File > Example Project > PtolemyDocExamples >Numeric_Control_prj; from the Schematic window, choose File > Open Design,BusSplit2_example.dsn, BusSplit3_example.dsn, BusSplit5_example.dsn, orBusSplit7_example.dsn.

3-32 BusSplit6

BusSplit7


Pin Inputs

Pin Outputs

Notes/Equations

1. BusSplit7 splits an input bus into 7 busses. If the input bus width is N, and theoutput bus widths are M1, M2, M3, M4, M5, M6, and M7 thenN=M1+M2+M3+M4+M5+M6+M7 is required. The first M1 inputs go to the firstoutput bus, while the next M2 inputs go to the second output bus, and so on.






2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

6 output#5 anytype

7 output#6 anytype

8 output#7 anytype

BusSplit7 3-33



3-34 BusSplit7

BusSplit8


Pin Inputs

Pin Outputs

Notes/Equations

1. BusSplit8 splits an input bus into 8 busses. If the input bus width is N, and theoutput bus widths are M1, M2, ... , M8 then N=M1+M2+ ... +M8 is required.The first M1 inputs go to the first output bus, while the next M2 inputs go to thesecond output bus, and so on.





2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

6 output#5 anytype

7 output#6 anytype

8 output#7 anytype

9 output#8 anytype

BusSplit8 3-35




3-36 BusSplit8

BusSplit9


Pin Inputs

Pin Outputs

Notes/Equations

1. BusSplit9 splits an input bus into 9 busses. If the input bus width is N, and theoutput bus widths are M1, M2, ... , M9 then N=M1+M2+ ... +M9 is required.The first M1 inputs go to the first output bus, while the next M2 inputs go to thesecond output bus, and so on.





2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

6 output#5 anytype

7 output#6 anytype

8 output#7 anytype

9 output#8 anytype

10 output#9 anytype

BusSplit9 3-37




3-38 BusSplit9

Chop

Description Chop input data into blocksLibrary Numeric, ControlClass SDFChopC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. On each execution, the Chop component reads a block of nRead data items andwrites them to the output with the given Offset. The number of data itemswritten is given by nWrite. The output block contains all or part of the input


nRead number of data items read 128 int [1, ∞)

nWrite number of data itemswritten

64 int [1, ∞)

Offset start of output blockrelative to start of inputblock

0 int (-∞, ∞)

UsePastInputs use previously read inputs:NO, YES

YES enum


1 input anytype


2 output anytype

Chop 3-39


block, depending on Offset and nWrite. Offset specifies where in the outputblock the first (oldest) data item in the input block will lie. If Offset is positive,the first Offset output data items will be data items consumed on previousfirings (if UsePastInputs parameter is YES), or 0 (otherwise). If Offset isnegative, the first Offset input data items will be discarded.

2. This component reads a sequence of input data items of any type, and writes asequence of data items constructed from the input sequence (and possiblyzeros). The number of input data items consumed is given by nRead, and thenumber of output data items produced is given by nWrite. The Offset parameter(default 0) specifies where in the output block the first (oldest) input should go.

A simple use of this component is to pad a block of inputs with 0s(zero-padding). Set Offset to 0 and use nWrite>nRead. Another simple use is toobtain overlapping windows from an input stream. Set UsePastInputs to YES,use nWrite > nRead, and set Offset equal to nWrite-nRead.

The general operation is illustrated with the following examples. If Offset ispositive, there are two possible scenarios:

The symbol i refers to any input data item. The left-most symbol refers to theoldest input data item of the ones consumed in a given firing. The symbol prefers to a data item that is either 0 (if UsePastInputs is NO) or is equal to apreviously consumed input data item (if UsePastInputs is YES). The symbol 0refers to a zero-valued data item. In the first of the above examples, the entireinput block is copied to the output, and then filled out with 0s. In the secondexample, only a portion of the input block fits. The remaining input data itemsare discarded.

iiiiii nRead = 6\ \ Offset = 2

ppiiiiii00 nWrite = 10

iiiiii nRead = 6\ \ Offset = 2

ppiii nWrite = 5

3-40 Chop

When the Offset is negative, the corresponding scenarios are:

In the first of these examples, the first two input data items are discarded; inthe second example, the first two and the last input data item are discarded.

The zero-valued data items are constructed using the .c initialize() method ofthe appropriate data item class. This returns a floating point (real) zero, aninteger zero, a complex zero, and so forth, for numerically-valued data items.However, if the data item is a matrix message data item, then matrix ormessages of type DUMMY are used for zeros.


iiiiii nRead = 6/ / Offset = -2

iiii000000 nWrite = 10

iiiiii nRead = 6/ / Offset = -2

iii nWrite = 3

Chop 3-41


ChopVarOffset

Description Chop input data into blocks with offset controlLibrary Numeric, ControlClass SDFChopVarOffsetDerived From ChopC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. ChopVarOffset has the same functionality as the Chop component except thatthe Offset parameter is determined at run time by a control input and theUsePastInputs parameter is set to FALSE and not accessible.



nRead number of data items read 128 int [1, ∞)

nWrite number of data itemswritten

64 int [1, ∞)


1 input anytype

2 offsetCntrl int


3 output anytype

3-42 ChopVarOffset

Commutator

Description Synchronous Data CommutatorLibrary Numeric, ControlClass SDFCommutatorC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component takes N input streams and synchronously combines them intoone output stream. It consumes B input data packets from each input (where Bis BlockSize), and produces N×B data packets on the output.



BlockSize Number of particles in ablock.

1 int [1, ∞)




2 output anytype

Commutator 3-43


Commutator2

Description 2-Input Synchronous Data CommutatorLibrary Numeric, ControlClass SDFCommutatorC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component takes 2 input streams and synchronously combines them intoone output stream. It accepts 2 single signals, both of the same type.

It consumes B input data packets from each input (where B is BlockSize), andproduces 2B data packets on the output. The first B data packets on the outputcome from the first input, the next B data packets from the next input.




1 int [1, ∞)


1 input#1 anytype

2 input#2 anytype


3 output anytype

3-44 Commutator2

Commutator3


Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Commutator3 takes 3 input streams and synchronously combines them into oneoutput stream. It accepts 3 single signals, all of the same type.

It consumes B input data packets from each input (where B is BlockSize), andproduces 3B data packets on the output. The first B data packets on the outputcome from the first input, the next B data packets from the next input, and soon.



1 int [1, ∞)


1 input#1 anytype

2 input#2 anytype

3 input#3 anytype


4 output anytype

Commutator3 3-45



3-46 Commutator3

Commutator4


Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Commutator4 takes 4 input streams and synchronously combines them into oneoutput stream. It accepts 4 single signals, all of the same type.

It consumes B input data packets from each input (where B is BlockSize), andproduces 4B data packets on the output. The first B data packets on the output



1 int [1, ∞)


1 input#1 anytype

2 input#2 anytype

3 input#3 anytype

4 input#4 anytype


5 output anytype

Commutator4 3-47


come from the first input, the next B data packets from the next input, and soon.


3-48 Commutator4

Delay

Description Delay ComponentLibrary Numeric, ControlClass HOFDelayDerived From Nop

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component delays input tokens from output by N samples. The initial Noutput tokens have a null value.

2. For timed signals, use the DelayRF component.



N N 1 int [0, ∞)





Delay 3-49


DeMux

Description Data demultiplexerLibrary Numeric, ControlClass SDFDeMuxC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. DeMux demultiplexes one input onto any number of output streams. DeMuxconsumes B packets of data from the input, where B is the BlockSize. These Bdata packets are copied to exactly one output, determined by the control input.The other outputs get a zero of the appropriate type.

2. Integers 0 through N-1 are accepted at the control input, where N is thenumber of outputs. If the control input is outside this range, all outputs getzero.


BlockSize number of data items in ablock

1 int [1, ∞)


1 input anytype

2 control int



3-50 DeMux


DeMux 3-51


DeMux2

Description 2-Output Data DemultiplexerLibrary Numeric, ControlClass SDFDeMuxC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. DeMux2 directs one input to either of two outputs based on the logic state (0 or1) of the control input. DeMux2 produces 2 single signal outputs, all of the sametype as the input.




1 int [1, ∞)


1 input anytype

2 control int


3 output#1 anytype

4 output#2 anytype

3-52 DeMux2

Distributor

Description Synchronous Data DistributorLibrary Numeric, ControlClass SDFDistributorC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Distributor synchronously splits one input stream into N output streams. Itconsumes N×B input particles (where B = BlockSize) and sends the first Bparticles to the first output, the next B particles to the next output, and so on. Itproduces a single signal output of the same type as input.

The number of output streams, N, is equal to the number of other componentinput pins connected to the Distributor output pin. For an ordered distributionof output streams to input pins, a BusSplit[2, ... , 9] component can be



1 int [1, ∞)


1 input anytype



Distributor 3-53


connected to the Distributor output pin and other component input pinsconnected to the BusSplit[2, ... , 9] component output pins.


3-54 Distributor

Distributor2

Description 2-Output Synchronous Data DistributorLibrary Numeric, ControlClass SDFDistributorC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Distributor2 synchronously splits one input stream into 2 output streams. Itconsumes 2×B input particles (where B = BlockSize) and sends the first Bparticles to the first output and the next B particles to the second output. Itproduces 2 single signal outputs, both of the same type as the input.




1 int [1, ∞)


1 input anytype


2 output#1 anytype

3 output#2 anytype

Distributor2 3-55


Distributor3


Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Distributor3 synchronously splits one input stream into 3 output streams. Itconsumes 3×B input particles (where B = BlockSize) and sends the first Bparticles to the first output, the second B particles to the second output, and thethird B particles to the third output. It produces 3 single signal outputs, all ofthe same type as the input.



1 int [1, ∞)


1 input anytype


2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

3-56 Distributor3


Distributor3 3-57


Distributor4


Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Distributor4 synchronously splits one input into 4 output streams. It consumes4×B input particles (where B = BlockSize) and sends the first B particles to thefirst output, the second B particles to the second output, the third B particles tothe third output, and the fourth B particles to the fourth output. It produces 4single signal outputs, all of the same type as the input.



1 int [1, ∞)


1 input anytype


2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

3-58 Distributor4


Distributor4 3-59


DownSample

Description Data Down SamplerLibrary Numeric, ControlClass SDFDownSampleC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Down-sampling is also referred to as decimation. This component reduces thesampling rate of its input signal by an integer Factor ratio. Decimation isperformed by keeping one sample at the output for every Factor samples at theinput.

2. This component does not have a built-in lowpass filter before decimation. Toavoid aliasing, it may be necessary for the user to ensure that the input signalbandwidth is appropriately limited by connecting a lowpass filter at the input.


Factor downsample factor 2 int [1, ∞)

Phase downsample phase 0 int [0, Factor-1]


1 input anytype


2 output anytype

3-60 DownSample

3. Phase tells which sample to output: if Phase=0, the most recent sample is theoutput; if Phase=Factor-1 the oldest sample is the output. y[n] =x[Factor*(n+1)-Phase-1)], where n is the output sample number, y is the output,and x is the input. (Note that phase has the opposite sense of the Phaseparameter in the UpSample component, but the same sense as the Phaseparameter in the FIR component.)

4. For timed signals, use the DSampleRF component.


DownSample 3-61


EnableUDSample

Description Data Up/Down SamplerLibrary Numeric, Control

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. EnableUDSample can be used to resample the input signal at a new rate.Resampling occurs only when the Enable parameter is set to YES.

2. When USample is greater than 1 upsampling will occur. Upsampling is done assample and hold (repeat input sample USample times).


Enable enable the up/downsampling: NO, YES

NO enum

USample upsample ratio 1 int [1, ∞)

DSample downsample ratio 1 int [1, ∞)


1 input input signal anytype


2 output output signal anytype

3-62 EnableUDSample

When DSample is greater than 1 downsampling will occur. The downsamplingphase is DSample-1, that is, the first out of every DSample samples is selectedand the subsequent DSample-1 samples are discarded.

If USample is smaller than DSample loss of information may occur.


EnableUDSample 3-63


Fork

Description Copy input particles to each output.Library Numeric, ControlClass HOFForkDerived From Base

Pin Inputs

Pin Outputs

Notes/Equations

1. Fork is generally used to explicitly connect a single output port of a componentto multiple input ports of other components. Fork cannot be used to connect amulti-port output of a component to multiple multi-port inputs of othercomponents. For example, the input of the Fork component cannot be connectedto a bus of width >1.

2. In many data flow graphs, the explicit use of this component is optional. If notused, it will be automatically inserted when multiple inputs are connected tothe same output in a schematic.

Automatically inserted Fork components are not always desirable:

• When multi-port inputs or outputs are used, auto-forking can causeproblems—for example, two outputs and several inputs on the same net.


1 input anytype



3-64 Fork

• When there is a delay on one of the arcs, Fork must be explicitly inserted bythe user to avoid ambiguity about the location of the delay.


Fork 3-65


Fork2

Description Copy input particles to each output.Library Numeric, ControlClass HOFFork

Pin Inputs

Pin Outputs

Notes/Equations

1. Fork2 is generally used to explicitly connect a single output port of a componentto multiple input ports of other components. Fork2 cannot be used to connect amulti-port output of a component to multiple multi-port inputs of othercomponents. For example, the input of the Fork2 component cannot beconnected to a bus of width >1.


Automatically inserted Fork2 components are not always desirable:



1 input anytype


2 output#1 anytype

3 output#2 anytype

3-66 Fork2

• When there is a delay on one of the arcs, Fork2 must be explicitly inserted bythe user to avoid ambiguity about the location of the delay.

3. Fork2 connects a single output port of a component to 2 input ports of othercomponents. It has 2 single output ports rather than one multi-port output.


Fork2 3-67


Fork3


Pin Inputs

Pin Outputs

Notes/Equations






1 input anytype


2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

3-68 Fork3




Fork3 3-69


Fork4


Pin Inputs

Pin Outputs

Notes/Equations





1 input anytype


2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

3-70 Fork4





Fork4 3-71


Fork5


Pin Inputs

Pin Outputs

Notes/Equations





1 input anytype


2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

6 output#5 anytype

3-72 Fork5





Fork5 3-73


Fork6


Pin Inputs

Pin Outputs

Notes/Equations





1 input anytype


2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

6 output#5 anytype

7 output#6 anytype

3-74 Fork6





Fork6 3-75


Fork7


Pin Inputs

Pin Outputs

Notes/Equations




1 input anytype


2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

6 output#5 anytype

7 output#6 anytype

8 output#7 anytype

3-76 Fork7






Fork7 3-77


Fork8


Pin Inputs

Pin Outputs

Notes/Equations



1 input anytype


2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

6 output#5 anytype

7 output#6 anytype

8 output#7 anytype

9 output#8 anytype

3-78 Fork8







Fork8 3-79


Fork9


Pin Inputs

Pin Outputs

Notes/Equations



1 input anytype


2 output#1 anytype

3 output#2 anytype

4 output#3 anytype

5 output#4 anytype

6 output#5 anytype

7 output#6 anytype

8 output#7 anytype

9 output#8 anytype

10 output#9 anytype

3-80 Fork9







Fork9 3-81


IfElse

Description Map one of two blocksLibrary Numeric, ControlClass HOFIfElseDerived From Map

Parameters

Pin Inputs

Pin Outputs

Notes/Equations


Condition Select ’False’ or ’True’ pathbased on the Condition:False, True

True enum False or True


1 input Input to the IfElse component multiple anytype

2 true_mapoutput Connect to the output pin, if any, of the design paththat will be selected if Condition evaluates to TRUE

multiple anytype

3 false_mapoutput Connect to the output pin, if any, of the design paththat will be selected if Condition evaluates to FALSE

multiple anytype


4 true_mapinput Connect to the input pin, if any, of the design paththat will be selected if Condition evaluates to TRUE

multiple anytype

5 output Output from the IfElse component multiple anytype

6 false_mapinput Connect to the input pin, if any, of the design paththat will be selected if Condition evaluates to FALSE

multiple anytype

3-82 IfElse

1. IfElse can be used to select one of the two components, the one in the true pathor the one in the false path, and insert it in the signal flow path. If more thanone component need to be connected to the true/false path they must be placedin a subnetwork and the subnetwork connected to the path.

The Condition parameter determines which path will be selected. If Conditionis set to False, then the false path is selected; if Condition is set to True, thenthe true path is selected; if Condition is set to a variable or expression, thevariable or expression must have a value of 0 or 1 (0 is treated as False and 1 istreated as True). Other values will result in a simulation error.

2. IfElse is similar to the Mux2 component with some differences as well asadvantages and disadvantages. Figure 3-1 shows how IfElse and Mux2 can beused to generate equivalent schematics; these schematics will produce identicalresults assuming Condition is 0 or 1.

The important difference between IfElse and Mux2 is that IfElse operates atthe graph level (which means that the component not selected by IfElse iscompletely removed from the graph before the simulation starts), whereasMux2 operates at the signal level (which means that both input signals of Mux2must be generated, then Mux2 selects one of them).

The advantage of operating at the graph level is that because one of the twocomponents connected to the true or false path of IfElse is completely removedfrom the graph, only the selected one is simulated thus saving computingresources. On the other hand, the advantage of Mux2 is that the control signalthat selects which of the two input signals will be selected can change duringthe simulation. In fact, this (a varying control signal) is the most typical use ofMux2. Having a constant control signal, as shown in Figure 3-1, is not a typicaluse of Mux2 (the purpose of the example in Figure 3-1 is to help explainsimilarities/differences between IfElse and Mux2 and not to provide a typicalexample for Mux2).

Another difference between the two schematics in Figure 3-1 is that theCondition parameter of IfElse is not sweepable, whereas the Level parameter ofthe ConstInt component (although constant during the simulation) issweepable.

IfElse 3-83


Figure 3-1. Equivalent Schematics Using IfElse and Mux2

3. Although the Condition parameter of IfElse cannot be swept, the parameters ofthe components in the true or false path can be swept; for this, the expressionssetting the values of these parameters must be enclosed in double quotes. Forexample, if a Repeat component is connected to the true or false path of IfElseand there is a swept variable called Rate, in order to use this variable to set theNumTimes parameter of Repeat the assignment should be done asNumTimes="Rate" or NumTimes="3*Rate+1".

If more complicated expressions using functions such as sin(), log(), or sqrt()need to be used, then an intermediate variable must be defined. For the

3-84 IfElse

example described above, in order to set NumTimes to int( sqrt(Rate) +3*log(Rate) ) an intermediate variable (RepeatFactor for example) must bedefined in a VAR block as RepeatFactor=int( sqrt(Rate) + 3*log(Rate) ). Thenthe NumTimes parameter of Repeat must be set as NumTimes="RepeatFactor".

The above examples are exceptions to how expressions using swept variablesare used to assign values to component parameters. These exceptions applyonly to the parameters of the components connected to the true or false paths ofIfElse.

4. IfElse is intended for use with numeric components. Timed components can beconnected to the true or false path of IfElse but any series or shunt resistorsconnected outside IfElse that could form resistor networks with the resistorsinside the timed components will not be correctly evaluated.

Connecting Analog/RF subnetworks to the true or false path of IfElse is notsupported. The simulator will not error out but the results of the simulation arenot guaranteed to be correct.

5. To access examples that show how this component is used: from the Mainwindow, choose File > Example Project > PtolemyDocExamples >Numeric_Control_prj; from the Schematic window, choose File > Open Design,IfElse_Example1.dsn, IfElse_Example2.dsn, or IfElse_Example3.dsn. Moreexamples showing the usage of IfElse are the Bits and the TkConstellationsubnetworks (place these components in a schematic window and push intothem).


IfElse 3-85


InitDelay

Description Initial Delay ComponentLibrary Numeric, ControlClass HOFInitDelayDerived From Delay

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. InitDelay delays input tokens from output by N sets of initial delay tokens.



N N 1 int [0, ∞)

InitialDelays StringArray containing alist of intial delay tokens.

0 string array





3-86 InitDelay

Mux

Description Data multiplexerLibrary Numeric, ControlClass SDFMuxC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Mux multiplexes any number of inputs onto one output stream. At each firing,BlockSize data packets are consumed on each input, but only one of these blocksof data is copied to the output, as determined by the control input. Integersfrom 0 through N-1 are accepted at the control input, where N is the number ofinputs. If the control input is outside this range, an error is signaled.

Use of a BusMerge component at input 2 of the Mux is recommended to ensurethat the order of inputs is not ambiguous. When a BusMerge component is



1 int [1, ∞)


1 control int



3 output anytype

Mux 3-87


used, control inputs 0 through N-1 select inputs at pin 1 through N of theBusMerge, respectively.


3-88 Mux

Mux2

Description 2-Input Data MultiplexerLibrary Numeric, ControlClass SDFMuxC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Mux2 multiplexes 2 inputs onto one output stream. At each firing, BlockSizedata packets are consumed on each single signal input pin. Only one of theseblocks of data is copied to the output; the one copied is determined by thecontrol input. Integers 0 to 1 are accepted at the control input; 0 selects theinput at pin 2; 1 selects the input at pin 3.



1 int [1, ∞)


1 control int

2 input#1 anytype

3 input#2 anytype


4 output anytype

Mux2 3-89



3-90 Mux2

Repeat

Description Data repeaterLibrary Numeric, ControlClass SDFRepeatC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Repeat repeats each input data packet the specified number of times(NumTimes) on the output. Note that this is a sample rate change, andtherefore affects the number of invocations of downstream components.



NumTimes repetition factor 2 int [1, ∞)


1 int [1, ∞)


1 input anytype


2 output anytype

Repeat 3-91


Reverse

Description Data reverserLibrary Numeric, ControlClass SDFReverseC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. On each execution, Reverse reads a block of N samples and writes the samplesbackwards.



N number of data items readand written

64 int [1, ∞)


1 input anytype


2 output anytype

3-92 Reverse

Trainer

Description Initial Sample TrainerLibrary Numeric, ControlClass SDFTrainerC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Trainer passes the value of the train input to the output for the firstTrainLength samples, then passes the decision input to the output. Thiscomponent is designed for use with adaptive equalizers that require a trainingsequence at startup, but it can be used whenever one sequence is used during astartup phase, and another sequence after that.

2. During the startup phase, the decision inputs are discarded. After the startupphase, the train inputs are discarded.


TrainLength number of training samplesto use

100 int [0, ∞)


1 train anytype

2 decision anytype


3 output anytype

Trainer 3-93



3-94 Trainer

Transpose

Description Data transposerLibrary Numeric, ControlClass SDFTransposeC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Transpose transposes a rasterized matrix (one that is read as a sequence ofdata items, row by row, and written in the same form). The number of dataitems produced and consumed equals the product of SamplesInaRow andNumberOfRows.



SamplesInaRow number of input samplesconstituting a row

8 int [1, ∞)

NumberOfRows number of rows in the inputmatrix

8 int [1, ∞)


1 input anytype


2 output anytype

Transpose 3-95


UpSample

Description Data Up SamplerLibrary Numeric, ControlClass SDFUpSampleC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The Upsample component upsamples by a given Factor, giving inserted samplesthe value Fill. The Phase parameter tells where to put the sample in an outputblock. A Phase of 0 indicates to output the input sample first followed by theinserted samples. The maximum Phase is Factor-1. y[Factor*n]=x[n+Phase],where n is the input sample number, y is the output, x is the input.


Factor number of samplesproduced

2 int [1, ∞)

Phase where to put the input inthe output block

0 int [0, Factor-1]

Fill value to fill the output block 0.0 real (-∞, ∞)


1 input anytype


2 output anytype

3-96 UpSample

2. Although the Fill parameter is a floating-point (real) number, if the input is ofsome other type, such as complex, then Fill data will be obtained by casting Fillto the appropriate type.

3. For timed signals, use the USampleRF component.

The USampleRF component has options for specifying how the inserted valueswill be generated: SampleAndHold, ZeroInsertion, PolyPhaseFilter, Linear.

The UpSample component implements the ZeroInsertion option only, assumingFill is set to 0. While UpSample cannot implement other USampleRF options,other components in the Numeric library can be used to implement them.

• The SampleAndHold option can be implemented by the Repeat component.The NumTimes parameter of the Repeat component should be set to theupsampling factor and the BlockSize parameter should be set to 1. Figure 3-2shows how to set the Repeat and the USampleRF components to getequivalent results.

Figure 3-2. Equivalence of Repeat and SampleAndHold Option of USampleRF

• The PolyPhaseFilter option can be implemented by the RaisedCosinecomponent. Parameters of the RaisedCosine component should be set asfollows: Decimation=1, DecimationPhase=0, Interpolation=N, Length=20*N,SymbolInterval=N, ExcessBW=a, and SquareRoot=0 (where N is theUSampleRF Ratio parameter value and a is the USampleRF ExcessBWparameter value). Figure 3-3 shows how to set the RaisedCosine and theUSampleRF components to get equivalent results.

UpSample 3-97


Figure 3-3. Equivalence of RaisedCosine and PolyPhaseFilter Option of USampleRF.

• The Linear option can be implemented by the FIR component. FIRparameters should be set as follows: Taps= "0 (1/N) (2/N) ... ((N-1)/N) 1((N-1)/N) ... (1/N)", Decimation=1, DecimationPhase=0, Interpolation=N(where N is the USampleRF Ratio parameter value). (Note that the open andclose quotes in the Taps parameter value are required.) Figure 3-4 shows howto set the FIR and the USampleRF components to get equivalent results.

Figure 3-4. Equivalence of FIR and Linear Option of USampleRF

• For completeness, Figure 3-5 shows the equivalance of UpSample and theZeroInsertion option USampleRF.

3-98 UpSample

Figure 3-5. Equivalence of UpSample and ZeroInsertion Option of USampleRF


UpSample 3-99


3-100 UpSample

Chapter 4: Numeric Logic Components

Introduction

The Numeric Logic component library contains operators on Boolean valued integersignals (values are either 0 or 1) or double precision floating-point (real) signals. Eachcomponent produces Boolean integer values. Positive logic is used: low (or false) = 0,high (or true) = 1.

If a component receives another class of signal, the received signal is automaticallyconverted to the signal class specified as the input of the component. Auto conversionfrom a higher to a lower precision signal class may result in loss of information. Fordetails on conversions between different classes of signals, refer to “Conversion ofData Types” in the ADS Ptolemy Simulation manual.

Introduction 4-1

Numeric Logic Components

DFF

Description D-Type Binary Data Flip-Flop (Edge Triggered)Library Numeric, LogicClass SDFDFFDerived From baseOmniSysNumericStar

Pin Inputs

Pin Outputs

Notes/Equations

1. Function table


1 R clear input int

2 C clock input int

3 D D input int

4 S preset input int


5 Q Q output int

6 NQ inverted Q output int

Inputs Outputs

R (Pin 1) C (Pin 2) D (Pin 3 S (Pin 4) Q (Pin 5) NQ (Pin 6)

H x x L H L

L x x H L H

L x x L H H

H UP H H H L

H UP L H L H

4-2 DFF

2. At the first sample, the outputs Q and NQ are equal to L and H, respectively.

3. Input, output and clock signal values of the DFF component, with S (pin 4) andR (pin 1) both tied to a high logic level, are shown in Figure 4-1.

4. For information regarding numeric logic component signals, refer to the“Introduction” on page 4-1.

H L x H Q0 NQ0

whereS = input preset, active with logic low levelR = input clear, active with logic low levelC = input clock, active with low to high transitionx = don’t care stateL = logic low level. Input: < 0.5; Output: 0.0H = logic high level. Input: > 0.5; Output: 1.0UP = low-to-high transitionQ0 = previous Q stateNQ = inverted Q stateNQ0 = previous inverted Q state

Inputs Outputs

R (Pin 1) C (Pin 2) D (Pin 3 S (Pin 4) Q (Pin 5) NQ (Pin 6)

DFF 4-3


Figure 4-1. DFF Input, Output, and Clock Signal Values

InputSignal D(pin 3)

InputSignal C(pin 2)

OutputSignal Q(pin 5)

Output SignalQ (pin 6)

4-4 DFF

DivByN

Description Binary Data Divide-By-N CounterLibrary Numeric, LogicClass SDFDivByNDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. DivByN is a model of a positive edge-triggered, modulo N down counter. Theinput to the component is a clock signal; the output is a signal that is high orlow, depending on whether the current counter value is greater or less thanfloor (N/2). (Note that the counter value itself is not available as an output.)

Let M(k) denote the counter value after the kth positive clock edge. Then

M(0) = N0M(k) = (M(k−1) −1) modulo N, k ≥ 1


N divide-by factor 1 int [1, ∞)

N0 initial counter value 0 int [0, N)


1 input input signal int


2 output output signal int

DivByN 4-5


2. The input and output signal values of the DivByN component, parameters N=5and N0=4, are shown in Figure 4-2.

Note that the initial counter value is 4, and therefore the output is low (becauseit is ≥ 2 (floor(5/2)). When the first input positive edge occurs, the counter isdecremented to 3 and the output is still low. At the second input positive edge,the counter is decremented to 2 and the output is low. At the third positive edgethe counter is decremented to 1, which makes the output high (because it is < 2(floor(N/2))). Similarly, at the fourth positive edge, the counter decrements to 0and the output is high. At the fifth positive edge, the counter decrements tonegative and is therefore reset to 4 and the output is low.

The input and output signal values of the DivByN component, parameters N=5and N0=1, are shown in Figure 4-3.

Note that the initial counter value is 1, and therefore the output is high(because it is < 2 (floor(5/2)). At the first input positive edge, the counter isdecremented to 0, which means that the output is still high. At the secondpositive edge the counter is reset to 4 and the output is low.

V2 t( )0 if M(k) floor N

2-----

≥

1 if M(k) < floor N2-----

=

4-6 DivByN

Figure 4-2. DivByN Input and Output Signal Values,N=5 and N0=4

Figure 4-3. DivByN Input and Output Signal Values,N=5 and N0=1


OutputSignal

InputSignal

InputSignal

OutputSignal

DivByN 4-7


JKFF

Description Binary Data J-K Type Flip-FlopLibrary Numeric, LogicClass SDFJKFFDerived From baseOmniSysNumericStar

Pin Inputs

Pin Outputs

Notes/Equations

1. Function table:


1 R clear input int

2 K K input int

3 C clock input int

4 J J input int

5 S preset input int


6 Q Q output int

7 NQ inverted Q output int

Input Output

R (pin 1) K (pin 2) C (pin 3) J (pin 4) S (pin 5) Q (pin 6) NQ (pin 7)

L x x x L H H

H x x x L H L

L x x x H L H

H L UP L H Q0 NQ0

4-8 JKFF

2. At the first sample, the outputs Q and NQ are equal to L and H, respectively.

3. The input and output signal values of the JKFF component, with S (pin 5) andR (pin 1) both tied to a high logic level, are shown in Figure 4-4.

The clock signal (not shown) is set such that it is first active (low to hightransition occurs) at the first 0.5 grid unit and has a period of 1 grid unit.

H L UP H H H L

H H UP L H L H

H H UP H H TOGGLE

whereC = input clock, active with low to high transitionS = input preset, active with logic low levelR = input clear, active with logic low levelx = don’t care stateL = logic low level; Inputs < 0.5; Outputs 0.0

H = logic high level; Inputs ≥ 0.5; Outputs 1.0UP = low-to-high transitionQ0 = previous Q stateNQ = inverted Q stateNQ0 = previous inverted Q state

Input Output

R (pin 1) K (pin 2) C (pin 3) J (pin 4) S (pin 5) Q (pin 6) NQ (pin 7)

JKFF 4-9


Figure 4-4. JKFF Input and Output Signal Values


OutputSignal Q(pin 6)

Output SignalNQ (pin 7)

Input SignalK (pin 2)

InputSignal J(pin 4)

4-10 JKFF

LFSR

Description Linear feedback shift registerLibrary Numeric, LogicClass SDFLFSRDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The linear feedback shift register component can be used to generate PNsequences with user-defined recurrence relations. The input to the LFSR is aclock signal. A new bit value is generated at the output every time the inputsignal transitions from 0 to 1. Figure 4-5 illustrates an LFSR model.


Seed initial value loaded into theshift register

1 int

FeedbackList tap positions for non-zerofeedback coefficients

7 3 2 1 int array


1 clock clock signal int



LFSR 4-11


Figure 4-5. LFSR Model

Data is shifted to the right in the shift register. The length of the shift registeris r. The numbers a(1), a(2), ... , a(r) are the binary feedback coefficientsspecified by FeedbackList.

The shift register length r is defined by the largest value in FeedbackList. Forexample, a FeedbackList of 7 3 2 1 results in a shift register length of 7; themaximum value allowed in FeedbackList is 31, which results in a maximumshift register length of 31.

The initial contents of the shift register are specified by the value of Seed. Themaximum meaningful value for Seed is 2r-1 for a specific FeedbackList. Themaximum Seed value allowed is 231-1.

The following equations describe the operation of LFSR.

where

D(0) = Seed2 (0)D(−1) = Seed2 (1)...D(1− r) = Seed2 (r − 1)

and

Dn−1 Dn−2 Dn−r

+

Xa(1) a(2).. . . . . . . . . . . . . . . . . . . . . . ... . . .a(r) = 1

MODULO 2 ADDER

OUTPUT

X

Dn

X

D n( ) a k( )D n k–( )k 1=

r

∑ mod2 for n 1≥=

4-12 LFSR

where

Seed2(k) ∈0,1 for 0 ≤ k < rExample: Let Seed=2, and r=7

Then

Seed2 (0) = 0Seed2 (1) = 1Seed2 (2) = 0...Seed2 (6) = 0

Therefore,

D(0) = Seed2 (0) = 0D(−1) = Seed2 (1) = 1D(−2) = Seed2 (2) = 0...D(−6) = Seed2 (6) = 0

2. The binary feedback coefficients are specified by FeedbackList, which is a list offeedback coefficients. The coefficients are specified by listing the locationswhere the feedback coefficients equal 1. For example, the recurrence relation

D(n) = (D(n− 7) + D(n− 3) + D(n− 2) + D(n− 1) )mod 2

is specified by the list [7, 3, 2, 1].

Table 4-1 is an extensive list of feedback coefficients for linear feedback shiftregisters showing one or more alternate feedback connections for a givennumber of stages.

Seed Seed2 k( )2k

k o≥∑=

LFSR 4-13


Table 4-1. Feedback Connections for Linear m-Sequences *

NumberofStages Code Length Maximal Taps

2a 3 [2, 1]

3a 7 [3, 1]

4 15 [4, 1]

5a 31 [5, 2] [5, 4, 3, 2] [5, 4, 2, 1]

6 63 [6, 1] [6, 5, 2, 1,] [6, 5, 3, 2,]

7a 127 [7, 1] [7, 3] [7, 3, 2, 1,] [7, 4, 3, 2,] [7, 6, 4, 2] [7, 6, 3, 1] [7, 6, 5, 2] [7,6, 5, 4, 2, 1] [7, 5, 4, 3, 2, 1]

8 255 [8, 4, 3, 2] [8, 6, 5, 3] [8, 6, 5, 2] [8, 5, 3, 1] [8, 6, 5, 1] [8, 7, 6, 1] [8, 7,6, 5, 2, 1] [8, 6, 4, 3, 2, 1]

9 511 [9, 4] [9, 6, 4, 3] [9, 8, 5, 4] [9, 8, 4, 1] [9, 5, 3, 2] [9, 8, 6, 5] [9, 8, 7, 2][9, 6, 5, 4, 2] [9, 7, 6, 4, 3, 1] [9, 8, 7, 6, 5, 3]

10 1023 [10, 3] [10, 8, 3, 2] [10, 4, 3, 1] [10, 8, 5, 1] [10, 8, 5, 4] [10, 9, 4, 1][10, 8, 4, 3] [10, 5, 3, 2] [10, 5, 2, 1] [10, 9, 4, 2]

11 2047 [11, 1] [11, 8, 5, 2] [11, 7, 3, 2] [11, 5, 3, 5] [11, 10, 3, 2] [11, 6, 5, 1][11, 5, 3, 1] [11, 9, 4, 1] [11, 8, 6, 2] [11, 9, 8, 3]

12 4095 [12, 6, 4, 1] [12, 9, 3, 2] [12, 11, 10, 5, 2, 1] [12, 11, 6, 4, 2, 1] [12, 11,9, 7, 6, 5] [12, 11, 9, 5, 3, 1] [12, 11, 9, 8, 7, 4] [12, 11, 9, 7, 6, 5] [12,9, 8, 3, 2, 1] [12, 10, 9, 8, 6, 2]

13a 8191 [13, 4, 3, 1] [13, 10, 9, 7, 5, 4] [13, 11, 8, 7, 4, 1] [13, 12, 8, 7, 6, 5][13, 9, 8, 7, 5, 1] [13, 12, 6, 5, 4, 3] [13, 12, 11, 9, 5, 3] [13, 12, 11, 5,2, 1] [ 13, 12, 9, 8, 4, 2] [13, 8, 7, 4, 3, 2]

14 16,383 [14, 12, 2, 1] [14, 13, 4, 2] [14, 13, 11, 9] [14, 10, 6, 1] [14, 11, 6, 1][14, 12, 11, 1] [14, 6, 4, 2] [14, 11, 9, 6, 5, 2] [14, 13, 6, 5, 3, 1] [14,13, 12, 8, 4, 1] [14, 8, 7, 6, 4, 2] [14, 10, 6, 5, 4, 1] [14, 13, 12, 7, 6, 3][14, 13, 11, 10, 8, 3]

15 32,767 [15, 13, 10, 9] [15, 13, 10, 1] [15, 14, 9, 2] [15, 1] [15, 9, 4, 1] [15, 12,3, 1] [15, 10, 5, 4] [15, 10, 5, 4, 3, 2] [15, 11, 7, 6, 2, 1] [15, 7, 6, 3, 2,1][15, 10, 9, 8, 5, 3] [15, 12, 5, 4, 3, 2] [15, 10, 9, 7, 5, 3] [15, 13, 12,10] [15, 13, 10, 2] [15, 12, 9, 1] [15, 14, 12, 2] [15, 13, 9, 6] [15, 7, 4,1] [15, 4] [15, 13, 7, 4]

16 65,535 [16, 12, 3, 1] [16, 12, 9, 6] [16, 9, 4, 3] [16, 12, 7, 2] [16, 10, 7, 6] [16,15, 7, 2] [16, 9, 5, 2] [16, 13, 9, 6] [16, 15, 4, 2] [16, 15, 9, 4]

17a 131,071 [17, 3] [17, 3, 2] [17, 7, 4, 3] [17, 16, 3, 1] [17, 12, 6, 3, 2, 1] [17, 8, 7,6, 4, 3] [17, 11, 8, 6, 4, 2] [17, 9, 8, 6, 4, 1] [17, 16, 14, 10, 3, 2] [17,12, 11, 8, 5, 2]

18 262,143 [18, 7] [18, 10, 7, 5] [18, 13, 11, 9, 8, 7, 6, 3] [18, 17, 16, 15, 10, 9, 8,7] [18, 15, 12, 11, 9, 8, 7, 6]

19a 524,287 [19, 5, 2, 1] [19, 13, 8, 5, 4, 3] [19, 12, 10, 9, 7, 3] [19, 17, 15, 14, 13,12, 6, 1] [19, 17, 15, 14, 13, 9, 8, 4, 2, 1] [19, 16, 13, 11, 19, 9, 4, 1][19, 9, 8, 7, 6, 3] [19, 16, 15, 13, 12, 9, 5, 4, 2, 1] [19, 18, 15, 14, 11,10, 8, 5, 3, 2] [19, 18, 17, 16, 12, 7, 6, 5, 3, 1]

4-14 LFSR

*Reprinted by permission of John Wiley & Sons. From Spread Spectrum Systems,2nd edition, p. 87, Robert C. Dixon. Copyright 1984 by John Wiley & Sons, Inc.

3. An alternative implementation of the LFSR is shown in Figure 4-6. In order toget the same output sequence from the two implementations the followingrelationships should hold between a(i) and b(i):

b(i) = a(r-i), i = 1, 2, ... , r-1.

20 1, 048,575 [20, 3] [20, 9, 5, 3] [20, 19, 4, 3] [20, 11, 8, 6, 3, 2] [20, 17, 14, 10, 7,4, 3, 2]

21 2,097,151 [21, 2] [21, 14, 7, 2] [21, 13, 5, 2] [21, 14, 7, 6, 3, 2] [21, 8, 7, 4, 3, 2][21, 10, 6, 4, 3, 2] [21, 15, 10, 9, 5, 4, 3, 2] [21, 14, 12, 7, 6, 4, 3, 2][21, 20, 19, 18, 5, 4, 3, 2]

22 4,194,303 [22,1] [22, 9, 5, 1] [22, 20, 18, 16,6, 4, 2, 1] [22, 19, 16, 13, 10, 7, 4,1] [22, 17, 9, 7, 2, 1] [22, 17, 13, 12, 8, 7, 2, 1] [22, 14, 13, 12, 7, 3, 2,1]

23 8,388,607 [23, 5] [23, 17, 11, 5] [23, 5, 4, 1] [23, 12, 5, 4] [23, 21, 7, 5] [23, 16,13, 6, 5, 3] [23, 11, 10, 7, 6, 5] [23, 15, 10, 9, 7, 5, 4, 3] [23, 17, 11, 9,8, 5, 4, 1] [23, 18, 16, 13, 11, 8, 5, 2]

24 16,777,215 [24, 7, 2] [24, 4, 3, 1] [24, 22, 20, 18, 16, 14, 11, 9, 8, 7, 5, 4] [24, 21,19, 18, 17, 16, 15, 14, 13, 10, 9, 5, 4, 1]

25 33,554, 431 [25, 3] [25, 3, 2, 1] [25, 20, 5, 3] [25, 12, 5, 4] [25, 17, 10, 3, 2, 1] [25,23, 21, 19, 9, 7, 5, 3] [25, 18, 12, 11, 6, 5, 4] [25, 20, 16, 11, 5, 3, 2,1] [25, 12, 11, 8, 7, 6, 4, 3]

26 67,108,863 [26, 6, 2, 1] [26, 22, 21, 16, 12, 11, 10, 8, 5, 4, 3, 1]

27 134,217,727 [27, 5, 2, 1] [27, 18, 11, 10, 9, 5, 4, 3]

28 268,435,455 [28, 3] [28, 13, 11, 9, 5, 3] [28, 22, 11, 10, 4, 3] [28, 24, 20, 16, 12, 8,4, 3, 2, 1]

29 536,870,911 [29, 2] [29, 20, 11, 2] [29, 13, 7, 2] [29, 21, 5, 2] [29, 26, 5, 2] [29, 19,16, 6, 3, 2] [29, 18, 14, 6, 3, 2]

30 1,073,741,823 [30, 23, 2, 1] [30, 6, 4, 1] [30, 24, 20, 16, 14, 13, 11, 7, 2, 1]

31a 2,147,483,647 [31, 29, 21, 17] [31, 28, 19, 15] [31, 3] [31, 3, 2, 1] [31, 13, 8, 3] [31,21, 12, 3, 2, 1] [31, 20, 18, 7, 5, 3] [31, 30, 29, 25] [31, 28, 24, 10][31, 20, 15, 5, 4, 3] [31, 16, 8, 4, 3, 2]

32 4,294,967,295 [32, 22, 2, 1] [32, 7, 5, 3, 2, 1] [32, 28, 19, 18, 16, 14, 11, 10, 9, 6, 5,1]

33 8,589,934,591 [33, 13] [33, 22, 13, 11] [33, 26, 14, 10] [33, 6, 4, 1] [33, 22, 16, 13,11, 8]

61a 2,305,843,009,213, 693, 951 [61, 5, 2, 1]

89a 618,970,019,642,690,137,449,562,112 [89, 6, 5, 3]

Table 4-1. Feedback Connections for Linear m-Sequences (continued)*

NumberofStages Code Length Maximal Taps

LFSR 4-15


Figure 4-7 illustrates implementation for a shift register of length 5 andFeedbackList="2 5".

The sequence of the LFSR states in both implementations and the output(rightmost bit of the state) is shown in Figure 4-8. The initial state wasassumed to be 10000.

Although the shift register in the two implementations does not go through thesame sequence of states, the output sequence is the same for both. It is alsoworth noting that if the initial state is different from 10000, the outputsequences may not be exactly the same but a shifted version of each other.

Figure 4-6. Alternative Implementation of LFSR

Figure 4-7. Implementation of 5-Stage LFSR

b(1) b(2) b(r-1)

Implementation 1

Implementation 2

4-16 LFSR

Figure 4-8. LFSR States

4. Input and output signal voltages of the LFSR component are shown inFigure 4-9.

Implementation 1 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0

0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0

Implementation 21 0 0 0 00 1 0 0 00 0 1 0 00 0 0 1 00 0 0 0 11 0 0 1 00 1 0 0 11 0 1 1 00 1 0 1 11 0 1 1 11 1 0 0 11 1 1 1 00 1 1 1 11 0 1 0 11 1 0 0 00 1 1 0 00 0 1 1 00 0 0 1 11 0 0 1 11 1 0 1 11 1 1 1 11 1 1 0 11 1 1 0 00 1 1 1 00 0 1 1 11 0 0 0 11 1 0 1 00 1 1 0 11 0 1 0 00 1 0 1 00 0 1 0 11 0 0 0 0

LFSR 4-17


Figure 4-9. LFSR Input and Output Signal Voltages


InputSignal

OutputSignal

4-18 LFSR

Logic

Description test logicLibrary Numeric, LogicClass SDFLogicC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Logic applies a logical operation to all inputs. The inputs are integersinterpreted as Boolean values.

2. The NOT operation requires only one input.



Logic test logic: NOT, AND,NAND, OR, NOR, XOR,XNOR

AND enum


1 input Input logic values. multiple int


2 output Result of the logic test, with FALSE equal to zero andTRUE equal to anon-zero integer (not necessarily 1).

int

Logic 4-19


LogicAND

Description Multiple input logical AND functionLibrary Numeric, LogicClass SDFLogicC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicAND applies the AND logical operation to all inputs.






int

4-20 LogicAND

LogicAND2

Description 2-Input Logical AND FunctionLibrary Numeric, Logic

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicAND2 applies the AND logical operation to both inputs.



1 input1 int

2 input2 int


3 output int

LogicAND2 4-21


LogicInverter

Description Logic inverterLibrary Numeric, LogicClass SDFLogicC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicInverter applies the logic inversion operation on the input.






int

4-22 LogicInverter

LogicLatch

Description Logic LatchLibrary Numeric, LogicClass SDFLogicLatchDerived From baseOmniSysNumericStar

Pin Inputs

Pin Outputs

Notes/Equations

1. Function table:


1 data input data int



3 output output data int

Input Output

Data (pin 1) Clock (pin 2) Q (pin 3)

L H L

H H H

x L Q0

whereClock = input clock, active with logic high levelx = don’t care stateL = logic low level; Inputs < 0.5; Outputs 0.0H = logic high level; Inputs > 0.5; Outputs 1.0Q0 = previous Q state

LogicLatch 4-23


Initially, at the first sample, the output Q is equal to L.

2. This component is clock level sensitive. If the user prefers a clock edge-triggeredlatch, the DFF component can be used with S=R=H.

3. The input, clock, and output signal voltages of the LogicLatch component areshown.


ClockSignal

InputSignal

OutputSignal

4-24 LogicLatch

LogicNAND

Description Multiple input logical NAND functionLibrary Numeric, LogicClass SDFLogicC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicNAND applies the NAND logical operation to all inputs.






int

LogicNAND 4-25


LogicNAND2

Description 2-Input Logical NAND FunctionLibrary Numeric, Logic

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicNAND2 applies the NAND logical operation to both inputs.



1 input1 int

2 input2 int


3 output int

4-26 LogicNAND2

LogicNOR

Description Multiple input logical NOR functionLibrary Numeric, LogicClass SDFLogicC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicNOR applies the NOR logical operation to all inputs.






int

LogicNOR 4-27


LogicNOR2

Description 2-Input Logical NOR FunctionLibrary Numeric, Logic

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicNOR2 applies the NOR logical operation to both inputs.



1 input1 int

2 input2 int


3 output int

4-28 LogicNOR2

LogicOR

Description Multiple input logical OR functionLibrary Numeric, LogicClass SDFLogicC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicOR applies the OR logical operation to all inputs.






int

LogicOR 4-29


LogicOR2

Description 2-Input Logical OR FunctionLibrary Numeric, Logic

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicOR2 applies the OR logical operation to both inputs.



1 input1 int

2 input2 int


3 output int

4-30 LogicOR2

LogicXNOR

Description Multiple input logical XNOR functionLibrary Numeric, LogicClass SDFLogicC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicXNOR applies the XNOR logical operation to all inputs.






int

LogicXNOR 4-31


LogicXNOR2

Description 2-Input Logical XNOR FunctionLibrary Numeric, Logic

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicXNOR2 applies the XNOR logical operation to both inputs.



1 input1 int

2 input2 int


3 output int

4-32 LogicXNOR2

LogicXOR

Description Multiple input logical XOR functionLibrary Numeric, LogicClass SDFLogicC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicXOR applies the XOR logical operation to all inputs.






int

LogicXOR 4-33


LogicXOR2

Description 2-Input Logical XOR FunctionLibrary Numeric, Logic

Pin Inputs

Pin Outputs

Notes/Equations

1. LogicXOR2 applies the XOR logical operation to both inputs.



1 input1 int

2 input2 int


3 output int

4-34 LogicXOR2

Multiple

Description Multiple TestLibrary Numeric, LogicClass SDFMultipleC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Multiple outputs a logic high if the signal is an integer multiple of test;otherwise output is a logic low.



1 signal Is this a multiple of the other input? int

2 test Reference input (must be positive) int


3 mult Equals 1 if signal is a multiple of test int

Multiple 4-35


Test

Description Comparison testLibrary Numeric, LogicClass SDFTestC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. For EQ condition, Test outputs 1 if the following expression is satisfied(otherwise output is 0):


Condition test condition: EQ, NE, GT,GE, LT, LE

EQ enum

Tolerance finite-precision parameterfor EQ and NE conditionsonly

0.0 real (-∞, ∞)

CrossingsOnly if True, output is True onlywhen the test resulttoggles: False, True

False enum


1 Signal Signal to compare against the test (left hand side) real

2 Test Comparison test real


3 output Result of the test int

4-36 Test

test − signal≥ Tolerance

For NE condition, Test outputs 1 if the following expression is satisfied(otherwise output is 0):

test − signal< Tolerance

For GT, GE, LT, or LE condition, Test outputs 1 if the following expression issatisfied (otherwise output is 0):

(test) condition (signal)


Test 4-37


TestEQ

Description Comparision test (equal to)Library Numeric, LogicClass SDFTestC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. TestEQ outputs 1 if the following expression is satisfied (otherwise output is 0):

test − signal ≤ Tolerance




0.0 real (-∞, ∞)


False enum






4-38 TestEQ

TestGE

Description Comparision test (greater than or equal to)Library Numeric, LogicClass SDFTestC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. TestGE outputs 1 if the following expression is satisfied (otherwise output is 0):

(signal) GE (test)




False enum






TestGE 4-39


TestGT

Description Comparision test (greater than)Library Numeric, LogicClass SDFTestC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. TestGT outputs 1 if the expression

(signal) GT (test)

is satisfied; otherwise output is 0.




False enum






4-40 TestGT

TestGT 4-41


TestLE

Description Comparision test (less than or equal to)Library Numeric, LogicClass SDFTestC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. TestLE outputs 1 if the expression

(signal) LE (test)





False enum






4-42 TestLE

TestLE 4-43


TestLT

Description Comparision test (less than)Library Numeric, LogicClass SDFTestC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. TestLT outputs 1 if the expression

(signal) LT (test)





False enum






4-44 TestLT

TestLT 4-45


TestNE

Description Comparision test (not equal to)Library Numeric, LogicClass SDFTestC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. TestNE outputs 1 if the expression

test − signal > Tolerance

is satisfied; otherwise, output is 0.



0.0 real (-∞, ∞)


False enum






4-46 TestNE


TestNE 4-47


4-48 TestNE

Chapter 5: Numeric Math Components

Introduction

The Numeric Math components library contains integer, double precisionfloating-point (real), fixed-point (fixed), and complex mathematical scalar operators.Each component accepts a specific class of signal and outputs a resultant signal.(These components do not accept any matrix class of signal.)

If a component receives another class of signal, the received signal is automaticallyconverted to the signal class specified as the input of the component. Auto conversionfrom a higher to a lower precision signal class may result in loss of information. Theauto conversion from timed, complex or floating-point (real) signals to a fixed signaluses a default bit width of 32 bits with the minimum number of integer bits needed torepresent the value. For example, the auto conversion of the floating-point (real)value of 1.0 creates a fixed-point value with precision of 2.30, and a value of 0.5 wouldcreate one of precision of 1.31. For details on conversions between different classes ofsignals, refer to “Conversion of Data Types” in the ADS Ptolemy Simulation manual.

Some components operate with fixed-point numbers. These components use one ormore parameters that define the characteristics of the fixed-point processing. Theseparameters include: OverflowHandler, OutputPrecision, RoundFix, ReportOverflow,and others. For details on the use of these parameters for fixed-point componentsrefer to “Parameters for Fixed-Point Components” in the ADS Ptolemy Simulationmanual. The arithmetic used by these components is two’s complement. Therefore,all precision values must specify at least one bit to the left of the decimal point (usedas sign bit).

Introduction 5-1

Numeric Math Components

Abs

Description Absolute ValueLibrary Numeric, MathClass SDFAbsC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Abs outputs the absolute value of the input as a floating-point (real) value.

where:

y(n) is the output for sample nx(n) is the input for sample n

2. For information regarding numeric math component signals, refer to the“Introduction” on page 5-1.


1 input real


2 output real

y n( ) x n( )=

5-2 Abs

Add

Description Multiple Input AdderLibrary Numeric, MathClass SDFAddC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Add outputs the sum of inputs as a floating-point (real) value.



1 input multiple real


2 output real

Add 5-3


Add2

Description 2-Input AdderLibrary Numeric, Math

Pin Inputs

Pin Outputs

Notes

1. Add2 outputs the sum of the two inputs as a floating-point (real) value.



1 input1 real

2 input2 real


3 output real

5-4 Add2

AddCx

Description Complex Multiple Input AdderLibrary Numeric, MathClass SDFAddCxC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. AddCx outputs the sum of inputs as a complex value.



1 input multiple complex


2 output complex

AddCx 5-5


AddCx2

Description 2-Input Complex AdderLibrary Numeric, Math

Pin Inputs

Pin Outputs

Notes

1. AddCx2 outputs the sum of the two inputs as a complex value.



1 input1 complex

2 input2 complex


3 output complex

5-6 AddCx2

AddFix

Description Fixed-Point Multiple Input AdderLibrary Numeric, MathClass SDFAddFixDerived From SDFFixC++ Code

Parameters

Pin Inputs


OverflowHandler output overflowcharacteristic: wrapped,saturate, zero_saturate,warning

wrapped enum

ReportOverflow simulation overflow errorreport option:DONT_REPORT,REPORT

REPORT enum

RoundFix fixed-point computations,assignments, and datatype conversions option:TRUNCATE, ROUND

TRUNCATE enum

UseArrivingPrecision use precision of arrivingdata: NO, YES

NO enum

InputPrecision precision of input (usedonly ifUseArrivingPrecision is setto NO)

2.14 precision

OutputPrecision precision of output in bitsand accumulation

2.14 precision


1 input multiple fix

AddFix 5-7


Pin Outputs

Notes/Equations

1. AddFix outputs the sum of inputs as a fixed-point value.

2. If the fixed-point operations cannot fit into the precision specified, overflowoccurs with the overflow characteristic specified by OverflowHandler. IfReportOverflow=REPORT, after the simulation has finished the number ofoverflow errors (if any) will be reported. RoundFix identifies whetherfixed-point computations are truncate or round method. IfUseArrivingPrecision=NO, the input is cast to the precision specified byInputPrecision.

For details on these fixed-point parameters refer to “Parameters for Fixed-PointComponents” in the ADS Ptolemy Simulation manual.

3. If UseArrivingPrecision=YES, then components that send a NULL particle ontheir first firing should not be connected at the input of this component. Forexample, when a Delay component is connected at its input, such a NULLparticle has a precision of 1.0 and the output value will be forced to 0.



2 output fix

5-8 AddFix

AddFix2

Description 2-Input Fixed-Point AdderLibrary Numeric, Math

Parameters

Pin Inputs

Pin Outputs


OverflowHandler output overflowcharacteristic: wrapped,saturate, zero saturate,warning

wrapped enum

ReportOverflow simulation overflow errorreport: DONT REPORT,REPORT

REPORT enum

RoundFix fixed-point computations,assignments, and datatype conversions:TRUNCATE, ROUND

TRUNCATE enum


NO enum

InputPrecision precision of input(usedonly ifUseArrivingPrecision is setto NO)

2.14 precision

OutputPrecision precision of outputaccumulation

2.14 precision


1 input1 fix

2 input2 fix


3 output fix

AddFix2 5-9


Notes/Equations

1. AddFix2 outputs the sum of the two inputs as a fixed-point value with precisionspecified by OutputPrecision.




5-10 AddFix2

AddInt

Description Integer Multiple Input AdderLibrary Numeric, MathClass SDFAddIntC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. AddInt outputs the sum of inputs as an integer value.


1 input multiple int


2 output int

AddInt 5-11


AddInt2

Description 2-Input Integer AdderLibrary Numeric, Math

Pin Inputs

Pin Outputs

Notes

1. AddInt2 outputs the sum of the two inputs as an integer value.


1 input1 int

2 input2 int


3 output int

5-12 AddInt2

Average

Description AveragerLibrary Numeric, MathClass SDFAverageC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Average calculates the output floating-point (real) average for a specifiednumber of input samples or blocks of input samples. Blocks of successive inputsamples are treated as vectors and produce a block of output values.


NumInputsToAverage number of input data itemsto average

8 int [1, ∞)

BlockSize input blocks of this size willbe averaged to produce anoutput block

1 int [1, ∞)


1 input real


2 output real

Average 5-13


AverageCx

Description Complex averagerLibrary Numeric, MathClass SDFAverageCxC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. AverageCx calculates the output complex average for a specified number ofinput samples or blocks of complex input samples. Blocks of successive inputsamples are treated as vectors and produce a block of output values.


NumInputsToAverage number of input data itemsto average

8 int [1, ∞)

BlockSize input blocks of this size willbe averaged to produce anoutput block

1 int [1, ∞)


1 input complex


2 output complex

5-14 AverageCx

Cos

Description Cosine FunctionLibrary Numeric, MathClass SDFCosC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Cos calculates the cosine of its input, which is assumed to be an angle inradians.

where:



1 input real


2 output real

y n( ) x n( )( )cos=

Cos 5-15


DB

Description dB valueLibrary Numeric, MathClass SDFDBC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. DB converts the input value to floating-point (real) dB scale. Zero and negativevalues are assigned the Min value.

2. If the input signal is a power measurement set Type to Power; if the inputsignal is an amplitude measurement set Type to Amplitude.

If Type = Power as 10log(input):


Min minimum output value -100 real (-∞, ∞)

Type type of input signalmeasurement: Power as10*log(input), Amplitude as20*log(input)

Amplitude as20*log(input)

enum


1 input real


2 output real

5-16 DB

If Type = Power as 20log(input):

where y(n) is the output for sample n, x(n) is the input for sample n

y n( )10log10x n( ) if 10log10x n( ) Min≥

Min otherwise

=

y n( )20log10x n( ) if 20log10x n( ) Min≥

Min otherwise

=

DB 5-17


DivByInt

Description Integer divisionLibrary Numeric, MathClass SDFDivByIntC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. DivByInt calculates the integer output equal to the integer input divided by theinteger Divisor. Truncated integer division is used.


Divisor integer divisor 2 int (-∞, 0) or (0,

∞)


1 input int


2 output int

5-18 DivByInt

Exp

Description Exponential FunctionLibrary Numeric, MathClass SDFExpC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Exp calculates the floating-point (real) exponential function (base e) of theinput.

where:


2. The input value must be ≤ ln (maximum double-precision floating-point (real)value) to avoid overflow.


1 input real


2 output real

y n( ) ex n( )=

Exp 5-19


Floor

Description Floor FunctionLibrary Numeric, MathClass SDFFloorC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Floor outputs the integer floor of the input.

where:



1 input real


2 output int

y n( ) floor x n( )( )=

5-20 Floor

Gain

Description gain valueLibrary Numeric, MathClass SDFGainC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Gain calculates the floating-point (real) output equal to the input multiplied byGain.


Gain gain value 1.0 real (-∞, ∞)


1 input real


2 output real

Gain 5-21


GainCx

Description Complex gainLibrary Numeric, MathClass SDFGainCxC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. GainCx calculates the complex output equal to the input multiplied by thecomplex Gain.

2. For details on complex parameter values, refer to “Complex-Valued Parameters”in the ADS Ptolemy Simulation manual.


Gain gain value 1 complex


1 input complex


2 output complex

5-22 GainCx

GainFix

Description Fixed-Point GainLibrary Numeric, MathClass SDFGainFixDerived From SDFFixC++ Code

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum

Gain gain value 1.0 fix


NO enum


2.14 precision


2.14 precision


1 input fix

GainFix 5-23


Pin Outputs

Notes/Equations

1. GainFix calculates the fixed-point output equal to the input multiplied by Gain.





2 output fix

5-24 GainFix

GainInt

Description Integer gainLibrary Numeric, MathClass SDFGainIntC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. GainInt calculates the integer output equal to the input multiplied by theinteger Gain.


Gain gain value 1 int (-∞, ∞)


1 input int


2 output int

GainInt 5-25


Integrate

Description IntegratorLibrary Numeric, MathClass SDFIntegrateC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations


FeedbackGain gain on feedback path 1.0 real (-∞, ∞)

Top upper limit 0.0 real (-∞, ∞)

Bottom lower limit 0.0 real (-∞, ∞)

Saturate perform saturation: NO,YES

YES enum

State an internal state 0.0 real (-∞, ∞)


1 data real

2 reset int


3 output real

5-26 Integrate

1. Integrate calculates the output floating-point (real) summation for a specifiednumber of input samples or blocks of input samples. Blocks of successive inputsamples are treated as vectors and produce a block of output values.

2. Integrate is an integrator with leakage, limits, and reset. With the defaultparameters, input samples are simply accumulated, and the running sum is theoutput. To prevent any resetting in the middle of a run, connect a Const sourcewith value 0 to the reset input. Otherwise, whenever a non-zero is received onthis input, the accumulated sum is reset to the current input (that is, nofeedback).

3. Limits are controlled by Top and Bottom. If Top ≤ Bottom, no limiting isperformed; otherwise, the output is kept between Top and Bottom.

If Saturate=YES, saturation is performed. If Saturate=NO, wraparound isperformed. Limiting is performed before output.

4. Leakage is controlled by the FeedbackGain state. The output is the data inputplus FeedbackGain×State, where State is the previous output.

Integrate 5-27


Ln

Description Natural LogLibrary Numeric, MathClass SDFLnC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Ln outputs the floating-point (real) natural logarithm of the input.

where:


2. The input must be > 0.


1 input real


2 output real

y n( ) ln x n( )=

5-28 Ln

Math

Description Math FunctionLibrary Numeric, MathClass SDFMath

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Math performs the floating-point (real) mathematical functions:

y(n) = f (x(n))

where:


and where f( ) is any function that can be selected from the Type parameter.


Type mathematical function:Abs, Ceil, Exp, Floor, Ln,Log10, Pow10, Recip,Round, Sqr, Sqrt

Abs enum





Math 5-29


2. If Type = Abs, then y(n) = | x(n) |

If Type = Ceil, then y(n) = , where

If Type = Exp, then y(n) = e x(n)

If Type = Floor, then y(n) = , where

If Type = Ln, then y(n) = ln( x(n) )

If Type = Log10, then y(n) = log10( x(n) )

If Type = Pow10, then y(n) = 10 x(n)

If Type = Recip, then y(n) = 1 / x(n)

If Type = Round, then y(n) = closest integer to x(n) (numbers at the samedistance from two integers map away from 0; for example, 2.5 maps to 3 and-2.5 maps to -3)

If Type = Sqr, then y(n) = x(n)2

If Type = Sqrt, then y(n) =

x n( ) x n( ) x n( )≤ x n( ) 1+<

x n( ) x n( ) 1– x n( ) x n( )≤<

x n( )

5-30 Math

MathCx

Description Complex Math FunctionLibrary Numeric, MathClass SDFMathCxDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Math performs the complex mathematical functions:

y(n) = f (x(n))

where:



Type mathematical function:Abs, Ceil, Exp, Floor, Ln,Log10, Pow10, Recip,Round, Sqr, Sqrt, Conj

Abs enum





MathCx 5-31


and where f( ) is any function that can be selected from the Type parameter.

2. If Type = Abs, then y(n) = | x(n) | =

If Type = Ceil, then y(n) = (see Ceil function ofMath component)

If Type = Exp, then y(n) = e x(n) = e Re x(n) ( cos( Im x(n) ) + j sin( Im x(n) ) )

If Type = Floor, then y(n) = (see Floor function ofMath component)

If Type = Ln, then y(n) = , where is thephase of x(n) in radians.

If Type = Log10, then y(n) = log10( x(n) ) = ln( x(n) ) / ln( 10 ).

If Type = Pow10, then y(n) = 10 x(n) = e x(n) ln(10)

If Type = Recip, then y(n) = 1 / x(n) = ( Re x(n) - j Im x(n) ) / | x(n) | 2

If Type = Round, then y(n) = Round( Re x(n) ) + j Round( Im x(n) ) (seeRound function of Math component)

If Type = Sqr, then y(n) = x(n)2

If Type = Sqrt, then y(n) = , where is thephase of x(n) in radians.

If Type = Conj, then y(n) =

Re x n( ) 2 Im x n( ) 2+

Re x n( ) j Im x n( ) ×+

Re x n( ) j Im x n( ) ×+

x n( )( ) x n( )( )ln=ln j x n( )∠×+ x n( )∠

x n( ) x n( ) e j 0.5 x n( )∠×××= x n( )∠

Re x n( ) j Im x n( ) –

5-32 MathCx

MaxMin

Description Maximum or minimum valueLibrary Numeric, MathClass SDFMaxMinC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. MaxMin finds the minimum or minimum value or magnitude of a fixed numberof data values on the input.


N default samples 10 int [0, ∞)

MaxOrMin output value: min, max max enum

Compare compare input value ormagnitude: valueIn,magnitudeIn

valueIn enum

OutputType output value or magnitude:valueOut, magnitudeOut

valueOut enum


1 input real


2 output real

3 index int

MaxMin 5-33


Use MaxMin to operate over multiple data streams by preceding it with aCommutator and set the N state accordingly.

2. If Compare=valueIn, the input with the maximum or minimum value is located;if Compare=magnitudeIn, the input with the maximum or minimum magnitudeis located.

3. If OutputType=magnitudeOut, the magnitude of the result is written to theoutput; if OutputType=valueOut, the result itself is written to the output.Returns maximum value among N input samples. The index of the output isalso provided (count starts at 0).

5-34 MaxMin

Modulo

Description Floating-point moduloLibrary Numeric, MathClass SDFModuloC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Modulo outputs the floating-point (real) remainder with the same sign as inputafter dividing the input by the Modulo parameter.

where:



Modulo modulo value 1.0 real (-∞, 0) or (0,

∞)





y n( ) fmod x n( )=

Modulo 5-35


ModuloInt

Description Integer moduloLibrary Numeric, MathClass SDFModuloIntC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. ModuloInt outputs the integer remainder with the same sign as input afterdividing the input by the integer Modulo parameter.

where:



Modulo modulo value 10 int (-∞, 0) or (0,

∞)


1 input input signal int



y n( ) mod x n( )=

5-36 ModuloInt

Mpy

Description Multiple Input MultiplierLibrary Numeric, MathClass SDFMpyC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Mpy outputs the product of inputs as a floating-point (real) value.


1 input multiple real


2 output real

Mpy 5-37


Mpy2

Description 2-Input MultiplierLibrary Numeric, MathClass SDFMpyC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Mpy2 outputs the product of the two inputs as a floating-point (real) value.


1 input#1 real

2 input#2 real


3 output real

5-38 Mpy2

MpyCx

Description Complex Multiple Input MultiplierLibrary Numeric, MathClass SDFMpyCxC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. MpyCx outputs the product of the complex inputs as a complex value.


1 input multiple complex


2 output complex

MpyCx 5-39


MpyCx2

Description 2-Input Complex MultiplierLibrary Numeric, MathClass SDFMpyCxC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. MpyCx2 outputs the product of two inputs as a complex value.


1 input#1 complex

2 input#2 complex


3 output complex

5-40 MpyCx2

MpyFix

Description Fixed-Point Multiple Input MultiplierLibrary Numeric, MathClass SDFMpyFixDerived From SDFFixC++ Code

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum


NO enum


2.14 precision


2.14 precision


1 input multiple fix

MpyFix 5-41


Pin Outputs

Notes/Equations

1. MpyFix outputs the product of the inputs as a fixed-point value.





2 output fix

5-42 MpyFix

MpyFix2

Description 2-Input Fixed-Point MultiplierLibrary Numeric, MathClass SDFMpyFixC++ Code

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum


NO enum


2.14 precision


2.14 precision


1 input#1 fix

2 input#2 fix

MpyFix2 5-43


Pin Outputs

Notes/Equations

1. MpyFix2 outputs the product of the two inputs as a fixed-point value.





3 output fix

5-44 MpyFix2

MpyInt

Description Integer Multiple Input MultiplierLibrary Numeric, MathClass SDFMpyIntC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. MpyInt outputs the product of the inputs as an integer value.


1 input multiple int


2 output int

MpyInt 5-45


MpyInt2

Description 2-Input Integer MultiplierLibrary Numeric, MathClass SDFMpyIntC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. MpyInt2 outputs the product of two inputs as an integer value.


1 input#1 int

2 input#2 int


3 output int

5-46 MpyInt2

Reciprocal

Description Reciprocal functionLibrary Numeric, MathClass SDFReciprocalC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Reciprocal calculates the reciprocal of the input, with an optional magnitudelimit.

If MagLimit = 0

If MagLimit ≠ 0 and input = 0


MagLimit magnitude limit; non-zerolimits the output magnitude

0.0 real (-∞, ∞)


1 input real


2 output real

y n( ) 1x n( )------------=

Reciprocal 5-47


y(n) = MagLimit

If MagLimit ≠ 0 and input ≠ 0

where:


y n( )

MagLimit if1

x n( )------------ MagLimit>

MagLimit if–1

x n( )------------ MagLimit–<

1x n( )------------ otherwise

=

5-48 Reciprocal

SDC1

Description 1-Input Symbolic Defined ComponentLibrary Numeric, MathClass SDFSDC

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component generates numeric data output that is evaluated using anexpression based on input data. Expression can be any valid expression,following the syntax used for writing expressions on a VAR block.

2. Input data is specified by predefined variables _v1, _v2, etc. where 1 and 2 is theport number. The Expression can also be dependent on predefined variable,Nsample, which is incremented for each firing of this component determined bythe schedule.


Expression Expression, function ofinputs

0.0 real


1 input#1 anytype


2 output Numeric output signal real

SDC1 5-49


SDC2


Parameters

Pin Inputs

Pin Outputs

Notes/Equations





0.0 real


1 input#1 anytype

2 input#2 anytype



5-50 SDC2

SDC3


Parameters

Pin Inputs

Pin Outputs

Notes/Equations





0.0 real


1 input#1 anytype

2 input#2 anytype

3 input#3 anytype



SDC3 5-51


SDC4


Parameters

Pin Inputs

Pin Outputs

Notes/Equations


2. Input data is specified by predefined variables _v1, _v2, etc. where 1 and 2 is theport number. The Expression can also be dependent on predefined variable,



0.0 real


1 input#1 anytype

2 input#2 anytype

3 input#3 anytype

4 input#4 anytype



5-52 SDC4

Nsample, which is incremented for each firing of this component determined bythe schedule.

SDC4 5-53


SDCCx1

Description 1-Input Symbolic Defined Component with Complex OutputLibrary Numeric, MathClass SDFSDCCx

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component generates complex data output that is evaluated using anexpression based on input data. Expression can be any valid expression,following the syntax used for writing expressions on a VAR block.




0.0+j*0.0 complex


1 input#1 anytype


2 output Numeric output signal complex

5-54 SDCCx1

SDCCx2


Parameters

Pin Inputs

Pin Outputs

Notes/Equations





0.0+j*0.0 complex


1 input#1 anytype

2 input#2 anytype



SDCCx2 5-55


SDCCx3


Parameters

Pin Inputs

Pin Outputs

Notes/Equations





0.0+j*0.0 complex


1 input#1 anytype

2 input#2 anytype

3 input#3 anytype



5-56 SDCCx3

SDCCx3 5-57


SDCCx4


Parameters

Pin Inputs

Pin Outputs

Notes/Equations


2. Input data is specified by predefined variables _v1, _v2, etc. where 1 and 2 is theport number. The Expression can also be dependent on predefined variable,



0.0+j*0.0 complex


1 input#1 anytype

2 input#2 anytype

3 input#3 anytype

4 input#4 anytype



5-58 SDCCx4

Nsample, which is incremented for each firing of this component determined bythe schedule.

SDCCx4 5-59


Sgn

Description Signum FunctionLibrary Numeric, MathClass SDFSgnC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Sgn calculates the signum of the input.

y(n) = sign of x(n)

where


2. The output is 1 if x ≥ 0. The output is −1 if x < 0.


1 input real


2 output int

5-60 Sgn

Sin

Description Sine FunctionLibrary Numeric, MathClass SDFSinC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Sin calculates the sine of its input, which is assumed to be an angle in radians.

y(n) = sin (x(n))

where



1 input real


2 output real

Sin 5-61


Sinc

Description Sinc FunctionLibrary Numeric, MathClass SDFSincC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Sinc calculates the floating-point (real) sinc of its input given in radians. Thesinc function is defined as sin(x)/x, with value 1.0 when x=0.


1 input The input x to the sinc function. real


2 output The output of the sinc function. real

5-62 Sinc

Sqrt

Description Square Root FunctionLibrary Numeric, MathClass SDFSqrtC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Sqrt calculates the floating-point (real) square root of the input.

where


2. The input value must be ≥ 0.


1 input real


2 output real

y n( ) x n( )=

Sqrt 5-63


Sub

Description Multiple Input SubtractorLibrary Numeric, MathClass SDFSubC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Sub outputs input1 minus all input2 values as a floating-point (real) value.


1 pos real

2 neg multiple real


3 output real

5-64 Sub

SubCx

Description Complex Multiple Input SubtractorLibrary Numeric, MathClass SDFSubCxC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. SubCx outputs input1 minus all input2 values as a complex value.


1 pos complex

2 neg multiple complex


3 output complex

SubCx 5-65


SubFix

Description Fixed-Point Multiple Input SubtractorLibrary Numeric, MathClass SDFSubFixDerived From SDFFixC++ Code

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum


NO enum


2.14 precision


2.14 precision


1 pos fix

2 neg multiple fix

5-66 SubFix

Pin Outputs

Notes/Equations

1. SubFix outputs input1 minus all input2 values as a fixed-point value.





3 output fix

SubFix 5-67


SubInt

Description Integer Multiple Input SubtractorLibrary Numeric, MathClass SDFSubIntC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. SubInt outputs input1 minus all input2 values as an integer value.


1 pos int

2 neg multiple int


3 output int

5-68 SubInt

Trig

Description Trigonometric functionLibrary Numeric, MathClass SDFTrigDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Trig performs the floating-point (real) trigonometric functions:

v2(t) = f (v1(t) )

where f( ) is any of the functions that can be selected from the Type parameter.

2. All angles are in radians.


Type function: Sin, Cos, Tan,Cot, Asin, Acos, Atan,Acot, Sinh, Cosh, Tanh,Coth, Asinh, Acosh, Atanh,Acoth

Sin enum





Trig 5-69


TrigCx

Description Complex trigonometric functionLibrary Numeric, MathClass SDFTrigCxDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component performs the complex trigonometric functions:

v2(t) = f (v1(t) )

where f( ) is any of the functions that can be selected from the Type parameter.

2. All angles are in radians.


Type function: Sin, Cos, Tan,Cot, Asin, Acos, Atan,Acot, Sinh, Cosh, Tanh,Coth, Asinh, Acosh, Atanh,Acoth

Sin enum





5-70 TrigCx

Variance

Description Variance functionLibrary Numeric, MathClass SDFVariance

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Variance calculates a running floating-point (real) estimate of the mean andvariance of the inputs.


BlockSize number of inputs toprocess between eachmean and varianceestimate

1 int [1, ∞)


1 in real


2 mean real

3 variance real

Variance 5-71


5-72 Variance

Chapter 6: Numeric Matrix Components

Introduction

Numeric matrix components provide basic matrix data processing functions such asmatrix addition, multiplication, inversion and more and operate on matrix data setsthat are integer, double precision floating-point (real)), fixed-point (fixed), or complexvalues. Each component accepts a specific class of signal and outputs a resultantsignal. (These components do not accept any scalar class of signal.)

If a component receives another class of signal, the received signal is automaticallyconverted to the signal class specified as the input of the component. Auto conversionfrom a higher to a lower precision signal class may result in loss of information. Theauto conversion from complex or floating-point (real) signals to a fixed signal uses adefault bit width of 32 bits with the minimum number of integer bits needed torepresent the value. For example, the auto conversion of the floating-point (real)value of 1.0 creates a fixed-point value with precision of 2.30; a value of 0.5 createsone with a precision of 1.31. For details on conversions between different classes ofsignals, refer to “Conversion of Data Types” in the ADS Ptolemy Simulation manual.


Some components operate with fixed-point numbers. These components use one ormore parameters that define the characteristics of the fixed-point processing. Theseparameters include: OverflowHandler, OutputPrecision, RoundFix, ReportOverflow,and others. For details on the use of these parameters for fixed-point componentsrefer to “Parameters for Fixed-Point Components” in the ADS Ptolemy Simulationmanual. The arithmetic used by these components is two’s complement. Therefore,all precision values must specify at least one bit to the left of the decimal point (usedas sign bit).

Introduction 6-1

Numeric Matrix Components

Abs_M

Description Absolute Value MatrixLibrary Numeric, MatrixClass SDFAbs_MDerived From MatrixBaseC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Abs_M outputs a matrix composed of the absolute value of each entry of theinput matrix.

2. For information regarding numeric matrix component signals, refer to the“Introduction” on page 6-1.


1 input real matrix


2 output real matrix

6-2 Abs_M

Add_M

Description Matrix AdderLibrary Numeric, MatrixClass SDFAdd_MDerived From MatrixBaseC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. Add_M adds all input matrices together and outputs the resulting matrix. Allinput matrices must be of the same dimensions.



1 input multiple real matrix



Add_M 6-3


Add2_M

Description 2-Input Matrix AdderLibrary Numeric, MatrixClass SDFAdd_MC++ Code

Pin Inputs

Pin Outputs

Notes

1. Add2 adds the two inputs and outputs the resulting matrix. The two inputmatrix signals must have the same matrix row and column values, otherwise anerror will be reported.



1 input#1 real matrix

2 input#2 real matrix



6-4 Add2_M

AddCx_M

Description Complex Matrix AdderLibrary Numeric, MatrixClass SDFAddCx_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. AddCx_M adds all input matrices and outputs the resulting matrix.

2. All input matrices must be of the same dimensions.



1 input multiple complex matrix


2 output complex matrix

AddCx_M 6-5


AddCx2_M

Description 2-Input Complex Matrix AdderLibrary Numeric, MatrixClass SDFAddCx_M

Pin Inputs

Pin Outputs

Notes

1. AddCx2 adds the two inputs and outputs the resulting matrix. The two inputmatrix signals must have the same matrix row and column values, otherwise anerror will be reported.



1 input#1 complex matrix

2 input#2 complex matrix



6-6 AddCx2_M

AddFix_M

Description Fixed Matrix AdderLibrary Numeric, MatrixClass SDFAddFix_MDerived From SDFFix

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum

UseArrivingPrecision use precision of arrivingmatrices: NO, YES

NO enum

InputPrecision precision of input matrixelements, in bits (used onlyif UseArrivingPrecision isset to NO)

2.14 precision


2.14 precision


1 input multiple fix matrix

AddFix_M 6-7


Pin Outputs

Notes/Equations

1. AddFix_M adds all input matrices and outputs the resulting matrix. If theresult of the sum for any entry in the matrix cannot be fit into the precision ofthe output, overflow occurs and is handled by OverflowHandler.







2 output fix matrix

6-8 AddFix_M

AddFix2_M

Description 2-Input Fixed-Point Matrix AdderLibrary Numeric, MatrixClass SDFAddFix_M

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum


NO enum


2.14 precision


2.14 precision


1 input#1 fix matrix

2 input#2 fix matrix

AddFix2_M 6-9


Pin Outputs

Notes/Equations

1. AddFix2_ M adds the two inputs and outputs the resulting matrix withprecision specified by OutputPrecision. The two input matrix signals must havethe same matrix row and column values, otherwise an error will be reported.






3 output fix matrix

6-10 AddFix2_M

AddInt_M

Description Integer Matrix AdderLibrary Numeric, MatrixClass SDFAddInt_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. AddInt_M adds all input matrices and outputs the resulting matrix. All inputmatrices must be of the same dimensions.



1 input multiple int matrix


2 output int matrix

AddInt_M 6-11


AddInt2_M

Description 2-Input Integer Matrix AdderLibrary Numeric, MatrixClass SDFAddInt_M

Pin Inputs

Pin Outputs

Notes/Equations

1. AddInt2_M adds the two inputs and outputs the resulting matrix. The twoinput matrix signals must have the same matrix row and column values,otherwise an error will be reported.



1 input#1 int matrix

2 input#2 int matrix


3 output int matrix

6-12 AddInt2_M

AvgSqrErr_M

Description Average Mean Squared Error MatrixLibrary Numeric, MatrixClass SDFAvgSqrErr_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. AvgSqrErr_M computes the average mean squared error over a set of inputmatrix pairs. The squared error between each corresponding element of a pairof input matrices (input1 and input2) is computed and the errors from eachelement are summed together. The sums are then averaged over the number ofinput matrix pairs. NumInputs gives the number of consecutive input matrixpairs that are averaged.


NumInputs number of input matrices toaverage

8 int [1, ∞)


1 input1 real matrix

2 input2 real matrix


3 output real

AvgSqrErr_M 6-13



6-14 AvgSqrErr_M

Conjugate_M

Description Conjugate MatrixLibrary Numeric, MatrixClass SDFConjugate_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. Conjugate_M outputs the conjugate of the input matrix. Each element of theoutput matrix is the complex conjugate of the corresponding input matrixelement.



1 input complex matrix



Conjugate_M 6-15


Delay_M

Description Matrix Delay ComponentLibrary Numeric, MatrixClass HOFDelay_MDerived From Delay

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Delay_M adds N initial matrices to the output signal.



N N 1 int [0, ∞)

NumRows number of rows in initialmatrix

2 int [1, ∞)

NumCols number of columns in initialmatrix

2 int [1, ∞)

InitialMatrixContents contents of CustomMatrix 1 0 0 1 string





6-16 Delay_M

Gain_M

Description Gain MatrixLibrary Numeric, MatrixClass SDFGain_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Gain_M multiplies a floating-point (real) matrix by a scalar gain value given bythe Gain parameter.



Gain gain to be multiplied witheach entry of the inputmatrix

1.0 real (-∞, ∞)


1 input real matrix



Gain_M 6-17


GainCx_M

Description Complex Gain MatrixLibrary Numeric, MatrixClass SDFGainCx_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. GainCx_M multiplies a complex matrix by a scalar complex gain value given bythe Gain parameter.




Gain gain to be multiplied witheach entry of the inputmatrix

1 complex





6-18 GainCx_M

GainFix_M

Description Fixed-Point Gain MatrixLibrary Numeric, MatrixClass SDFGainFix_MDerived From SDFFix

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum

Gain gain to be multiplied witheach input matrix entry

1.0 fix


NO enum


2.14 precision


2.14 precision


1 input fix matrix

GainFix_M 6-19


Pin Outputs

Notes/Equations

1. GainFix_M multiplies a fixed-point matrix by a fixed-point scalar given by theGain parameter.






2 output fix matrix

6-20 GainFix_M

GainInt_M

Description Integer Gain MatrixLibrary Numeric, MatrixClass SDFGainInt_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. GainInt_M multiplies an integer matrix by a scalar integer given by the Gainparameter.



Gain gain to be multiplied witheach input matrix entry

1 int (-∞, ∞)


1 input int matrix


2 output int matrix

GainInt_M 6-21


Hermitian_M

Description Hermitian MatrixLibrary Numeric, MatrixClass SDFHermitian_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. Hermitian_M performs a Hermitian transpose (conjugate transpose) on theinput matrix.






6-22 Hermitian_M

Inverse_M

Description Inverse MatrixLibrary Numeric, MatrixClass SDFInverse_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. The output matrix is the inverse of the input matrix.

2. The input matrix must be square.



1 input real matrix



input output× IdentityMatrix=

Inverse_M 6-23


InverseCx_M

Description Complex Inverse MatrixLibrary Numeric, MatrixClass SDFInverseCx_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. The complex output matrix is the inverse of the complex input matrix.








6-24 InverseCx_M

InverseFix_M

Description Fixed-Point Inverse MatrixLibrary Numeric, MatrixClass SDFInverseFix_MDerived From SDFFix

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum


NO enum


2.14 precision


2.14 precision


1 input fix matrix

InverseFix_M 6-25


Pin Outputs

Notes/Equations

1. The fixed-point output matrix is the inverse of the fixed-point input matrix.







2 output fix matrix


6-26 InverseFix_M

InverseInt_M

Description Integer Inverse MatrixLibrary Numeric, MatrixClass SDFInverseInt_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. The integer output matrix is the inverse of the input matrix. (Due to integerarithmetic limitations, the output may not be the exact inverse of the input.)




1 input int matrix


2 output int matrix

input output× IdentityMatrix≅

InverseInt_M 6-27


Kalman_M

Description Kalman Filter MatrixLibrary Numeric, MatrixClass SDFKalman_MDerived From MatrixBaseC++ Code

Parameters

Pin Inputs


StateDimension number of elements instate vector

5 int [1, ∞)

InputDimension number of elements inobservation vector

1 int [1, ∞)

InitialState initial value of state vector 0.0 [5] real array

InitialCorrMatrix initial value of correlationmatrix of error

.1 0 [5] .1 0 [5] .10 [5] .1 0 [5] .1

real array

InitialStateTransitionMatrix state transition matrix attime 0. PHI(1,0)

1 0 [5] 1 0 [5] 1 0[5] 1 0 [5] 1

real array

InitialProcessNoiseCorrMatrix correlation matrix ofprocess noise vector attime 0. Q(0)

0.0 [25] real array


1 input real matrix

2 StateTransitionMatrixAtTimeN real matrix

3 MeasurementMatrixAtTimeN real matrix

4 ProcessNoiseCorrMatrixAtTimeN real matrix

5 MeasurementNoiseCorrMatrixAtTimeN real matrix

6-28 Kalman_M

Pin Outputs

Notes/Equations

1. Kalman_M implements a Kalman filter using the one-step predictionalgorithm. The initial values for the state transition, correlation, process noisecorrelation matrices, and state vector are given as parameters.

2. Inputs are the current values of the state transition, process noise correlation,measurement noise correlation, and measurement matrices, and theobservation vector.

3. The single output is the state vector.

4. For details on using arrays of data for parameter values, refer to“Understanding Parameters” in the ADS Ptolemy Simulation manual.


References

[1]R.E. Kalman, “A new approach to linear filtering and prediction problems,”Trans. ASME, J. Basic Eng., Ser 82D, pp. 35-45, March 1960.

6. S. Haykin, Adaptive Filter Theory, Prentice-Hall, Inc., Englewood Cliffs, N.J.,1986.



Kalman_M 6-29


Matlab_M

Description Matlab Floating Point Matrix OutputLibrary Numeric, MatrixClass SDFMatlab_MDerived From Matlab

Parameters

Pin Inputs

Pin Outputs


ScriptDirectory An optional directoryspecifying where to findany custom Matlab files.You may use tildecharacters andenvironment variables inthe directory name.

string

MatlabSetUp Matlab command toexecute during beginmethod

string

MatlabFunction Matlab command toexecute for each simulationsample

string

MatlabWrapUp Matlab command toexecute during wrapupmethod

string




2 output multiple real matrix

6-30 Matlab_M

Notes/Equations

1. Matlab_M evaluates Matlab functions on its inputs and outputs floating-point(real) matrices.

2. ScriptDirectory is an optional directory specifying where to find any customMatlab files.

3. For more information about Matlab components, refer to “Introduction toMATLAB Cosimulation” in the ADS Ptolemy Simulation manual.


Matlab_M 6-31


MatlabCx_M

Description Matlab Complex Matrix OutputLibrary Numeric, MatrixClass SDFMatlabCx_MDerived From Matlab_M

Parameters

Pin Inputs

Pin Outputs



string


string


string


string




2 output multiple complex matrix

6-32 MatlabCx_M

Notes/Equations

1. MatlabCx_M evaluates Matlab functions on its inputs and outputs complexmatrices.




MatlabCx_M 6-33


MatlabF_M

Description Matlab Floating Point Matrix Output with Scripts ImportingLibrary Numeric, MatrixClass SDFMatlabF_MDerived From Matlab

Parameters

Pin Inputs

Pin Outputs



string


filename


filename


filename





6-34 MatlabF_M

Notes/Equations

1. MatlabF_M evaluates Matlab functions on its inputs and outputs floating-point(real) matrices.

2. MatlabSetup, MatlabFunction, and MatlabWrapUp inputs accept script filesonly.

3. ScriptDirectory is an optional directory specifying where to find any customMatlab files referenced inside MatlabSetup, MatlabFunction, andMatlabWrapUp scripts.



MatlabF_M 6-35


MatlabFCx_M

Description Matlab Complex Matrix Output with Scripts ImportingLibrary Numeric, MatrixClass SDFMatlabFCx_MDerived From MatlabF_M

Parameters

Pin Inputs

Pin Outputs



string


filename


filename


filename





6-36 MatlabFCx_M

Notes/Equations

1. MatlabFCx_M evaluates Matlab functions on its inputs and outputs complexmatrices.





MatlabFCx_M 6-37


MatlabLibLink

Description Matlab Cosimulation with Compile Mode SupportLibrary Numeric, MatrixClass SDFMatlabLibLink

Parameters

Pin Inputs

Pin Outputs


Library Compiled Matlab Libraryname, must start with lib

string

Setup Matlab Setup functionname

filename

SetupParm Optional Setup Parameterlist

complexarray

Function Matlab function name to beexecuted for eachsimulation sample

filename

Mode Mode of operation,automatic, force recompileor force script running:AUTO, COMPILE, SCRIPT

AUTO enum





6-38 MatlabLibLink

Notes/Equations

1. Ensure Matlab and Matlab Compiler are properly installed; ADS will call thecompiler for you; makefiles or manual compilation is not needed.

2. The Library name must start with lib; for example, libfoo, libbar. It specifies thelibrary name to be compiled or the library that already exists to link in. Librarywill be compiled into _prj\data directory. Pre-compiled shared library can alsobe placed under _prj\data directory to be picked up.

3. SetupParm specifies a list of function arguments that are passed into SetupMatlab function. The exact number of arguments specified in the given setupmatlab file must be provided; otherwise the simulation will crash without anywarnings.

The format is comma-separated arguments in curly braces ; for example,a,b,c.

• a, b, c can be ADS VAR variables, constants or equations.

• a,b,c on the schematic must not be surrounded by quotes; the componentdialog box format is @a,b,c .

4. Setup is the function name or .m file. You can browse Setup and Function .mfiles. It can remain blank if setup is not needed. The Library will be compiledunder your_prj\data directory.

5. Arguments of function are data passed from Input and Output Ports of thecomponents. Input Port 1 will be mapped to Input Argument 1.

6. Mode options are:

• AUTO will ONLY compile the .m files if Library with specified name is notfound in the library search path, LD_LIBRARY_PATH on Sun,SHLIB_PATH on Unix, etc.

• COMPILE will always recompile the .m files.

• SCRIPT will use the traditional Matlab link; it simply interprets .m files.

MatlabLibLink 6-39


MatlabLibLinkCx

Description Matlab Cosimulation with Compile Mode Support and Complex OutputLibrary Numeric, MatrixClass SDFMatlabLibLinkCxDerived From MatlabLibLink

Parameters

Pin Inputs

Pin Outputs


Library Compiled Matlab Libraryname, must start with lib

string

Setup Matlab Setup functionname

filename

SetupParm Optional Setup Parameterlist

complexarray

Function Matlab function name to beexecuted for eachsimulation sample

filename

Mode Mode of operation,automatic, force recompileor force script running:AUTO, COMPILE, SCRIPT

AUTO enum





6-40 MatlabLibLinkCx

Notes/Equations

1. Ensure Matlab and Matlab Compiler are properly installed; ADS will call thecompiler for you; makefiles or manual compilation is not needed.

2. The Library name must start with lib; for example, libfoo, libbar. It specifies thelibrary name to be compiled or the library that already exists to link in. Librarywill be compiled into _prj\data directory. Pre-compiled shared library can alsobe placed under _prj\data directory to be picked up.

3. SetupParm specifies a list of function arguments that are passed into SetupMatlab function. The exact number of arguments specified in the given setupmatlab file must be provided; otherwise the simulation will crash without anywarnings.

The format is comma-separated arguments in curly braces ; for example,a,b,c.

• a, b, c can be ADS VAR variables, constants or equations.

• a,b,c on the schematic must not be surrounded by quotes; the componentdialog box format is @a,b,c .

4. Setup is the function name or .m file. You can browse Setup and Function .mfiles. It can remain blank if setup is not needed. The Library will be compiledunder your_prj\data directory.

5. Arguments of function are data passed from Input and Output Ports of thecomponents. Input Port 1 will be mapped to Input Argument 1.

6. Mode options are:

• AUTO will ONLY compile the .m files if Library with specified name is notfound in the library search path, LD_LIBRARY_PATH on Sun,SHLIB_PATH on Unix, etc.

• COMPILE will always recompile the .m files.

• SCRIPT will use the traditional Matlab link; it simply interprets .m files.

MatlabLibLinkCx 6-41


MatlabSink

Description Matlab FunctionLibrary Numeric, MatrixClass SDFMatlabSinkDerived From Matlab_M

Parameters

Pin Inputs



string


string


string


string

NumberOfFirings number of invocationsduring a simulation

1 int [1, ∞)



6-42 MatlabSink

Notes/Equations

1. MatlabSink behaves like other Matlab components except that it does not haveany output. The total amount of data collected is determined byNumberOfFirings.




MatlabSink 6-43


MatlabSinkF

Description Matlab Function with Scripts ImportingLibrary Numeric, MatrixClass SDFMatlabSinkFDerived From MatlabF_M

Parameters

Pin Inputs



string


filename


filename


filename

NumberOfFirings number of invocationsduring a simulation

1 int [1, ∞)



6-44 MatlabSinkF

Notes/Equations

1. MatlabSinkF behaves like other Matlab components except that it does nothave any output. The total amount of data collected is determined byNumberOfFirings.





MatlabSinkF 6-45


Mpy_M

Description Matrix MultiplierLibrary Numeric, MatrixClass SDFMpy_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. Mpy_M multiplies the input matrices and outputs the resulting matrix.

2. The output matrix will have same number of rows as the Ainput and the samenumber of columns as the Binput.

3. The number of columns in the Ainput matrix must match the number of rows inthe Binput matrix.



1 Ainput real matrix

2 Binput real matrix



output Ainput Binput×=

6-46 Mpy_M

MpyCx_M

Description Complex Matrix MultiplierLibrary Numeric, MatrixClass SDFMpyCx_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. MpyCx_M multiplies the complex input matrices and outputs the resultingmatrix.



NumRows number of rows in initialmatrix

2 int [1, ∞)

NumCols number of columns in initialmatrix

2 int [1, ∞)


1 Ainput complex matrix

2 Binput complex matrix



MpyCx_M 6-47





6-48 MpyCx_M

MpyFix_M

Description Fixed-Point Matrix MultiplierLibrary Numeric, MatrixClass SDFMpyFix_MDerived From SDFFix

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum


NO enum


2.14 precision


2.14 precision


1 Ainput fix matrix

2 Binput fix matrix

MpyFix_M 6-49


Pin Outputs

Notes/Equations

1. MpyFix_M multiplies the input matrices and outputs the resulting fixed-pointmatrix. If the result of the multiplication for any entry in the matrix cannot befit into the precision of the output, overflow occurs and is handled byOverflowHandler.








3 output fix matrix


6-50 MpyFix_M

MpyInt_M

Description Integer Matrix MultiplierLibrary Numeric, MatrixClass SDFMpyInt_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. MpyInt_M multiplies the input matrices and outputs the resulting matrix.





1 Ainput int matrix

2 Binput int matrix


3 output int matrix


MpyInt_M 6-51


MpyScalar_M

Description Scalar and Matrix MultiplierLibrary Numeric, MatrixClass SDFMpyScalar_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. MpyScalar_M multiplies a floating-point (real) matrix by a scalar input value.



1 input real matrix

2 gain Input gain to be multiplied with the input matrix real



6-52 MpyScalar_M

MpyScalarCx_M

Description Matrix and Complex Scalar MultiplierLibrary Numeric, MatrixClass SDFMpyScalarCx_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. MpyScalarCx_M multiplies a complex matrix by a scalar complex input value.




2 gain Input gain to be multiplied with the input matrix complex



MpyScalarCx_M 6-53


MpyScalarFix_M

Description Scalar and Fixed-Point Matrix MultiplierLibrary Numeric, MatrixClass SDFMpyScalarFix_MDerived From SDFFix

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum


NO enum


2.14 precision


2.14 precision


1 input fix matrix

2 gain Input gain to be multiplied with the input matrix fix

6-54 MpyScalarFix_M

Pin Outputs

Notes/Equations

1. MpyScalarFix_M multiplies a fixed-point matrix by a scalar fixed-point inputvalue.






3 output fix matrix

MpyScalarFix_M 6-55


MpyScalarInt_M

Description Scalar and Integer Matrix MultiplierLibrary Numeric, MatrixClass SDFMpyScalarInt_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. MpyScalarCx_M multiplies an integer matrix by a scalar integer input value.



1 input int matrix

2 gain Input gain to be multiplied with the input matrix int


3 output int matrix

6-56 MpyScalarInt_M

MxCom_M

Description Composed MatrixLibrary Numeric, MatrixClass SDFMxCom_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations


OutputNumRows number of rows for outputmatrix

100 int [InputNumRows

, ∞)†

OutputNumColumns number of columns foroutput matrix

100 int [InputNumColu

mns, ∞)††

InputNumRows number of rows for inputmatrix

4 int [1, ∞)

InputNumColumns number of columns forinput matrix

4 int [1, ∞)

† must be an integer multiple of InputNumRows†† must be an integer multiple of InputNumColumns


1 input real matrix



MxCom_M 6-57


1. Each output matrix is composed from the input submatrices. The output matrixis filled with input submatrices in rasterized order; that is, the top of the outputmatrix is filled first, from left to right, with the first input matrices.


6-58 MxCom_M

MxDecom_M

Description Decomposed MatrixLibrary Numeric, MatrixClass SDFMxDecom_MDerived From MatrixBase

Parameters

Pin Inputs


StartRow starting row in input matrixto generate outputmatrices (first row is 1)

1 int [1, ∞)

StartCol starting column in inputmatrix to generate outputmatrices (first column is 1;therefore, the upper leftcorner of the matrix is (1,1)

1 int [1, ∞)

InputNumRows number of rows for inputmatrix

100 int [OutputNumRo

ws, ∞)†

InputNumCols number of columns frominput matrix to use togenerate the outputmatrices.

100 int [OutputNumCol

s, ∞)††

OutputNumRows number of rows for outputmatrix

4 int [1, ∞)

OutputNumCols number of columns foroutput matrix

4 int [1, ∞)

† must be an integer multiple of OutputNumRows†† must be an integer multiple of OutputNumCols


1 input Input matrix to be decomposed into the outputsubmatrices.

real matrix

MxDecom_M 6-59


Pin Outputs

Notes/Equations

1. All or part of the input matrix is decomposed into a sequence of outputsubmatrices. The part of input matrix to be decomposed is specified byStartRow, StartCol, InputNumRows, and InputNumColumns. The dimensionsof each output submatrix are specified by the OutputNumRows andOutputNumColumns.

2. For each input matrix, the number of output matrices is:



2 output Output matrices with dimensionsOutputNumRows*OutputNumCols.

real matrix

InputNumRowsOutputNumRows---------------------------------------------------- InputNumColumns

OutputNumColumns---------------------------------------------------------------×

6-60 MxDecom_M

Pack_M

Description Pack MatrixLibrary Numeric, MatrixClass SDFPack_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Pack_M constructs a complex output matrix from scalar input values. Inputsare entered into the matrix in rasterized order; for example, for an M×N matrix,the first row is filled from left to right using the first N input values.



NumRows number of rows in outputmatrix

2 int [1, ∞)

NumCols number of columns inoutput matrix

2 int [1, ∞)


1 input real



Pack_M 6-61


PackCx_M

Description Pack Complex MatrixLibrary Numeric, MatrixClass SDFPackCx_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. PackCx_M constructs a complex output matrix from scalar input values. Inputsare entered into the matrix in rasterized order; for example, for an M×N matrix,the first row is filled from left to right using the first N input values.




2 int [1, ∞)


2 int [1, ∞)


1 input complex



6-62 PackCx_M

PackFix_M

Description Pack Fixed-Point MatrixLibrary Numeric, MatrixClass SDFPackFix_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. PackFix_M constructs a fixed-point output matrix from scalar input values.Inputs are entered into the matrix in rasterized order; for example, for an M×Nmatrix, the first row is filled from left to right using the first N input values.

2. There are no fixed-point parameters for this component because fixed-pointarithmetic is not performed.



2 int [1, ∞)


2 int [1, ∞)


1 input fix


2 output fix matrix

PackFix_M 6-63



6-64 PackFix_M

PackInt_M

Description Pack Integer MatrixLibrary Numeric, MatrixClass SDFPackInt_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. PackInt_M constructs an integer output matrix from scalar input values.Inputs are entered into the matrix in rasterized order; for example, for an M×Nmatrix, the first row is filled from left to right using the first N input values.




2 int [1, ∞)


2 int [1, ∞)


1 input int


2 output int matrix

PackInt_M 6-65


SampleMean_M

Description Mean Value MatrixLibrary Numeric, MatrixClass SDFSampleMean_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. SampleMean_M finds the average value of the elements of the input matrix.



1 input real matrix


2 output real

6-66 SampleMean_M

Sub_M

Description SubtractionLibrary Numeric, MatrixClass SDFSub_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. Sub_M outputs the pos input matrix minus all neg inputs.




1 pos real matrix

2 neg multiple real matrix



Sub_M 6-67


SubCx_M

Description Complex SubtractionLibrary Numeric, MatrixClass SDFSubCx_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. SubCx_M outputs the pos input matrix minus all of the neg inputs.




1 pos complex matrix

2 neg multiple complex matrix



6-68 SubCx_M

SubFix_M

Description Fixed SubtractionLibrary Numeric, MatrixClass SDFSubFix_MDerived From SDFFix

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum


NO enum


2.14 precision


2.14 precision


1 pos fix matrix

2 neg multiple fix matrix

SubFix_M 6-69


Pin Outputs

Notes/Equations

1. SubFix_M outputs the pos input matrix minus the neg inputs.







3 output fix matrix

6-70 SubFix_M

SubInt_M

Description Integer SubtractionLibrary Numeric, MatrixClass SDFSubInt_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. SubInt_M outputs the pos input matrix minus all of the neg inputs.




1 pos int matrix

2 neg multiple int matrix


3 output int matrix

SubInt_M 6-71


SubMx_M

Description SubmatrixLibrary Numeric, MatrixClass SDFSubMx_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs


StartRow starting row in thesubmatrix within the inputmatrix. The first (top) row ina matrix is 1.

1 int [1, ∞)

StartCol starting column in thesubmatrix within the inputmatrix. The first (left)column in a matrix is 1;therefore, the upper leftcorner of the matrix is(1,1).

1 int [1, ∞)

NumRows number of rows forsubmatrix

2 int [1, ∞)

NumCols number of columns forsubmatrix

2 int [1, ∞)


1 input real matrix



6-72 SubMx_M

Notes/Equations

1. Output matrix is a submatrix of the input matrix. The parameters specify thesize and position of the output submatrix from within the input matrix.


SubMx_M 6-73


SubMxCx_M

Description Complex SubmatrixLibrary Numeric, MatrixClass SDFSubMxCx_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs



1 int [1, ∞)


1 int [1, ∞)


1 int [1, ∞)


1 int [1, ∞)





6-74 SubMxCx_M

Notes/Equations



SubMxCx_M 6-75


SubMxFix_M

Description Fixed SubmatrixLibrary Numeric, MatrixClass SDFSubMxFix_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs



1 int [1, ∞)


1 int [1, ∞)


2 int [1, ∞)


1 int [1, ∞)


1 input fix matrix


2 output fix matrix

6-76 SubMxFix_M

Notes/Equations


2. There are no fixed-point parameters because fixed-point arithmetic is notperformed. The output precision is the same as the input precision.


SubMxFix_M 6-77


SubMxInt_M

Description Integer SubmatrixLibrary Numeric, MatrixClass SDFSubMxInt_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs



1 int [1, ∞)


1 int [1, ∞)


1 int [1, ∞)


1 int [1, ∞)


1 input int matrix


2 output int matrix

6-78 SubMxInt_M

Notes/Equations

1. The output matrix is a submatrix of the input matrix. The parameters specifythe size and position of the output submatrix from within the input matrix.


SubMxInt_M 6-79


SVD_M

Description Singular Value Decomposition of a Toeplitz MatrixLibrary Numeric, MatrixClass SDFSVD_MDerived From MatrixBaseC++ Code

Parameters

Pin Inputs


Threshold threshold for similarities;algorithm assumes valuesbelow Threshold havereached zero

0.00000000000000001

real (-∞, ∞)

MaxIterations maximum iterations forSVD convergence

30 int [1, ∞)

GenerateLeft matrix generation of leftsingular vectors: Do notGenerate Left SingularVectors, Generate LeftSingular Vectors

Generate LeftSingular Vectors

enum

GenerateRight matrix generation of rightsingular vectors: Do notGenerate Right SingularVectors, Generate RightSingular Vectors

Generate RightSingular Vectors

enum


1 input Input stream. real matrix

6-80 SVD_M

Pin Outputs

Notes/Equations

1. SVD_M computes the singular-value decomposition (SVD) of an input Toeplitzmatrix A by decomposing A into A = UWV′ , where U and V are orthogonalmatrices and V′ represents the transpose of V.

2. The input matrix must be a Toeplitz matrix. The output S is the diagonal of thematrix W, the output L is the matrix U, and the output R is the matrix V. If theinput matrix is of size M rows by N columns, the output S will be of size N×1,output L will be of size M×N, and output R will be of size N×N.

3. The MaxIterations parameter allows the user to control the number ofiterations that the SVD algorithm will be allowed to run before stopping.Normally, the SVD algorithm will converge before this number of iterations isreached but this parameter is provided to prevent non-convergent matricesfrom causing the component to run too long.

4. The execution time of SVD_M may be reduced by using the GenerateLeft andGenerateRight parameters to specify that the matrices of the left and rightsingular vectors not be generated. The vector of singular values (the S output)is always generated.

5. S. Haykin, Modern Filters, pp. 333-335, Macmillan Publishing Company, NewYork, 1989.

6. See Also: Toeplitz_M



2 svals The singular values of input - The diagonal of "W". real matrix

3 rsvec Right singular vectors of input - "V". real matrix

4 lsvec Left singular vectors of input - "W". real matrix

SVD_M 6-81


Table_M

Description Lookup Table MatrixLibrary Numeric, MatrixClass SDFTable_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations


NumRows number of rows for eachmatrix in the table

2 int [1, ∞)

NumCols number of columns foreach matrix in the table

2 int [1, ∞)

FloatTable table containing matrices.Each matrix withdimensions NumRows xNumCols is given in rowmajor ordering.

0.0 0.0 0.0 0.0 1.01.0 1.0 1.0

real array †

† FloatTable number of elements must be an integer multiple of the output matrix size (NumRows * NumCols)


1 input the index for table lookup. The first matrix is index"0"

int


2 output the matrix in the table corresponding to the index. real matrix

6-82 Table_M

1. Table_M implements a matrix lookup table indexed by an integer-valued input.The output will be the matrix corresponding to the index input. The input mustbe from 0 to N-1, inclusive, where N is the number of matrices in the table.FloatTable specifies the entries of matrices in the table.

2. Entries of each matrix in the table should be given in row major ordering.Therefore, the upper left corner entry of the first matrix is the first value in thetable, and the first NumCols items in the table parameter make up the first rowof the first matrix in the table.

3. An error occurs if the index input value is out of bounds.

4. For details on these fixed-point parameters refer to “Parameters for Fixed-PointComponents” in the ADS Ptolemy Simulation manual.


Table_M 6-83


TableCx_M

Description Complex Lookup Table MatrixLibrary Numeric, MatrixClass SDFTableCx_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



1 int [1, ∞)


1 int [1, ∞)

ComplexTable table containing matrices.Each matrix withdimensions NumRows xNumCols is given in rowmajor ordering.

1.0+j 1.0-j(-1.0+j) (-1.0-j)

complexarray

†

† ComplexTable number of elements must be an integer multiple of the output matrix size (NumRows * NumCols)



int


2 output the matrix in the table corresponding to the index. complex matrix

6-84 TableCx_M

1. TableCx_M implements a matrix lookup table indexed by an integer-valuedinput. The output will be a the matrix corresponding to the index input. Theinput must be from 0 to N-1, inclusive, where N is the number of matrices in thetable. ComplexTable specifies the entries of matrices in the table.

Entries of each matrix in the table should be given in row major ordering.Therefore, the upper left corner entry of the first matrix is the first value in thetable, and the first NumCols items in the table parameter make up the first rowof the first matrix in the table.

An error occurs if the index input value is out of bounds.


For details on using complex arrays of data, refer to “Value Types” in the ADSPtolemy Simulation manual.


TableCx_M 6-85


TableInt_M

Description Integer Lookup Table MatrixLibrary Numeric, MatrixClass SDFTableInt_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



1 int [1, ∞)


2 int [1, ∞)

IntTable table containing matrices.Each matrix withdimensions NumRows xNumCols is given in rowmajor ordering.

1 1 1 -1 -1 1 -1-1

int array †

† IntTable number of elements must be an integer multiple of the output matrix size (NumRows * NumCols)



int


2 output the matrix in the table corresponding to the index. int matrix

6-86 TableInt_M

1. TableInt_M implements a matrix lookup table indexed by an integer-valuedinput. The output will be a the matrix corresponding to the index input. Theinput must be from 0 to N-1, inclusive, where N is the number of matrices in thetable. IntTable specifies the entries of matrices in the table.

2. The entries of each matrix in the table should be given in row major ordering.Therefore, the upper left corner entry of the first matrix is the first value in thetable, and the first NumCols items in the table parameter make up the first rowof the first matrix in the table.

3. An error occurs if the index input value is out of bounds.



TableInt_M 6-87


Toeplitz_M

Description Toeplitz MatrixLibrary Numeric, MatrixClass SDFToeplitz_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Toeplitz_M builds a rectangular Toeplitz matrix from the input scalar values.

2. This component generates an output matrix X, with dimensionsNumRows × NumCols, from an input stream ofNumRows+NumCols−1particles. The output matrix is a Toeplitz matrix suchthat


NumRows number of rows in theoutput matrix

2 int [1, ∞)

NumCols number of columns in theoutput matrix

2 int [1, ∞)


1 input Input stream. real


2 output the data matrix X. real matrix

6-88 Toeplitz_M

the first row is

the second row is

and so forth until the last row, which is

where NumRows = N−M+1 and NumCols = M and conversely M = NumColsand N = NumRows + NumCols − 1.


x M 1–( ) x M 2–( ) … x 0( )

x M( ) x M 1–( ) x M 2–( ) … x 1( )

x N 1–( ) x N 2–( ) … x N M–( )

Toeplitz_M 6-89


ToeplitzCx_M

Description Complex Toeplitz MatrixLibrary Numeric, MatrixClass SDFToeplitzCx_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. ToeplitzCx_M builds a rectangular Toeplitz matrix from the input scalar values.

2. ToeplitzCx_M generates an output matrix X, with dimensions NumRows ×NumCols, from an input stream of NumRows + NumCols − 1 particles. Theoutput matrix is a Toeplitz matrix such that



2 int [1, ∞)


2 int [1, ∞)


1 input Input stream. complex


2 output Data matrix X. complex matrix

6-90 ToeplitzCx_M

the first row is

the second row is


where NumRows = N-M+1 and NumCols = M and conversely, M = NumCols andN = NumRows + NumCols − 1.


x M 1–( ) x M 2–( ) … x 0( )

x M( ) x M 1–( ) x M 2–( ) … x 1( )

x N 1–( ) x N 2–( ) … x N M–( )

ToeplitzCx_M 6-91


ToeplitzFix_M

Description Fixed Toeplitz MatrixLibrary Numeric, MatrixClass SDFToeplitzFix_MDerived From SDFFix

Parameters

Pin Inputs



wrapped enum


REPORT enum


TRUNCATE enum


NO enum


2.14 precision


2.14 precision


2 int [1, ∞)


2 int [1, ∞)


1 input Input stream. fix

6-92 ToeplitzFix_M

Pin Outputs

Notes/Equations

1. ToeplitzFix_M builds a rectangular Toeplitz matrix from the input scalarvalues.

2. This component generates an output matrix X, with dimensions NumRows ×NumCols, from an input stream of NumRows + NumCols − 1 particles. Theoutput matrix is a Toeplitz matrix such that

the first row is

the second row is


where NumRows = N−M+1 and NumCols = M and conversely, M = NumColsand N = NumRows + NumCols − 1.





2 output the data matrix X. fix matrix

x M 1–( ) x M 2–( ) … x 0( )

x M( ) x M 1–( ) x M 2–( ) … x 1( )

x N 1–( ) x N 2–( ) … x N M–( )

ToeplitzFix_M 6-93



6-94 ToeplitzFix_M

ToeplitzInt_M

Description Integer Toeplitz MatrixLibrary Numeric, MatrixClass SDFToeplitzInt_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. ToeplitzInt_M builds a rectangular Toeplitz matrix from input scalar values.

2. This component generates an output matrix X, with dimensions NumRows ×NumCols, from an input stream of NumRows + NumCols − 1 particles. Theoutput matrix is a Toeplitz matrix such that



2 int [1, ∞)


2 int [1, ∞)


1 input Input stream. int


2 output the data matrix X. int matrix

ToeplitzInt_M 6-95


the first row is

the second row is


where NumRows = N−M+1 and NumCols = M and conversely M = NumColsand N = NumRows + NumCols − 1.


x M 1–( ) x M 2–( ) … x 0( )

x M( ) x M 1–( ) x M 2–( ) … x 1( )

x N 1–( ) x N 2–( ) … x N M–( )

6-96 ToeplitzInt_M

Transpose_M

Description Transpose MatrixLibrary Numeric, MatrixClass SDFTranspose_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. Transpose_M outputs the transpose of the input matrix.



1 input real matrix



Transpose_M 6-97


TransposeCx_M

Description Complex Transpose MatrixLibrary Numeric, MatrixClass SDFTransposeCx_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. TransposeCx_M outputs the transpose of the input matrix.






6-98 TransposeCx_M

TransposeFix_M

Description Fixed Transpose MatrixLibrary Numeric, MatrixClass SDFTransposeFix_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. TransposeFix_M outputs the transpose of the input matrix.




1 input fix matrix


2 output fix matrix

TransposeFix_M 6-99


TransposeInt_M

Description Integer Transpose MatrixLibrary Numeric, MatrixClass SDFTransposeInt_MDerived From MatrixBase

Pin Inputs

Pin Outputs

Notes/Equations

1. TransposeInt_M outputs the transpose of the input matrix.



1 input int matrix


2 output int matrix

6-100 TransposeInt_M

UnPk_M

Description Unpack MatrixLibrary Numeric, MatrixClass SDFUnPk_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The scalar outputs are each of the elements of the input matrix. The elementsare sent to the output row-by-row, top-to-bottom. Top row entries are sent first(left to right) followed by the next row down, and so on.



NumRows number of rows in inputmatrix

2 int [1, ∞)

NumCols number of columns in inputmatrix

2 int [1, ∞)


1 input real matrix


2 output real

UnPk_M 6-101


UnPkCx_M

Description Unpack Complex MatrixLibrary Numeric, MatrixClass SDFUnPkCx_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations





2 int [1, ∞)


2 int [1, ∞)




2 output complex

6-102 UnPkCx_M

UnPkFix_M

Description Unpack Fixed MatrixLibrary Numeric, MatrixClass SDFUnPkFix_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations





2 int [1, ∞)


2 int [1, ∞)


1 input fix matrix


2 output fix

UnPkFix_M 6-103



6-104 UnPkFix_M

UnPkInt_M

Description Unpack Integer MatrixLibrary Numeric, MatrixClass SDFUnPkInt_MDerived From MatrixBase

Parameters

Pin Inputs

Pin Outputs

Notes/Equations




NumRows number of rows in the inputmatrix

2 int [1, ∞)

NumCols number of columns in theinput matrix

2 int [1, ∞)


1 input int matrix


2 output int

UnPkInt_M 6-105


6-106 UnPkInt_M

Chapter 7: Numeric Signal ProcessingComponents

IntroductionThe numeric signal processing components provide basic signal processing functionson single data points or arrays of data that are integer, double precision floating-point(real), fixed-point (fixed), or complex values. Each component accepts a specific classof signal and outputs a resultant signal. (These components do not accept any matrixclass of signal.)

If a component receives another class of signal, the received signal is automaticallyconverted to the signal class specified as the input of the component. Auto conversionfrom a higher to a lower precision signal class may result in loss of information. Theauto conversion from timed, complex or floating-point (real) signals to a fixed signaluses a default bit width of 32 bits with the minimum number of integer bits needed torepresent the value. For example, the auto conversion of the floating-point (real)value of 1.0 creates a fixed-point value with precision of 2.30; a value of 0.5 wouldcreate one of precision of 1.31. For details on conversions between different classes ofsignals, refer to “Conversion of Data Types” in the ADS Ptolemy Simulation manual.


Some components operate with fixed-point numbers. These components use one ormore parameters that define the characteristics of the fixed-point processing. Theseparameters include: OverflowHandler, OutputPrecision, RoundFix, ReportOverflow,and others. For details on the use of these parameters for fixed-point componentsrefer to “Parameters for Fixed-Point Components” in the ADS Ptolemy Simulationmanual. The arithmetic used by these components is two’s complement. Therefore,all precision values must specify at least one bit to the left of the decimal point (usedas sign bit)

7-1

Numeric Signal Processing Components

Autocor

Description Autocorrelation estimatorLibrary Numeric, Signal ProcessingClass SDFAutocorC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Autocor estimates the autocorrelation function of the input signal. Every timethe component fires it reads N samples from its input and outputs 2*L values toits output.

The output values represent the values of the input signal’s autocorrelationfunction


NoInputsToAvg number of input samples toaverage

256 N int (NoLags, ∞)

NoLags number of lags to output 64 L int (0, ∞)

Unbiased autocorrelation estimatebias: NO, YES

YES enum





7-2 Autocor

,

evaluated for k=-L+1, ... , L

( is output first and is output last).

The 2*L values written to the output make the output almost symmetrical(discard the last sample to get a perfectly symmetric output).

2. Both unbiased and biased estimates are supported.

• If Unbiased=YES, the autocorrelation estimate is

The unbiased estimate does not guarantee a positive definite sequence, so apower spectral estimate based on this autocorrelation estimate may havenegative components.

• If Unbiased=NO, the autocorrelation estimate is

This estimate is biased because the outermost lags have fewer than N termsin the summation, yet the summation is still normalized by N.

3. For information regarding numeric signal processing component signals, referto the “Introduction” on page 7-1.

References


rxˆ k( )

rxˆ L– 1+( ) rx

ˆ L( )

rxˆ k( )

1N k–----------------- x n( )x n k+( ) L– 1+( ) k L≤ ≤,

n 0=

N 1– k–

∑0 otherwise,

=

rxˆ k( )

1N----- x n( )x n k+( ) L– 1+( ) k L≤ ≤,

n 0=

N 1– k–

∑0 otherwise,

=

Autocor 7-3


Biquad

Description Biquad IIR FilterLibrary Numeric, Signal ProcessingClass SDFBiquadC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Biquad is a 2-pole, 2-zero digital IIR filter (a biquad). This IIR filter has aZ-domain transfer function of


D1 first-order denominatorcoefficient

-1.1430 real (-∞, ∞)

D2 second-order denominatorcoefficient

0.41280 real (-∞, ∞)

N0 zeroth-order numeratorcoefficient

0.067455 real (-∞, ∞)

N1 first-order numeratorcoefficient

0.135 real (-∞, ∞)

N2 second-order numeratorcoefficient

0.067455 real (-∞, ∞)


1 input real


2 output real

7-4 Biquad

(7-1)

The default is a Butterworth filter with a cutoff 0.1 times sampling frequency.

2. The transfer function in Eq. (7-1) results in the following second orderdifference equation.

where


3. The transfer function in Eq. (7-1) is a linear time invariant system and can berearranged to yield difference equation in direct form II as shown in Figure 7-1.

Indeed, it is the minimum number of delay elements required to implement asystem with transfer function given by Eq. (7-1). An implementation with theminimum number of delay elements is also referred to as a canonic formimplementation.

Figure 7-1.

4. See also: IIR, IIR_Cx, IIR_Fix.


References


H z( ) Y z( )X z( )-------------

N0 N1z 1– N2z 2–+ +

1 D1z 1– D2z 2–+ +

-------------------------------------------------------= =

y n( ) N0x n( ) N1x n 1–( ) N2x n 2–( ) D1y n 1–( )– D2y n 2–( )–+ +=

X[n] Y[n]N0

D1

D2

N1

Z-1

N2

Z-1

Biquad 7-5


BiquadCascade

Description IIR filter with cascaded biquad IIR sectionsLibrary Numeric, Signal ProcessingClass SDFBiquadCascade

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. BiquadCascade is a cascade of 2-pole, 2-zero digital IIR filter (a biquad). ThisIIR filter has a Z-domain transfer function of


Taps sets of six biquadcoefficients

0.067455 0.1350.067455 1.0-1.143 0.4128

real array


1 input real


2 output The outputs from each of the biquads in thecascade, starting with the output from last.

multiple real

H z( ) ΠYi z( )Xi z( )--------------- Π

N0i N1iz1– N2iz

2–+ +

D0i D1iz1– D2iz

2–+ +

-------------------------------------------------------------= =

7-6 BiquadCascade

2. Each biquad section is defined by six coefficients in order: N0i N1i N2i D0i D1iD2i.

3. The multi-output pin contains each of the outputs of the cascade, starting withthe output from the last.

4. See also: Biquad, IIR, IIR_Cx, IIR_Fix.


References


BiquadCascade 7-7


BlockAllPole

Description All-Pole Filter for Data BlocksLibrary Numeric, Signal ProcessingClass SDFBlockAllPoleC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. BlockAllPole implements an all-pole filter with coefficients that are periodicallyupdated from the outside. For each set of coefficients, a block of input samples isprocessed, all in one firing.


BlockSize number of inputs that useeach coefficient set

128 int (0, ∞)

Order number of new coefficientsto read each time

16 int (0, ∞)


1 signalIn real

2 coefs Coefficients of the denominator polynomial real


3 signalOut real

7-8 BlockAllPole

2. The BlockSize parameter tells how often the updates occur. This integerparameter specifies how many input samples are to be processed using each setof coefficients. The Order parameter tells how many coefficients there are.

3. The transfer function of the filter is

where the d values are the externally specified coefficients and M is the value ofthe Order parameter.

4. Decimation or interpolation is not supported.



H z( ) 1

1 d1z 1–– d2z 2–

– …– dMz M––

------------------------------------------------------------------------------------=

BlockAllPole 7-9


BlockFIR

Description FIR filter for data blocksLibrary Numeric, Signal ProcessingClass SDFBlockFIRC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



128 int (0, ∞)


16 int (0, ∞)

Decimation decimation ratio 1 int (0, ∞)


Interpolation interpolation ratio 1 int (0, ∞)


1 signalIn real

2 coefs real


3 signalOut real

7-10 BlockFIR

1. BlockFIR implements an FIR filter with coefficients that are periodicallyupdated from the outside. For each set of coefficients, a block of input samples isprocessed, all in one firing.

The BlockSize parameter tells how often updates occur. This integer parameterspecifies how many input samples are to be processed using each set ofcoefficients. The Order parameter tells the number of coefficients.

2. This filter efficiently implements rational sample rate changes. When theDecimation ratio is ≥1 the filter behaves as if it were followed by a DownSamplecomponent; when the Interpolation ratio is set, the filter behaves as if it werepreceded by an UpSample component. However, the implementation is muchmore efficient than it would be using UpSample and DownSample. A polyphasestructure is used internally, avoiding unnecessary use of memory andmultiplication by 0. Arbitrary sample-rate conversions by rational factors canbe accomplished this way.

3. The DecimationPhase parameter is somewhat subtle. It is equivalent to thePhase parameter of the DownSample component. When decimating, samplesare conceptually discarded (although a polyphase structure does not actuallycompute the discarded samples). To decimate by a factor of three, one of everythree outputs is selected. The DecimationPhase parameter determines which ofthese is selected. When DecimationPhase is 0 (default) the most recent samplesare the ones selected.

4. When designing a multirate filter, avoid aliasing. One may assume that thefilter sample rate is the product of the Interpolation parameter and the inputsample rate. Equivalently, one may use the product of the Decimationparameter and the output sample rate.



References

[1]F. J. Harris, “Multirate FIR Filters for Interpolating and Desampling,”Handbook of Digital Signal Processing, Academic Press, 1987.

BlockFIR 7-11


BlockLattice

Description Forward Lattice Filter for Data BlocksLibrary Numeric, Signal ProcessingClass SDFBlockLatticeC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. BlockLattice implements a forward lattice filter with coefficients that areperiodically updated from the outside. For each set of coefficients, a block ofinput samples is processed, all in one firing.



128 int (0, ∞)


16 int (0, ∞)


1 signalIn real

2 coefs real


3 signalOut real

7-12 BlockLattice

The BlockSize parameter tells how often the updates occur. This parameterspecifies how many input samples are to be processed using each set ofcoefficients. The Order parameter tells the number of coefficients.

2. The structure of this filter is shown in Figure 7-2. The reflection (PARCOR)coefficients should be specified left to right, K1 to Kn, as shown.

Figure 7-2. BlockLattice Filter Structure.

3. The definition of reflection coefficients varies in the literature. The reflectioncoefficients in [2] and [3] are the negative of the ones used by BlockLattice,which correspond to the definition in most other texts, and to the definition ofpartial-correlation (PARCOR) coefficients in the statistics literature.

The signs of the coefficients used in BlockLattice are appropriate for valuesgiven by the LevDur and Burg components.

4. See also: BlockRLattice, Lattice, RLattice.


References

[1]J. Makhoul, “Prediction: A Tutorial Review,” Proc. IEEE, Vol. 63, pp. 561-580,Apr. 1975.



X[n] ...

...

Y[n]

Z−1 = unit delays

= adders

Z−1 Z−1 Z−1

−K1

−K1

−Kn

−Kn

BlockLattice 7-13


BlockRLattice

Description Recursive Lattice Filter for Data BlocksLibrary Numeric, Signal ProcessingClass SDFBlockRLatticeC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. BlockRLattice implements a block recursive lattice filter with coefficients thatare periodically updated from the outside. For each set of coefficients, a block ofinput samples is processed, all in one firing.



128 int (0, ∞)


16 int (0, ∞)


1 signalIn real

2 coefs real


3 signalOut real

7-14 BlockRLattice

The BlockSize parameter tells how often the updates occur. This parameterspecifies how many input samples are to be processed using each set ofcoefficients. The Order parameter tells the number of coefficients.

2. The filter structure is shown in Figure 7-3. The reflection (or PARCOR)coefficients should be entered from K1 to Kn, where K1 through Kn are specifiedas shown.

Figure 7-3. BlockRLattice Filter Structure

3. The definition of reflection coefficients varies in the literature. The reflectioncoefficients in [2] and [3] are the negative of the ones used by BlockRLattice,which correspond to the definition in most other texts, and to the definition ofpartial-correlation (PARCOR) coefficients in the statistics literature.

The signs of the coefficients used in BlockRLattice are appropriate for valuesgiven by the LevDur and Burg components.

4. See also: BlockLattice, Lattice, RLattice.


References




X[n] ...

...

Y[n]+Kn +Kn-1 +K1

−Kn −Kn-1 −K1

Z−1

Z−1 Z−1 Z−1

= unit delays

= adders

BlockRLattice 7-15


Burg

Description Linear predictor coefficients estimatorLibrary Numeric, Signal ProcessingClass SDFBurgC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Burg uses Burg’s algorithm to estimate the linear predictor coefficients of aninput random process. The number of inputs looked at is given by theNumInputs parameter and the order of the autoregressive (AR) model is given


Order order of the regression(also number ofcoefficients to generate)

8 int (0, ∞)

NumInputs number of inputs used togenerate each set ofcoefficients

64 int (0, ∞)


1 input Input random process. real


2 lp AR coefficients output. real

3 refl Lattice predictor coefficients output. real

4 errPower Prediction error power. real

7-16 Burg

by the Order parameter. Order specifies how many outputs appear on the lp andrefl output portholes.

These outputs are, respectively, the autoregressive (AR) parameters (also calledthe linear predictor parameters), and the reflection coefficients. Theautoregressive (AR) coefficients are the estimated coefficients of the all-polefilter that could have produced the observations (input data) given a white noiseinput.

2. The definition of reflection coefficients varies in the literature. The reflectioncoefficients in [2] and [3] are the negative of the ones generated by Burg, whichcorrespond to the definition in most other texts, and to the definition ofpartial-correlation (PARCOR) coefficients in the statistics literature.

3. The errPower output is the power of the prediction error as a function of themodel order. There are Order+1 output samples, and the first samplecorresponds to the prediction error of a 0th order predictor. This is simply anestimate of the input signal power.

4. See also: BlockAllPole, BlockLattice, BlockRLattice, LevDur.


References

[1]J. Makhoul, “Linear Prediction: A Tutorial Review”, Proc. IEEE, Vol. 63, pp.561-580, Apr. 1975.



Burg 7-17


Convolve

Description Causal ConvolutionLibrary Numeric, Signal ProcessingClass SDFConvolveC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Convolve convolves two causal finite sequences. Set TruncationDepth largerthan the number of output samples of interest; if it is smaller, you will getunexpected results after TruncationDepth samples.

2. If one input has finite length and does not change over time, whereas the otherinput can be arbitrarily long, use the FIR component. Set the Taps parameter ofthe FIR component to the values of the finite length sequence. For example, if


TruncationDepth maximum number of termsin convolution sum

256 int (0, ∞)


1 inA real

2 inB real


3 out real

7-18 Convolve

the finite length sequence is 1.5, 3.1, 2.8, 1.2, -1.9, 0.4, set Taps to "1.5 3.1 2.81.2 -1.9 0.4".

If one input has finite length and changes over time, whereas the other inputcan be arbitrarily long, use the BlockFIR component. BlockFIR allows filteringof a signal in fixed size blocks where each input block is filtered with a differentset of coefficients.

3. See also: ConvolCx.


References


Convolve 7-19


ConvolCx

Description Complex causal convolutionLibrary Numeric, Signal ProcessingClass SDFConvolCxC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. ConvolCx convolves two complex causal finite sequences. Set TruncationDepthlarger than the number of output samples of interest; if it is smaller, you willget unexpected results after TruncationDepth samples.

2. If one input has finite length and does not change over time, whereas the otherinput can be arbitrarily long, use the FIR_Cx component. Set the Tapsparameter of the FIR_Cx component to the values of the finite length sequence.


TruncationDepth maximum number of termsin convolution sum

256 int (0, ∞)


1 inA complex

2 inB complex


3 out complex

7-20 ConvolCx

For example, if the finite length sequence is (1.5,3.1), (2.8,1.2), (-1.9,0.4), setTaps to "(1.5,3.1) (2.8,1.2) (-1.9,0.4)".

3. See also: Convolve.


ConvolCx 7-21


CrossCorr

Description Cross-correlationLibrary Numeric, Signal ProcessingClass SDFCrossCorrDerived From AutocorC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. CrossCorr estimates the cross-correlation function of its two inputs. Every timethe component fires it reads N samples from each of its two inputs.


NoInputsToAvg number of input samples toaverage

256 N int (NoLags, ∞)

NoLags number of lags to output 64 L int (0, ∞)

Unbiased autocorrelation estimatebias: NO, YES

YES enum



2 input2 second input signal real



4 delay delay of input2 with respect to input1 int

7-22 CrossCorr

The number of values written on the output pin is 2*L. These values representthe values of the cross-correlation function

,

evaluated for k = -L+1, ..., L

( is output first and is output last).

One sample per firing is written on delay pin 4; it represents the estimateddelay of the second input signal with respect to the first input signal (negativevalues mean that the signal at pin 1 is delayed with respect to the signal at pin2).

2. Both unbiased and biased estimates are supported.

• If Unbiased=YES, the autocorrelation estimate is

• If Unbiased=NO, the cross-correlation estimate is

This estimate is biased because the outermost lags have fewer than N termsin the summation, and yet the summation is still normalized by N.

rxyˆ k( )

rxyˆ L– 1+( ) rxy

ˆ L( )

rxy k( )ˆ

1N k–----------------- x n( ) y n k+( ) 0 k L≤ ≤,⋅

n 0=

N 1– k–

∑

1N k–----------------- y n( ) x n k+( ) -L k 0< <,⋅

n 0=

N 1– k–

∑0 otherwise,

=

rxy k( )ˆ

1N----- x n( ) y n k+( ) 0 k L≤ ≤,⋅

n 0=

N 1– k–

∑

1N----- y n( ) x n k+( ) -L k 0< <,⋅

n 0=

N 1– k–

∑0 otherwise,

=

CrossCorr 7-23



References

[1]A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing,Prentice-Hall: Englewood Cliffs, NJ, 1989

7-24 CrossCorr

DTFT

Description Discrete-time Fourier transformLibrary Numeric, Signal ProcessingClass SDFDTFT

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1.DTFT calculates the discrete-time Fourier transform (DTFT) of the sequenceapplied at its signal input at each of the frequency points specified on the omegainput. Every time the component fires it reads L samples from its signal inputand N samples from its omega input and writes N samples to its output.

2. The DTFT of a sequence x[n] is a continuous function of ω defined by


Length length of input signal 8 L int (0, ∞)

NumberOfSamples number of transformsamples to output

128 N int (0, ∞)

TimeBetweenSamples time between inputsamples (T)

1.0 T real (0, ∞)


1 signal Signal to be transformed. complex

2 omega Frequency values at which to sample the transform. real


3 dtft The samples of the transform. complex

DTFT 7-25


If sequence x[n] is obtained by sampling a continuous time signal xc(t) atintervals of Ts, that is x[n] = xc(nTs), and if Xc(f), the continuous-time Fouriertransform of xc(t), equals 0 for f > 1/(2T), then X(jω) and Xc(f) have the followingrelationship:

, for f < 1 / (2T).

3. The DTFT component can calculate X(jω) at arbitrary values of ω for sequencesx[n] of finite length. Let the L values on the signal input be x[0], x[1], ... , x[L-1]and the N values on the omega input be ω[0], ω[1], ... , ω[Ν−1]. Then the N valuesat the output are:

, i = 0, 1, ... , N - 1.

where T is the time between samples (TimeBetweenSamples). Notice that inthis last formula the exponent of e has the extra term T compared to theformula defining the DTFT. Therefore, to calculate the Fourier transform of thecorresponding continuous time signal xc(t) at the frequencies fi, i = 0, 1, ... , N,generate the values ωi = 2πfi and apply them at the omega input. And, scale theoutput by T. The values fi do not need to span the entire frequency range of thesignal or be equally spaced.

4. To access the example that shows how this component is used: from the Mainwindow, choose File > Example Project > PtolemyDocExamples >Numeric_Signal_Processing_prj; from the Schematic window, choose File >Open Design, DTFT_example.dsn.


References


X jω( ) x n[ ] e jωn–×n ∞–=

∞

∑=

Xc f( ) T X j 2πfT×( )× T x n[ ] e j2πfTn–×n ∞–=

∞

∑×= =

X jω i[ ]( ) x n[ ]e jω i[ ]nT–

n 0=

L 1–

∑=

7-26 DTFT

FFT_Cx

Description Complex fast Fourier transformLibrary Numeric, Signal ProcessingClass SDFFFT_CxC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. FFT algorithms are based on the fundamental principle of decomposing thecomputation of the discrete Fourier transform of a sequence of length N intosuccessively smaller DFT. Many different algorithms are generated based onthe decomposing principle, all with comparable improvements in computationalspeed.


Order base 2 of the transformsize

8 int [0, ∞)

Size number of input samples toread

256 int[1, 2Order ]

Direction direction of transform:Inverse, Forward

Forward enum


1 input complex


2 output complex

FFT_Cx 7-27


2. FFT_Cx computes the DFT of a complex input using the fast Fourier transform(FFT) algorithm. FFT_Cx reads Size (default 256) complex samples, zero padsthe data if necessary, then takes an FFT of length 2Order where Size ≤ 2Order.

The default value of Order is 8. Direction specifies a forward or inverse FFT. Asingle firing of FFT_Cx consumes Size inputs and produces 2Order outputs.

3. See also: DTFT.


References


7-28 FFT_Cx

FIR

Description FIR filterLibrary Numeric, Signal ProcessingClass SDFFIRC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. FIR implements a finite-impulse response filter with multirate capability. Thedefault tap coefficients correspond to an eighth-order, equiripple, linear-phase,


Taps filter tap values -.040609-.001628 .17853.37665 .37665.17853 -.001628-.040609

real array



Interpolation interpolation ratio 1 int [1, ∞)


1 signalIn real


2 signalOut real

FIR 7-29


lowpass filter. The cutoff frequency is approximately one-third of the Nyquistfrequency.

2. The filter coefficients are specified by the Taps parameter. The filter coefficientsmay be specified directly or they may be read from a file. To load filtercoefficients from a file, replace the default coefficients with the string <filename,for example, "</filters/f1.txt", (use an absolute path name for the filename toallow the FIR filter to work as expected regardless of the directory where thesimulation process actually runs). For details on using arrays of data forparameter values, refer to “Understanding Parameters” in the ADS PtolemySimulation manual

3. This filter efficiently implements rational sample rate changes. When theDecimation ratio is ≥1, the filter behaves exactly as if it were followed by aDownSample component; similarly, when the Interpolation ratio is set, the filterbehaves as if it were preceded by an UpSample component. However, theimplementation is much more efficient than it would be using UpSample andDownSample. A polyphase structure is used internally, avoiding unnecessaryuse of memory and unnecessary multiplication by 0. Arbitrary sample-rateconversions by rational factors can be accomplished this way.

4. The DecimationPhase parameter is somewhat subtle. It is equivalent to thePhase parameter of the DownSample component. When decimating, samplesare conceptually discarded (although a polyphase structure does not actuallycompute the discarded samples). For example, to decimate by a factor of 3, oneof every 3 outputs is selected. The DecimationPhase parameter determineswhich of these is selected. If DecimationPhase is 0 (default), the most recentsamples are selected.

5. When designing a multirate filter, avoid accidentally introducing aliasing. Onemay assume that the filter sample rate is the product of the Interpolationparameter and the input sample rate. Equivalently, one may use the product ofthe Decimation parameter and the output sample rate.

6. See also: FIR_Cx, FIR_Fix.


References


7-30 FIR

[2] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing,Prentice-Hall: Englewood Cliffs, NJ, 1989.

[3] P. P. Vaidyanathan, “Multirate Digital Filters, Filter Banks, PolyphaseNetworks, and Applications: A Tutorial,” Proc. of the IEEE, vol. 78, no. 1, pp.56-93, Jan. 1990.

FIR 7-31


FIR_Cx

Description Complex FIR filterLibrary Numeric, Signal ProcessingClass SDFFIR_CxC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations


Taps filter tap values (-.040609,0.0)(-.001628,0.0)(.17853,0.0)(.37665,0.0)(.37665,0.0)(.17853,0.0)(-.001628,0.0)(-.040609,0.0)

complexarray





1 signalIn complex


2 signalOut complex

7-32 FIR_Cx

1. The FIR_Cx component implements a complex-valued finite-impulse responsefilter with multirate capability. The default tap coefficients correspond to aneighth-order, equiripple, linear-phase, lowpass filter. The cutoff frequency isapproximately one-third of the Nyquist frequency.

2. The filter coefficients are specified by the Taps parameter. The real andimaginary parts should be enclosed in parenthesis, for example (0.1,0.3). Thefilter coefficients may be specified directly or they may be read from a file. Toload filter coefficients from a file, replace the default coefficients with the string<filename, for example, "</filters/f1.txt", (use an absolute path name for thefilename to allow the FIR filter to work as expected regardless of the directorywhere the simulation process actually runs).



4. This filter efficiently implements rational sample rate changes. When theDecimation ratio is ≥1, the filter behaves exactly as if it were followed by aDownSample component; similarly, when the Interpolation ratio is set, the filterbehaves as if it were preceded by an UpSample component. However, theimplementation is much more efficient than it would be using UpSample andDownSample. A polyphase structure is used internally, avoiding unnecessaryuse of memory and unnecessary multiplication by 0. Arbitrary sample-rateconversions by rational factors can be accomplished this way.



7. See also: FIR, FIR_Fix.

FIR_Cx 7-33



References


7-34 FIR_Cx

FIR_Fix

Description Fixed-Point FIR FilterLibrary Numeric, Signal ProcessingClass SDFFIR_FixDerived From SDFFixC++ Code

Parameters



wrapped enum


REPORT enum


TRUNCATE enum


fix array





NO enum

InputPrecision precision of input signal, inbits (used only ifUseArrivingPrecision is setto NO)

2.14 precision

FIR_Fix 7-35


Pin Inputs

Pin Outputs

Notes/Equations

1. FIR implements a finite-impulse response filter with fixed-point capability. Thedefault tap coefficients correspond to an eighth-order, equiripple, linear-phase,lowpass filter. The cutoff frequency is approximately one-third of the Nyquistfrequency.

2. The filter coefficients are specified by the Taps parameter. During filter outputcomputation, the precision of the filter taps is converted according to theTapPrecision parameter. The filter coefficients may be specified directly or theymay be read from a file. To load filter coefficients from a file, replace the defaultcoefficients with the string <filename, for example, "</filters/f1.txt", (use anabsolute path name for the filename to allow the FIR filter to work as expectedregardless of the directory where the simulation process actually runs). Fordetails on using arrays of data for parameter values, refer to “UnderstandingParameters” in the ADS Ptolemy Simulation manual.

3. This filter efficiently implements rational sample rate changes. When theDecimation ratio is ≥1, the filter behaves exactly as if it were followed by aDownSample component; similarly, when the Interpolation ratio is set, the filterbehaves as if it were preceded by an UpSample component. However, theimplementation is much more efficient than it would be using UpSample andDownSample. A polyphase structure is used internally, avoiding unnecessary

TapPrecision precision of tap values, inbits

2.14 precision

AccumulationPrecision precision of accumulation,in bits

2.14 precision


2.14 precision


1 signalIn fix


2 signalOut fix


7-36 FIR_Fix

use of memory and unnecessary multiplication by 0. Arbitrary sample-rateconversions by rational factors can be accomplished this way.



6. If the fixed-point operations cannot fit into the precision specified, overflowoccurs with the overflow characteristic specified by OverflowHandler. IfReportOverflow=REPORT, after the simulation has finished the number ofoverflow errors (if any) will be reported. RoundFix identifies whetherfixed-point computations are truncate or round method. IfUseArrivingPrecision=NO, the input is cast to the precision specified byInputPrecision. TapPrecision indicates how many bits are used to represent thefilter taps.



8. See also: FIR, FIR_Cx, DownSample, UpSample.


References


FIR_Fix 7-37


[2] P. P. Vaidyanathan, “Multirate Digital Filters, Filter Banks, PolyphaseNetworks, and Applications: A Tutorial,” Proc. of the IEEE, vol. 78, no. 1, pp.56-93, Jan. 1990.

7-38 FIR_Fix

Hilbert

Description Hilbert transformLibrary Numeric, Signal ProcessingClass SDFHilbertDerived From FIRC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component approximates the Hilbert transform of the input signal byusing an FIR filter. The response is truncated symmetrically at −N/2 and N/2[1], which is accurate enough for some applications. For high accuracy it may be





N number of taps in theHilbert filter

64 int [1, ∞)


1 signalIn real


2 signalOut real

Hilbert 7-39


necessary to use the Parks- McClellan algorithm [2] to design a custom Hilberttransformer filter [1,3].

2. The Hilbert transform requires an infinite length set of FIR tap coefficients foraccurate representation. This model approximates the Hilbert transform with afinite list of FIR taps. For practical accuracy, it is recommended N≥64.

3. See also: FIR.


References


[2] T. W. Parks and J. H. McClellan, “Chebyshev Approximation for NonrecursiveDigital Filters With Linear Phase,” IEEE Trans. on Circuit Theory, vol. 19, no.2, pp. 189-194, March 1972.

[3] L. R. Rabiner, J. H. McClellan, and T. W. Parks, “FIR Digital Filter DesignTechniques Using Weighted Chebyshev Approximation,” Proc. of the IEEE, vol.63, no. 4, pp. 595-610, April 1975.

7-40 Hilbert

IIR

Description IIR FilterLibrary Numeric, Signal ProcessingClass SDFIIRC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. IIR implements an infinite impulse response filter of arbitrary order in a directform II as shown in Figure 7-4.

2. The parameters specify H(z), the Z-transform of an impulse response h(n). Theoutput of IIR is the convolution of the input with h(n).

The transfer function is of the form


Gain gain 1 real (-∞, ∞)

Numerator numerator coefficients .5 .25 .1 real array

Denominator denominator coefficients 1 .5 .3 real array


1 signalIn real


2 signalOut real

IIR 7-41


where

Gain specifies GNumerator and Denominator specify N(z-1) and D(z-1), respectively.

Both arrays start with the constant terms of the polynomial and decrease inpowers of z (increase in powers of 1/z). (The constant term of D is not omitted,as is common in other programs that assume it has been normalized to unity.)

Figure 7-4. IIR Filter Structure

3. The Numerator and Denominator array values may be specified directly or theymay be read from a file. To load array values for a file, replace the default valueswith the string <filename, for example, "</filters/f1.txt", (use an absolute pathname for the filename to allow obtain expected results regardless of thedirectory where the simulation process actually runs). For details on usingarrays of data for parameter values, refer to “Understanding Parameters” in theADS Ptolemy Simulation manual.

4. The numerical finite precision noise increases with the filter order. To minimizethis distortion, expand the filter into a parallel or cascade form.

5. See also: Biquad, IIR_Cx, IIR_Fix.


References

H z( ) GN z 1–( )

D z 1–( )-------------------=

X[n] Y[n]

D1

Z−1

Z−1

Z−1

DN-1

DN

N1

NN-1

NN

N0

7-42 IIR


IIR 7-43


IIR_Cx

Description Complex IIR FilterLibrary Numeric, Signal ProcessingClass SDFIIR_Cx

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. IIR_Cx implements a complex infinite impulse response (IIR) filter of arbitraryorder in a direct form II realization.




Gain gain 1.0 complex

Numerator numerator coefficients (0.5, 0) (0.25, 0)(0.1, 0)

complexarray

Denominator denominator coefficients (1.0, 0) (0.5, 0)(0.3, 0)

complexarray


1 signalIn complex


2 signalOut complex

7-44 IIR_Cx

3. The parameters specify H(z), the Z-transform of an impulse response h(n). Theoutput is the convolution of the input with h(n). The transfer function is of theform

where

Gain specifies GNumerator and Denominator specify N(z-1) and D(z-1), respectively.

Both arrays start with the constant terms of the polynomial and decrease inpowers of z (increase in powers of 1/z). (The constant term of D is not omitted,as is common in other programs that assume it has been normalized to unity.)

4. The Numerator and Denominator array values may be specified directly or theymay be read from a file. To load array values for a file, replace the default valueswith the string <filename, for example, "</filters/f1.txt", (use an absolute pathname for the filename to allow obtain expected results regardless of thedirectory where the simulation process actually runs).

For details on using arrays of data for parameter values, refer to“Understanding Parameters” in the ADS Ptolemy Simulation manual.

5. The numerical finite precision noise increases with the filter order. To minimizethis distortion, it is often desirable to expand the filter into a parallel or cascadeform.

6. See also: Biquad. IIR, IIR_Fix.


References


H z( ) GN z 1–( )

D z 1–( )-------------------=

IIR_Cx 7-45


IIR_Fix

Description Fixed IIR FilterLibrary Numeric, Signal ProcessingClass SDFIIR_FixDerived From SDFFixC++ Code

Parameters



wrapped enum


REPORT enum


TRUNCATE enum

Gain gain 1 real (-∞, ∞)

Numerator numerator coefficients .5 .25 .1 real array

Denominator denominator coefficients 1 .5 .3 real array

CoefPrecision precision of coefficients 2.14 precision


NO enum

InputPrecision precision of input signal, inbits (used only ifUseArrivingPrecision is setto NO)

2.14 precision

AccumPrecision precision of state, in bits 2.14 precision

StatePrecision precision of state, in bits 2.14 precision


2.14 precision

7-46 IIR_Fix

Pin Inputs

Pin Outputs

Notes/Equations

1. IIR_Fix implements an infinite impulse response filter in a direct form IIrealization using fixed point arithmetic.

The transfer function is of the form

where

N() and D() are polynomialsGain specifies GNumerator and Denominator specify N() and D(), respectively.

Both arrays start with the constant terms of the polynomial and decrease inpowers of z (increase in powers of 1/z). The coefficients are rounded to theprecision given by CoefPrecision. (The constant term of D is not omitted, as iscommon in other programs that assume that it has been normalized to unity.Also, before the numerator and denominator coefficients are quantized, they arerescaled so that the leading denominator coefficient is unity. The gain ismultiplied through the numerator coefficients as well.)

2. The numerical finite precision noise increases with the filter order. To minimizethis distortion, expand the filter into a parallel or cascade form.

3. Quantization is performed in several places. First, the coefficients arequantized (rounded) to CoefPrecision. This is done after the coefficients havebeen rescaled to make the initial denominator coefficient unity. The input isoptionally quantized (rounded) to precision specified by InputPrecision. Themultiplication of the state by the coefficients preserves full precision, but the


1 signalIn fix


2 signalOut fix

H z( ) GN z 1–( )

D z 1–( )-------------------=

IIR_Fix 7-47


result is quantized to AccumPrecision after being added to other products. Thestate variables are stored with the precision given by StatePrecision. Beforebeing sent out, the output values are quantized (rounded) to OutputPrecision.

4. The Numerator and Denominator array values may be specified directly or theymay be read from a file. To load array values for a file, replace the default valueswith the string <filename, for example, "</filters/f1.txt", (use an absolute pathname for the filename to allow obtain expected results regardless of thedirectory where the simulation process actually runs).


5. If the fixed-point operations cannot fit into the precision specified, overflowoccurs with the overflow characteristic specified by OverflowHandler. IfReportOverflow=REPORT, after the simulation has finished the number ofoverflow errors (if any) will be reported. RoundFix identifies whetherfixed-point computations are truncate or round method. IfUseArrivingPrecision=NO, the input is cast to the precision specified byInputPrecision. TapPrecision indicates how many bits are used to represent thefilter taps.



7. See also: Biquad, IIR, IIR_Cx.


References


7-48 IIR_Fix

Lattice

Description Lattice FilterLibrary Numeric, Signal ProcessingClass SDFLatticeC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Lattice implements a Lattice filter. The structure of this filter is shown inFigure 7-5. The reflection (PARCOR) coefficients should be specified left toright, K1 to Kn, as shown.

Using the same coefficients in the RLattice component will result in the inversetransfer function.

2. The default reflection coefficients correspond to the optimal linear predictor foran AR process generated by filtering white noise with the following filter:


ReflectionCoefs reflection or PARCORcoefficients

0.804534-0.8205770.521934 -0.205

real array


1 signalIn real


2 signalOut real

Lattice 7-49


Because this filter is minimum phase, the transfer function of the lattice filter isH-1(z) .

Figure 7-5. Lattice Filter Structure

3. To read other reflection coefficients from a file, replace the default coefficientswith <filename>. Use the full path of the filename so that the simulation willwork correctly without regard to the directory from which it runs. For details onusing arrays of data for parameter values, refer to “Understanding Parameters”in the ADS Ptolemy Simulation manual.

4. The definition of reflection coefficients varies in the literature. The reflectioncoefficients in [2] and [3] are the negative of the ones used by Lattice, whichcorrespond to the definition in most other texts, and to the definition ofpartial-correlation (PARCOR) coefficients in the statistics literature.

The signs of the coefficients used in Lattice are appropriate for values given bythe LevDur and Burg components.

5. See also: BlockLattice, BlockRLattice, RLattice.


References

[1]J. Makhoul, “Prediction: A Tutorial Review,” Proc. IEEE, Vol. 63, pp. 561-580,Apr. 1975.

H z( ) 1

1 2z 1–– 1.91z 2–

0.91z 3–– 0.205z 4–

+ +----------------------------------------------------------------------------------------------------=

X[n] ...

...

Y[n]

−Kn

Z−1 = unit delays

= adders

Z−1 Z−1 Z−1

−Kn

−K1

−K1

7-50 Lattice



Lattice 7-51


LevDur

Description FIR and lattice linear predictor coefficientsLibrary Numeric, Signal ProcessingClass SDFLevDurC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. LevDur takes as inputs an autocorrelation function, or estimates produced bythe Autocor component, and uses the Levinson-Durbin algorithm to computeboth reflection coefficients and FIR linear predictor coefficients.

2. If the Autocor component is set so that its Unbiased parameter is 0, then thecombined effect of Autocor and LevDur is called the autocorrelation algorithm.Order should be the same as the Autocor NoLags parameter.


Order order of recursion 8 int (0, ∞)


1 autocor Autocorrelation estimate real


2 lp FIR linear predictor coefficients output. real

3 refl Lattice predictor coefficients output. real

4 errPower Prediction error power. real

7-52 LevDur

3. On the errPower output, a sequence of Order+1 samples gives the predictionerror power for each predictor order from 0 to Order. The first sample, whichcorresponds to the 0th-order predictor, is an estimate of the power of the inputprocess. (For signals without noise, the errPower output can sometimes end upbeing a small negative number.)

4. The lp output gives the coefficients of an FIR filter that performs linearprediction for the input process. This set of coefficients is suitable for directlyfeeding the BlockFIR filter component. The number of coefficients produced isequal to Order.

5. The refl output is the reflection coefficients, suitable for feeding directly to theBlockLattice component, which will then generate the forward and backwardprediction error. The number of coefficients produced is equal to Order.

6. The definition of reflection coefficients varies in the literature. The reflectioncoefficients in [2] and [3] are the negative of the ones generated by LevDur,which correspond to the definition in most other texts, and to the definition ofpartial-correlation (PARCOR) coefficients in the statistics literature.

7. See also: Autocor, BlockFIR, BlockLattice.


References

[1]J. Makhoul, “Linear Prediction: A Tutorial Review,” Proc. IEEE, vol. 63, pp.561-580, Apr. 1975.



LevDur 7-53


LMS

Description LMS adaptive filterLibrary Numeric, Signal ProcessingClass SDFLMSDerived From FIRC++ Code

Parameters

Pin Inputs

Pin Outputs



real array



StepSize adaptation step size 0.01 real (0, ∞)

ErrorDelay update loop delay 1 int [1, ∞)

SaveTapsFile filename in which to savefinal tap values

string


1 signalIn real

2 error real


3 signalOut real

7-54 LMS

Notes/Equations

1. LMS is an adaptive filter using the least-mean square algorithm. The initialfilter coefficients are given by the Taps parameter. The default initialcoefficients give an 8th-order, linear phase lowpass filter. To read initialcoefficients from a file, replace the default coefficients with <filename>,preferably specifying a complete path. For details on using arrays of data forparameter values, refer to “Understanding Parameters” in the ADS PtolemySimulation manual.

LMS supports decimation, but not interpolation.

2. When used correctly, this LMS adaptive filter will adapt to try to minimize themean-squared error of the signal at its error input [1]. The output of the filtershould be compared to (subtracted from) some reference signal to produce anerror signal. That error signal should be fed back to the error input. TheErrorDelay parameter must equal the total number of delays in the path fromthe output of the filter back to the error input. This ensures correct alignment ofthe adaptation algorithm. The number of delays must be greater than 0 or thesimulation will deadlock.

The adaptation algorithm is the well-known LMS, or stochastic-gradient,algorithm.

3. If the SaveTapsFile string is non-null, a file will be created with the name givenby that string, and the final tap values will be stored there after the run hascompleted.

4. See also: LMS_Cx, LMS_Leak, LMS_OscDet.


References

[1]S. Haykin, Adaptive Filter Theory, Prentice Hall: Englewood Cliffs, NJ. 1991.2nd ed.

LMS 7-55


LMS_Cx

Description Complex LMS adaptive filterLibrary Numeric, Signal ProcessingClass SDFLMS_CxDerived From FIR_CxC++ Code

Parameters

Pin Inputs


Taps filter tap values (-.040609,0.0)(-.001628,0.0)(.17853,0.0)(.37665,0.0)(.37665,0.0)(.17853,0.0)(-.001628,0.0)(-.040609,0.0)

complexarray






string


1 signalIn complex

2 error complex

7-56 LMS_Cx

Pin Outputs

Notes/Equations

1. LMS_Cx implements an adaptive filter using the least-mean square algorithm.The initial filter coefficients are given by the Taps parameter. The default initialcoefficients give an 8th-order, linear phase lowpass filter. To read initialcoefficients from a file, replace the default coefficients with <filename>,preferably specifying a complete path. For details on using arrays of data forparameter values, refer to “Understanding Parameters” in the ADS PtolemySimulation manual.

LMS_Cx supports decimation, but not interpolation.



3. When used correctly, this LMS adaptive filter will adapt to try to minimize themean-squared error of the signal at its error input [1]. The output of the filtershould be compared (subtracted from) some reference signal to produce an errorsignal. That error signal should be fed back to the error input. The ErrorDelayparameter must equal the total number of delays in the path from the output ofthe filter back to the error input. This ensures correct alignment of theadaptation algorithm. The number of delays must be greater than 0 or thesimulation will deadlock.

The adaptation algorithm is the well-known LMS, or stochastic-gradientalgorithm.

4. If the SaveTapsFile string is non-null, a file will be created with the name givenby that string, and the final tap values will be stored there after the run hascompleted.

5. See also: LMS, LMS_Leak, LMS_OscDet.



3 signalOut complex

LMS_Cx 7-57


References

[1]S. Haykin, Adaptive Filter Theory, Prentice Hall: Englewood Cliffs, NJ. 1991.2nd ed.

7-58 LMS_Cx

LMS_Leak

Description LMS Adaptive Filter with Input Step SizeLibrary Numeric, Signal ProcessingClass SDFLMS_LeakDerived From LMSC++ Code

Parameters

Pin Inputs



real array





string

Mu coefficient update leakfactor

0.0 real (-∞, ∞)


1 signalIn real

2 error real

3 step Step-size for LMS algorithm. real

LMS_Leak 7-59


Pin Outputs

Notes/Equations

1. LMS_Leak is an LMS adaptive filter in which the step size is input (to the stepinput) every iteration. In addition, the Mu parameter specifies a leakage factorin the updates of the filter coefficients.

2. If two identical LMS_Leak filters are used as an adaptive predictive coder anddecoder then, with Mu nearly equal to but greater than 0.0, the effects ofchannel errors between the coder and decoder will decay rather thanaccumulate. As Mu increases, the effects of channel errors decay more quickly,but the size of the error input increases also. See page 54 of [1].

3. ErrorDelay must equal the total number of delays in the path from the outputof the filter back to the error input. This ensures correct alignment of theadaptation algorithm. The number of delays must be >0 or the simulation willdeadlock.

4. If the SaveTapeFile string is non-null, a file will be created with the name givenby that string, and the final tape values will be stored there after the run hascompleted.

5. See also: LMS, LMS_Cx, LMS_OscDet.


References

[1]W. Honig and D. G. Messerschmitt, Adaptive Filters, Kluwer AcademicPublishers, Norwood MA, 1985.


4 signalOut real

7-60 LMS_Leak

LMS_OscDet

Description LMS adaptive filter with sinusoid detectionLibrary Numeric, Signal ProcessingClass SDFLMS_OscDetDerived From LMSC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations





string

InitialOmega initial estimated angle, inradians

pi/4 real (-∞, ∞)


1 signalIn real

2 error real


3 signalOut real

4 cosOmega Current estimated value of the cosine of thefrequency of the dominatesinusoidal component of the input signal.

real

LMS_OscDet 7-61


1. LMS_OscDet tries to lock onto the strongest sinusoidal component in the inputsignal, and outputs the current estimate of the cosine of the frequency of thestrongest component. LMS_OscDet is a 3-tap least-mean square filter whosefirst and third coefficients are fixed while the second coefficient is adapted. It isa normalized version of the Direct Adaptive Frequency Estimation Technique.

2. The initial taps of this LMS filter are 0.5, −1, 0.5. The second tap is adaptedwhile the others are held fixed. The second tap is equal to -a1; its adaptationhas the form

where

and y[n] is the output of this filter, which can be used as the error signal.

The step size term µ is fixed by the value of the StepSize parameter. You caneffectively vary the step size by attenuating the error term as

assuming that k = 1, 2, 3, and so forth. When the error becomes relatively small,this filter gives an estimate of the strongest sinusoidal component:

The taps here are scaled by one-half from those of other implementations;therefore, the output of the filter is also scaled by one-half. To compensate forthis scaling µ is multiplied by 2 relative to other implementations with fullscale taps.

3. LMS_OscDet outputs the current value of a1 on the cosOmega output port. Theinitial value is a1=1 (0 frequency) so the initial value of the second tap is −1.

4. ErrorDelay must equal the total number of delays in the path from the outputof the filter back to the error input. This ensures correct alignment of theadaptation algorithm. The number of delays must be >0 or the simulation willdeadlock.

y n[ ] 12---x n[ ] a1 k[ ]x n 1–[ ]–

12---x n 2–[ ]+=

a1 k[ ] a1 k 1–[ ] 4µe n[ ]x n 1–[ ]+=

e n[ ] y n[ ]k

------------=

a1 ω( )cos=

7-62 LMS_OscDet

5. If the SaveTapeFile string is non-null, a file will be created with the name givenby that string, and the final tape values will be stored there after the run hascompleted.

6. See also: LMS, LMS_Cx, and LMS_Leak.


LMS_OscDet 7-63


PattMatch

Description Cross-correlation with template inputLibrary Numeric, Signal ProcessingClass SDFPattMatchC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. PattMatch accepts a template and a search window and tries to find theposition in the search window where the template matches best. Every time thecomponent fires, it reads TempSize samples from its templ input and WinSizesamples from its window input. At the same time, it writes one sample to itsindex output and (WinSize - TempSize + 1) samples to its values output.


TempSize number of samples intemplate

32 int (0, ∞)

WinSize number of samples insearch template

176 int [TempSize, ∞)


1 templ template input real

2 window window input real


3 index index output int

4 values cross-correlation output real

7-64 PattMatch

The algorithm for finding the best template match position starts by placing thetemplate at the left end of the window (first samples of template and windoware aligned) and calculating the cross-correlation between them. Then thetemplate is shifted across the window one sample at a time and thecross-correlation is computed at each step until the template reaches the rightend of the window (last samples of template and window are aligned). Thecross-correlation values are output on the values output. The index output isthe value of the shift (in number of samples) that gives the largestcross-correlation.

2. The cross-correlation values are normalized against the energy of the windowunder the template:

where T is the template, W is the window, n is the index value and Tsize equalsTempSize.

Note that if the template is identical to a certain segment of the window, thenthe cross-correlation value C(n) for that segment will be 1.0. Therefore, theindex with the highest cross-correlation value may not be the best match if thatvalue is greater than 1.0.


4. To access the example that shows how this component is used: from the Mainwindow, choose File > Example Project > PtolemyDocExamples >Numeric_Signal_Processing_prj; from the Schematic window, choose File >Open Design, PattMatch_example.dsn.

C n( )

T m( )W m n+( )m 0=

Tsize 1–

∑

W m n+( )W m n+( )m 0=

Tsize 1–

∑------------------------------------------------------------------------=

PattMatch 7-65


RLattice

Description Recursive Lattice FilterLibrary Numeric, Signal ProcessingClass SDFRLatticeC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. RLattice implements a recursive lattice filter (also referred to as the Latticeinverse filter). The structure of this filter is:


ReflectionCoefs reflection or PARCORcoefficients

0.804534-0.8205770.521934 -0.205

real array


1 signalIn real


2 signalOut real

7-66 RLattice

where Z-1 are unit delays and + are adders. The reflection (or PARCOR)coefficients should be entered from K1 to Kn, left to right, where K1 through Knare specified as above.

2. Using the same coefficients in the Lattice component will result in the inversetransfer function.

3. The default reflection coefficients correspond to the optimal linear predictor foran AR process generated by filtering white noise with the following filter:

4. To read other reflection coefficients from a file, replace the default coefficientswith <filename>. Use the full path of the filename so that the simulation willwork correctly without regard to the directory from which it runs. For details onusing arrays of data for parameter values, refer to “Understanding Parameters”in the ADS Ptolemy Simulation manual.

5. The definition of reflection coefficients varies in the literature. The reflectioncoefficients in [2] and [3] are the negative of the ones used by RLattice, whichcorrespond to the definition in most other texts, and to the definition ofpartial-correlation (PARCOR) coefficients in the statistics literature.

The signs of the coefficients used in RLattice are appropriate for values given bythe LevDur and Burg components.

6. See also: BlockLattice, BlockRLattice, IIR, Lattice.


X[n] ...

...

Y[n]

−K1

Z−1 = unit delays

= adders

Z−1 Z−1Z−1

+K1

−Kn-1

+Kn-1

−Kn

+Kn

H z( ) 1

1 2z 1–– 1.91z 2–

0.91z 3–– 0.205z 4–

+ +----------------------------------------------------------------------------------------------------=

RLattice 7-67


References




7-68 RLattice

SlidWinAvg

Description Sliding-Window AverageLibrary Numeric, Signal ProcessingClass SDFSlidWinAvgC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. SlidWinAvg outputs the average of the last WindowSize input values.

For the first (WindowSize -1) output samples for which less than WindowSizeinput samples are available, the missing values are assumed to be 0.

This component is equivalent to an FIR filter with WidowSize taps all equal to1/WindowSize.


WindowSize size of sliding window 3 int (1, ∞)





SlidWinAvg 7-69


7-70 SlidWinAvg

Chapter 8: Numeric Sources

Introduction

The Numeric Sources component library contains scalar and matrix signal sourcesfor floating-point (real), fixed-point, complex and integer data.


Some components operate with fixed-point numbers. These components use one ormore parameters that define the characteristics of the fixed-point processing. Theseparameters include: OverflowHandler, OutputPrecision, RoundFix, ReportOverflow,and others. For details on the use of these parameters for fixed-point components arefer to “Parameters for Fixed-Point Components” in the ADS Ptolemy Simulationmanual. The arithmetic used by these components is two’s complement. Therefore,all precision values must specify at least one bit to the left of the decimal point (usedas sign bit)

Introduction 8-1

Numeric Sources

Bits

Description Binary random bits outputLibrary Numeric, Sources

Parameters

Pin Outputs

Notes/Equations

1. Bits generates random or pseudo-random binary bit sequences.

2. When Type = Random, Bits generates a random output bit sequence for whichthe probability of each bit being 0 is equal to ProbOfZero. If ProbOfZero is set toa value less than 0 it is considered to be equal to 0; if ProbOfZero is set to avalue greater than 1 it is considered to be equal to 1.

(The LFSR_Length and LFSR_InitState parameters are ignored in this mode.)


Type type of bit sequence,random or pseudo random:Random, Prbs

Random enum

ProbOfZero probability of bit valuebeing zero (used whenType=Random)

0.5 real [0, 1]

LFSR_Length Linear Feedback ShiftRegister length (usedwhen Type=Prbs)

12 L int [2, 31]

LFSR_InitState Linear Feedback ShiftRegister initial state (usedwhen Type=Prbs)

1 int[1, 2L -1]


1 output output bit stream int

8-2 Bits

The random bit sequence is generated by making use of the random numbergenerator. Therefore, the bit pattern will be different for each instance of theBits component. In addition, if other components that use the random numbergenerator (for example, Noise, IID_Gaussian, RES with RTemp > -273.15) areadded or removed from a design the output bit sequences from the Bitscomponents will change.

The output bit sequence is also dependent on the value of the DefaultSeedparameter in the data flow controller (DF), which provides the initial seed forthe random number generator.

• When DefaultSeed = 0, the initial seed value is obtained from the systemtime so the output bit sequence generated for each simulation will bedifferent even if nothing else changes on the design.

• When DefaultSeed > 0, the output bit sequence generated for eachsimulation, though statistically random, has the same initial seed startingcondition and therefore results in reproducible simulations.

3. When Type = Prbs, the output bit sequence is pseudo-random and is generatedby using an LFSR (linear feedback shift register).

The LFSR_Length parameter sets the LFSR length that, in turn, defines theperiod of the sequence (2L-1). If LFSR_Length is outside its valid range [2, 31],it is reset to its default value of 12.

The LFSR_InitState parameter sets the initial state of the LFSR. IfLFSR_InitState is outside its valid range [1, 2L-1], it is reset to its default valueof 1. The ProbOfZero parameter is ignored in this mode of operation. Since therandom number generator is not used in this case, the output bit sequence doesnot depend on the DefaultSeed parameter of the DF controller.

Two instances of the Bits source with Type set to Prbs and the same values forthe LFSR_Length and LFSR_InitState parameters will generate the exactsame output no matter what the DefaultSeed value is or if the rest of the designis modified.

To get two or more uncorrelated pseudo-random bit sequences, place two ormore Bits components, set their Type parameters to Prbs, their LFSR_Lengthparameters to the same value, and their LFSR_InitState parameters todifferent values. The maximum number of uncorrelated sequences one cangenerate with LFSRs of length L is 2L-1.

4. See also: LFSR.

Bits 8-3

Numeric Sources

5. For information regarding numeric source signals, refer to the “Introduction” onpage 8-1.

8-4 Bits

ComplexExp

Description Complex exponential sourceLibrary Numeric, SourcesClass SDFComplexExpDerived From SineGen

Parameters

Pin Outputs

Notes/Equations

1. ComplexExp generates the sequence of numbers given bycos(ω × n + φ) + j × sin(ω × n + φ), n = 0, 1, ... ,where ω equals RadiansPerSample and φ equals InitialRadians.



RadiansPerSample radians per sample pi/50 real (-∞, ∞)

InitialRadians initial phase, in radians 0 real (-∞, ∞)



ComplexExp 8-5

Numeric Sources

Const

Description Constant outputLibrary Numeric, SourcesClass SDFConstC++ Code

Parameters

Pin Outputs

Notes/Equations

1. Const outputs a constant signal with a value given by the Level parameter(default 0.0).



Level value 0.0 real (-∞, ∞)


1 output real

8-6 Const

ConstCx

Description Complex constant outputLibrary Numeric, SourcesClass SDFConstCxC++ Code

Parameters

Pin Outputs

Notes/Equations

1. ConstCx outputs a complex constant signal with the real part given by the Realparameter (default 0.0) and the imaginary part given by the Imag parameter(default 0.0).



Real real part 0.0 real (-∞, ∞)

Imag imaginary part 0.0 real (-∞, ∞)


1 output complex

ConstCx 8-7

Numeric Sources

ConstFix

Description Fixed-Point Constant OutputLibrary Numeric, SourcesClass SDFConstFixDerived From SDFFixC++ Code

Parameters

Pin Outputs

Notes/Equations

1. ConstFix outputs a fixed-point constant signal with a value given by the Levelparameter (default 0.0).



wrapped enum


REPORT enum


TRUNCATE enum

Level constant value 0.0 fix (-∞, ∞)


2.14 precision


1 output fix

8-8 ConstFix

2. The output precision is specified using an l.r format: l is the number of bits tothe left of the decimal place (including the sign bit); r is the number of bits tothe right of the decimal place. For example, the precision 2.22 would represent a24-bit fixed-point number with 1 sign bit, 1 integer bit, and 22 fractional bits.

3. This component uses two’s-complement arithmetic; the values of theOutputPrecision parameter given by the user must specify at least 1 bit to theleft of the decimal place (used a sign bit).


ConstFix 8-9

Numeric Sources

ConstInt

Description Integer constant outputLibrary Numeric, SourcesClass SDFConstIntC++ Code

Parameters

Pin Outputs

Notes/Equations

1. ConstInt outputs a constant signal with a value given by the Level parameter(default 0).



Level constant value 0 int (-∞, ∞)


1 output int

8-10 ConstInt

Cx_M

Description Complex Matrix OutputLibrary Numeric, SourcesClass SDFCx_MDerived From MatrixConstant

Parameters

Pin Outputs

Notes/Equations

1. Cx_M produces a matrix with complex entries. Entries are read from theComplexMatrixContents array parameter in rasterized order; for example, foran M×N matrix, the first row is filled from left to right using the first N valuesfrom the array.

The ComplexMatrixContents value may be specified directly or they may beread from a file. To use data from a file, replace the default coefficients with thestring, <filename.



NumRows the number of rows in thematrix

2 int [1, ∞)

NumCols the number of columns inthe matrix

2 int [1, ∞)

ComplexMatrixContents complex valued elementsof output matrix

1 j (-1) (-j) complexarray



Cx_M 8-11

Numeric Sources



8-12 Cx_M

DataPattern

Description Patterned data sourceLibrary Numeric, SourcesClass SDFDataPattern

Parameters

Pin Outputs

Notes/Equations

1. This model is used to generate one of eight patterned bit streams.

2. For the DataPattern parameter:

• if PN9 is selected, a 511-bit pseudo-random test pattern is generatedaccording to CCITT Recommendation O.153

• if PN15 is selected, a 32767-bit pseudo-random test pattern is generatedaccording to CCITT Recommendation O.151

• if FIX4 is selected, a zero-stream is generated

• if x_1_x_0 is selected, where x equals 4, 8, 16, 32, or 64, a periodic bit streamis generated, with the period being 2 × x. In one period, the first x bits are 1sand the second x bits are 0s.


DataPattern data pattern: PN9, PN15,FIX4, _4_1_4_0,_8_1_8_0, _16_1_16_0,_32_1_32_0, _64_1_64_0

PN9 enum


1 output patterned data output int

DataPattern 8-13

Numeric Sources


References

[1]CCITT, Recommendation O.151(10/92).

[2] CCITT, Recommendation O.153(10/92).

8-14 DataPattern

Diagonal_M

Description Diagonal Matrix OutputLibrary Numeric, SourcesClass SDFDiagonal_MDerived From MatrixBase

Parameters

Pin Outputs

Notes/Equations

1. Diagonal_M outputs a diagonal matrix of size (RowsCols × RowsCols) with thediagonal elements given in the DiagonalElements parameter. All diagonalelements are floating-point (real) numbers.



RowsCols number of rows andcolumns in output squarematrix

2 int [1, ∞)

DiagonalElements diagonal elements ofoutput matrix

1.0 2.0 real array



Diagonal_M 8-15

Numeric Sources

DiagonalCx_M

Description Complex Diagonal Matrix OutputLibrary Numeric, SourcesClass SDFDiagonalCx_MDerived From MatrixBase

Parameters

Pin Outputs

Notes/Equations

1. DiagonalCx_M outputs a diagonal matrix of size (RowsCols × RowsCols) withthe diagonal elements given in the DiagonalElements parameter. All diagonalelements are complex numbers.




2 int [1, ∞)

DiagonalElements complex diagonal elementsof output matrix

1 j complexarray



8-16 DiagonalCx_M

DiagonalFix_M

Description Fixed-Point Diagonal Matrix OutputLibrary Numeric, SourcesClass SDFDiagonalFix_MDerived From SDFFix

Parameters

Pin Outputs

Notes/Equations



wrapped enum


REPORT enum


TRUNCATE enum


2 int [1, ∞)


2.14 string

DiagonalElements fixed-point diagonalelements of output matrix

1 -2 fix array


1 output fix matrix

DiagonalFix_M 8-17

Numeric Sources

1. DiagonalFix_M outputs a diagonal matrix of size (RowsCols × RowsCols) withthe diagonal elements given in the DiagonalElements parameter with thespecified precision.

2. This component uses two’s-complement arithmetic; the values of theOutputPrecision parameter given by the user must specify at least 1 bit to theleft of the decimal place (used as sign bit).


8-18 DiagonalFix_M

DiagonalInt_M

Description Integer Diagonal Matrix OutputLibrary Numeric, SourcesClass SDFDiagonalInt_MDerived From MatrixBase

Parameters

Pin Outputs

Notes/Equations

1. DiagonalInt_M outputs a diagonal matrix of size (RowsCols × RowsCols) withthe diagonal elements given in the DiagonalElements parameter. All diagonalelements are integer numbers.




2 int [1, ∞)

DiagonalElements integer diagonal elementsof output matrix

1 2 int array


1 output int matrix

DiagonalInt_M 8-19

Numeric Sources

Fix_M

Description Fixed-Point Matrix OutputLibrary Numeric, SourcesClass SDFFix_MDerived From SDFFix

Parameters

Pin Outputs

Notes/Equations



wrapped enum


REPORT enum


TRUNCATE enum


2 int [1, ∞)


2 int [1, ∞)

FixMatrixContents fixed-point elements ofoutput matrix

1 -2 2 -2 fix array


2.14 precision


1 output fix matrix

8-20 Fix_M

1. Fix_M generates a matrix with fixed-point entries. Entries are read from theFixMatrixContents array parameter in rasterized order; for example, for anM× N matrix, the first row is filled left to right using the first N values from thearray. All entries have the same precision, as specified by OutputPrecision.

2. The FixMatrixContents value may be specified directly or they may be readfrom a file. To use data from a file, replace the default coefficients with thestring, <filename. For details on using arrays of data for parameter values, referto “Understanding Parameters” in the ADS Ptolemy Simulation manual.



Fix_M 8-21

Numeric Sources

Float_M

Description Matrix OutputLibrary Numeric, SourcesClass SDFFloat_MDerived From MatrixConstant

Parameters

Pin Outputs

Notes/Equations

1. Float_M produces a matrix with floating-point (real) entries. Entries are readfrom the FloatMatrixContents array parameter in rasterized order; forexample, for an M× N matrix, the first row is filled from left to right using thefirst N values from the array.

2. The FloatMatrixContents value may be specified directly or they may be readfrom a file. To use data from a file, replace the default coefficients with thestring, <filename, For details on using arrays of data for parameter values, referto “Understanding Parameters” in the ADS Ptolemy Simulation manual.



2 int [1, ∞)


2 int [1, ∞)

FloatMatrixContents floating-point(real)elements of matrix

1.0 -2.0 2.0 -2.0 real array



8-22 Float_M


Float_M 8-23

Numeric Sources

IID_Gaussian

Description IID Gaussian Distributed Noise OutputLibrary Numeric, SourcesClass SDFIID_GaussianC++ Code

Parameters

Pin Outputs

Notes/Equations

1. IID_Gaussian generates an identically independently distributed whiteGaussian pseudo-random process with mean (default 0) and variance (default1) specified by the Mean and Variance parameters.

2. The noise is random for each IID_Gaussian instance. The noise is dependent onthe value of the DefaultSeed in the data flow controller (DF). WhenDefaultSeed=0, the noise generated for each simulation is different. WhenDefaultSeed > 0, the noise generated for each simulation, though random, hasthe same initial seed starting condition and thus results in reproduciblesimulations.



Mean mean of distribution 0.0 real (-∞, ∞)

Variance variance of distribution 1.0 real (-∞, ∞)


1 output real

8-24 IID_Gaussian

IID_Uniform

Description IID Uniform Distributed Noise OutputLibrary Numeric, SourcesClass SDFIID_UniformC++ Code

Parameters

Pin Outputs

Notes/Equations

1. IID_Uniform generates an identically independently distributed uniformlydistributed pseudo-random process. The output is uniformly distributedbetween Lower (default 0.0) and Upper (default 1.0) limits.

2. Noise is random for each IID_Uniform instance and is dependent on the valueof the DefaultSeed in the data flow controller (DF). When DefaultSeed=0, thenthe noise generated for each simulation is different; when DefaultSeed>0, thenthe noise generated for each simulation, though random, has the same initialseed starting condition and thus results in reproducible simulations.



Lower lower limit 0.0 real (-∞, ∞)

Upper upper limit 1.0 real [Lower, ∞)


1 output real

IID_Uniform 8-25

Numeric Sources

Identity_M

Description Identity Matrix OutputLibrary Numeric, SourcesClass SDFIdentity_MDerived From MatrixBase

Parameters

Pin Outputs

Notes/Equations

1. Identity_M outputs an identity matrix of the specified size.




2 int [1, ∞)



8-26 Identity_M

IdentityCx_M

Description Complex Identity Matrix OutputLibrary Numeric, SourcesClass SDFIdentityCx_MDerived From MatrixBase

Parameters

Pin Outputs

Notes/Equations

1. IdentityCx_M outputs an identity matrix of the specified size.




2 int [1, ∞)



IdentityCx_M 8-27

Numeric Sources

IdentityFix_M

Description Fixed-Point Identity Matrix OutputLibrary Numeric, SourcesClass SDFIdentityFix_MDerived From SDFFix

Parameters

Pin Outputs

Notes/Equations

1. IdentityFix_M outputs an identity matrix of the specified size with the specifiedprecision.



wrapped enum


REPORT enum


TRUNCATE enum


2 int [1, ∞)


2.14 string


1 output fix matrix

8-28 IdentityFix_M



IdentityFix_M 8-29

Numeric Sources

IdentityInt_M

Description Integer Identity Matrix OutputLibrary Numeric, SourcesClass SDFIdentityInt_MDerived From MatrixBase

Parameters

Pin Outputs

Notes/Equations

1. IdentityInt_M outputs an identity matrix of the specified size.



2 int [1, ∞)


1 output int matrix

8-30 IdentityInt_M

ImpulseFloat

Description Impulse outputLibrary Numeric, SourcesClass SDFImpulseFloatC++ Code

Parameters

Pin Outputs

Notes/Equations

1. ImpulseFloat generates a single impulse or an impulse train, with anamplitude specified by Level (default 0.0). If Period (default 0) is equal to 0,then only a single impulse is generated; otherwise Period specifies the period ofthe impulse train. The impulse or impulse train is delayed by the amountspecified by Delay.



Level height of impulse 1.0 real (-∞, ∞)

Period if greater than zero, periodof impulse train

0 int [0, ∞)

Delay output delay 0 int [0, ∞)


1 output real

ImpulseFloat 8-31

Numeric Sources

Int_M

Description Integer Matrix OutputLibrary Numeric, SourcesClass SDFInt_MDerived From MatrixConstant

Parameters

Pin Outputs

Notes/Equations

1. Int_M produces a matrix with integer entries. Entries are read from theIntMatrixContents array parameter in rasterized order; for example, for anM× N matrix, the first row is filled from left to right using the first N valuesfrom the array.

2. The IntMatrixContents value may be specified directly or they may be readfrom a file. To use data from a file, replace the default coefficients with thestring, <filename. For details on using arrays of data for parameter values, referto “Understanding Parameters” in the ADS Ptolemy Simulation manual.



2 int [1, ∞)


2 int [1, ∞)

IntMatrixContents integer elements of outputmatrix

1 -2 2 -2 int array


1 output int matrix

8-32 Int_M


Int_M 8-33

Numeric Sources

NumericExpression

Description Numeric Expression Data outputLibrary Numeric, SourcesClass SDFNumericExpression

Parameters

Pin Outputs

Notes/Equations

1. This component is used to generate numeric data output evaluated using anexpression. Expression can be any valid expression, following the syntax usedfor writing expression on a VAR block.

If the Expression is dependent on predefined variable, Nsample, then theoutput will be dependent on the sample number, which is incremented for eachfiring of this component determined by the schedule.



Expression expression, which can befunction of "Nsample"

0.0+j*0.0 complex


1 output numeric source output signal complex

8-34 NumericExpression

NumericSource

Description Numeric signal generator using data setLibrary Numeric, SourcesClass SDFNumericSource

Parameters

Pin Outputs

Notes/Equations


ControlSimulation if set to YES, Period ( or ifPeriod=0 then the index oflast data sample in the file)determines how long thesimulation will run: NO,YES

NO enum

Periodic if YES then output isperiodic: NO, YES

YES enum

Period period of the outputwaveform if Periodic=YES.If Period=0 then period isthe index of the last datasample read

0 int [0, ∞)

DataSet dataSet file to constructExpression from

filename

Expression variable/sink name fromdataset or a valid dataSetexpression ( data can bemulti dimensional from 1-Dto 3-D )

string


1 output Numeric source output signal anytype

NumericSource 8-35

Numeric Sources

1. This component is used to generate numeric data output evaluated using apre-generated dataset. Expression can be any valid expression using variablesavailable in the dataset. The syntax used for writing expression is the same aswriting an expression to display the data in a Data Display window.

If the dataset was generated using a Sweep, and the expression results inmultidimensional data, the output will be matrix data. The expression mustevaluate into data that is up to 3-dimensional. Any expression that results inhigher dimension (> 3-D) data will error out. To reduce the dimensionality, usethe "[...,::,...]" operator.

For example, consider a design that has a NumericSink N1 and 3 levels ofsweep. If such a dataset is used for generating data using NumericSource andthe Expression was set to "N1", the simulation will error out saying it was 4-dimensional data. To fix it you can use "N1[0,::,::,::]", which will now generate3-dimensional matrix data at the output.

If the length of simulation is larger than the available data in the dataset, usethe Periodic and Period parameters to repeat the old data. The Periodicparameter must be set to YES for the output to repeat after the sample numberequal to Period. If Periodic=YES and Period=0, the Period will be the index onthe last data read in the dataset, and all of the data from the dataset will beread and repeated. If Periodic=NO, the output will be zero after all data is read.

If ControlSimulation=YES, Period will determine how long the simulation runs.If Period=0, the simulation will run until the last data in the dataset is read.

2. The variable specified in an expression cannot be a variable that representsmatrix data generated using DSP designs.


8-36 NumericSource

RampFix

Description Fixed-Point Ramp OutputLibrary Numeric, SourcesClass SDFRampFixDerived From SDFFixC++ Code

Parameters

Pin Outputs

Notes/Equations



wrapped enum


REPORT enum


TRUNCATE enum


2.14 precision

Step increment from one sampleto the next

1.0 fix (-∞, ∞)

Value initial (or latest) valueoutput by RampFix

0.0 fix (-∞, ∞)


1 output fix

RampFix 8-37

Numeric Sources

1. RampFix generates a ramp signal, starting at Value (default 0.0) andincrementing by the step size specified by Step (default 1.0).


3. The value of the Step and Value parameters and their precision in bits can bespecified using two different notations.

Specifying only a value in the dialog box would create a fixed-point numberwith the default precision, which has a total length of 32 bits with the numberof integer bits set as required by the value of the parameter. For example, thedefault value 1.0 creates a fixed-point object with precision 2.30, and a valuelike 0.5 would create one with precision 1.31.

An alternate way of specifying the value and the precision is to use theparentheses notation, which will be interpreted as (value, precision). Forexample, (2.546, 3.5) would create a fixed-point object by casting thedouble-precision floating-point (real) number 2.546 to a fixed-point precision of3.5.

This component has three precision specifications:

• OutputPrecision given by user

• Step parameter precision (default or given by user)

• Value parameter precision (default or given by user)

Certain conditions must be satisfied to get reasonable results.

• the Step parameter precision should not have more integer or fractional bitsthan OutputPrecision. Otherwise, the extra (if any) fractional bits will behandled according to the value of the RoundFix parameter and the extra (ifany) integer bits will be handled according to the value of theOverflowHandler parameter.

• if Value is not equal to 0, the OutputPrecision should not have more integeror fractional bits than Value parameter precision. Otherwise, the extra (ifany) fractional bits will be handled according to the value of the RoundFixparameter and the extra (if any) integer bits will be handled according to thevalue of the OverflowHandler parameter.

Examples (OverflowHandler=wrapped and RoundFix=TRUNCATE isassumed):

8-38 RampFix

• Specifying OutputPrecision="5.1" and Step=0.25, will result in a constantoutput equal to the value of the Value parameter possibly wrapped andtruncated to fit the output precision.

• Specifying OutputPrecision="5.1", Step=0.5 and Value=4.0 (default precisionis 4.28) will result in an output starting at 4.0, incrementing by 0.5 at eachstep and saturating when 7.5 is reached.

• Specifying OutputPrecision="4.1", Step=0.75 and Value="(3.0,4.1)" will resultin an output starting at 3.0, incrementing by 0.5 at each step and wrappingto −8 after 7.5 is reached. The same output is obtained if Value has otherprecisions specified that have more integer or fractional bits thanOutputPrecision. For example, "(3.0,6.3)" will produce the same results.


RampFix 8-39

Numeric Sources

RampFloat

Description Ramp outputLibrary Numeric, SourcesClass SDFRampFloatC++ Code

Parameters

Pin Outputs

Notes/Equations

1. RampFloat generates a ramp signal, starting at Value (default 0.0) andincrementing by the step size (default 1.0) specified by the Step parameter.

Because doubles have finite precision, the maximum value that RampFloat canoutput is Step/DBL_EPSILON. For example, for a Step of 1, the maximum is1FFFFFFFFFFFFF, or 9007199254740991. After that value, the output willremain constant.




1.0 real (-∞, ∞)

Value initial value output 0.0 real (-∞, ∞)


1 output real

8-40 RampFloat

RampInt

Description Integer ramp outputLibrary Numeric, SourcesClass SDFRampIntC++ Code

Parameters

Pin Outputs

Notes/Equations

1. RampInt generates an integer ramp signal, starting at Value (default 0) andincrementing by the step size specified by Step (default 1).




1 int (-∞, ∞)

Value initial value output 0 int (-∞, ∞)


1 output int

RampInt 8-41

Numeric Sources

ReadFile

Description Waveform output from fileLibrary Numeric, SourcesClass SDFReadFileC++ Code

Parameters

Pin Outputs

Notes/Equations

1. ReadFile reads ASCII data from a file. The simulation can be halted at end offile, the file contents can be periodically repeated, or the file contents can bepadded with zeroes.

2. The input file is to be a text file that contains real array data in ADS Ptolemyformat. For details on this file format refer to “Understanding Parameters” inthe ADS Ptolemy Simulation manual.



FileName input file name file.txt filename

ControlSimulation control simulation: NO,YES

NO enum

OutputType output type: zero padded,periodic

periodic enum


1 output real

8-42 ReadFile

ReadFilePreProc

Description Waveform output from file with preprocessing using a shell commandLibrary Numeric, SourcesClass SDFReadFilePreProcDerived From ReadFile

Parameters

Pin Outputs

Notes/Equations

1. ReadFilePreProc pre-processes the ASCII datafile specified in the FileNameparameter, using the perl script provided in PerlFile parameter. It is equivalentto executing the command ‘perl PerlFile FileName’ then using the results asASCII input to the design. The original datafile is not modified; instead, theprocessed file is temporarily saved in the data directory (under the nametmp<InstanceName>.txt) and removed at the end of simulation. The simulationcan be halted at the end of file, the file contents can be periodically repeated, orthey can be padded with zeroes.


FileName input file name file.txt filename


NO enum

OutputType output type: zero padded,periodic

periodic enum

PerlFile data file pre-processingperl script

filename


1 output real

ReadFilePreProc 8-43

Numeric Sources

2. The resulting file must be a text file that contains real array data in ADSPtolemy format. For details on this file format refer to “UnderstandingParameters” in the ADS Ptolemy Simulation manual.

3. Use of this component is demonstrated in the Example Project >PtolemyDocExamples >Numeric_Sources_prj. Open the networks designReadFilePreProc_example.dsn.

4. Also see: ReadFile.


8-44 ReadFilePreProc

Rect

Description Rectangular pulse outputLibrary Numeric, SourcesClass SDFRectC++ Code

Parameters

Pin Outputs

Notes/Equations

1. Rect generates a rectangular pulse of height and width specified by Height andWidth. If Period > 0, the pulse is repeated with the given period.



Height height of rectangular pulse 1.0 real (-∞, ∞)

Width width of rectangular pulse 8 int [0, ∞)

Period if greater than zero,repetition period of pulsestream

0 int [0, ∞)



Rect 8-45

Numeric Sources

RectCx

Description Complex rectangular pulse outputLibrary Numeric, SourcesClass SDFRectCxC++ Code

Parameters

Pin Outputs

Notes/Equations

1. RectCx generates a complex rectangular pulse specified by Height and Width. IfPeriod > 0, the pulse is repeated with the given period.




Height height of rectangular pulse 1.0 complex


Period period of pulse stream 1024 int [0, ∞)



8-46 RectCx

RectCxDoppler

Description Complex rectangular Doppler pulse outputLibrary Numeric, SourcesClass SDFRectCxDopplerDerived From RectCxC++ Code

Parameters




Bandwidth signal bandwidth 1.0e9 real [0.0, ∞)

Te duration time 30.0*10^-6 real [0.0, ∞)

Fe emission frequency 3.0e9 real [0.0, ∞)

Fsimu simulation frequency 8.0e6 real [0.0, ∞)

Vn target velocity 150.0 real [0.0, ∞)

Tp pulse period 1.0e-3 real [0.0, ∞)

Np pulse number 16 int [0, ∞)

Fpor carrier frequency 3.0e9 real [0.0, ∞)

C light speed 3.0e8 real [0.0, 3e8)

SNRn signal-to-noise ratio 10.0 real [0, ∞)

SqrPthn square root of noise power 1.0 real [0, ∞)

Sdelay target delay 0 real [0.0, ∞)

RectCxDoppler 8-47

Numeric Sources

Pin Outputs

Notes/Equations

1. RectCxDoppler generates a complex rectangular pulse of width specified byWidth. If Period > 0, the pulse is repeated with the given period.




8-48 RectCxDoppler

RectFix

Description Fixed-Point Rectangular Pulse OutputLibrary Numeric, SourcesClass SDFRectFixDerived From SDFFixC++ Code

Parameters

Pin Outputs

Notes/Equations



wrapped enum


REPORT enum


TRUNCATE enum

Height height of rectangular pulse 1.0 fix (-∞, ∞)




2.14 precision


1 output output signal fix

RectFix 8-49

Numeric Sources

1. RectFix generates a fixed-point rectangular pulse specified by Height andWidth. If Period > 0, the pulse is repeated with the given period.

2. OutputPrecision is specified using an l.r format, where l is the number of bits tothe left of the decimal place (including the sign bit) and r is the number of bitsto the right of the decimal place. For example, the precision 2.22 wouldrepresent a 24-bit fixed-point number with 1 sign bit, 1 integer bit, and 22fractional bits.



8-50 RectFix

SineGen

Description Sine wave outputLibrary Numeric, SourcesClass SDFSineGenC++ Code

Parameters

Pin Outputs

Notes/Equations

1. SineGen generates the sequence of numbers given by sin( ω × n +Φ), n=0, 1, ... ,where ω equals RadiansPerSample and Φ equals InitialRadians.



RadiansPerSample radians per sample pi/50 real (-∞, ∞)

InitialRadians initial phase, in radians 0 real (-∞, ∞)



SineGen 8-51

Numeric Sources

WaveForm

Description Waveform outputLibrary Numeric, SourcesClass SDFWaveFormC++ Code

Parameters

Pin Outputs

Notes/Equations

1. Waveform outputs a waveform specified by Value. You can get periodic signalswith any period, and halt a simulation at the end of the given waveform.Table 8-1 summarizes the operations.

Value can be specified directly or read from a file. To use data from a file,replace the default coefficients with the string, <filename. For details usingarrays of data for parameter values, refer to “Understanding Parameters” in theADS Ptolemy Simulation manual. The size of the array is currently limited to20,000 samples. The complete file is be read and its contents stored in an array.


Value waveform values 1 -1 real array


NO enum

Periodic periodic output: NO, YES YES enum

Period period of waveform whengreater than zero

0 int [0, ∞)


1 output real

8-52 WaveForm

To read longer files use the ReadFile component, which reads one sample at atime and therefore uses less storage.


Table 8-1.

StopSimulation Periodic Period Operation

do not stop yes 0 period is length of waveform

do not stop yes N>0 period is N

do not stop no any output the waveform once, then zeros

stop at end any any stop after outputting the waveform once

WaveForm 8-53

Numeric Sources

WaveFormCx

Description Complex waveform outputLibrary Numeric, SourcesClass SDFWaveFormCxC++ Code

Parameters

Pin Outputs

Notes/Equations

1. WaveFormCx outputs a complex waveform as specified by Value. You can getperiodic signals with any period, and halt a simulation at the end of the givenwaveform. Table 8-2 summarizes the operations.

The Value may be specified directly or they may be read from a file. To use datafrom a file, replace the default coefficients with the string, <filename. The size ofthe array is currently limited to 20,000 samples. The entire file will be read andits contents stored in an array. To read longer files, use the ReadFile component,which reads one sample at a time and therefore uses less storage.


Value waveform values (1) (-1) complexarray


NO enum

Periodic periodic output: NO, YES YES enum

Period period of waveform whengreater than zero

0 int [0, ∞)


1 output complex

8-54 WaveFormCx




Table 8-2.

StopSimulation Periodic Period Operation

do not stop yes 0 period is length of waveform

do not stop yes N>0 period is N

do not stop no any output the waveform once, then zeros

stop at end any any stop after outputting the waveform once

WaveFormCx 8-55

Numeric Sources

Window

Description Window dataLibrary Numeric, SourcesClass SDFWindowC++ Code

Parameters

Pin Outputs

Notes/Equations

1. Window generates standard window functions or periodic repetitions ofstandard window functions. One period of samples is produced at eachsimulation. It produces output values that are samples of a standardwindowing function.

2. Length is the length of the window to produce; most window functions have a 0value at the first and last sample.


Name name of window function togenerate (Rectangle,Bartlett, Hanning,Hamming, Blackman,SteepBlackman, or Kaiser)

Hanning string

Length length of window functionto produce

256 int [4, ∞)

Period period of the output 0 int [0, ∞)

WindowParameters array of values for thewindow

0 real array


1 output real

8-56 Window

3. Period specifies the period of the output signal. The window will be zero-paddedif required. Period=0 means a period equal to Length.

A negative period will produce one window, then output 0 for all later samples.A period of less than the window length will be equivalent to a period of thewindow length (that is, Period=0).

4. For the Kaiser window, the first entry in WindowParameters is taken as thebeta parameter that is proportional to the stopband attenuation of the window.

5. The WindowParameters value may be specified directly or they may be readfrom a file. To use data from a file, replace the default coefficients with thestring, <filename.


6. Leland Jackson, Digital Filters and Signal Processing, 2nd ed., KluwerAcademic Publishers, ISBN 0-89838-276-9, 1989.


Window 8-57

Numeric Sources

8-58 Window

Chapter 9: Numeric Special Functions

Introduction

The numeric special functions components provide data processing functions commonto communication systems such as signal quantizers, signal compressor, signalexpandors and other block that operate on single data points or arrays of data thatare integer, double precision floating-point (real), or complex values. Each componentaccepts a specific class of signal and outputs a resultant signal. (These components donot accept any matrix class of signal.)

If a component receives another class of signal, the received signal is automaticallyconverted to the signal class specified as the input of the component. Auto conversionfrom a higher to a lower precision signal class may result in loss of information. Theauto conversion from timed, complex or floating-point (real) signals to a fixed signaluses a default bit width of 32 bits with the minimum number of integer bits needed torepresent the value. For example, the auto conversion of the floating-point (real)value of 1.0 creates a fixed-point value with precision of 2.30, and a value of 0.5 wouldcreate one of precision of 1.31. For details on conversions between different classes ofsignals, refer to “Conversion of Data Types” in the ADS Ptolemy Simulation manual.


Introduction 9-1

Numeric Special Functions

AdaptLinQuant

Description Adaptive linear quantizerLibrary Numeric, Special FunctionsClass SDFAdaptLinQuantC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. AdaptLinQuant quantizes the input to the number of levels given by 2Bits. Thequantization levels are uniformly spaced at the step size given by the inStepinput value and are odd symmetric about zero. Therefore, the high threshold is(2Bits - 1)(inStep/2), and the low threshold is the negative of the high threshold.


Bits number of bits 8 int [1, 31]


1 input real

2 inStep real


3 amplitude real

4 outStep real

5 stepLevel int

9-2 AdaptLinQuant

2. Rounding to the nearest level is performed. The output level will equal highonly if the input level equals or exceeds high. If the input is below low, then thequantized output will equal low.

3. The quantized value is output on the amplitude port as a floating-point (real)value, the step size is output on the outStep port as a floating-point (real) value,and the index of the quantization level is output on the stepLevel port as anon-negative integer between 0 and 2Bits - 1.

4. For information regarding numeric special function component signals, refer tothe “Introduction” on page 9-1.

AdaptLinQuant 9-3


Compress

Description Compression part of a companderLibrary Numeric, Special FunctionsClass SDFCompressDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs


Type compression law: MU-law,A-law

MU-law enum

CompressionK compression constant 1 real

Max maximum input valuemagnitude

1 real (0.0, ∞)





9-4 Compress

Notes/Equations

1. Compress can be used to obtain the MU-law and A-law compressioncharacteristics. The output signal is always a baseband signal.


Compress 9-5


Let x′(n) = x(n)/Max

MU-law:

A-law:

where

y(n) is the Output for sample nx(n) is the Input for sample nVM is Max, the maximum input value magnitudeµ is the compression constant for MU-lawA is the compression constant for A-law

3. The output signal versus input signal plot of the Compress component, withType=MU-law, CompressionK=255, and Max=1V, is shown.


y n( ) V Mx′ n( )[ ] 1.0 µ x′ n( )+ lnsgn

1.0 µ+( )ln--------------------------------------------------------------------------- for µ 0≥=

y n( )V M

x′ n( )[ ] A x′ n( )sgn1.0 A( )ln+

-------------------------------------------------- for x′ n( ) 1 A⁄<

V Mx′ n( )[ ] 1 A x′ n( )[ ]ln+ sgn

1 A( )ln+---------------------------------------------------------------------------- for x′ n( ) 1 A⁄≥

=

Output signal(units)

Input signal(units)

9-6 Compress

DeadZone

Description Dead Zone NonlinearityLibrary Numeric, Special FunctionsClass SDFDeadZoneDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs


K magnitude gain 1 real (-∞, 0.0) or

(0.0, ∞)

Low lower dead zone value 0 real (-∞, High)

High higher dead zone value 1 real (-∞, ∞)





DeadZone 9-7


Notes/Equations

1. DeadZone models a dead zone nonlinearity. Its output is always a floating-point(real) signal.

where:

y(n) is the output for sample nx(n) is the input for sample nK is the magnitude of the gainVh is the High dead zone valueVl is the Low dead zone value

2. The output signal versus input signal plot of DeadZone, with K=1, Low=0 andHigh=1, is shown in Figure 9-1.

Figure 9-1. DeadZone signal plot


y n( )

K x n( ) Vh–( ) for x n( ) Vh>

K x n( ) Vl–( ) for x n( ) Vl<

0 otherwise

=


Input signal (units)

9-8 DeadZone

Dirichlet

Description Dirichlet (aliased sinc) functionLibrary Numeric, Special FunctionsClass SDFDirichletC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Dirichlet computes the normalized Dirichlet kernel (also called the aliased sincfunction).

2. The value of the normalized Dirichlet kernel at x = 0 is always 1, and thenormalized Dirichlet kernel oscillates between −1 and +1. The normalizedDirichlet kernel is periodic in x with a period of either 2π when N is odd or 4πwhen N is even.


N length of Dirichlet kernel 10 int (-∞, ∞)


1 input The input x to the Dirichlet kernel. real


2 output The output of the Dirichlet kernel. real

Dirichlet 9-9


3. The Dirichlet kernel is the discrete-time Fourier transform (DTFT) of a sampledpulse function. The parameter N is the length of the pulse [1]. See also Sinccomponent.


References


9-10 Dirichlet

Expand

Description Expander part of a companderLibrary Numeric, Special FunctionsClass SDFExpandDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs


Type compression law: MU-law,A-law

MU-law enum

CompressionK compression constant 1 real

Max maximum input valuemagnitude

1 real (0.0, ∞)





Expand 9-11


Notes/Equations

1. Expand can be used to obtain the A-law and MU-law expansion characteristics.The output of this component is always a baseband signal.

2. The following equations describe the characteristics of the component:

Let

.

Then

MU-law:

A-law:

where:

y(n) is the output for sample nx(n) is the input for sample nVM is Max, the maximum input value magnitudeµ is the compression constant for MU-LawA is the compression constant for A-Law

3. The output signal versus input signal plot of the Expand component, withType=MU-law, CompressionK=255, and Max=1V, is shown in Figure 9-2.


x' n( ) x n( ) V M⁄=

y n( )V M

µ---------- x' n( )( ) 1 µ+( ) x n( )

1–( )sgn=

y n( )

V M 1 ln A( )+( )A

----------------------------------------x' n( ) for x' n( ) 1 A⁄<

V MA

---------- x' n( )( )e x' n( ) 1 ln A( )+( ) 1–( )sgn forx' n( ) 1 A⁄>

=

9-12 Expand

Figure 9-2. Expand Component Signal Plot


Input signal(units)

Expand 9-13


LatchClocked

Description Data Latch with Clock InputLibrary Numeric, Special FunctionsClass SDFLatchClockedDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs


ResetCx complex output when resetpin is high

0.0 complex




3 reset reset signal int



9-14 LatchClocked

Notes/Equations

1. LatchedClocked can be used to latch complex numbers. The input is latchedwith the positive edge of the clock. The outputs can be reset asynchronously tothe values specified by input2 and input3 by setting the signal at the reset pinto high.

The component is positive edge sensitive to the clock input and level sensitive tothe reset input. The reset signal is asynchronous.



LatchClocked 9-15


Limit

Description LimiterLibrary Numeric, Special FunctionsClass SDFLimitC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Limit can be used to model two different types of limiting nonlinearities. Theoutput is always a floating-point (real) signal.


K magnitude gain 1.0 real (-∞, 0.0) or

(0.0, ∞)

Bottom lower output saturationvalue

0.0 real (-∞, Top)

Top higher output saturationvalue

1.0 real (-∞, ∞)

Type type of limiting curve:linear, atan

linear enum


1 input real


2 output real

9-16 Limit

2. If Type=linear

If Type=atan:

where:

y(n) is the output for sample nx(n) is the input for sample nVl is the lower output saturation value (Bottom)Vh is the higher output saturation value (Top)K is the magnitude of the gain

3. The output signal versus input signal plot of Limit (parameters K=1, Vl =−1,and Vh=1) is shown in Figure 9-3 for linear and atan types.


y n( )

Vl if x n( )VlK------<

Kx n( ) ifVl( )K

----------- x n( )VhK

--------≤≤

Vh if x n( )VhK

-------->

y n( )Vh Vl–

π--------------------=

1–tan

4Kx n( ) 2 Vh Vl+( )–

Vh Vl–-------------------------------------------------------

Limit 9-17


Figure 9-3. Limit Component Signal Plot


Input signal(units)

Type=atan

Type=linear

9-18 Limit

LinQuantIdx

Description Uniform quantizer with step number outputLibrary Numeric, Special FunctionsClass SDFLinQuantIdxC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. LinQuantIdx quantizes the input value to the number of levels given by theLevels parameter plus 1. The quantization levels are uniformly spaced betweenLow and High inclusive. Rounding down is performed—the output level willequal High if the input level equals or exceeds High; if the input is below Low,


Levels number of quantizationlevels

128 int [1, ∞)

Low lower limit of signalexcursion

-3.0 real (-∞, High)

High upper limit of signalexcursion

3.0 real (-∞, ∞)


1 input real


2 amplitude real

3 stepNumber int

LinQuantIdx 9-19


the quantized output will equal Low. The quantized value is output to theSignalOut port, while the index of the quantization is output to theStepNumber port. This integer output is useful for components that need aninteger input.


9-20 LinQuantIdx

MuLaw

Description Mu law compressorLibrary Numeric, Special FunctionsClass SDFMuLawC++ Code

Parameters

Pin Inputs

Pin Outputs


Compress enable compression 1 int

Mu mu parameter, a positiveinteger

255 int [0, ∞)

Denom denominator of mu-lawdefinition

1.0 real (-∞, ∞)


1 input real


2 output real

MuLaw 9-21


Notes/Equations

1. MuLaw transforms the input using a logarithmic mapping if the Compressparameter is true. In telephony, applying µ−law to 8-bit sampled data is calledcompanding and is used to quantize the dynamic range of speech moreaccurately [1]. The transformation is defined in terms of the non-negativeinteger parameter Mu:

where



References

[1]S. Haykin, Communication Systems 3rd ed., John Wiley Sons, 1994, p. 380.

y n( ) 1.0 µ x n( )+ ln1.0 µ+( )ln

-------------------------------------------- for µ 0≥=

9-22 MuLaw

OrderTwoInt

Description Ordered Two Integer OutputLibrary Numeric, Special FunctionsClass SDFOrderTwoIntC++ Code

Pin Inputs

Pin Outputs

Notes/Equations

1. OrderTwoInt takes two inputs and outputs the greater and lesser of the twointeger inputs.

where


1 upper int

2 lower int


3 greater int

4 lesser int

y1 max x1 x2),(=

y2 min x1 x2),(=

OrderTwoInt 9-23


y1 is the greater outputy2 is the lesser outputx1 is the upper inputx2 is the lower input


9-24 OrderTwoInt

PcwzLinear

Description Piecewise Linear Map OutputLibrary Numeric, Special FunctionsClass SDFPcwzLinearC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. PcwzLinear implements a piecewise linear mapping from the input to theoutput.

Mapping is given by a sequence of (x,y) pairs that specify breakpoints in thefunction; the sequence of x values must be increasing. The functionimplemented by this component can be represented by drawing straight linesbetween the (x,y) pairs, in sequence. Default mapping is the tent map, in whichinputs between −1.0 and 0.0 are linearly mapped into the range −1.0 to 1.0.


Breakpoints endpoints and breakpointsin the mapping

(-1.0,-1.0)(0.0,1.0) (1.0,-1.0)

complexarray





PcwzLinear 9-25


Inputs between 0.0 and 1.0 are mapped into the same range, but with oppositeslope, 1.0 to −1.0. If the input is outside the range specified in the x values of thebreakpoints, then the appropriate extreme value will be used for the output.Therefore, for the default map: if the input is −2.0, the output will be −1.0; if theinput is +2.0, the output will again be −1.0.




9-26 PcwzLinear

Polynomial

Description Polynomial input-output relationshipLibrary Numeric, Special FunctionsClass SDFPolynomial

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This component models a system with a polynomial input-output relationship.If the input is x, the output is y = c0 + c1 × x + c2 × x2 + ... + cN × xN, where N isthe order of the polynomial and c0, ... , cN are the elements of the Coefficientsparameter.



Coefficients Polynomial coefficients,0-th order coefficient first

0 1 real array





Polynomial 9-27


Quant

Description QuantizerLibrary Numeric, Special FunctionsClass SDFQuantC++ Code

Parameters

Pin Inputs

Pin Outputs


Thresholds quantization thresholds, inincreasing order

0.0 real array

Levels output levels. If empty use0, 1, 2, ...

real array


1 input real


2 output real

9-28 Quant

Notes/Equations

1. Quant quantizes the input value to one of N+1 possible output levels using Nthresholds.

• For input ≤ nth threshold, but > all previous thresholds, the output will be thenth level.

• For input > all thresholds, the output is N+1th level.

• For input < all thresholds, the output is 0th level.

2. If the level is specified, there must be one more level than thresholds. Thedefault value for level is 0, 1, 2, ... N.

This component takes on the order of log N steps to find the right level, whereasthe linear quantizer component LinQuantIdx takes a constant amount of time.Therefore, for linear quantization, use the LinQuantIdx component.

3. Assume that the Thresholds parameter is set to (8.1, 9.2, 10.3) and that theLevels parameter is not set so that the default values of (0.0, 1.0, 2.0, 3.0) areused. An input of −1.5 would give an output of 0.0; an input of 8.2 would give anoutput of 1.0; and, an input of 15.5 would give an output of 3.0.



Quant 9-29


QuantIdx

Description Quantizer with Step Number OutputLibrary Numeric, Special FunctionsClass SDFQuantIdxDerived From QuantC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. QuantIdx quantizes the input value to one of N+1 possible output levels usingN thresholds. This component also outputs the quantization level(stepNumber).


Thresholds quantization thresholds, inincreasing order

0.0 real array

Levels output levels. If empty use0, 1, 2, ...

real array


1 input real


2 output real

3 stepNumber Level of the quantization from 0 to N-1 int

9-30 QuantIdx

For an input less than or equal to the nth threshold, but larger than all previousthresholds, the output will be the nth level. If the input is greater than allthresholds, the output is the N+1th level. If the input is less than all thresholds,the output is the 0th level.

2. If the level is specified, there must be one more level than thresholds. Thedefault value for level is 0, 1, 2, ... N. This component takes on the order of log Nsteps to find the right level, whereas the linear quantizer componentLinQuantIdx takes a constant amount of time. Therefore, for linearquantization, use the LinQuantIdx component.

3. Assume that the Thresholds parameter is set to (8.1, 9.2, 10.3) and that theLevels parameter is not set so that the default values of (0.0, 1.0, 2.0, 3.0) areused. An input of −1.5 would give an output of 0.0; an input of 8.2 would give anoutput of 1.0; and, an input of 15.5 would give an output of 3.0.



QuantIdx 9-31


Quantizer

Description Quantizer Using CodeBookLibrary Numeric, Special FunctionsClass SDFQuantizerC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Quantizer quantizes the input value to the nearest output value in the givencodebook. The nearest value is found by a full search of the codebook, so thiscomponent will be significantly slower than either the Quant or LinQuantIdxcomponents. The absolute value of the difference is used as a distance measure.The index of the closest value in the codebook is also output.



FloatCodebook possible output values 0.0 1.0 2.0 3.0 4.05.0 6.0 7.0 8.0 9.0

real array


1 input real


2 output Closest value in the codebook real

3 outIndex Index of the closest value in the codebook int

9-32 Quantizer


Quantizer 9-33


Quantizer2D

Description 2-dimensional quantizerLibrary Numeric, Special FunctionsClass SDFQuantizer2DDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs


VxMax maximum real output level 1.0 real (-∞, ∞)

VxMin minimum real output level -1.0 real (-∞, VxMax)

Nx number of real outputlevels

16 int [1, ∞)

VyMax maximum imaginary outputlevel

1.0 real (-∞, ∞)

VyMin minimum imaginary outputlevel

-1.0 real (-∞, VyMax)

Ny number of imaginaryoutput levels

16 int [1, ∞)

QuantList user-defined quantizationpoints

complexarray





9-34 Quantizer2D

Notes/Equations

1. The complex number input is mapped to one of a finite set of complex numbers.Any arbitrary set of points can be specified as the set of output points by using afile or a list, or else the parameters VxMax, VxMin, Nx, VyMax, VyMin and Nycan be used to set up a rectangular grid of output points.

The ability to specify output points by a file or a list can be used to definearbitrary 2D quantizers. Each input is mapped to the nearest output point,where the metric used to determine the nearest output point is the Euclideandistance. This type of a quantizer is also referred to as a Voronoi or a nearestneighbor vector quantizer [1].

Figure 9-4 shows an example where three output points P1, P2, and P3 havebeen specified. The entire 2D plane is then divided into 3 regions, R1, R2, andR3, which are shown by the dotted lines. Any input point in region R1 ismapped to the output point P1 (and similarly for the other regions).

Figure 9-5 illustrates how a rectangular grid of output points can be set up byusing the parameters VxMax, VxMin, Nx, VyMax, VyMin and Ny.

Due to the regular lattice structure of this quantizer, it can be implementedefficiently in terms of speed. Therefore, it is more efficient to use this secondmethod of specifying a quantizer than using a file or a list of output points.

When a file or list is used to specify the list of output points, data is entered forthe QuantList parameter as an ordered list of complex values.

Data entered as an explicit array has the form:

QuantList = "(1, 0) (0.707, 0.707) (0, 1) (-0.707, 0.707) (-1, 0)(-0.707, -0.707) (0, -1) (0.707, -0.707)”

As an alternative from an explicit list, this data set can be contained in a textfile and referenced by name as follows:

QuantList = "<myquantlist.cx"

where the file named myquantlist.cx must be located in the current project datasubdirectory. If not in the data subdirectory, then the file name must include thefull directory path as the prefix to the file name. The contents of this file issimply the complex values where the separator can be a comma, space, tab, ornew line, with one or more complex pairs per line:

Quantizer2D 9-35


(1, 0) (0.707, 0.707)(0, 1) (-0.707, 0.707)(-1, 0) (-0.707, -0.707)(0, -1) (0.707, -0.707)

This above data set can be used to create a quantizer for an 8-PSK receiverwhose signal set consists of 8 points equally spaced on a unit circle. Figure 9-6shows the points and the decision regions (in dotted lines) for this quantizer.




Figure 9-4. 2D Quantizer with Three Output Points

Figure 9-5. 2D Quantizer with Output Points On a Grid

P1

P2

P3

R1

R2

R3

XMax

YMax

YMin

Nx = 3Ny = 4

XMin

9-36 Quantizer2D

Figure 9-6. Quantizer2D

Quantizer2D 9-37


SchmittTrig

Description Schmitt TriggerLibrary Numeric, Special FunctionsClass SDFSchmittTrigDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. SchmittTrig is a Schmitt trigger with programmable levels. The output isalways a floating-point (real) signal.

2. The output signal versus input signal plot, with parameters ILow= −1,IHigh=1, OLow= −1, and OHigh=1, is shown in Figure 9-7.


ILow lower input trigger value -1 real (-∞, IHigh)

IHigh higher input trigger value 1 real (-∞, ∞)

OLow lower output trigger value -1 real (-∞, OHigh)

OHigh higher output trigger value 1 real (-∞, ∞)





9-38 SchmittTrig

Figure 9-7. SchmittTrig Signal Plot



Input signal (units)VIL VIH

Voh

Vol

SchmittTrig 9-39


Table

Description Indexed Lookup Table OutputLibrary Numeric, Special FunctionsClass SDFTableC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Table implements a real-valued lookup table indexed by an integer-valuedinput. The input must lie between 0 and N −1, inclusive, where N is the size ofthe table. The table of values listed for the Values parameter must be less than20,000 values long. Its first component is indexed by a zero-valued input. Anerror occurs if the input value is out of the array bounds.

The input must be in the range: 0 ≤ input < size of Values.



Values table of values to output -1, 1 real array


1 input int


2 output real

9-40 Table


Table 9-41


TableCx

Description Indexed Complex Lookup Table OutputLibrary Numeric, Special FunctionsClass SDFTableCxC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. TableCx implements a complex-valued lookup table indexed by aninteger-valued input. The input must lie between 0 and N-1, inclusive, where Nis the size of the table. The table of values listed for the Values parameter mustbe less than 20,000 values long. Its first component is indexed by a zero-valuedinput. An error occurs if the input value is out of the array bounds.




Values table of values to output (1), (j), (-1), (-j),(0), (1), (j), (1)

complexarray


1 input int


2 output complex

9-42 TableCx


TableCx 9-43


TableInt

Description Indexed Integer Lookup Table OutputLibrary Numeric, Special FunctionsClass SDFTableIntC++ Code

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. TableInt implements an integer-valued lookup table indexed by aninteger-valued input. The input must lie between 0 and N-1, inclusive, where Nis the size of the table. The table of values listed for the Values parameter mustbe less than 20,000 values long. Its first component is indexed by a zero-valuedinput. An error occurs if the input value is out of the array bounds.




Values table of values to output -1, 1 int array


1 input int


2 output int

9-44 TableInt


TableInt 9-45


Toggle

Description Data Toggle with Clock InputLibrary Numeric, Special FunctionsClass SDFToggleDerived From baseOmniSysNumericStar

Pin Inputs

Pin Outputs

Notes/Equations

1. Let

v1(t) = input1v2(t) = input2v3(t) = controlv4(t) = output,

then


1 input1 input signal 1 complex

2 input2 input signal 2 complex

3 control control signal real



v4 t( )v2 t( ) when v3 t( ) 0.5≥

v1 t( ) when v3 t( ) 0.5<

=

9-46 Toggle

Here, v1(t), v2(t) and v4(t) are complex valued signals with real and imaginaryparts. If v3(t) is complex valued, its imaginary part is ignored and only the realpart is considered.


Toggle 9-47


Unwrap

Description Unwrap phaseLibrary Numeric, Special FunctionsClass SDFUnwrapC++ Code

Parameters

Pin Inputs

Pin Outputs


OutPhase initial output phase 0.0 real (-∞, ∞)

PrevPhase initial wrapped phase ofinput signal for computingthe first phase difference(phase change)

0.0 real (-∞, ∞)


1 input real


2 output real

9-48 Unwrap

Notes/Equations

1. Unwrap unwraps a phase plot, removing discontinuities of magnitude 2π.Unwrap assumes that the phase never changes by more than π in one sampleperiod; it also assumes that the input is in the range [−π,π].


Unwrap 9-49


9-50 Unwrap

Chapter 10: Numeric Synthesizable DSPComponents

Introduction

The numeric synthesizable DSP components provide digital signal processingfunctions on single data points of data that are fixed-point (fixed). These componentsdo not accept any matrix class of signal.

If a component receives another class of signal, the received signal is automaticallyconverted to the signal class specified as the input of the component. Auto conversionfrom a higher to a lower precision signal class may result in loss of information. Theauto conversion from timed, complex or floating-point (real) signals to a fixed signaluses a default bit width of 32 bits with the minimum number of integer bits needed torepresent the value. For example, the auto conversion of the floating-point (real)value of 1.0 creates a fixed-point value with precision of 2.30; a value of 0.5 wouldcreate one of precision of 1.31. For details on conversions between different classes ofsignals, refer to “Conversion of Data Types” in the ADS Ptolemy Simulation manual.

These components are used for simulating fixed-point designs and for designimplementation using the DSP Synthesis and HDL Code Generation tools.

Synthesizable DSP components (such as registers, counters, shift registers) that haveclock inputs have the following simulation behavior depending on whether clockinputs are connected or not. If clock is not connected, then each simulation step istaken as a positive clock edge; for example, if the data register RegSyn clock is notconnected, then RegSyn simulates a a unit-step delay. If clock is connected, then thecomponent will simulate according to the clock input state; for example, if the dataregister RegSyn clock is connected, then RegSyn simulates as a positive edge clocksensitive register.

Synthesizable DSP components (such as registers, counters, and shift registers) thathave set inputs have the following simulation behavior depending on whether the setinputs are connected or not. If the set input is not connected, then the component isreset at the first simulation step. If the set input is connected, then the componentwill simulate according to the set input state.

For synthesizable DSP components that perform math operations (such as adders,subtractors, gain blocks, and filters), the ArithType parameter specifies thearithmetic type of the output signal and can be set to TWOS_COMPLEMENT or

10-1

Numeric Synthesizable DSP Components

UN_SIGNED values. When the input fixed-point signal has an arithmetic type thatis not the same as ArithType, the bit pattern representing the input number will beinterpreted in the arithmetic defined by ArithType. This can lead to unexpectedresults; therefore, arithmetic types should not be mixed when performing mathoperations.

For design implementation, a design network consisting of synthesizable DSPcomponents can be sent to the DSP synthesis or HDL code generation tool. Anyunconnected clock input pins will be connected up to a global clock signal after DSPsynthesis or HDL code generation. Similarly, any unconnected Set input pins will beconnected up to a global reset signal after DSP synthesis or HDL code generation.

10-2 Introduction

AbsSyn

Description AbsoluteLibrary Numeric, Synthesizable DSPClass SDFAbsSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. AbsSyn presents an output with the absolute value of the given data input.



TRUNCATE enum

OutputPrecision precision of the output inbits

2.14 precision

ArithType arithmetic type of output:TWOS_COMPLEMENT,UN_SIGNED

TWOS_COMPLEMENT

enum

OvflowType overflow characteristic fordevice: WRAPPED,SATURATE

WRAPPED enum


1 Data fix


2 Result fix

AbsSyn 10-3


2. OutputPrecision specifies the fixed-point precision format of the output. Forexample, if OutputPrecision=1.15, 1 bit is used for representing the integer partof the output, and 15 bits are used to represent the fractional portion of theoutput.

3. For information regarding numeric synthesizable DSP functions refer to the“Introduction” on page 10-1.

10-4 AbsSyn

AddSyn

Description Adder/SubtractorLibrary Numeric, Synthesizable DSPClass SDFAddSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs



TRUNCATE enum


2.14 precision


TWOS_COMPLEMENT

enum


WRAPPED enum

AddSub enumeration state: ADD,SUBTRACT

ADD enum


1 A fix

2 B fix

3 Sub fix


4 Result fix

AddSyn 10-5


Notes/Equations

1. The add/sub control input pin is optional.

• If the add/sub control input pin is not connected, the AddSub parameter isused to specify whether the adder adds or subtracts.

• If the add/sub control input pin is connected: a zero value indicates add; anon-zero value indicates subtract. (The AddSub parameter is ignored in thiscase.)

2. OutputPrecision specifies the fixed-point precision format of the output. Forexample, if OutputPrecision=1.15, 1 bit is used to represent the integer part ofthe output, and 15 bits are used to represent the fractional portion of theoutput.

3. When AddSub is used as an adder, out = A + B; when AddSub is used as asubtractor, out = A − B.

4. Bit alignment is automatic at the inputs so the two input values are addedcorrectly. This is done by zero padding or sign extending the inputs such thattheir decimal points are aligned.

5. When the arithmetic type of an input to AddSyn is different from the ArithTypeparameter of AddSyn, then AddSyn interprets the input bit pattern in thearithmetic type specified by the ArithType parameter. For example, assumethat the ArithType of AddSyn is TWOS_COMPLEMENT and that one of itsinputs is 0.7 represented in unsigned arithmetic and 0.8 precision. Thecorresponding bit pattern is 10110011 (1 × 1/2 + 0 × 1/4 + 1 × 1/8 + 1 × 1/16 +0 × 1/32 + 0 × 1/64 + 1 × 1/128 + 1 × 1/256 = 0.69921875).

In two’s complement this bit pattern represents a negative number since thefirst bit is 1. To get the magnitude of this number we first complement the bitsto get 01001100 and then add 1 to get 01001101. Therefore, this bit pattern hasa value of -(0 × 1/2 + 1 × 1/4 + 0 × 1/8 + 0 × 1/16 + 1 × 1/32 + 1 × 1/64 + 0 × 1/128+ 1 × 1/256 = 0.30078125), and this is the value that AddSyn will use.

Thus, arithmetic types should not be mixed when adding or subtractingfixed-point numbers.


10-6 AddSyn

AndSyn

Description Bitwise ANDLibrary Numeric, Synthesizable DSPClass SDFAndSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The input bus is composed of Size number of smaller bus segments. Each bussegment within the input bus is of bitwidth Width. AndSyn performs a bitwiseAND of the bus segments resulting in the output Result of bitwidth Width. Forexample, Width=8, Size=2 means that the input bus is interpreted as having 2bus segments, each of bitwidth 8. The output of AndSyn is the bitwise AND ofthe 2 bus segments, as illustrated in Figure 10-1.


Width size of a bus segmentwithin the input bus

8 int

Size number of bus segmentswithin the input bus

2 int


1 Data fix


2 Result fix

AndSyn 10-7


Figure 10-1. Width=8, Size=2

2. An example design where two 8-bit signals are ANDed together is shown inFigure 10-2.

Figure 10-2. AndSyn Example Design


10-8 AndSyn

And2Syn

Description 2-input ANDLibrary Numeric, Synthesizable DSPClass SDFAnd2SynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a 2-input AND gate that takes a bitwise AND of inputs A and B(both of bitwidth Width) and outputs the results; that is, Result = A and B.



Width Width of an input bus. 8 int


1 A fix

2 B fix


3 Result fix

And2Syn 10-9


BPSKSyn

Description BPSK EncoderLibrary Numeric, Synthesizable DSPClass SDFBPSKSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The output signal Result of the BPSK encoder is a twos-complement fixed-pointnumber with 1 sign bit and (Width −1) fractional bits.

An input bit value of 1 is mapped to the most positive-valued fixed-pointnumber that can be represented by 1 sign bit and (Width-1) fractional bits.Conversely, an input bit value of 0 is mapped to the next-to-mostnegative-valued fixed-point number that can be represented by 1 sign bit and(Width-1) fractional bits. This ensures that the positive and negative valuedoutputs of the model have the same magnitude.


Width bit width of encoder output 8 int


1 Data fix


2 Result fix

10-10 BPSKSyn

For example, with Width = 8, mapping will be done in the following manner:

• input bit value of 1 will be mapped to 01111111

• input bit value of 0 will be mapped to 10000001


BPSKSyn 10-11


BarShiftSyn

Description Barrel ShifterLibrary Numeric, Synthesizable DSPClass SDFBarShiftSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs



2.14 precision


TWOS_COMPLEMENT

enum

Mode type of shifting:LOGICAL_SHIFT,ARITHMETIC_SHIFT,ROTATE_SHIFT

LOGICAL_SHIFT enum

Direction direction of shift in thebarrel shifter:RIGHT_SHIFT,LEFT_SHIFT

LEFT_SHIFT enum

NShift number of bit positions toshift by

0 int


1 Data Input data fix

2 Dist Dist control input for how many bits to shift by fix


3 Result Barrel shift result fix

10-12 BarShiftSyn

Notes/Equations

1. BarShiftSyn shifts the input bits by the amount specified by the control inputDist or (if Dist is not connected) by the integer parameter NShift. The outputbit width, number of integer bits, and arithmetic type are set by the parametersof the barrel shifter.

• Logical shifting to the right(Mode=LOGICAL_SHIFT, Direction=RIGHT_SHIFT)inserts zeros in the vacated most significant bits; logical shifting to the left(Mode=LOGICAL_SHIFT, Direction=LEFT_SHIFT)is the same as Arithmetic shifting to the left.

• Arithmetic shifting to the right(Mode=ARITHMETIC_SHIFT, Direction=RIGHT_SHIFT)will sign extend the vacated most significant bits.

• Rotate shifting to the right(Mode=ROTATE_SHIFT, Direction=RIGHT_SHIFT)will shift the least significant bits into the vacated most significant bits.Conversely, Rotate shifting to the left(Mode=ROTATE_SHIFT, Direction=LEFT_SHIFT)will shift the most significant bits into the vacated least significant bits.


3. Direction of shifting is done assuming that the MSB is on the left and LSB is onthe right. LEFT_SHIFT will shift towards the MSB. Conversely, RIGHT_SHIFTwill shift towards the LSB.


BarShiftSyn 10-13


BitFillSyn

Description Bit FillLibrary Numeric, Synthesizable DSPClass SDFBitFillSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. BitFillSyn takes the single bit input and copies it to an output bus of bitwidthWidth. It replicates the single bit input value to the output bus.



Width size of output bus 1 int


1 Data fix


2 Result fix

10-14 BitFillSyn

BufferSyn

Description BufferLibrary Numeric, Synthesizable DSPClass SDFBufferSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. BufferSyn inverts the bits within the input bus based on the InvMaskparameter; 1 in a bit position in InvMask will invert the corresponding bit inthe input bus.

InvMask can be specified in hex (0x prefix), octal (0 prefix),binary (0b prefix), or decimal (without a 0 prefix). For example, if Width=2:

• to invert both inputs bits, specify: InvMask=0x3 (hex), InvMask=03 (octal),InvMask=0b11 (binary), InvMask=3 (decimal).


Width number of bits in input 16 int

InvMask bit mask pattern 0 int


1 Data fix


2 Result fix

BufferSyn 10-15


• to invert the LSB of the two input bits, specify: InvMask=0x1 (hex),InvMask=01 (octal), InvMask=0b01 (binary), InvMask=1 (decimal).


10-16 BufferSyn

Bus8MergeSyn

Description 8-Bit-to-Bus MergeLibrary Numeric, Synthesizable DSPClass SDFBus8MergeSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Bus8MergeSyn merges its eight 1-bit inputs into a bus.


Width number of bits in outputbus

int


1 Data0 fix

2 Data1 fix

3 Data2 fix

4 Data3 fix

5 Data4 fix

6 Data5 fix

7 Data6 fix

8 Data7 fix


9 Output fix

Bus8MergeSyn 10-17


2. The most significant bit in the output bus is taken from the 1-bit Data7 inputpin; the next most significant bit is taken from the 1-bit Data6, and so on.

3. Width parameter specifies the size of the output bus. Input pins must beconnected to the appropriate Width. For example: if Width=1, Data7 isconnected; if Width=5, input pins Data7, Data6, Data5, Data4, and Data3 mustall be connected.


10-18 Bus8MergeSyn

Bus8RipSyn

Description Bus-to-8-Bit RipperLibrary Numeric, Synthesizable DSPClass SDFBus8RipSynDerived From SDFHPFix

Pin Inputs

Pin Outputs

Notes/Equations

1. Bus8RipSyn rips out the highest byte in the data input bus and outputs themas 1-bit outputs.

2. The most significant bit in the data input bus is output on the pin markedOutput7; correspondingly, the least significant bit in the data input bus isoutput on the pin marked Output0.


1 Data fix


2 Output0 fix

3 Output1 fix

4 Output2 fix

5 Output3 fix

6 Output4 fix

7 Output5 fix

8 Output6 fix

9 Output7 fix

Bus8RipSyn 10-19



10-20 Bus8RipSyn

BusMergeSyn

Description Bus MergeLibrary Numeric, Synthesizable DSPClass SDFBusMergeSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. BusMergeSyn merges the two input buses A and B into a larger, merged bus.

In the merged bus, A will be located in the MSB portion, while B will be locatedin the LSB portion.

2. The output bitwidth is specified by Width and must be equal to the sum of thetwo input bitwidths.

3. The output arithmetic type is always unsigned, Width number of integer bits, 0fractional bits.


Width bitwidth of output 0 int


1 A fix

2 B fix


3 Result fix

BusMergeSyn 10-21



10-22 BusMergeSyn

BusRipSyn

Description Bus RipperLibrary Numeric, Synthesizable DSPClass SDFBusRipSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



2.14 precision


TWOS_COMPLEMENT

enum

Offset how far to right of MSB(Sign bit forTWOS_COMPLEMENT) totake ripped bit_vector

0 int

RipPrecision precision of ripped-outsegment of input bus

2.6 precision


1 Data fix


2 Result fix

3 PassThru fix

BusRipSyn 10-23


1. BusRipSyn rips out a smaller contiguous bit vector (Fix) from the input bitvector (Fix).

2. The arithmetic type of the RIP output is the same as ArithType.



10-24 BusRipSyn

CastSyn

Description CastLibrary Numeric, Synthesizable DSPClass SDFCastSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. CastSyn copies the bits within the input bus to the output bus. It does not alterthe input bits, but only changes the precision and arithmetic type associatedwith the input bits. The total number of output bits should be the same as theinput.

2. OutputPrecision specifies the fixed-point precision format of the output. Forexample, if OutputPrecision=1.15, 1 bit is used for representing the integer part



2.14 precision


TWOS_COMPLEMENT

enum


1 Data fix


2 Result fix

CastSyn 10-25


of the output, and 15 bits are used to represent the fractional portion of theoutput.


10-26 CastSyn

CombFiltSyn

Description Comb FilterLibrary Numeric, Synthesizable DSP : XilinxClass SDFCombFiltSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model implements the transfer function of (1-z-M) which comprises thecomb section of a comb filter, where M = PipeStages. In other words, a delayed



2.14 precision


TWOS_COMPLEMENT

enum

PipeStages Depth of pipeline, must be> 0.

1 int


1 Data Data input fix

2 Clock Clock input -- optional control pin fix

3 CE Clock enable input -- optional control pin fix


4 Result Comb Filter output fix

CombFiltSyn 10-27


version of the input data value (PipeStages clocks previously) is subtractedfrom the present input data value. In discrete equation form, it can berepresented as:

Result = Data - Data(Delayed_by_M_clocks)

Figure 10-3. Internal Structure of Comb Section Model


10-28 CombFiltSyn

CompSyn

Description CompareLibrary Numeric, Synthesizable DSPClass SDFCompSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



TWOS_COMPLEMENT

enum

Mode condition to be tested:EQUAL,LESS_OR_EQUAL,GREATER_OR_EQUAL

EQUAL enum


1 A fix

2 B fix


3 Result fix

4 ResultB fix

CompSyn 10-29


1. CompSyn compares the value as represented by the two inputs and tests for thecondition specified by Mode. If the condition is TRUE, the output out will go

HIGH and the output will go LOW.

2. Comparison modes are: A=B, A ≤ B, A ≥ B.


out

10-30 CompSyn

Comp6Syn

Description Compare with 6 OutputsLibrary Numeric, Synthesizable DSPClass SDFComp6SynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Comp6Syn compares the value as represented by the two inputs and tests forsix conditions. If a condition is TRUE, the output result is a 1, else 0.



TWOS_COMPLEMENT

enum


1 A fix

2 B fix


3 GT fix

4 GE fix

5 LT fix

6 LE fix

7 EQ fix

8 NE fix

Comp6Syn 10-31


2. Comparison modes are: A ≠ B, A=B, A ≤ B, A < B, A ≥ B, A > B.


10-32 Comp6Syn

ConstSyn

Description ConstantLibrary Numeric, Synthesizable DSPClass SDFConstSynDerived From SDFHPFix

Parameters

Pin Outputs

Notes/Equations

1. ConstValue is converted to the precision and type specified by OutputPrecisionand ArithType.





2.14 precision


TWOS_COMPLEMENT

enum

ConstValue constant value of device,specified as a real value

1.0 real


1 Result fix

ConstSyn 10-33


CountCombSyn

Description Counter Combinational LogicLibrary Numeric, Synthesizable DSPClass SDFCountCombSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. CountCombSyn models the combinational logic portion of a Johnson, LFSR(linear feedback shift register), or Gray counter. Usage is illustrated.


Width size of counter 8 int

CounterType type of counter:JOHNSON_CTR,LFSR_CTR, GRAY_CTR

JOHNSON_CTR enum

LFSR_Poly LFSR polynomial to beused in LFSR counter

0xff string


1 Data fix


2 Result fix

10-34 CountCombSyn

2. LFSR_Poly sets the LFSR polynomial to be used whenCounterType=LFSR_CTR. It is specified as a hex string; for example,LFSR_Poly=0xFE.


CountCombSyn 10-35


CounterSyn

Description Binary CounterLibrary Numeric, Synthesizable DSPClass SDFCounterSynDerived From SDFHPFix

Parameters

Pin Inputs


Width size of binary counter 16 int

ValueS value of counter when Setis asserted (low)

0 int


1 Clock Clock signal -- if connected, counter is positive edgetriggered on clock transitions.

If un-connected, counter increments atevery simulation step

fix

2 CE Clock Enable signal -- if connected and asserted(high) enables counter when asserted (high). If un-connected, default is for counterto be always enabled

fix

3 Up Up/Down control signal -- if connected and asserted(high) counter counts up.

If un-connected, default is to for counterto count up.

fix

4 Set Set/Reset control signal -- if connected and asserted(low) counter resets asynchronously to 0.

If un-connected, counter is never resetexcept initially.

fix

10-36 CounterSyn

Pin Outputs

Notes/Equations

1. The Binary Counter is positive-edge clock triggered when the CE pin is asserted(high).

2. The control pins are optional—they do not have to be connected.

3. ValueS can be specified in hex (0x prefix), octal (0 prefix),binary (0b prefix), or decimal (without a 0 prefix).

For example, to specify a ValueS of decimal value 31, setValueS=31 (decimal), ValueS=0x1F (hex), ValueS=037 (octal), orValueS=0b11111 (binary).



5 Q Counter output signal -- parallel data. fix

CounterSyn 10-37


DPRamSyn

Description Dual-Port RAMLibrary Numeric, Synthesizable DSPClass SDFDPRamSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs



2.14 precision


TWOS_COMPLEMENT

enum

Depth size of (number of wordsin) RAM

16 int

ramFile name of file containinginitial RAM values(optional) (represented inhex data format in file)

filename


1 AddrR input read address fix

2 AddrW input write address fix

3 Data input data fix

4 WE write enable input: if low, then the input data iswritten to the RAM location specified by AddrW.

fix


5 Q output data fix

10-38 DPRamSyn

Notes/Equations

1. DPRamSyn models a dual-port RAM. Data in the RAM can be initialized byspecifying the file name in the ramFile parameter.

2. The path name for ramFile can be specified in several ways: one is to justspecify the file name, for example ramFile=foo, which is assumed to be locatedwithin the current project data directory; another is by specifying the absolutepath, as in ramFile=/usr/user_name/foo; or, the environmental variables canalso be used to set the file path name, for example ramFile=$ENV_FOO/foo,where ENV_FOO is an environmental variable.

3. The bitwidths and arithmetic type of the output data are defined by the deviceparameters. The size of the RAM is specified by the Depth parameter. Anexample file format is:

0x010xff0xca...and so on.

4. The data format in the file is assumed to be right-justified.

5. DPRamSyn is not intended to be synthesizable but only simulatable.



DPRamSyn 10-39


DPSKSyn

Description Differential BPSK EncoderLibrary Numeric, Synthesizable DSPClass SDFDPSKSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The output signal Result of the DPSK encoder is a twos-complement fixed-pointnumber with 1 sign bit and (Width-1) fractional bits.

The 1-bit input data is clocked (positive edge triggered) into a 2-deep FIFObuffer. Values of the 2-deep FIFO buffer are XORed together to get thedifferential output bit result. A resulting bit value of 1 (after the XOR operationon the 2 data bits in the FIFO buffer) is mapped to the most positive-valued


Width bit width of encoderoutputs

8 int


1 Data fix


3 Set Asynchronous set/reset input -- optional control pin fix


4 Result fix

10-40 DPSKSyn

fixed-point number that can be represented by 1 sign bit and (Width-1)fractional bits. Conversely, a resulting bit value of 0 is mapped to thenext-to-most negative-valued fixed-point number that can be represented by 1sign bit and (Width-1) fractional bits.

This ensures that the positive and negative valued outputs of the model havethe same magnitude.

Assertion of the Set input (a low value, i.e. 0) will clear the values of the FIFObuffers.

For example, with Width = 8, with an input bit sequence of 0 1 (with 0 beingolder, and 1 being the most recent), and assuming that initially the encoder isreset, the following will result:

• first input bit 0 will result in the XOR output of 00 = 0, which maps to10000001

• second input bit 1 will result in the XOR output of 10 = 1, which maps to01111111


DPSKSyn 10-41


Div2ClockSyn

Description Power-of-2 Clock DividerLibrary Numeric, Synthesizable DSPClass SDFDiv2ClockSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a divide-by-power-of-2 clock divider; options are to divide by 2, 4,8, or 16.



DivideBy Value to divide input Clockby.: TWO, FOUR, EIGHT,SIXTEEN

TWO enum


1 InClock Clock input fix



3 DivClock Clock output fix

10-42 Div2ClockSyn

FSMSyn

Description Mealy Finite State Machine (FSM)Library Numeric, Synthesizable DSPClass SDFFSMSynDerived From SDFHPFix

Parameters

Pin Inputs


fsmFile File containing Mealy FSMdefinition

user_defined.fsm filename

InputWidth Bit width of data input ofMealy FSM

1 int

StateWidth Bit width of state register ofMealy FSM

1 int

OutputWidth Bit width of output of MealyFSM

1 int

fsmFileFormat Format of Mealy FSMdefinition file: HEX,OCTAL, DECIMAL

HEX enum

Depth Number of row entries inFSM definition file

1 int

ResetStateVal Reset State Value 0 int

DefaultStateVal Default State Value 0 int

DefaultOutVal Default Output Value 0 int


1 Data fix


3 Reset Asynchronous set/reset input -- optional control pin fix

FSMSyn 10-43


Pin Outputs

Notes/Equations

1. This model implements a Mealy finite state machine. The state transitions andoutput values of the Mealy FSM are defined in the file specified in the fsmFileparameter. The format of the entries within the Mealy FSM definition file canbe hex (0x01FE, for example), octal (016, for example), or decimal (230, forexample).

Each line in the file contains the following entries separated by at least a space:the first entry is the input data value; the second entry is the present statevalue; the third entry is the next state value; the final entry is the output value.Thus, each line in the FSM definition file should look like:

input_data present_state next_state output

Consider the example of a Mealy FSM definition file entries:

• The first line in the example file specifies that given an input of 0x01, and apresent state of 0x00, the next state of the FSM will be 0x01, and the outputis 0x1.

• The second line specifies that given an input of 0x00, and a present state of0x00, the next state of the FSM will be 0x00, and the output is 0x0.

• The third line specifies that given an input of 0x01, and a present state of0x01, the next state of the FSM will be 0x02, and the output is 0x0. It shouldbe clear how the definition file is interpreted by the model from this example.

Any input and state combinations that are not covered by the Mealy FSMdefinition file will be covered by the default state and output values as specifiedin model parameters DefaultStateVal and DefaultOutVal.


4 Result fix

5 OutState fix

0x01 0x00 0x01 0x1

0x00 0x00 0x00 0x0

0x01 0x01 0x02 0x0

0x00 0x01 0x01 0x1

10-44 FSMSyn

The state of the Mealy FSM can be initialized to a known reset state byasserting the Reset input (by giving it a low value of 0) which will set the stateof the Mealy FSM to the value specified in model parameter ResetStateVal.

The values for parameters DefaultStateVal, DefaultOutVal, and ResetStateValcan be specified in decimal form (for example, DefaultOutVal = 15), or in hexform (for example, DefaultStateVal = 0x001).


FSMSyn 10-45


FixToFloatSyn

Description Fixed-Point to Floating-PointLibrary Numeric, Synthesizable DSPClass SDFFixToFloatSynDerived From SDFHPFix

Pin Inputs

Pin Outputs

Notes/Equations

1. FixToFloatSyn converts a fixed-point input to a floating-point (real) output.



1 Data Input fix type fix


2 Result Output float type real

10-46 FixToFloatSyn

FloatToFixSyn

Description Floating-Point to Fixed-PointLibrary Numeric, Synthesizable DSPClass SDFFloatToFixSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



TRUNCATE enum


2.14 precision


TWOS_COMPLEMENT

enum


WRAPPED enum


1 Data Input float type real


2 Result Output fix type fix

FloatToFixSyn 10-47


1. FloatToFixSyn converts a floating-point (real) input to a fixed-point output. Itquantizes by rounding and it saturates upon overflow.



10-48 FloatToFixSyn

GainSyn

Description GainLibrary Numeric, Synthesizable DSPClass SDFGainSynDerived From SDFHPFix

Parameters

Pin Inputs



TRUNCATE enum


2.14 precision


TWOS_COMPLEMENT

enum


WRAPPED enum

Gain gain of device specified asa real value. It is convertedto the precision ofGainPrecision of ArithTypearithmetic

1.0 real

GainPrecision precision of gain in bits andprecision of accumulation.When the gain valueextends outside of theprecision, the overflow typeis called

2.14 precision


1 Data fix

GainSyn 10-49


Pin Outputs

Notes/Equations

1. GainSyn models a gain block that multiplies the input value by the specifiedGain (quantized by GainPrecision) and outputs the result at the specifiedOutputPrecision.

2. OutputPrecision specifies the fixed-point precision format of the output: ifOutputPrecision=1.15, 1 bit is used to represent the integer part of the output,and 15 bits are used to represent the fractional portion of the output.



2 Result fix

10-50 GainSyn

LCounterSyn

Description Loadable Binary CounterLibrary Numeric, Synthesizable DSPClass SDFLCounterSynDerived From SDFHPFix

Parameters

Pin Inputs


Width size of binary counter 16 int

ValueS value to which the counteris set when Set is asserted(high)

0 int


1 Data Input data signal fix

2 Clock Clock signal -- if connected, counter is positive edgetriggered on clock transitions.

If un-connected, counter increments atevery simulation step

fix

3 CE Clock Enable signal -- if connected and asserted(high) enables counter when asserted (high). If un-connected, default is for counterto be always enabled

fix

4 Up Up/Down control signal -- if connected and asserted(high) counter counts up.

If un-connected, default is to for counterto count up.

fix

LCounterSyn 10-51


Pin Outputs

Notes/Equations

1. LCounterSyn is positive-edge clock triggered when the count enabled pin isasserted (high).

2. The control pins are optional—they do not have to be connected.




5 Set Set/Reset control signal -- if connected and asserted(low) counter resets asynchronously to 0.

If un-connected, counter is never resetexcept initially.

fix

6 Load Load control signal -- if connected and asserted(low) counter loads Data input. If un-connected, counter never loadsData input.

fix


7 Q Counter output signal -- parallel data. fix


10-52 LCounterSyn

MultSyn

Description MultiplierLibrary Numeric, Synthesizable DSPClass SDFMultSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



TRUNCATE enum


2.14 precision


TWOS_COMPLEMENT

enum


WRAPPED enum


1 A fix

2 B fix


3 Result fix

MultSyn 10-53


1. MultSyn multiplies two data inputs.



10-54 MultSyn

MuxSyn

Description MuxLibrary Numeric, Synthesizable DSPClass SDFMuxSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The input bus is composed of Size number of smaller bus segments. Each bussegment within the input bus is of bitwidth Width. MuxSyn selects one of theSize bus segments and outputs it as result. The sel input is used to controlwhich bus segment is selected. A value of 0 in sel will select the least significant


Width size of bus segment withinthe input bus

8 int


2 int

WidthS bit width of select controlinput

1 int


1 Data fix

2 Sel fix


3 Result fix

MuxSyn 10-55


bus segment; a value of 1 will select the next-to-least-significant bus segment,and so on. Refer to Figure 10-4.

Figure 10-4. Width=8, Size=2, WidthS=1


10-56 MuxSyn

Mux2Syn

Description 2-input MultiplexerLibrary Numeric, Synthesizable DSP : XilinxClass SDFMux2SynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a 2-input multiplexer. It selects input Data0 or Data1 dependingon the value of its Sel input. If the Sel input value is 0 (low value), Data0 isassigned to its output Result; if the Sel input value is 1 (high value), Data1 isassigned to its output Result.





1 Data0 fix

2 Data1 fix

3 Sel fix


4 Result fix

Mux2Syn 10-57


Mux3Syn


Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a 3-input multiplexer. It selects one of 3 inputs Data0, or Data1 orData2 depending on the value of its Sel0 and Sel1 inputs given in Table 10-1,




1 Data0 fix

2 Data1 fix

3 Data2 fix

4 Sel0 fix

5 Sel1 fix


6 Result fix

10-58 Mux3Syn


Table 10-1. Data Selection

Sel1 Sel0 Result

0 0 Data0

0 1 Data1

1 0 Data2

1 1 invalid input

Mux3Syn 10-59


Mux4Syn


Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a 4-input MUX; it selects input Data0, Data1, Data2, or Data3based on the values of inputs Sel0 and Sel1 given in Table 10-2.




1 Data0 fix

2 Data1 fix

3 Data2 fix

4 Data3 fix

5 Sel0 fix

6 Sel1 fix


7 Result fix

10-60 Mux4Syn



Sel1 Sel0 Result

0 0 Data0

0 1 Data1

1 0 Data2

1 1 Data3

Mux4Syn 10-61


Nand2Syn

Description 2-input NANDLibrary Numeric, Synthesizable DSPClass SDFNand2SynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a 2-input NAND gate, which takes a bitwise NAND of inputs Aand B (both of bitwidth Width) and outputs the results, that is,Result = A NAND B.




8 int


1 A fix

2 B fix


3 Result fix

10-62 Nand2Syn

Nor2Syn

Description 2-input NORLibrary Numeric, Synthesizable DSPClass SDFNor2SynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a 2-input NOR gate. It takes a bitwise NOR of inputs A and B,(both of bitwidth Width) and outputs the results, that is, Result = A NOR B.




8 int


1 A fix

2 B fix


3 Result fix

Nor2Syn 10-63


NotSyn

Description NOTLibrary Numeric, Synthesizable DSPClass SDFNotSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a NOT gate. It takes a bitwise NOT of input Data and outputs theresults, that is, Result = NOT(Data).




8 int


1 Data fix


2 Result fix

10-64 NotSyn

OQPSKSyn

Description Offset QPSK EncoderLibrary Numeric, Synthesizable DSPClass SDFOQPSKSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The output signals of the OQPSK encoder are 2 twos-complement fixed-pointnumbers with 1 sign bit and (Width −1) Iout and Qout fractional bits.

The In-phase data input DataI is clocked into an internal register (in the modelwe will call dataireg) on the positive Clock edge, while the Quadrature-phase



8 int


1 DataI fix

2 DataQ fix

3 Clock fix



5 Iout fix

6 Qout fix

OQPSKSyn 10-65


data input DataQ is clocked into its internal register (in the model we will calldataqreg) on the negative Clock edge (that is, a half symbol time later).

Assertion of the Set input (a low value, that is, 0) will clear the values of theinternal data registers.

For each dataireg or dataqreg bit value of 1, a mapping to the fixed-pointnumber (represented by a 1 sign bit and (Width −1) fractional bits) closest to thenegative value of the square root of 1/2 (that is, −0.7071067811..) is done.Conversely, for each dataireg or dataqreg bit value of 0, a mapping to the fixedpoint number (represented by a 1 sign bit and (Width −1) fractional bits) closestto the square root of 1/2 (that is, +0.7071067811..) is done.

For example, with Width = 8, mapping will be done in the following manner.

Note that, with 1 sign bit and 7 fractional bits twos-complement:

• 01011011 corresponds to 0.7109375

• 10100101 corresponds to −0.7109375


dataireg dataqreg --> Output Iout Output Qout

0 0 --> 01011011 01011011

0 1 --> 01011011 10100101

1 0 --> 10100101 01011011

1 1 --> 10100101 10100101

10-66 OQPSKSyn

Or2Syn

Description 2-input ORLibrary Numeric, Synthesizable DSPClass SDFOr2SynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a 2-input OR gate. It takes a bitwise OR of its inputs A and B(both of bitwidth Width) and outputs the results, that is, Result = A OR B.




8 int


1 A fix

2 B fix


3 Result fix

Or2Syn 10-67


OrSyn

Description Bitwise ORLibrary Numeric, Synthesizable DSPClass SDFOrSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The input bus is composed of Size number of smaller bus segments. Each bussegment within the input bus is of bitwidth Width. OrSyn performs a bitwiseOR of the bus segments resulting in the output result of bitwidth Width. Forexample, if Width=8, Size=2 means that the input bus is interpreted as having2 bus segments, each of bitwidth 8. The output of OrSyn is the bitwise OR of the2 bus segments, as illustrated in Figure 10-5.


Width size of bus segment withininput bus

8 int

Size number of bus segmentswithin input bus

2 int


1 Data fix


2 Result fix

10-68 OrSyn


2. An example design where two 8-bit signals are ORed together is shown inFigure 10-6.

Figure 10-6. OrSyn Example Design


OrSyn 10-69


PI4DQPSKSyn

Description Pi/4 DQPSK EncoderLibrary Numeric, Synthesizable DSPClass SDFPI4DQPSKSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The 2 output signals of the π/4-DQPSK encoder are twos-complement fixed-point numbers with 1 sign bit and (Width-1) fractional bits Iout and Qout.

In-phase and Quadrature-phase data inputs DataI, DataQ are clocked intointernal registers on the positive Clock edge. Outputs Iout and Qout are rotated



8 int


1 DataI fix

2 DataQ fix

3 Clock fix



5 Iout fix

6 Qout fix

10-70 PI4DQPSKSyn

in phase increments that are multiples of π/4 (that is, multiples of 45 degrees)depending on the values of DataI and DataQ. Phase rotations are specified inTable 10-3.

Assertion of the Set input (a low value, i.e. 0) will clear the values of theinternal registers of the model and the outputs (Iout, Qout) are set to the fixedpoint numbers closest to the value of (sqrt(1/2), sqrt(1/2)), where sqrt(1/2)denotes the square root of 1/2 (as close as can be represented by 1 sign bit and(Width-1) fractional bits in twos-complement).


Table 10-3. Phase Rotations

Input DataI Input DataQ Rotate (Iout, Qout) by

0 0 +π/4 ( +45 deg)

0 1 −π/4 ( −45 deg)

1 0 +3π/4 ( +135 deg)

1 1 −3π/4 ( -135 deg)

PI4DQPSKSyn 10-71


PSK8Syn

Description 8-PSK EncoderLibrary Numeric, Synthesizable DSPClass SDFPSK8SynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. Output signals of the 8-PSK encoder are 2 twos-complement fixed-pointnumbers with 1 sign bit and (Width-1) fractional bits, Iout and Qout. The 3-bitinput Data is mapped to the Iout and Qout outputs according to Table 10-4.



8 int


1 Data fix


2 Iout fix

3 Qout fix

10-72 PSK8Syn

For example, with Width = 8, mapping will be done in the following manner:


• 01011011 corresponds to 0.7109375

• 10100101 corresponds to -0.7109375

• 01111111 corresponds to 1.0- 2-7

• 10000001 corresponds to -1.0 + 2-7


Table 10-4. Data Mapping

Input Data Iout (real-value) Qout (real-value)

000 value closest to +sqrt(1/2) value closest to +sqrt(1/2)

001 0.01.0 - 2-(Width-1)

010 -sqrt(1/2) +sqrt(1/2)

011-1.0 + 2-(Width-1) 0.0

100 -sqrt(1/2) -sqrt(1/2)

101 0.0 -1.0 + 2-(Width-1)

110 +sqrt(1/2) -sqrt(1/2)

1111.0 - 2-(Width-1) 0.0

Input DataIout(twos-complement binary)

Qout(twos-complement binary)

000 01011011 01011011

001 00000000 01111111

010 10100101 01011011

011 10000001 00000000

100 10100101 10100101

101 00000000 10000001

110 01011011 10100101

111 01111111 00000000

PSK8Syn 10-73


QPSKSyn

Description QPSK EncoderLibrary Numeric, Synthesizable DSPClass SDFQPSKSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The output signals of the QPSK encoder are 2 twos-complement fixed-pointnumbers with 1 sign bit and (Width −1) fractional bits, Iout and Qout.

For each DataI or DataQ input bit value of 1, a mapping to the fixed-pointnumber (represented by a 1 sign bit and (Width −1) fractional bits) closest to thenegative value of the square root of 1/2 (that is, −0.7071067811..) is done.Conversely, for each DataI or DataQ input bit value of 0 a mapping to the fixed



8 int


1 DataI fix

2 DataQ fix


3 Iout fix

4 Qout fix

10-74 QPSKSyn

point number (represented by a 1 sign bit and (Width-1) fractional bits) closestto the square root of 1/2 (that is, +0.7071067811..) is done.

For example, with Width = 8, mapping will be done as in Table 10-5.


• 01011011 corresponds to 0.7109375

• 10100101 corresponds to −0.7109375


Table 10-5.

Input DataI Input DataQ --> Output Iout Output Qout

0 0 --> 01011011 01011011

0 1 --> 01011011 10100101

1 0 --> 10100101 01011011

1 1 --> 10100101 10100101

QPSKSyn 10-75


RamSyn

Description RAMLibrary Numeric, Synthesizable DSPClass SDFRamSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs



2.14 precision


TWOS_COMPLEMENT

enum

Depth size of (number of wordsin) RAM

16 int

ramFile name of file containinginitial RAM values(optional) (represented inhex data format in file)

filename


1 Addr input address fix


3 WE write enable input: if low then the input Data iswritten into the RAM location specified by Addr.

fix


4 Q output data fix

10-76 RamSyn

Notes/Equations

1. RamSyn models the RAM. Data in the RAM can be initialized by specifying thefile name in the ramFile parameter.

2. The path name for ramFile can be specified in several ways: one is to justspecify the file name, for example ramFile=foo, which is assumed to be locatedwithin the current project data directory; another is to specify the absolutepath, as in ramFile=/usr/user_name/foo; or, the environmental variables canalso be used to set the file path name, for example ramFile=$ENV_FOO/foo,where ENV_FOO is an environmental variable.

3. The bitwidths and arithmetic type of the output data are defined by the deviceparameters. The size of the RAM is specified by the Depth parameter. Anexample file format is:

0x010xff0xca...and so on.


5. RamSyn is not intended to be synthesizable but only simulatable.



RamSyn 10-77


RegSyn

Description Data RegisterLibrary Numeric, Synthesizable DSPClass SDFRegSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



2.14 precision


TWOS_COMPLEMENT

enum

ValueS value loaded into theregister when the Setcontrol pin is asserted

0 int







5 Q Register data output fix

10-78 RegSyn

1. RegSyn is positive-edge triggered and latches the input data upon detecting thepositive edge.

2. The control pins are optional; if they are not connected, the defaults will be:

• Clock not connected, the device reverts to a unit-delay register.

• CE connected and high, the input data is latched by the register upon apositive clock edge.

• CE connected and low (it holds a value of 0), the register output stays thesame and the input data is not latched.

• CE not connected, the clock is enabled by default and the input data islatched by the register upon a positive clock edge.

• Set connected and low, the register output is set to the value specified by theparameter ValueS.

• Set connected and high, the register output is not set to ValueS.

• Set not connected, the register output is never set to ValueS.





RegSyn 10-79


RomSyn

Description ROMLibrary Numeric, Synthesizable DSPClass SDFRomSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. RomSyn reads the specified file of ASCII hex values and stores them in a lineararray to model the ROM.



2.14 precision


TWOS_COMPLEMENT

enum

romFile name of file containingROM values (representedin hex data format in file)

filename

Depth size of (number of wordsin) ROM

1 int


1 Addr fix


2 Q fix

10-80 RomSyn

2. The path name for romFile can be specified in several ways: one is to justspecify the file name, for example romFile=foo, which is assumed to be locatedwithin the current project data directory; another is to specify the absolutepath, as in romFile=/usr/user_name/foo; or, the environmental variables canalso be used to set the file path name, for example romFile=$ENV_FOO/foo,where ENV_FOO is an environmental variable.

3. The input address value is used as an index into the array. An example fileformat:

0x0ff0a0x0bcd9...and so on.


5. RomSyn can now be mapped to synthesizable HDL code.



RomSyn 10-81


ShiftRegPPSyn

Description Parallel In/Parallel Out Shift RegisterLibrary Numeric, Synthesizable DSPClass SDFShiftRegPPSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations


Width number of bits in internalstate of shift register

16 int

Dir direction of bit shift: RIGHT,LEFT

LEFT enum


0 int



2 Serin Serial bit input fix


4 Load Load control input -- optional control pin fix

5 Shift Shift control input -- optional control pin fix



7 Q Shifted data output fix

10-82 ShiftRegPPSyn

1. ShiftRegPPSyn (Parallel_In/Parallel_Out) clock is positive-edge triggered andshifts the internal register data upon detecting the positive edge.

2. Direction of shifting is done assuming that the MSB is on the left and the LSBis on the right. For example, if Dir=LEFT, then shifting is done toward theMSB; conversely, if Dir=RIGHT, then shifting is done toward the LSB.




ShiftRegPPSyn 10-83


ShiftRegPSSyn

Description Parallel In/Serial Out Shift RegisterLibrary Numeric, Synthesizable DSPClass SDFShiftRegPSSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



16 int


LEFT enum


0 int









10-84 ShiftRegPSSyn

1. ShiftRegPSSyn (Parallel_In/Serial_Out) clock is positive-edge triggered andshifts the internal register data upon detecting the positive edge.



ShiftRegPSSyn 10-85


ShiftRegSPSyn

Description Serial In/Parallel Out Shift RegisterLibrary Numeric, Synthesizable DSPClass SDFShiftRegSPSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



16 int


LEFT enum

ValueS value loaded into theregister when the setcontrol pin is asserted

0 int








10-86 ShiftRegSPSyn

1. ShiftRegSPSyn (Serial_In/Parallel_Out) clock is positive-edge triggered andshifts the internal register data upon detecting the positive edge.





ShiftRegSPSyn 10-87


SineCosineSyn

Description Sine/Cosine Look-up TableLibrary Numeric, Synthesizable DSP : XilinxClass SDFSineCosineSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model implements a sine or cosine look-up table; given an input phasevalue, it outputs a fixed point value (1 sign bit, (OutWidth-1) fractional bitstwos-complement) corresponding to the Sine or Cosine of the phase.

2. The (optional) 1-bit control input SineOrCosine determines whether a sine orcosine value is evaluated by the model.


OutWidth Output width of NCO. 10 int

PhaseInWidth Width of PhaseIn input. 10 int


1 PhaseIn Phase input -- unsigned fix


3 SineOrCosine SineOrCosine -- controls whether sine or cosine isoutput

fix


4 Out fix

10-88 SineCosineSyn

• If the SineOrCosine pin is un-connected (in other words, unused) then thedefault output of the model is a sine value.

• If the SineOrCosine pin is connected, then a low value (corresponding to 0)will cause the model to output a cosine value, and, conversely a high value(corresponding to 1) will cause the model to output a sine value.

3. The input phase value in PhaseIn is interpreted within the model as anunsigned fixed point number (with PhaseInWidth integer bits, and no fractionalbits) and the value of sine(2π × PhaseIn/(2PhaseInWidth)) orcosine(2π × PhaseIn/(2PhaseInWidth)) is evaluated, and output. The output valuein Out is represented as a twos-complement, 1-sign bit, (OutWidth-1) fractionalbits, fixed point number.


SineCosineSyn 10-89


SinkRespSyn

Description Response SinkLibrary Numeric, Synthesizable DSPClass SDFSinkStimSyn

Parameters

Pin Inputs

Notes/Equations

1. SinkRespSyn collects Fix data for test vector responses.



Start sample number at which tostart recording

DefaultNumericStart

int

Stop sample number at which tostop recording

DefaultNumericStop

int


1 input input signal fix

10-90 SinkRespSyn

SinkStimSyn

Description Stimulus SinkLibrary Numeric, Synthesizable DSPClass SDFSinkStimSynDerived From SDFHPFix

Parameters

Pin Inputs

Notes/Equations

1. SinkStimSyn collects Fix data for test vector stimulus.



Start sample number at which tostart recording

DefaultNumericStart

int

Stop sample number at which tostop recording

DefaultNumericStop

int


1 input input signal fix

SinkStimSyn 10-91


XorSyn

Description Bitwise XORLibrary Numeric, Synthesizable DSPClass SDFXorSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. The input bus is composed of Size number of smaller bus segments. Each bussegment within the input bus is of bitwidth Width. XorSyn performs a bitwiseXOR of the bus segments resulting in the output Result of bitwidth Width. Forexample, Width=8, Size=2 means that the input bus is interpreted as having 2bus segments, each of bitwidth 8. The output of XorSyn is the bitwise XOR ofthe 2 bus segments, as illustrated in Figure 10-7.


Width size of a bus segmentwithin the input bus

8 int


2 int


1 Data fix


2 Result fix

10-92 XorSyn


2. An example design where two 8-bit signals are XORed together is shown inFigure 10-8.

Figure 10-8. XorSyn Example


XorSyn 10-93


Xor2Syn

Description 2-input XORLibrary Numeric, Synthesizable DSPClass SDFXor2SynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a 2-input XOR gate. It takes a bitwise XOR of inputs A and B(both of bitwidth Width) and outputs the results, that is, Result = A XOR B.





1 A fix

2 B fix


3 Result fix

10-94 Xor2Syn

ZeroInterpSyn

Description Zero insertion interpolatorLibrary Numeric, Synthesizable DSPClass SDFZeroInterpSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a data interpolator. It performs an upsampling of the input databy inserting extra zeros (UpSampleRatio −1 zeros) for each input data. For



TWOS_COMPLEMENT

enum

UpSampleRatio Up-sample ratio 2 int

DataPrecision Precision of output data --its bitwidth must equalinput data bitwidth

2.14 precision



2 Clock Clock input fix

3 Reset Asynchronous set/reset input -- optional control pin fix


4 Result Clock output fix

ZeroInterpSyn 10-95


example, given an input value of 0x1F, with UpSampleRatio equal to 2(meaning this model is upsampling by 2), the output Result will give the values0x1F, 0.


10-96 ZeroInterpSyn

ZeroInterpSyn 10-97


10-98 ZeroInterpSyn

Chapter 11: Numeric Synthesizable DSPXilinx Components

IntroductionThe Xilinx numeric synthesizable DSP components simulate fixed-point functionsthat can also be implemented in Xilinx FPGA (field programmable gate arrays) usingthe Xilinx cores generated by the Xilinx CORE Generator System software.

For synthesizable DSP components that perform math operations (such as adders,subtractors, gain blocks, and filters), the ArithType parameter specifies thearithmetic type of the output signal and can be set to TWOS_COMPLEMENT orUN_SIGNED values. When the input fixed-point signal has an arithmetic type thatis not the same as ArithType, the bit pattern representing the input number will beinterpreted in the arithmetic defined by ArithType. This can lead to unexpectedresults; therefore, arithmetic types should not be mixed when performing mathoperations.

For design implementation, a design network consisting of synthesizable DSPcomponents can be sent to the DSP synthesis or HDL code generation tool. Anyunconnected clock input pins will be connected up to a global clock signal after DSPsynthesis or HDL code generation. Similarly, any unconnected Set input pins will beconnected up to a global reset signal after DSP synthesis or HDL code generation.

Introduction 11-1

Numeric Synthesizable DSP Xilinx Components

AccumSyn

Description Scaled by 1/2 AccumulatorLibrary Numeric, Synthesizable DSP : XilinxClass SDFAccumSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



2.14 precision


TWOS_COMPLEMENT

enum


1 Data Data input -- Data input which is loaded by assertingLoad input

fix

2 Load Load input -- loads Data into accumulator ofaccumulator

fix





6 Result fix

11-2 AccumSyn

1. This model is a scale-by-half accumulator. Physically, the model can be viewedas an adder that adds the present input Data to one-half the value of theprevious output of the adder. The delayed adder output feedback is achieved byusing an internal data register that is clocked by the positive edge transitions ofthe Clock 1-bit. In discrete equation form, the equation defining the model is:

Result = Previous_Result/2 + Data

Figure 11-1. Internal Structure of Scale-by-Half Accumulator Model

2. The Clock input is optional:

• if it is connected, the model will operate based on the positive edgetransitions of the Clock input

• if it is not connected, the model will operate as if every sample step of thesimulator is a positive edge transition

3. Assertion of the Reset input by bringing it low (a value of 0) will clear theinternal data register.

4. The (optional) CE input is the clock-enable control for the internal data register.

• if it is connected and has a high value (a value of 1), the internal data registeris enabled and will load its input onto a positive Clock edge

• if it is not connected and low (a value of 0) the clock to the internal dataregister is disabled. The internal data register is always enabled when theCE input is not connected

5. The (optional) Load input is asserted by bring it high (a value of 1).

AccumSyn 11-3


• if it is asserted, the Data input is loaded into the internal data register

• if it is unconnected, the Load is never asserted

6. For information regarding numeric Xilinx synthesizable DSP functions refer tothe “Introduction” on page 11-1.

11-4 AccumSyn

AddRegSyn

Description Registered AdderLibrary Numeric, Synthesizable DSP : XilinxClass SDFAddRegSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs



TRUNCATE enum


2.14 precision


TWOS_COMPLEMENT

enum


WRAPPED enum


1 A fix

2 B fix





6 Result fix

AddRegSyn 11-5


Notes/Equations

1. This model is a registered adder. It calculates the addition of its A and B datainputs (A+B) and registers its output Result such that it has the specifiedprecision as set in the OutputPrecision parameter.



• if it is not connected, the model will operate as if every sample step of thesimulator is a positive edge transition

3. Assertion of the Reset input by bringing it low (a value of 0) will clear theoutput data register.

4. The (optional) CE input is the clock-enable control for the output data register:

• if it is connected and has a high value (a value of 1), the output data registeris enabled and will load the addition result upon a positive Clock edge.

• if it is connected, and low (a value of 0) the clock to the output data register isdisabled.

• if the CE input is not connected, the output data register is always enabled.


11-6 AddRegSyn

CombFiltSyn

Description Comb FilterLibrary Numeric, Synthesizable DSP : XilinxClass SDFCombFiltSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model implements the transfer function of (1-z-M) which comprises thecomb section of a comb filter, where M = PipeStages. In other words, a delayed



2.14 precision


TWOS_COMPLEMENT

enum

PipeStages Depth of pipeline, must be> 0.

1 int






4 Result Comb Filter output fix

CombFiltSyn 11-7


version of the input data value (PipeStages clocks previously) is subtractedfrom the present input data value. In discrete equation form, it can berepresented as:

Result = Data - Data(Delayed_by_M_clocks)

Figure 11-2. Internal Structure of Comb Section Model


11-8 CombFiltSyn

DPRamRegSyn

Description Registered Dual-Port RAMLibrary Numeric, Synthesizable DSP : XilinxClass SDFDPRamRegSynDerived From SDFHPFix

Parameters

Pin Inputs



2.14 precision


TWOS_COMPLEMENT

enum

Depth Number of words in RAM 16 int

ramFile File containing initial RAMvalues

filename

ramFileFormat Format of RAM init file.:REAL, HEX

HEX enum


1 AddrR input read address fix

2 AddrW input write address fix




6 WE write enable input: if low, then the input data iswritten to the RAM location specified by AddrW.

fix

DPRamRegSyn 11-9


Pin Outputs

Notes/Equations

1. This model implements a dual-port RAM with a registered output. Given aninput address in AddrW (write address), and data in Data, the model will writethe input Data into an internal array if WE is asserted by a low value. If WE isnot asserted, then the model will not write Data into the address location asspecified in AddrW. The input address in AddrR (read address) is used to readout the data in the dual-port RAM model, which is sent to the output Q.

2. The output of the dual-port RAM is registered with a positive edge Clock input.The clock enable CE control input is optional:

• if it is not connected, the model is always enabled

• if it is connected, it is enabled by a high value in CE

3. The initial values in the dual-port RAM can be defined in the (optional) file asspecified in the ramFile parameter. The format of the file is specified by theramFileFormat parameter; the initial values can be specified as REAL or HEX.The address of each initial data read into the model is the same as the linenumber of the corresponding data read from the initialization file.

The initial values are specified as a column of values as in the followingexamples.

• if ramFileFormat = REAL, which specifies that the RAM initialization filecontains real values, an example of such a file would be:

0.980.240.12...

From this example, the model will interpret the first line as address 0 withdata equal to the fixed-point value corresponding to 0.98, and so on. Notethat the model will convert the real values to its fixed-point representationusing the specified precision in the OutputPrecision parameter, andarithmetic type as specified in the ArithType parameter.


7 Q output data fix

11-10 DPRamRegSyn

• if ramFileFormat = HEX, an example of such a file would be:

0x7f0x060x08...

From this example, the model will interpret the first line as address 0 withdata equal to 0x7f, and so on.

4. The Depth parameter specifies the number of words in the dual-port RAM.


DPRamRegSyn 11-11


DualNCOSyn

Description Dual Channel Numerically Controlled OscillatorLibrary Numeric, Synthesizable DSP : XilinxClass SDFDualNCOSynDerived From SDFHPFix

Parameters

Pin Inputs


SetType Mode for Set/Reset controlinput.: ASYNCHRONOUS,SYNCHRONOUS,SET_PIN_NOTUSED

ASYNCHRONOUS

enum


PhaseAccWidth Width of phaseaccumulator in NCO.

16 int

PhaseWidth Number of bits used fromphase accumulator forsine/cosine table.

8 int

PhaseIncrWidth Width of phase incrementinput.

10 int


1 PhaseIncr fix




11-12 DualNCOSyn

Pin Outputs

Notes/Equations

1. This model implements a dual-output numerically controlled oscillator (NCO).Given a phase increment PhaseIncr input value, it outputs sine and cosinefixed-point signals (1 sign bit, (OutWidth-1) fractional bits twos-complement)with a frequency proportional to the value of the PhaseIncr input.

2. When the Load input is asserted by bringing it high (a value of 1), thePhaseIncr input data is loaded into an internal phase increment register in theNCO model. The input phase increment value in PhaseIncr is interpretedwithin the model as an unsigned fixed-point number (with PhaseIncrWidthinteger bits, and no fractional bits).

3. The model contains a phase accumulator (of bitwidth PhaseAccWidth) thatadds the value in the phase increment register to the previous phaseaccumulator value. The result of the phase accumulator (actually the mostsignificant PhaseWidth bits of the phase accumulator) is used as an index to asine/cosine look-up table that outputs the sine and cosine values correspondingto the current phase accumulator value.

The output sine and cosine signals SineOut, CosineOut are represented astwos-complement, 1-sign bit, (OutWidth −1) fractional bits, fixed-pointnumbers.

4. Assertion of the Reset input by bringing it low (a value of 0) will clear the NCOphase increment register and the phase accumulator.


5 SineOut fix

6 CosineOut fix

DualNCOSyn 11-13


Figure 11-3. Internal Structure of Dual-Output NCO Model


11-14 DualNCOSyn

FIRSyn

Description General Finite Impulse Response (FIR) FilterLibrary Numeric, Synthesizable DSP : XilinxClass SDFFIRSynDerived From SDFHPFix

Parameters

Pin Inputs



2.14 precision


TWOS_COMPLEMENT

enum

NumOfTaps Number of taps in FIR filter. 1 int

CoefPrecision Precision of thecoefficients in thecoefficient file.

2.14 precision

DataPrecision Precision of theDataFeedThru output(used in cascading FIRfilters).

2.14 precision

CoefFile File containing FIRcoefficient values.

filename

CoefFileFormat Format of FIR Coefficientsfile.: REAL, HEX

HEX enum


1 DataIn Data input fix



FIRSyn 11-15


Pin Outputs

Notes/Equations

1. This model is a FIR (finite impulse response) filter model. It implements ageneral parallel FIR structure and retains full precision internally whencomputing filter output values. The only quantization done is at the Resultoutput.

Figure 11-4. Internal Structure of FIR Model

2. The Result output of the FIR model is the final result of the FIR filtering donewithin the model, and quantized to the precision specified by OutputPrecision.

3. Data from the DataIn input is clocked into the internal data registers of the FIRmodel upon the positive edge transitions of the Clock input if the Clock pin isconnected. If the Clock pin is not connected, data is shifted into the internaldata registers at every sample step in the simulator.

4. The 1-bit Reset input pin is asserted by bring it low (value of 1), which will clearall internal data registers.

5. The DataFeedThru output of the FIR model is the output of the oldest data inthe internal data registers.

The user can use this output to feed the next stage of a FIR filter model in orderto create a cascade of FIR filter models. This may be useful for the user in thecontext of Xilinx core generation (in the ADS DSP Synthesis / HDL CodeGenerator) since there is a maximum limit on the filter order of Xilinx FIR


4 Result FIR result output (with precision OutputPrecision) fix

5 DataFeedThru Data output (with precision DataPrecision =precision of DataIn input)

fix

11-16 FIRSyn

cores. By cascading sections of FIR cores, the user can build a larger order FIRfilter than the maximum for just one FIR core.

6. The filter tap coefficients of the FIR filter are defined in the file as specified inthe CoefFile parameter. The format of the file is specified by the CoefFileFormatparameter; tap coefficients can be specified as REAL or HEX values. The tapcoefficients are specified as a column of values in the file. The 0th tap filtercoefficient is the value on the first line of the filter tap coefficient file, the 1thtap filter coefficient corresponds to the value on the second line, the 2th tapfilter coefficient corresponds to the value on the third line, and so on.

Consider the following examples:

• If CoefFileFormat = REAL, which specifies that the filter tap coefficient filecontains real values for the filter tap coefficients, an example of such a filewould be:

0.980.240.120.05-0.130.21...

• If CoefFileFormat = HEX which specifies that the filter tap coefficient filecontains hex values for the filter tap coefficients, an example of such a filewould be:

0x7f0x060x020x8f0x070x08...

7. The NumOfTaps parameter specifies the number of tap coefficients to be readfrom the file specified by CoefFile.

• If NumOfTaps is assigned a value that is less than the taps value provided inCoefFile, only the first NumOfTaps coefficients will be picked from the file.

FIRSyn 11-17


• If NumOfTaps is greater than the taps provided, the rest of the taps will bepadded with 0.

8. The CoefPrecision parameter specifies the precision of the filter tap coefficients,that is, the number of integer bits (including the sign bit) and the number offractional bits to be used to represent the filter tap coefficients.


11-18 FIRSyn

FixedGainSyn

Description Fixed GainLibrary Numeric, Synthesizable DSP : XilinxClass SDFFixedGainSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs



TRUNCATE enum


2.14 precision


TWOS_COMPLEMENT

enum


WRAPPED enum

Gain Gain of device specified asa real value.

1.0 real

GainPrecision Precision of the gainparameter.

2.14 precision


1 Data fix


2 Result fix

FixedGainSyn 11-19


Notes/Equations

1. FixedGainSyn models a gain block that multiplies the input value by thespecified Gain (quantized by GainPrecision) and outputs the result at thespecified OutputPrecision.

2. OutputPrecision specifies the fixed-point precision format of the output: ifOutputPrecision=1.15, 1 bit is used to represent the integer part of the output,and 15 bits are used to represent the fractional portion of the output.


11-20 FixedGainSyn

IntegratorSyn

Description IntegratorLibrary Numeric, Synthesizable DSP : XilinxClass SDFIntegratorSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations



2.14 precision


TWOS_COMPLEMENT

enum


1 Data Data input -- Data input which is loaded by assertingLoad input

fix

2 Load Load input -- loads Data into accumulator ofintegrator

fix





6 Result fix

IntegratorSyn 11-21


1. This model is a first order integrator. It has a transfer function of (1- z-1)-1

where z-1 refers to a unit Clock delay. Physically, the model can be viewed as anadder that adds the present input Data to the previous output of the adder. Thedelayed adder output feedback is achieved by using an internal data registerthat is clocked by the positive edge transitions of the Clock 1-bit. In discreteequation form, the equation defining the model is:

Result = Previous_Result + Data

Figure 11-5. Internal Structure of Integrator Model

2. The Clock input is optional.

• if it is connected, the model will operate based on the positive edgetransitions of the Clock input.

• if it is not connected, the model will operate as if every sample step of thesimulator is a positive edge transition.

3. Assertion of the Reset input by bringing it low (a value of 0) will clear theinternal data register.

4. The (optional) CE input is the clock-enable control for the internal data register.

• if it is connected and has a high value (a value of 1), then the internal dataregister is enabled and will load its input upon a positive Clock edge.

• if it is not connected, and low (a value of 0) then the clock to the internal dataregister is disabled. The internal data register is always enabled when theCE input is not connected.

5. The (optional) Load input is asserted by bring it high (a value of 1).

11-22 IntegratorSyn

• if it is asserted, the Data input is loaded into the internal data register.

• if it is unconnected, the Load is never asserted.


IntegratorSyn 11-23


MultRegSyn

Description Registered MultiplierLibrary Numeric, Synthesizable DSP : XilinxClass SDFMultRegSynDerived From SDFHPFix

Parameters

Pin Inputs



TRUNCATE enum


2.14 precision


TWOS_COMPLEMENT

enum


WRAPPED enum

Latency Latency in clock cycles formultiplier result.

1 int


1 A input A fix

2 B input B fix



11-24 MultRegSyn

Pin Outputs

Notes/Equations

1. This model is a registered adder. It calculates the multiplication of its A and Bdata inputs (A × B) and registers its output Result such that it has the specifiedprecision as set in the OutputPrecision parameter.





4. The (optional) CE input is the clock-enable control for the output data register.


• if it is connected and low (a value of 0) the clock to the output data register isdisabled.




5 Result Registered multiplier output fix

MultRegSyn 11-25


Mux2Syn


Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a 2-input multiplexer. It selects input Data0 or Data1 dependingon the value of its Sel input. If the Sel input value is 0 (low value), Data0 isassigned to its output Result; if the Sel input value is 1 (high value), Data1 isassigned to its output Result.





1 Data0 fix

2 Data1 fix

3 Sel fix


4 Result fix

11-26 Mux2Syn

Mux3Syn


Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a 3-input multiplexer. It selects one of 3 inputs Data0, or Data1 orData2 depending on the value of its Sel0 and Sel1 inputs given in Table 11-1,




1 Data0 fix

2 Data1 fix

3 Data2 fix

4 Sel0 fix

5 Sel1 fix


6 Result fix

Mux3Syn 11-27




Sel1 Sel0 Result

0 0 Data0

0 1 Data1

1 0 Data2

1 1 invalid input

11-28 Mux3Syn

Mux4Syn


Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a 4-input MUX; it selects input Data0, Data1, Data2, or Data3based on the values of inputs Sel0 and Sel1 given in Table 11-2.




1 Data0 fix

2 Data1 fix

3 Data2 fix

4 Data3 fix

5 Sel0 fix

6 Sel1 fix


7 Result fix

Mux4Syn 11-29




Sel1 Sel0 Result

0 0 Data0

0 1 Data1

1 0 Data2

1 1 Data3

11-30 Mux4Syn

NCOSyn

Description Numerically Controlled OscillatorLibrary Numeric, Synthesizable DSP : XilinxClass SDFNCOSynDerived From SDFHPFix

Parameters

Pin Inputs


SetType Mode for Set/Reset controlinput.: ASYNCHRONOUS,SYNCHRONOUS,SET_PIN_NOTUSED

ASYNCHRONOUS

enum


PhaseAccWidth Width of phaseaccumulator in NCO.

16 int

PhaseWidth Number of bits used fromphase accumulator forsine/cosine table.

8 int

PhaseIncrWidth Width of phase incrementinput.

10 int


1 PhaseIncr fix





fix

NCOSyn 11-31


Pin Outputs

Notes/Equations

1. This model implements an Numerically Controlled Oscillator (NCO). Given aphase increment PhaseIncr input value, it outputs a sine or cosine fixed-pointsignal (1 sign bit, (OutWidth-1) fractional bits twos-complement) with afrequency proportional to the value of the PhaseIncr input.

When the Load input is asserted by bring it high (a value of 1), the PhaseIncrinput data is loaded into an internal phase increment register in the NCOmodel. The input phase increment value in PhaseIncr is interpreted within themodel as an unsigned fixed-point number (with PhaseIncrWidth integer bits,and no fractional bits).

The model contains a phase accumulator (of bitwidth PhaseAccWidth) whichadds the value in the phase increment register to the previous phaseaccumulator value. The result of the phase accumulator (actually the mostsignificant PhaseWidth bits of the phase accumulator) is used as an index to asine/cosine look-up table that outputs a sine or cosine value corresponding tothe current phase accumulator value.

Figure 11-6. Internal Structure of NCO model

2. The output sine or cosine signal in Out is represented as a twos-complement,1-sign bit, (OutWidth-1) fractional bits, fixed-point number.


6 Out fix

11-32 NCOSyn

3. The 1-bit control input SineOrCosine is optional. It is used to determinewhether a sine or cosine signal is evaluated by the model.

• if the SineOrCosine pin is not connected, the default output of the model is asine signal.

• if the SineOrCosine pin is connected: a low value (corresponding to 0) willcause the model to output a cosine signal; conversely, a high value(corresponding to 1) will cause the model to output a sine signal.

4. Assertion of the Reset input by bringing it low (a value of 0) will clear the NCOphase increment register and the phase accumulator.


NCOSyn 11-33


RamRegSyn

Description Registered Random-Access-Memory (RAM)Library Numeric, Synthesizable DSP : XilinxClass SDFRamRegSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs



2.14 precision


TWOS_COMPLEMENT

enum

Depth Number of words in RAM. 16 int

ramFile File containing initial RAMvalues.

filename

ramFileFormat Format of RAM init file.:REAL, HEX

HEX enum


1 Addr input address fix




5 WE write enable input: if low then the input Data iswritten into the RAM location specified by Addr.

fix


6 Q output data fix

11-34 RamRegSyn

Notes/Equations

1. This model implements a RAM with a registered output.

Given an input address in Addr, and data in Data, the model will write theinput Data into an internal array if WE is asserted by a low value; if WE is notasserted, the model will put data addressed by Addr onto its output Q.

2. The output of the RAM is registered with a positive edge Clock input.

The clock enable CE control input is optional:


• if it is connected, it is enabled by a high value in CE.

The initial values in the RAM can be defined in the (optional) file as specified inthe ramFile parameter. The format of the file is specified by the ramFileFormatparameter; initialization values can be specified as REAL or HEX. The addressof each initial data read into the model is the same as the line number of thecorresponding data read from the initialization file.

The initial values are specified as a column of values as in the followingexamples.

• If ramFileFormat = REAL which specifies that the RAM initialization filecontains real values, then an example of such a file would be:

0.980.240.12...

From this example, the model will interpret the first line as address 0 withdata equal to the fixed-point value corresponding to 0.98, and so on. Notethat the model will convert the real values to its fixed-point representationusing the specified precision in the OutputPrecision parameter, andarithmetic type as specified in the ArithType parameter.

• If ramFileFormat = HEX, then an example of such a file would be:

0x7f0x060x08

RamRegSyn 11-35


.

.

.

From this example, the model will interpret the first line as address 0 withdata equal to 0x7f, and so on.

3. The Depth parameter specifies the number of words in the RAM.


Σ

11-36 RamRegSyn

RomRegSyn

Description Registered Read-Only-Memory (ROM)Library Numeric, Synthesizable DSP : XilinxClass SDFRomRegSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs



2.14 precision


TWOS_COMPLEMENT

enum

romFile Filename containing ROMdata.

filename

romFileFormat Format of ROM init file.:REAL, HEX

HEX enum

Depth Number of words in ROM. 1 int


1 Addr fix





5 Q fix

RomRegSyn 11-37


Notes/Equations

1. This model implements a ROM with a registered output. Given an inputaddress in Addr, the model will put the data addressed by Addr onto output Q.

2. The output of the ROM is registered with a positive edge Clock input.

The clock enable CE control input is optional.


• if it is connected, it is enabled by a high value in CE.

3. The initial values in the ROM can be defined in the file specified in the romFileparameter. The format of the file is specified by the romFileFormat parameter;data can be specified as REAL or HEX values. The address of each data valueread into the model is the same as the line number of the corresponding dataread from the file.

4. The values are specified as a column of values as in the following examples.

If romFileFormat = REAL which specifies that the ROM file contains realvalues, then an example of such a file would be:

0.980.240.12...

From the above file example, the model will interpret the first line as address 0with data equal to the fixed point value corresponding to 0.98, etc. Note that themodel will convert the real values to its fixed point representation using thespecified precision in the OutputPrecision parameter, and arithmetic type asspecified in the ArithType parameter.

If romFileFormat = HEX, then an example of such a file would be:

0x7f0x060x08...

From the above file example, the model will interpret the first line as address 0with data equal to 0x7f, and so on.

11-38 RomRegSyn

5. The Depth parameter specifies the number of words in the ROM.


RomRegSyn 11-39


SerialFIRSyn

Description Serial Finite Impulse Response (FIR) FilterLibrary Numeric, Synthesizable DSP : XilinxClass SDFSerialFIRSynDerived From SDFHPFix

Parameters

Pin Inputs



2.14 precision


TWOS_COMPLEMENT

enum



2.14 precision

DataPrecision Precision of the input data. 2.14 precision


filename


HEX enum



2 BitClock Bit Clock input -- Bit-rate clock fix

3 DataClock Data Clock input -- input sample rate clock fix


11-40 SerialFIRSyn

Pin Outputs

Notes/Equations

1. This model is a bit-serial finite impulse response (FIR) filter model. Itimplements a bit-serial FIR structure and retains full precision internally whencalculating filter output values.

The only quantization done is at the Result output of the model.

2. The Result output of the bit-serial FIR model is the final result of the FIRfiltering done within the model, and quantized to the precision specified byOutputPrecision.

3. Data from DataIn input is clocked into the internal data registers of thebit-serial FIR model upon the positive edge transitions of the DataClock input.

4. The BitClock input is used to simulate the bit-serial nature of the FIR filter; itclocks the result of the FIR filter into a FIFO buffer of depth equal to the totalnumber of bits in DataIn (as specified by the DataPrecision parameter). If thetotal number of bits in DataPrecision is equal to W, there is a delay equal to WBitClock positive edges before the FIR filter output is sent to Result.

5. The 1-bit Reset input pin is asserted by bring it low (a value of 1), which willclear all the internal data registers.

6. The filter tap coefficients of the bit-serial FIR filter is defined in the filespecified in the CoefFile parameter. The format of the file is specified by theCoefFileFormat parameter; tap coefficients can be specified as REAL or HEXvalues. The tap coefficients are specified as a column of values in the file. The0th tap filter coefficient is the value on the first line of the filter tap coefficientfile; the 1th tap filter coefficient corresponds to the value on the second line; the2th tap filter coefficient corresponds to the value on the third line, and so on.

Consider the following examples.

• If CoefFileFormat = REAL, which specifies that the filter tap coefficient filecontains real values for the filter tap coefficients, an example of such a filewould be:



SerialFIRSyn 11-41


0.980.240.120.05-0.130.21...

• If CoefFileFormat = HEX, which specifies that the filter tap coefficient filecontains hex values for the filter tap coefficients, an example of such a filewould be:

0x7f0x060x020x8f0x070x08...

7. The NumTaps parameter specifies the number of tap coefficients to be readfrom the file specified by CoefFile.



11-42 SerialFIRSyn

SineCosineSyn

Description Sine/Cosine Look-up TableLibrary Numeric, Synthesizable DSP : XilinxClass SDFSineCosineSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs

Notes/Equations

1. This model implements a sine or cosine look-up table; given an input phasevalue, it outputs a fixed point value (1 sign bit, (OutWidth-1) fractional bitstwos-complement) corresponding to the Sine or Cosine of the phase.

2. The (optional) 1-bit control input SineOrCosine determines whether a sine orcosine value is evaluated by the model.



PhaseInWidth Width of PhaseIn input. 10 int


1 PhaseIn Phase input -- unsigned fix



fix


4 Out fix

SineCosineSyn 11-43


• If the SineOrCosine pin is un-connected (in other words, unused) then thedefault output of the model is a sine value.

• If the SineOrCosine pin is connected, then a low value (corresponding to 0)will cause the model to output a cosine value, and, conversely a high value(corresponding to 1) will cause the model to output a sine value.

3. The input phase value in PhaseIn is interpreted within the model as anunsigned fixed point number (with PhaseInWidth integer bits, and no fractionalbits) and the value of sine(2π × PhaseIn/(2PhaseInWidth)) orcosine(2π × PhaseIn/(2PhaseInWidth)) is evaluated, and output. The output valuein Out is represented as a twos-complement, 1-sign bit, (OutWidth-1) fractionalbits, fixed point number.


11-44 SineCosineSyn

SubRegSyn

Description Registered SubtracterLibrary Numeric, Synthesizable DSP : XilinxClass SDFSubRegSynDerived From SDFHPFix

Parameters

Pin Inputs

Pin Outputs



TRUNCATE enum


2.14 precision


TWOS_COMPLEMENT

enum


WRAPPED enum


1 A fix

2 B fix





6 Result fix

SubRegSyn 11-45


Notes/Equations

1. This model is a registered subtracter. It calculates the subtraction of its A and Bdata inputs (A-B) and registers its output Result such that it has the specifiedprecision as set in the OutputPrecision parameter.

2. The Clock input is optional.

• if it is connected, the model will operate based on the positive edgetransitions of the Clock input.



4. The (optional) CE input is the clock-enable control for the output data register.


• if it is connected, and low (a value of 0), the clock to the output data registeris disabled.



11-46 SubRegSyn

SymFIRSyn

Description Symmetric Finite Impulse Response (FIR) FilterLibrary Numeric, Synthesizable DSP : XilinxClass SDFSymFIRSynDerived From SDFHPFix

Parameters



2.14 precision


TWOS_COMPLEMENT

enum



2.14 precision

DataPrecision Precision of theMidDataOut output (usedin cascading FIR filters).

2.14 precision


filename


HEX enum

CascadeMode Use filter in cascademode? NO, YES

NO enum

SymmetricMode Is filter symmetric oranti-symmetric?SYMMETRIC,ANTI_SYMMETRIC

SYMMETRIC enum

SymFIRSyn 11-47


Pin Inputs

Pin Outputs

Notes/Equations

1. This model is a symmetric FIR (finite impulse response) filter model. Itimplements a general parallel FIR structure with symmetric filter tapcoefficients. It retains full precision internally when calculating filter outputvalues. The only quantization done is at the Result output of the model.

Figure 11-7. Internal Structure of Symmetric FIR Model





4 MidDataIn Mid point data input (optional) (with precision =precision of DataIn input)

fix



6 DataOut End point data output (with precision DataPrecision= precision of DataIn input)

fix

7 MidDataOut Mid point data output (with precision DataPrecision =precision of DataIn input)

fix

11-48 SymFIRSyn

2. Data from DataIn input is clocked into the internal data registers of the FIRmodel upon the positive edge transitions of the Clock input if the Clock pin isconnected. If the Clock pin is not connected, then data is shifted into theinternal data registers at every sample step in the simulator.

3. The (optional) input MidDataIn and outputs MidDataOut and DataOut areused when cascading several Symmetric FIR models. Cascading may bedesirable in the case where there is a limit on the FIR filter order perSymmetric FIR model, which is the case in the Xilinx CORE GeneratorSymmetric FIR filter that is limited, at most, to 20 filter taps per SymmetricFIR core.

The parameter CascadeMode should be set to YES if the model is to be cascadedto feed another Symmetric FIR model or NO if it does not feed into anotherSymmetric FIR model. If CascadeMode is set to NO for no cascading, then(internally within the model), the MidDataIn input takes its input data fromthe MidDataOut output of the model.

Cascading of several Symmetric FIR filter models is illustrated Figure 11-8.

Figure 11-8. Cascading of Several Symmetric FIR Filter Models

4. The parameter SymmetricMode is used to select whether the FIR filtercoefficients are symmetric or anti-symmetric.

5. The Result output of the symmetric FIR model is the final result of the FIRfiltering done within the model, and quantized to the precision specified byOutputPrecision.

6. The 1-bit Reset input pin is asserted by bring it low (i.e., value of 1), which willclear all the internal data registers.

SymFIRSyn 11-49


7. Since the filter is symmetric or anti-symmetric, only the first half of the filtertap coefficients need to be defined in the filter definition file.

The filter tap coefficients of the FIR filter is defined in the file as specified in theCoefFile parameter. The format of the file is specified by the CoefFileFormatparameter; the tap coefficients can be specified as real or hex values. The tapcoefficients are specified as a column of values in the file. The 0th tap filtercoefficient is the value on the first line of the filter tap coefficient file, the 1thtap filter coefficient corresponds to the value on the second line, the 2th tapfilter coefficient corresponds to the value on the third line, and so on.

Consider the following examples.

• If CoefFileFormat = REAL, which specifies that the filter tap coefficient filecontains real values for the filter tap coefficients, then an example of such afile would be:

0.980.240.120.05-0.130.21...

• if CoefFileFormat = HEX, which specifies that the filter tap coefficient filecontains hex values for the filter tap coefficients, then an example of such afile would be:

0x7f0x060x020x8f0x070x08...

8. The NumTaps parameter specifies the number of tap coefficients to be readfrom the file specified by CoefFile.


11-50 SymFIRSyn


Introduction 11-51


11-52 Introduction

Chapter 12: Obsolete Numeric Components

12-1

Obsolete Numeric Components

CoderConvolution

Description Convolutional coder for specific generator polynomialsLibrary Obsolete (not to be discontinued), NumericClass SDFCoderConvolutionDerived From baseOmniSysNumericStar

Parameters

Pin Inputs

Pin Outputs

Notes/Equations


Type convolutional code: rate1/2 m 7 g0 171 g1 133,rate 1/2 m 6 g0 51 g1 67,rate 1/2 m 6 g0 73 g1 61,rate 1/3 m 7 g0 171 g1133 g2 165, rate 1/3 k 6g0 51 g1 67 g2 75, rate1/3 m 7 g0 171 g1 133g2 145

rate 1/2 m 7 g0171 g1 133

enum


1 DI input data stream int

2 CI clock signal for input data int

3 CO clock signal for output data int


4 DO encoded output data stream int

12-2 CoderConvolution

Note This component is obsolete for new designs. (It is available only forcompatibility with designs created with ADS 1.3 or earlier.) There are no plans toremove this component from future ADS releases; however, enhancements or fixes ofany existing defects will not be made.

Please use the improved ConvolutionalCoder (Numeric, Advanced Comm library) fornew design work.

1. The convolutional encoder is used to encode data so that errors introduced dueto noise in the channel can be corrected by the decoder. A convolutional encoderis a linear feed-forward shift register network in which, for every k data bitsthat are shifted in, n encoded bits are shifted out. The structure of the encoderis specified by a set of generator polynomials g[i,j], 0≤i<k, 0≤j<n. The errorcorrecting capabilities of a code are determined by these generator polynomials.

Two examples of convolutional encoders are shown in Figure 12-1 andFigure 12-2. For the rate 1/2 coder shown in Figure 12-1, the connections for theoutput bit Y(t,0) can be specified by the binary string 1111001, where a 1represents a connection from the shift register to the modulo 2 adder and a 0represents no connection. This string can also be represented as the polynomialg[0,0] = 1+z+z2+z3+z6 or the octal number 171. Similarly, the encoded bit Y(t,1)has connections 1011011 which is equivalent to the polynomial

g[0,1] = 1+z2+z3+z5+z6 or the octal number 133.

In a similar manner, the rate 2/3 encoder shown in Figure 12-2 is described bythe polynomials

g[0,0] = 1 g[0,1]= 1 g[0,2] = 1+z g[1,0] = 1 g[1,1] = 1 g[1,2] = 1+z+z2

Two important characteristics of a convolutional code are its rate andconstraint length. If k data bits are shifted in for every n encoded bits shiftedout, the rate of the code equals k/n. If the maximum degree of the polynomials ism, then the constraint length of the code equals k(m+1). It is possible to obtaincodes with better error correcting capabilities by decreasing the rate or byincreasing the constraint length. Decreasing the rate increases the requiredbandwidth and increasing the constraint length increases the complexity of thedecoder. With Viterbi decoding, the practical limit for the constraint length of acode is approximately 8 with today’s technology. For larger constraint lengthcodes, different decoding methods such as sequential decoding are used.

CoderConvolution 12-3


Figure 12-1. Rate 1/2 Encoder

Figure 12-2. Rate 2/3 Encoder

2. The convolutional encoder model requires three inputs, the serial input datastream (DI), a clock signal to clock in the input data (CI), and a second clocksignal to clock out the output data bits (CO). The fourth pin is the output pin atwhich the encoded data (DO) appears as a serial bit stream. At each positiveedge of the clock signal CI (a positive edge occurs at the instant when the clock

X(t) X(t−1) X(t−2) X(t−3) X(t−4) X(t−5) X(t−6)

+

+

MODULO 2 ADDER

MODULO 2 ADDER

SERIALDATA IN

SERIAL DATAOUT

+

+

+

X(t) X(t−2) X(t−4)

X(t−5)X(t−3)X(t−1)

SERIALDATA IN

SERIAL DATAOUT


voltage becomes larger than a threshold of 0.5V), the input signal is sampledand decoded as a logical 1 or 0 by comparing the sampled value with a thresholdof 0.5V, and stored in a shift register. Each time k bits are clocked in, thecontents of the shift register are convolved with the generator polynomials toproduce the n output bits. These n output bits are clocked out at each positiveedge of CO.

Figure 12-3 shows a schematic representation of the implementation of a (n, k)convolutional encoder.

Figure 12-3. Schematic Diagram of a Convolutional Encoder

The input data bits are shifted into the serial in/parallel out shift register. Themodulo-k counter keeps track of the number of data bits shifted in. When theoutput of the modulo-k counter equals zero (that is, k bits have been clocked in),the output bits are generated by the block labelled logic for generatorpolynomials and loaded into the parallel in/parallel out shift register.Simultaneously the output bit of the flip-flop is set to a logic 1 (it is assumedthat the set and reset pins of this flip-flop are positive edge triggered). When theflip-flop is set, a positive edge from CO loads the data from the parallelin/parallel out shift register into the parallel in/serial out shift register and alsoresets the flip-flop to a zero. Subsequent positive edges of CO shift out the databits from the parallel in/serial out shift register. It is important to note that forproper operation of the encoder, the two clocks CI and CO must be adjusted so

SERIAL IN/PARALLEL OUTSHIFT REGISTER

PARALLEL IN/PARALLEL OUTSHIFT REGISTER

PARALLEL IN/SERIAL OUTSHIFT REGISTER

LOGIC FOR GENERATORPOLYNOMIALS

MODULO KCOUNTER

K INPUTNOR GATE

FLIP-FLOP

DATA IN

DATA OUT

CI

DI

DOCOCLOCK

CLOCK

CLOCK

LOAD/SHIFT



that exactly n bits are shifted out for every k bits that are shifted in. Also notethat if the clock edges of CI and CO occur simultaneously, CI is serviced first,then CO.

The output bits generated by the logic for generator polynomials block arecalculated as follows. Let T(0), T(1), T(2), .... be the time instances when thepositive edges of the input clock CI occur (a positive edge occurs at the instantwhen the clock voltage becomes larger than a threshold of 0.5V). Let the logicstates of the input voltage DI at these instances be X0, X1, ... . Then at timeinstance T(m k),(m > 0), the n output bits are given by the following equations:

Define the k polynomials Uo(z), ... , Uk−1(z) as

Let the n output bits at time T(m k) be Yn m, Yn(m+1), ... , Yn(m+n-1) . Then

where all the arithmetic is performed modulo-2.

3. Timing diagrams. For proper operation of the encoder, the periods of the inputand output clocks must be set up properly. For any (n, k) code the followingconditions must be satisfied by the clock signals.

Pin = PD, n Pout = k Pin

where PD = input data bit period, Pin= input clock period, and Pout= outputclock period.

The signal CI can be directly generated by a Rect component with a Height of 1,Width of Pin / 2 and Period of Pin. Similarly, the signal CO can be generated by aRect component with a Height of 1, Width of Pout / 2 and Period of Pout.

Figures 12-4 and 12-5 show the schematic and the input, output and clocksignals for the rate 1/2 coder (Figure 12-1). For this example the input bit periodis 40 samples. Also, although the positive clock edges of CI and CO occursimultaneously, CI is serviced first—the input data bit is sampled and theencoded bits are computed; CO is serviced next—the encoded bit is output.

U j z( ) X m i–( )k j+ Zi 1–

0 j k<≤i 1=

m

∑=

Yn m j+( ) gi j, z( )Ui z( )i 0=

k 1–

∑z 1=

0 j n<≤=


Figures 12-6 and 12-7 show the schematic and input, output, and clock signalsfor a rate 1/3 coder. For this example, the input bit period is 60 samples.

Figure 12-4. Rate 1/2 Encoder Schematic



Figure 12-5. Rate 1/2 Encoder Timing Diagram

Figure 12-6. Rate 1/3 Encoder Schematic


Figure 12-7. Rate 1/3 Encoder Timing Diagram



DecoderViterbi

Description Viterbi decoder for specific generator polynomialsLibrary Obsolete (not to be discontinued), NumericClass SDFDecoderViterbiDerived From baseOmniSysNumericStar

Parameters

Pin Inputs


Type convolutional code: rate1/2 m 7 g0 171 g1 133,rate 1/2 m 6 g0 51 g1 67,rate 1/2 m 6 g0 73 g1 61,rate 1/3 m 7 g0 171 g1133 g2 165, rate 1/3 k 6g0 51 g1 67 g2 75, rate1/3 m 7 g0 171 g1 133g2 145

rate 1/2 m 7 g0171 g1 133

enum

NumBits number of soft decision bits 2 int [0, ∞)

PathLen path memory truncationlength

35 int [1, ∞)†

ReNormTh metric renormalizationthreshold

10 int [1, ∞)

ReNormN metric renormalizationinterval

30 int [1, ∞)

† Typically set to 5 times the constraint length


1 DI input signal real

2 CI clock signal for input data real

3 CO clock signal for output data real

12-10 DecoderViterbi

Pin Outputs

Notes/Equations

Note This component is obsolete for new designs. (It is available only forcompatibility with designs created with ADS 1.3 or earlier.) There are no plans toremove this component from future ADS releases; however, enhancements or fixes ofany existing defects will not be made.

Please use the improved ViterbiDecoder (Numeric, Advanced Comm library) for newdesign work.

The Viterbi algorithm is an optimal method of decoding convolutional codes. Optimaldecoding decisions cannot be made on a symbol-by-symbol basis; instead, the entirereceived sequence must be compared with all possible transmitted sequences. Thenumber of possible transmitted sequences increases exponentially with time; anefficient method of comparing sequences is necessary.

The Viterbi algorithm is computationally efficient, but its complexity increasesexponentially with the constraint length of the code. The Viterbi decoder measureshow similar the received sequence is to a transmitted sequence by computing anumber called the path metric (the path metric of a sequence is computed by addingtogether numbers known as the symbol metric, which are a measure of how close areceived symbol is to each of the possible transmitted symbols). The transmittedsequence corresponding to the smallest path metric is declared to be the most likelyone.

The main features of the Viterbi decoder component are:

• The number of bits used to quantize the input data can be varied from1 to infinity. The default quantizer uniformly quantizes the region between -1Vand +1V; other types of quantizers can be specified by the user.

• The Euclidean metric is used as the default symbol metric (the Euclideanmetric is the absolute value of the difference between the two symbol voltages).Other metrics can be specified by the user. The decoder assumes that the


4 DO decoded output data stream real

5 M minimum path metric real

DecoderViterbi 12-11


metrics are additive (symbol metrics must be added, not multiplied) to obtainthe path metric. At a given time instant, the path with the smallest metric isassumed to be the most likely data sequence, and the first k bits on this pathare output as the decoded bits.

• The path memory can be varied by the user.

• Automatic bit synchronization is provided for.

• The metric of the most likely path is provided as an output—by which the stateof the channel can be monitored.

Setting Parameters

• NumBits Due to its complexity, the Viterbi algorithm is implemented usingdigital circuits and, therefore, cannot deal directly with analog signals. Thereceived signal must be sampled and quantized to convert the analog waveforminto a digital signal.

The Viterbi decoder model has a built-in A/D. The clock signal CI determinesthe sampling instances of the input signals. The characteristics of the A/D canbe specified by the user simply specifying the number of quantization bits withthe NumBits parameter; if NumBits=0, then the input signal is not quantizedand the Viterbi decoder will process the analog samples themselves. This isuseful to compare the degradation in performance due to quantization. IfNumBits > 0, the Viterbi decoder will automatically set up A/D with 2NumBits

levels that are uniformly spaced between −1V and +1V.

• PathLen An important aspect of the Viterbi decoding algorithm is that uponreceiving a code word, the decoder does not immediately decide on thecorresponding output. In fact, the ideal Viterbi decoder may need to examinethe entire received signal before decoding even the first bit. This is impracticalin most situations because the variable delay in decoding and the memoryrequired by the decoder would be unacceptable. In practice, only a fixed, finitenumber of symbols of the candidate sequences are stored by the decoder, andthe bits are decoded with a fixed delay.

The length of the past history that is stored can be specified by the PathLenparameter and the decoded bits appear at the output pin with a correspondingdelay of (PathLen + 1)/Fout, where Fout is the frequency of the output clocksignal, CO. As the value of PathLen is made larger, the performance of thedecoder improves but the delay involved in decoding becomes correspondingly


larger. Typically the value of PathLen can be chosen to equal 4 to 5 times theconstraint length of the code without a serious degradation in performance.

• ReNormTh and ReNormN Bit synchronization is an important requirement forViterbi decoding. Bit synchronization is the knowledge about which of thereceived bits is the first bit of a code word. This problem can be illustrated quitesimply as follows.

Let the input data bits to a rate 1/2 encoder be denoted by DI(0), DI(1), ... . Theencoder transmits 2 bits for each input data bit and let these encoded data bedenoted as DO(0,0), DO(0,1), DO(1,0), DO(1,1), ... , where DO(k,0) and DO(k,1)are the encoded bits corresponding to the input bit DI(k). Assume that thereceiver misses the first bit (say due to synchronization problems) and,therefore, in the absence of noise, receives the data stream DO(0,1), DO(1,0),DO(1,1), ... . Because the receiver has no knowledge that the first bit has beenmissed, it assumes that DO(0,1) and DO(1,0) are the encoded bitscorresponding to the first input data bit that will cause a decoding error and,similarly, the succeeding bits are also decoded incorrectly. Therefore, even in theabsence of noise, the Viterbi algorithm may decode the data incorrectly due tothe lack of bit synchronization.

When the Viterbi decoder is synchronized and operating under normalconditions, the number of decoding errors will depend on the channel noise.This bit error rate will determine the rate at which the metric of the most likelypath will change. Under typical operating conditions, the number of decodederrors will be small and, therefore, the metric of the most likely path will notincrease rapidly. In this situation, a rapid increase in the metric of the mostlikely path will indicate that the Viterbi decoder has lost bit synchronization.

ReNormTh and ReNormN can be set by the user to enable the Viterbi decoderto attempt automatic bit synchronization if necessary. The rate of increase ofthe minimum path metric is measured by monitoring the value of the minimumpath metric and the number of code words that have been received since thetime the minimum path metric was last reset to 0 (at time=0, all path metricsare initialized to 0).

Each time the minimum path metric exceeds the value specified by ReNormTh,the minimum path metric is subtracted from all path metrics (this resets thevalue of the minimum path metric to 0). If the number of code words received(after the minimum path metric was set to 0) is less than the value specified byReNormN, it is assumed that the decoder is out of bit synchronization (for an (n,k) code, the number of code words received = the number of received bits/n). In



this case resynchronization is attempted by clocking in an extra bit into thedecoder. And, all path metrics are reset to zero.

The values to which ReNormTh and ReNormN must be set can be determinedby running the decoder in and out of bit synchronization at the required BERand comparing the rate at which the minimum path metric changes in the twocases (the signal output on pin 5 of the Viterbi decoder element is equal to theminimum path metric/ReNormTh).

The waveform in Figure 12-8 illustrates an example in which a Viterbi decoderis run in synch in a channel with an Eb/No=7.3 dB. The values chosen wereReNormTh=10 and ReNormN=30. The metric signal reaches the thresholdvalue of 10 for the first time at about 80 µsec (note that the output on this pin isthe minimum path metric normalized by ReNormTh and, therefore, a signal of1V indicates that the minimum path metric is equal to the value specified byReNormTh). Because 1 code word (2 encoded bits) is transmitted in 1 µsec, 80code words are received in 80 µsec, which is greater than the value of 30specified by ReNormN. Therefore, the Viterbi decoder assumes that it is in bitsynchronization and does not make an attempt to resynchronize.

The waveform in Figure 12-9 shows the metric of the same Viterbi decoder thatis not in synch (in this case the values chosen were ReNormTh=10 andReNormN=1, which ensures that the decoder will never attemptresynchronization because the metric can change at most by a value of 2 with 1code word). (Note that the metric now varies rapidly and the metric is resetevery 25 µsec after the first 100 µsec.)

On the basis of these two measurements, it is obvious that a suitable value ofReNormN should lie between 25 and 80.

Figure 12-10 shows the metric of a Viterbi decoder that is initially out of synchand with ReNormTh=10 and ReNormN=30. It acquires synch at time =110 µsec and the metric varies normally thereafter.

The values for ReNormN and ReNormTh should be chosen with care: if theratio of ReNormTh/ReNormN is too large, the decoder will never attempt tosynchronize; if the ratio is too small, the decoder may mistake a burst ofchannel errors as a loss of synchronization and attempt to resynchronize evenwhen it is in synch.


Figure 12-8. Viterbi Decoder, Eb/No = 7.3 dB

Figure 12-9. Viterbi Decoder, ReNormTh=10, ReNormN=1

Figure 12-10. Viterbi Decoder, ReNormTh=10, ReNormN=30



Requirements of Clock Signals

The Viterbi decoder requires two clock signals, one to clock in the data (CI), and theother to clock out the data (CO). For proper operation of the decoder, the frequenciesof the input and output clocks must be set up properly. For any (n, k) code thefollowing conditions must be satisfied:

Fin = RD and n Fout = k Fin

where RD = input data rate, Fin = input clock frequency, and Fout = output clockfrequency.

The output clock frequency and the path memory truncation length, PathLen,determine the decoding delay according to the equation:

Decoding delay = (PathLen + 1)/Fout

The clock signals can be generated in a manner similar to that described for theconvolutional encoder element (see the documentation for the CoderConvolutioncomponent for details). It should also be noted that if the positive edges of CI and COoccur simultaneously, then CI is serviced first, then CO.

Validation of the Viterbi Decoder Model

Table 12-1 lists BER measurements for a rate 1/2 code (g[0,0]=171, g[0,1=133) and amemoryless, additive white Gaussian channel. Simulations were made with harddecision decoding (a binary quantizer) and with soft decision decoding (a 3-bitquantizer). Simulation results are listed along with results published byQUALCOMM (Technical Data Sheet, Q0256). Note that the published data and thesimulation results agree.

Table 12-1. BER Measurements

Hard Decision Soft Decision (3 Bits)

uncodedEb/No(dB) Simulated BER QUALCOMM BER Simulated BER QUALCOMM BER

3.0 8.2e-4 8e-4

3.5 2.13e-4 2e-4

4.0 6.37e-3 6.5e-3 3.4e-5 3.5e-5

4.5 1.82e-3 1.8e-3 7.2e-6 7e-6

5.0 6.0e-4 5.5e-4

5.5 1.0e-4 0.9e-4

6.0 3.88e-5 4.0e-5


References

[1]A. J. Viterbi and Omura, Principles of Digital Communication and Coding,McGraw Hill, 1979.

[2] S. Lin and D. J. Costello, Error Control Coding, Prentice Hall, 1983.

[3] J. A. Heller and I. M. Jacobs, “Viterbi Decoding for Satellite and SpaceCommunications,” IEEE Trans. Commn. Tech., COM-19, pp. 835-848, Oct. 1971.

12-17


12-18

Appendix A: WMAN Example Designs

IntroductionWMAN example designs created in ADS are based on the IEEE 802.16d Standard.These designs (constructed using the new Numeric Advanced Comm components,basic ADS components, and Matlab components) focus on the physical layer ofWMAN systems. They are intended to be a baseline system for designers to get anidea of what nominal or ideal system performance would be. Evaluations can be maderegarding degraded system performance due to system impairments that mayinclude nonideal component performance.

Access the designs from the ADS Main window: File > Example Project > Com_Sys >WMAN_802_16d_TX_prj.

The ADS2004A designs focus on transmitters: Test_WMAN_802_16dRF.dsn fortesting a DUT under a WMAN frequency division duplex downlink system;Test_WMAN_CodedSignals.dsn for generating fully-coded signals; and,Test_WMAN_ESG.dsn for downloading WMAN data to an ESG. Receiver designs willbe addressed beyond ADS2004A.

Agilent Instrument CompatibilityThese WMAN designs can be used for downloading data to Agilent instrumentthrough ESG_E4438C_Sink or CM_ESG_E4438C_Sink. WMAN data can driveAgilent ESG instruments such as E443xB or E4438C to generate RF signals. Usingthese RF WMAN signals from an E4438C, WMAN device under test (DUT) can betested. Basic system performances can be measured using Agilent 89600 SeriesVector Signal Analyzer (VSA) for spectrum as well as waveforms.

Table A-1 lists instrument models and Fireware revisions.

Table A-1. Agilent Instrument Compatibility Information

WMAN Designs ESG Models VSA Models

SpecVersion=802.16d,Dec. 2003 E443xB, Fireware Revision B.03.75

E4438C, Fireware Revision C.02.20

89600 Series, software version 5.0

A-1

WMAN Example Designs

For more information about the ESG series digital and analog RF signal generators,visit

http://www.agilent.com/find/ESG

For more information about the 89600 series vector signal analyzers, visit

http://www.agilent.com/find/89600

WMAN IEEE 802.16 SpecificationsIEEE 802.16a was initiated for WMAN systems. The revised version IEEE 802.16d[1] specifies the air interface of a fixed (stationary) point-to-multipoint broadbandwireless access system providing multiple services in a wireless metropolitan areanetwork. The standard includes a particular PHY specification applicable to systemsoperating at 2- to 11-GHz. The 2- to 11-GHz air interface has options such asWirelessMAN-SCa, WirelessMAN-OFDM, WirelessMAN-OFDMA, andWirelessHUMAN.

WMAN standards for both WirelessMAN-OFDM and WirelessMAN-OFDMA havephysical layers based on OFDM. OFDM transmits data simultaneously overmultiple, parallel frequency sub-bands and offers robust performance under severeradio channel conditions. OFDM also provides a convenient method for mitigatingdelay spread effects. A cyclic extension of the transmitted OFDM symbol can be usedto achieve a guard interval between symbols. Provided that this guard intervalexceeds the excess delay spread of the radio channel, the effect of the delay spread isconstrained to frequency selective fading of the individual sub-bands. This fading canbe canceled by means of a channel compensator, which takes the form of a single tapequalizer on each sub-band.

IEEE 802.16d OFDM physical layer settings are listed in Table A-2.

Table A-2. OFDM Physical Layer Specifications

Specification Settings

Information data rate 4-70 Mbps

Modulation QPSK OFDM, 16-QAM OFDM, and 64-QAM OFDM

Error correcting code Reed-Solomon plus Convolutional Code

Overall Coding rate 1/2, 3/4, 2/3

Basic FFT Size 256

Number of subcarriers 200, DC nulled

A-2

WMAN System DesignsWMAN system design basic components include signal sources, channels, receivers,and measurements. Signal sources and measurements based onWirelessMAN-OFDM are the focus in ADS2004A.

Signal Sources

IEEE 802.16d FDD DL signal sources are provided in the example project. Based onthe 16d Standard, a WMAN 16d downlink PHY PDU is defined (see Figure A-1) thatstarts with a long preamble for PHY synchronization. The preamble is followed by aframe control header (FCH) burst. The FCH burst is one OFDM symbol long and istransmitted using QPSK rate 1/2 with the mandatory coding scheme.

The FCH is followed by one or multiple downlink bursts, each transmitted withdifferent burst profiles. Each downlink burst consists of an integer number of OFDMsymbols, and its burst profiles are specified by a 4-bit DIUC in the DL-MAP. DIUCencoding is defined in the DCD messages.

Number of Pilot tones 8

Cyclic Prefix (or Guard Interval) 1/32,1/16,1/8 and 1/4 symbol period

Table A-2. OFDM Physical Layer Specifications (continued)

Specification Settings

A-3


Figure A-1. OFDM Frame Structure with FDD DL

With the OFDM PHY, a PHY burst (downlink or uplink), consists of an integernumber of OFDM symbols carrying medium access control (MAC) messages, i.e.,MAC PDUs. To form an integer number of OFDM symbols, a burst payload can bepadded by the bytes 0xFF. The payload is then scrambled, encoded, and modulatedusing the burst PHY parameters specified by the 16d Standard.

The example designs are to aid in understanding the WMAN 802.16d transmissionsystem and to find its basic performance in the physical layer. Simulation willgenerate single bursts of data, formatted for downlink in the mandatory codingschemes.

Figure A-2 shows an OFDM frame structure for the WMAN FDD DL system in theTest_WMAN_CodedSignal.dsn example; Figure A-2 highlights the main componentsat the sub-system level. (Refer to “Fully-Coded Signal Generation” on page A-21 fordetails regarding this design.)

frame n-1 frame n+1

DL subframe

frame n frame n+2

time

DL PHY PDU

One or more multiple DL bursts,each with different burst profiles

Preamble FCH DL burst #1 ... DL burst #m

DL Fr DL/UL-MAP, paddingPrefix DCD, UCD (optional)

MAC Header MAC msg payload CRC6 bytes (optional) (optional)

MAC Msg 1(MAC PDU-1)

MAC Msg n(MAC PDU-n) pad...

Rate ID4 bits

Length12 bits

HCS8 bits

One OFDM symbolwith known burst profile

A-4

Figure A-2. WMAN FDD DL System in ADS:Test_WMAN_CodedSignal.dsn

A-5


To understand WMAN FDD DL signal generation, basic components for constructingsub-systems will be described, then sub-system components such as preamblegeneration, FCH channel, data generation, OFDM modulation, multiplexing, andmeasurements for WMAN systems will be described.

This section describes the basic components used in the designs; for details regardingeach design, refer to “WMAN Design Example Descriptions” on page A-21.

Basic Components

Data Modulation

After bit interleaving, data bits in both FCH and DL data channels are enteredserially to the constellation mapper. Gray-mapping is needed for data modulationand the constellations are specified in Section 8.3.3.4 in 802.16d. In the WMANexamples, Mapper (Numeric Advanced Comm library) provides Gray-mapped QPSK,16-QAM and 64-QAM modulations.

Pilot Modulation

Pilot subcarriers are inserted into each data burst in order to constitute the symboland they are modulated according to their carrier location within the OFDM symbol.A PRBS generator will be used to produce a sequence. The polynomial for the PRBSgenerator is X11 + X9 + 1.

The pilot modulation value for OFDM symbol k is derived from wk. On the downlink,index k represents the symbol index relative to the beginning of the downlinksubframe; on the uplink, index k represents the symbol index relative to thebeginning of the burst. For uplink and downlink, the first symbol of the preamble isdenoted by k=1. Downlink and uplink initialization sequences are shown inFigure A-3. For the downlink, this results in the sequence11111111111000000000110... where the third 1 (w3 =1) will be used in the firstOFDM downlink symbol following the frame preamble. For each pilot (indicated byfrequency offset index), BPSK modulation will be derived as follows:

DL: C 88– C 38– C63 C= 88 1 2wk and C 63– C 13– C13 C= 38 1 2wk–= = =–= = =

UL: C 88– C 38– C13 C38 C= = 63 C88 1 2wk and C 63– C 13– 1 2wk–= =–= = = =

A-6

Figure A-3. PRBS for Pilot Modulation

To implement the pilot PRBS sequence in ADS, an LFSR component is used withparameter settings: Seed=2047 (corresponding to the initial sequence: 1 1 1 1 1 1 1 11 1 1) and FeedbackList="11 9". The random data generated from the LFSR can berecorded as a data file; a WaveFormCx component is used to read this data andoutput as the PRBS sequence for pilot modulation.

Multiplexing for Frame Structure

In the WMAN examples, the AsyncCommutator component with BusMerge2 is usedto multiplex 2 different data/signals/preambles as shown in Figure A-2. WithBusMerge3, AsyncCommutator can be used for multiplexing 3data/signals/preambles and with BusMerge4 for multiplexing 4data/signals/preambles.

Channel Coding Components

Channel coding components will be used for both FCH and data channels. Keycomponents for channel coding include a scrambler component, forward errorcorrection (FEC) component, and an interleaver component.

The Scrambler component scrambles data with the appropriate LFSR initializationfor uplink or downlink.

The shift-register of the randomizer is initialized for each new allocation. The PRBSgenerator is shown in Figure A-4. Each data byte to be transmitted is sequentiallyentered into the randomizer, MSB first. Preambles are not randomized. The seedvalue is used to calculate the randomization bits, which are combined in an XORoperation with the serialized bit stream of each burst. The randomizer sequence isapplied only to information bits.

987654321 10 11

InitializationSequences

DL: 111111111 1 1

UL: 101010101 0 1

MSB LSB

wk

A-7


Figure A-4. Scrambling Data Generation

The bits issued from the randomizer are applied to the encoder. On the downlink, therandomizer is re-initialized at the start of each frame with the sequence: 1 0 0 1 0 1 01 0 0 0 0 0 0 0.

To implement the scrambler, an LFSR component is used with parameter settings:Seeds=38144 (corresponding to initial sequence 1 0 0 1 0 1 0 0 0 0 0 0 0) andFeedbackList="15 14". The random data generated from the LFSR can be recorded asa data file; a WaveFormCx component is used to read this data and output as thescramble sequence.

WMAN FEC, consisting of the concatenation of a Reed-Solomon outer code and arate-compatible convolutional inner code, supports uplink and downlink. BTC andCTC support is optional. The Reed-Solomon convolutional coding rate 1/2 is used asthe coding mode when requesting access to the network and in the FCH burst.Encoding is performed by first passing data in block format through the RS encoder.

Reed-Solomon encoding is derived from a systematic RS(N=255, K=239, T=8) codeusing GF(28), where N is the number of overall bytes after coding, K is the number ofdata bytes before coding and T is the number of the data bytes that can be corrected.802.16d systems uses much smaller code blocks by puncturing the large code blocksdown to the required size.

In the WMAN_CodedSignals.dsn example a CoderRS component is used to generatethe RS code based on 802.16d.

Each RS block is followed by the binary convolutional encoder with native rate of 1/2,a constraint length of 7, using polynomial codes to drive its code bits; the encoder isillustrated in Figure A-5.

987654321 10 11

MSB LSB

15141312

data indata out

A-8

Figure A-5. Convolutional Encoder, Rate 1/2

Convolutional coded data will be punctured before interleaving. Puncturing patternsand serialization order used to realize different code rates are given in Table A-3,where 1 denotes a transmitted bit, 0 denotes a removed bit, and X and Y are inreference to Figure A-5.

Table A-4 gives the block sizes and the code rates used for different modulations andcode rates. As 64-QAM is optional, modulation codes are implemented only ifmodulation is implemented.

Table A-3. Inner Convolutional Code with Puncturing

Code Rates

Rate 1/2 2/3 3/4 5/6

dfree 10 6 5 4

X 1 10 101 10101

Y 1 11 110 11010

XY X1Y1 X1Y1Y2 X1Y1Y2X3 X1Y1Y2X3Y4X5

Table A-4. Channel Coding Rates

Modulation

UncodedBlock Size(bytes)

Coded BlockSize (bytes)

OverallCodingRate RS Code

CC CodeRate

QPSK 24 48 1/2 (32, 24, 4) 2/3

QPSK 36 48 3/4 (40, 36, 2) 5/6

16-QAM 48 96 1/2 (64, 48, 8) 2/3

1-bitDelay

1-bitDelay

1-bitDelay

1-bitDelay

1-bitDelay

1-bitDelay

DataInput

Y Output, G2 = 133oct

X Output, G1 = 171oct

A-9


An interleaver is used for coded signals. All encoded data bits are interleaved by ablock interleaver with a block size corresponding to the number of coded bits per theallocated subchannels per OFDM symbol Ncbps. The interleaver is defined by a 2-steppermutation: the first ensures that adjacent coded bits are mapped onto nonadjacentsubcarriers; the second ensures that adjacent coded bits are mapped alternately ontoless or more significant bits of the constellation, thus avoiding long runs of lowreliable bits. The Interleaver802 component performs the 2-step interleaving for theWMAN system.

The sub_RS_CC.dsn shown in Figure A-6 demonstrates how to generate thefully-coded signal using an RS-CC coding scheme based on 802.16d.

Figure A-6. FEC Subnetwork sub_RS_CC.dsn

This subnetwork includes a Reed-Solomon encoder component CoderRS, aconvolutional encoder component ConvolutionalCoder, and interleaver componentInterleaver802. Two subnetwork puncturing components were built for this design;by default sub_PuncRSCC is activated and sub_Puncturing is deactivated.

• The sub_PuncRSCC subnetwork shown in Figure A-7 is used for puncturingcoded data for CC code rate 2/3 only (see Table A-4). If all CC code rates need tobe supported, several subnetworks are needed using an IfElse component toswitch the subnetwork for different RateID.

16-QAM 72 96 3/4 (80, 72, 4) 5/6

64-QAM 96 144 2/3 (108, 96, 6) 3/4

64-QAM 108 144 3/4 (120, 108, 6) 5/6

Table A-4. Channel Coding Rates (continued)

Modulation

UncodedBlock Size(bytes)

Coded BlockSize (bytes)

OverallCodingRate RS Code

CC CodeRate

A-10

• The sub_Puncturing subnetwork shown in Figure A-8 supports all CC coderates defined in 802.16d.

To import Matlab functions for puncturing, a MatlabLibLink Functionparameter is specified to the Matlab function rsccpunc.m that is created basedon the puncturing given in Table A-4. This simple Matlab m file can be found inWMAN_802_16d_TX_prj\data. For details regarding MatlabLibLink, refer toChapter 10 “Introduction to MATLAB Cosimulation” in the ADS PtolemySimulation manual.

Figure A-7. sub_PuncRSCC.dsnPuncturing for CC Code Rate 2/3

Figure A-8. sub_Puncturing.dsnPuncturing for All CC Code Rates

A-11


Preambles

All preambles are structured as either one of two OFDM symbols as specified inSection 8.3.3.6 Draft IEEE 802.16d Std [1].

The first preamble in the downlink PHY PDU (as well as the initial rangingpreamble) consists of two consecutive OFDM symbols (the combination of the twoOFDM symbols is referred to as the long preamble). The first OFDM symbol usesonly subcarriers indices that are a multiple of 4. As a result, the time domainwaveform of the first symbol consists of 4 repetitions of 64-sample fragment, precededby a cyclic prefix (CP). The second OFDM symbol uses only even subcarriers,resulting in a time domain structure with 2 repetitions of a 128-sample fragment,preceded by a CP. The time domain structure is illustrated in Figure A-9.

Figure A-9. Downlink and Network Entry Preamble Structure

The frequency domain sequences for all full-bandwidth preambles are derived fromthe sequence:

Pall(-100:100)=1-j, 1-j, -1-j, 1+j, 1-j, 1-j, -1+j, 1-j, 1-j, 1-j, 1+j, -1-j, 1+j, 1+j, -1-j, 1+j,-1-j, -1-j, 1-j, -1+j, 1-j, 1-j, -1-j, 1+j, 1-j, 1-j, -1+j, 1-j, 1-j, 1-j, 1+j, -1-j, 1+j, 1+j, -1-j,1+j, -1-j, -1-j, 1-j, -1+j, 1-j, 1-j, -1-j, 1+j, 1-j, 1-j, -1+j, 1-j, 1-j, 1-j, 1+j, -1-j, 1+j, 1+j,-1-j, 1+j, -1-j, -1-j, 1-j, -1+j, 1+j, 1+j, 1-j, -1+j, 1+j, 1+j, -1-j, 1+j, 1+j, 1+j, -1+j, 1-j,-1+j, -1+j, 1-j, -1+j, 1-j, 1-j,1+j, -1-j, -1-j, -1-j, -1+j, 1-j, -1-j, -1-j, 1+j, -1-j, -1-j, -1-j, 1-j,-1+j, 1-j, 1-j, -1+j, 1-j, -1+j,-1+j, -1-j, 1+j, 0, -1-j, 1+j, -1+j, -1+j, -1-j, 1+j, 1+j, 1+j, -1-j,1+j, 1-j, 1-j, 1-j, -1+j, -1+j, -1+j, -1+j, 1-j, -1-j, -1-j, -1+j, 1-j, 1+j, 1+j, -1+j, 1-j, 1-j, 1-j,-1+j, 1-j, -1-j, -1-j, -1-j, 1+j,1+j, 1+j, 1+j, -1-j, -1+j, -1+j, 1+j, -1-j, 1-j, 1-j, 1+j, -1-j, -1-j,-1-j, 1+j, -1-j, -1+j, -1+j, -1+j, 1-j, 1-j, 1-j, 1-j, -1+j, 1+j, 1+j, -1-j, 1+j, -1+j, -1+j, -1-j,1+j, 1+j, 1+j, -1-j, 1+j, 1-j, 1-j, 1-j, -1+j, -1+j, -1+j, -1+j, 1-j, -1-j, -1-j, 1-j, -1+j, -1-j,-1-j, 1-j, -1+j, -1+j, -1+j, 1-j, -1+j,1+j, 1+j, 1+j, -1-j, -1-j, -1-j, -1-j, 1+j, 1-j, 1-j

The frequency domain sequence for the 4 times 64 sequence P 4x64 is defined by:

The frequency domain sequence for the 2 times 128 sequence P EVEN is defined by:

CP 64 64 64 64 CP 128128

Tg Tg TbTb

P4 64 k( )×2 2 conj PALL k( )( )××

0

=kmod4 0=

kmod4 0≠

A-12

Figure A-10 shows generation of the long preamble for a WMAN FDD downlinktransmitter.

• Data file Preamble_1_16d.txt (located at WMAN_802.16d_TX_prj/data) basedon the full-bandwidth preambles and 4 times 64 sequence equations can be usedfor the frequency preamble with 4 times 64 sequence. This Preamble 1 will begenerated by using a WaveFormCx component referring to data filePreamble_1_16d.txt.

• Using another WaveFormCx component referring to data filePreamble_2_16d.txt based on full-bandwidth preambles and 2 times 128sequence equations, Preamble 2 with 2 times 128 sequence will also begenerated.

BusMerge2 and AsyncCommutator components are used to multiplex Preamble 1and Preamble 2. The long preamble through LoadIFFTBuff802, FFT_Cx, andAddGuard form OFDM symbols with guard interval.

Figure A-10. Long Preamble Generation

PEVEN k( )2 PALL k( )×

0

=kmod2 0=

kmod2 0≠

A-13


FCH Structure

As specified in Section 8.3.4.1 Draft IEEE 802.16d Std [1], the FCH containsdownlink frame prefix to specify the burst profile and length of downlink burst 1.Downlink frame prefix fields are:

• Rate_ID Defines the burst profile of the following burst. Encoding is specifiedin Table A-5.

• Length Number of OFDM symbols (PHY payload) in the burst immediatelyfollowing the FCH burst.

• HCS An 8-bit header check sequence used to detect errors in the downlinkframe prefix.

The basic content of the FCH symbol is the downlink frame prefix implemented insub_FCH.dsn (Figure A-11). In the FCH, key parameters RateID and Length areincluded in the header. The HCS generation can be modeled by a CRC check, wherethe transmitter takes the Rate_ID and Length bytes as the input of the CRC encoderand outputs the HCS code.

As can be seen in Figure A-12, the FCH symbol from X7 will be scrambled by thescramble sequence from ReadFile and LogicXOR2, channel coded throughsub_RS_CC channel coder, mapped by Mapper, then ready for framing the WMANsignal. (Scrambler, RS-CC channel coding, and mapping were discussed in the section“Basic Components” on page A-6.)

Table A-5. OFDM Rate ID Encoding

Rate_ID Modulation RS-CC Rate

0 QPSK 1/2

1 QPSK 3/4

2 16-QAM 1/2

3 16-QAM 3/4

4 64-QAM 2/3

5 64-QAM 3/4

6 - 15 Reserved

A-14

Figure A-11. sub_FCH.dsnFCH Structure

Figure A-12. Scrambling, Channel Coding, and Mapping for FCH Symbol

A-15


Downlink Burst Generation

The sub_Data.dsn, shown in Figure A-13, generates the WMAN downlink burst(formed by MAC Header, MAC Msg, and Padding). The input data stream to themodulation is selected as random data with a specific data length. In Figure A-14,packed data is scrambled by ReadFile and LogicXOR2, channel-coded throughsub_RS_CC, mapped with Mapper, and ready for framing the WMAN signal.(Scrambler, RS-CC channel coding, and mapping were discussed in the section “BasicComponents” on page A-6.)

Figure A-13. sub_Data.dsnDownlink Burst Generation

Figure A-14. Scrambling, Channel Coding, and Mapping for Data Symbols

A-16

OFDM Modulation

The WMAN physical layer is based on OFDM modulation.

An OFDM symbol is made up of subcarriers, the number of which determines theFFT size as illustrated in Figure A-15. WMAN subcarriers types include:

• Data subcarriers for data transmission.

• Pilot subcarriers for various estimation purposes.

• Null subcarriers (no transmission at all) for guard band and DC subcarrier.

The guard band (illustrated in Figure A-16) enables the signal to naturally decay andcreate FFT brick wall shaping.

Figure A-15. OFDM Symbol

Inverse-Fourier-transforming creates the OFDM waveform; this time duration isreferred to as the useful symbol time Tb. A copy of the last Tg of the useful symbolperiod CP is used to collect multipath while maintaining the orthogonality of thetones. Figure A-16 illustrates this OFDM symbol structure in the time domain.

Figure A-16. OFDM Symbol Time Structure

TgTs

Tb

A-17


Figure A-17 shows OFDM modulation in ADS. Downlink data and FCH signalthrough channel coding and mapping are multiplexed. MuxOFDMSym802 thenmultiplexes pilot and data carriers to form WMAN OFDM symbols in the frequencydomain. LoadIFFTBuff802 and FFT_Cx then perform an inverse-FFT to form theWMAN OFDM symbols in the time domain. AddGuard adds a guard interval tocomplete the OFDM symbols.

Figure A-17. OFDM Modulation

A-18

Measurements

Measurements are provided for waveforms, spectrum, power, and constellation.

TimedSink models are directly used to display waveforms for preamble, FCH,medium access control data, and whole framed signals.

SpectrumAnalyzerResBW is used to measure the spectrum for the WMAN signals.

Signal power is measured in the region that does not include signal idle. Thetotal_pwr expression in the data display window is used with two data displaymarkers for specifying region. For CCDF, WMAN downlink frame can be measuredby using power_ccdf in the data display window with two data display markers forspecifying the region to be measured as shown in Examples.

For the WMAN constellation measurement, sub_WMAN_Constellation.dsn is used.As shown in Figure A-18 this design integrates RF demodulation, OFDMdemodulation, demultiplexing for Data and SIGNAL, and sinks for displaying Dataas well as Signal constellations. NumericSink Constellation_data displays 16-QAMconstellation for data and BPSK Constellation for the pilot; NumericSinkConstellation_sig displays FCH SIGNAL constellations.

A-19


Figure A-18. sub_WMAN_Constellation.dsnConstellation Measurement

A-20

WMAN Design Example DescriptionsThe WMAN_802_16d_prj includes: Test_WMAN_CodedSignals.dsn for fully-codedsignal generation; Test_WMAN_RFSource.dsn for transmitter test; andTest_WMAN_ESG.dsn for downloading a WMAN signal to an ESG. These designs aredescribed in the following sections. Simulation will generate single bursts of data,formatted for downlink in the mandatory coding schemes. (The optional FEC featuresare not supported.)

Fully-Coded Signal Generation

Test_WMAN_CodedSignals.dsn demonstrates how to build an OFDM framestructure for the WMAN frequency division duplex downlink (FDD DL) system inADS; the schematic is shown in Figure A-19.

The main components are provided at the subsystem level and include longpreamble, frame control header (FCH) and FDD DL data generation, OFDMmodulation, multiplexing, RF modulation, and measurements. Signals are fullycoded by RS-CC encoding and framed based on the 16d Standard.

An RF modulator for modulation of the fully-coded WMAN signal to the RF carrierfrequency is followed by an RFGain power amplifier as the DUT.

To show system performance in time as well as frequency domains, TimeSink andSpectrumAnalyzerResBW are used for both input and output of the DUT.

• In the time domain, the amplitude of the framed WMAN signal is displayedfirst, total power and CCDF are then measured using total_pwr and power_ccdfexpressions; simulation results are shown in Figure A-20.

• In the frequency domain, WMAN signal spectrum is measured for both inputand output of the DUT; simulation results are shown in Figure A-21.

A-21


Figure A-19. Test_WMAN_CodedSignal.dsn Schematic

A-22

Figure A-20. Power and CCDF Measurement Results

Figure A-21. Spectrum Measurement Results

A-23


Default settings for basic signal information are listed in Table A-6.

Table A-6. Default Settings for WMAN Measurements

Parameter Descriptions Default Setting

FSource Source carrier frequency 2.4 GHz

SourceR Source resistor 50 Ohm

Source Power Source power 20 dBm

Bandwidth System bandwidth 20m MHz

RateID Rate ID 216-QAM, coded block size 48,uncoded block size 96, overallcoding rate 1/2

Data Length Data length in bytes 256

FFT size FFT size 512

DL Frame Time FDD Downlink frame time 92 us

Guard Interval Guard interval 1/4

Idle Interval Idle interval time 2 us

Data Sub-carriers Number of subcarriers for data 200

Pilot Carriers Number of subcarriers for pilot 8

Measured Frames Number of frames measured 2

A-24

Transmission Test

Test_WMAN_RFSource.dsn tests WMAN transmission; the schematic is shown inFigure A-22.

Figure A-22. Test_WMAN_RFSource.dsn Schematic

The top level of this schematic consists of: WMAN source (sub_WMAN_802_16dRF);DUT (CktAmp with EnvOutSelector); and measurements.

sub_WMAN_802_16dRF is a local subnetwork component to generate apartially-coded WMAN signal. By pushing into this subnetwork, we can see thedesign is the same as the signal source in Figure A-19, except there is no FEC insub_WMAN_802_16dRF. For the transmission test, basic performance includingspectrum, power, CCDF, and constellation measurements will produce the sameresults with or without FEC.

Key parameters defined in Signal_Generation_Vars and Measurement_Vars, providean easy way to configure the transmitter at the top-level design. The DUT can bereplaced by customer’s DUT that will then be measured for performance.

The RF Envelope measurement is used to show the time envelope and spectrum ofeach field in the 802.16d RF signal frame: preambles, FCH and DL Data fields. Twosignals are tested, the RF source signal at the input of the RF DUT and the Meas

A-25


signal at the output of the RF DUT. RF envelope time and spectrum measurementsare implemented for each signal. Results are shown in Figure A-23.

SpectrumAnalyzerResBW is used to measure the spectrum for the WMAN signals.Results are shown in Figure A-24.

Figure A-23. Time Envelope and Spectrum of Each Frame Field

A-26

Figure A-24. Spectrum Measurement Results

A-27


Power and CCDF measurement results are shown in Figure A-25. The downlinkburst can be measured by using the power_ccdf measurement expression based onthe DUT input and output waveforms.

Figure A-25. Power and CCDF Measurement Results

A-28

Constellation measurement results shown in Figure A-26 include BPSK constellationfor pilot signal, QPSK for FCH, and 16-QAM for medium access control data.

Figure A-26. Constellation Measurement Results

A-29


Signal Downloading to ESGc

Test_WMAN_ESG.dsn generates and downloads a WMAN signal to an Agilent ESGsignal generator; the schematic is shown in Figure A-27.

Figure A-27. Test_WMAN_ESG.dsn Schematic

The RF signal generated by sub_WMAN_802_16dRF is converted to I and Q datathrough CxToRect and sent to CM_ESG_E4438C_Sink to download data to the ESGc(E4438C). The downloaded framed signal can drive ARB signal generator in ESGc forgenerating a test signal for WMAN system, sub-system, and component tests.

A WMAN power amplifier DUT can be tested using this WMAN signal. Basic systemperformances can be measured using Agilent 89600 Series Vector Signal Analyzer(VSA) for spectrum as well as waveforms.

A-30

Key Parameters

Each design in WMAN_802_16d_TX_prj contains VAR blocks for ease of setting keyparameters. Parameter settings are described here.

Signal_Generation_Vars:

• FSource specifies RF carrier frequency.

• SourcePower specifies source output power in dBm or W.

• BandOption specifies system bandwidth 1.75, 3.5, 7, 14, or 28 MHz; values areBandOption=0, 1, 2, 3, 4, respectively. Other bandwidths are not supported. Ifbandwidth < 0, set BandOption=0; if bandwidth >4, set BandOption=4.

• Rate_ID specifies data modulation and channel coding types. Table A-4 listsRateID parameters of 802.16d associate with coding rate per modulation. Forexample for RateID=2, modulation type is specified as 16-QAM and overallcoding rate is 1/2.

• DataLength is used to set the number of data bytes in a frame (or burst). Thereare 8 bits per byte.

• OversamplingOption sets the oversampling ratio of 802.16d RF signal source.Options from 0 to 4 result in oversampling ratio 1, 2, 4, 8, 16 whereoversampling ratio = 2OversamplingOption. If oversampling ratio < 0, setOversamplingOption=0; if oversampling ratio >4, set OversamplingOption=4. Ifthe oversampling ratio = 22 = 4 and the simulation RF bandwidth is larger thanthe system bandwidth by a factor of 4 (e.g. for Bandwidth=14 MHz, thesimulation RF bandwidth = 14 MHz × 4 = 16 MHz). The FFT size is determinedby OversamplingOption. FFTsize=256 × 2OversamplingOption. WhenOversamplingOption=0, 1,2,3,4, FFTsize=256,512,1024,2048 and 4096.

• IdleInterval specifies the idle interval between two consecutive frames whengenerating an 802.16d signal source.

• GuardInterval is used to set cyclic prefix in an OFDM symbol. The value rangeof GuardInterval is [0.0,1.0]. The cyclic prefix is a fractional ratio of the IFFTlength. In 802.16d, GuardInterval=1/32, 1/16, 1/8, 1/4 of the useful OFDMsymbol time.

A-31


Measurement_Vars (Test_WMAN_RFSouce.dsn and Test_WMAN_CodedSignals.dsn)

• FMeasure specifies the carrier frequency for the measurement.

• Carriers specifies the number of subcarriers for an OFDM signal.

• MeasFrames specifies the number of frames for measuring the Constellation.

ESG_Setting_Vars (Test_WMAN_ESG.dsn)

• NumberOfSubFrames specifies the number of frames measured.

• SubFrameTime specifies the signal frame time.

• Stop specifies the signal stop time to be sent to the ESG.

References[1]Draft IEEE Standard for Metropolitan Area Networks IEEE

P802.16-REVd/D2-2003, Dec, 2003

A-32

Index
AAbs, 5-2Abs_M, 6-2AbsSyn, 10-3AccumSyn, 11-2ActivatePath, 3-2ActivatePath2, 3-4AdaptLinQuant, 9-2Add, 5-3Add_M, 6-3Add2, 5-4Add2_M, 6-4AddCx, 5-5AddCx_M, 6-5AddCx2, 5-6AddCx2_M, 6-6AddFix, 5-7AddFix_M, 6-7AddFix2, 5-9AddFix2_M, 6-9AddGuard, 1-2AddInt, 5-11AddInt_M, 6-11AddInt2, 5-12AddInt2_M, 6-12AddRegSyn, 11-5AddSyn, 10-5ADPCM_Coder, 2-2ADPCM_Decoder, 2-4ADPCM_FromBits, 2-6ADPCM_ToBits, 2-7And2Syn, 10-9AndSyn, 10-7AsyncCommutator, 3-6AsyncDistributor, 3-8Autocor, 7-2Average, 5-13AverageCx, 5-14AvgSqrErr_M, 6-13AWGN_Channel, 2-8BBarShiftSyn, 10-12Biquad, 7-4BiquadCascade, 7-6BitFillSyn, 10-14
Bits, 8-2BlockAllPole, 7-8BlockFIR, 7-10BlockLattice, 7-12BlockPredictor, 2-10BlockRLattice, 7-14BPSKSyn, 10-10BufferSyn, 10-15Burg, 7-16Bus, 3-10Bus8MergeSyn, 10-17Bus8RipSyn, 10-19BusMerge2, 3-11BusMerge3, 3-12BusMerge4, 3-13BusMerge5, 3-14BusMerge6, 3-16BusMerge7, 3-18BusMerge8, 3-20BusMerge9, 3-22BusMergeSyn, 10-21BusRipSyn, 10-23BusSplit2, 3-24BusSplit3, 3-25BusSplit4, 3-27BusSplit5, 3-29BusSplit6, 3-31BusSplit7, 3-33BusSplit8, 3-35BusSplit9, 3-37CCastSyn, 10-25Chop, 3-39ChopVarOffset, 3-42CoderConvolution, 12-2CoderRS, 2-12CombFiltSyn, 10-27, 11-7Commutator, 3-43Commutator2, 3-44Commutator3, 3-45Commutator4, 3-47Comp6Syn, 10-31ComplexExp, 8-5Compress, 9-4CompSyn, 10-29

Index-1

Conjugate_M, 6-15Const, 8-6ConstCx, 8-7ConstFix, 8-8ConstInt, 8-10ConstSyn, 10-33ConvolCx, 7-20ConvolutionalCoder, 1-7Convolve, 7-18Cos, 5-15CountCombSyn, 10-34CounterSyn, 10-36CRC_Coder, 1-10CRC_Decoder, 1-12CrossCorr, 7-22Cx_M, 8-11DDataPattern, 8-13DB, 5-16DeadZone, 9-7DecoderRS, 2-15DecoderViterbi, 12-10Deinterleaver802, 1-14Delay, 3-49Delay_M, 6-16Demapper, 1-17DeMux, 3-50DeMux2, 3-52DeScrambler, 2-21DeSpreader, 2-23DFF, 4-2Diagonal_M, 8-15DiagonalCx_M, 8-16DiagonalFix_M, 8-17DiagonalInt_M, 8-19Dirichlet, 9-9Distributor, 3-53Distributor2, 3-55Distributor3, 3-56Distributor4, 3-58Div2ClockSyn, 10-42DivByInt, 5-18DivByN, 4-5DownSample, 3-60DPRamRegSyn, 11-9DPRamSyn, 10-38DPSKSyn, 10-40DTFT, 7-25

DualNCOSyn, 11-12EEnableUDSample, 3-62Exp, 5-19Expand, 9-11FFFT_Cx, 7-27FIR, 7-29FIR_Cx, 7-32FIR_Fix, 7-35FIRSyn, 11-15Fix_M, 8-20FixedGainSyn, 11-19FixToFloatSyn, 10-46Float_M, 8-22FloatToFixSyn, 10-47Floor, 5-20Fork, 3-64Fork2, 3-66Fork3, 3-68Fork4, 3-70Fork5, 3-72Fork6, 3-74Fork7, 3-76Fork8, 3-78Fork9, 3-80FreqPhase, 2-24FSMSyn, 10-43GGain, 5-21Gain_M, 6-17GainCx, 5-22GainCx_M, 6-18GainFix, 5-23GainFix_M, 6-19GainInt, 5-25GainInt_M, 6-21GainSyn, 10-49HHermitian_M, 6-22Hilbert, 7-39HilbertSplit, 2-26IIdentity_M, 8-26IdentityCx_M, 8-27IdentityFix_M, 8-28IdentityInt_M, 8-30IfElse, 3-82

Index-2

IID_Gaussian, 8-24IID_Uniform, 8-25IIR, 7-41IIR_Cx, 7-44IIR_Fix, 7-46ImpulseFloat, 8-31InitDelay, 3-86Int_M, 8-32Integrate, 5-26IntegratorSyn, 11-21InterleaveDeinterleave, 2-28Interleaver802, 1-23Inverse_M, 6-23InverseCx_M, 6-24InverseFix_M, 6-25InverseInt_M, 6-27JJKFF, 4-8KKalman_M, 6-28LLatchClocked, 9-14Lattice, 7-49LCounterSyn, 10-51LevDur, 7-52LFSR, 4-11Limit , 9-16LinQuantIdx, 9-19LMS, 7-54LMS_Cx, 7-56LMS_Leak, 7-59LMS_OscDet, 7-61Ln, 5-28LoadIFFTBuff802, 1-26Logic, 4-19LogicAND, 4-20LogicAND2, 4-21LogicInverter, 4-22LogicLatch, 4-23LogicNAND, 4-25LogicNAND2, 4-26LogicNOR, 4-27LogicNOR2, 4-28LogicOR, 4-29LogicOR2, 4-30LogicXNOR, 4-31LogicXNOR2, 4-32LogicXOR, 4-33

LogicXOR2, 4-34MMapper, 1-30Math, 5-29MathCx, 5-31Matlab_M, 6-30MatlabCx_M, 6-32MatlabF_M, 6-34MatlabFCx_M, 6-36MatlabLibLink, 6-38MatlabLibLinkCx, 6-40MatlabSink, 6-42MatlabSinkF, 6-44MaxMin, 5-33Modulo, 5-35ModuloInt, 5-36Mpy, 5-37Mpy_M, 6-46Mpy2, 5-38MpyCx, 5-39MpyCx_M, 6-47MpyCx2, 5-40MpyFix, 5-41MpyFix_M, 6-49MpyFix2, 5-43MpyInt, 5-45MpyInt_M, 6-51MpyInt2, 5-46MpyScalar_M, 6-52MpyScalarCx_M, 6-53MpyScalarFix_M, 6-54MpyScalarInt_M, 6-56MuLaw, 9-21Multiple, 4-35MultRegSyn, 11-24MultSyn, 10-53Mux, 3-87Mux2, 3-89Mux2Syn, 10-57, 11-26Mux3Syn, 10-58, 11-27Mux4Syn, 10-60, 11-29MuxOFDMSym802, 1-36MuxSyn, 10-55MxCom_M, 6-57MxDecom_M, 6-59NNand2Syn, 10-62NCOSyn, 11-31

Index-3

NoiseChannel, 2-30NonlinearDistortion, 2-31Nor2Syn, 10-63NotSyn, 10-64numeric communications components, 2-1numeric logic components, 4-1numeric math components, 5-1numeric matrix components, 6-1numeric signal processing components, 7-1numeric sources, 8-1numeric special functions, 9-1numeric synthesizable DSP components, 10-1numeric synthesizable DSP Xilinx components, 11-1NumericExpression, 8-34NumericSource, 8-35OOQPSKSyn, 10-65Or2Syn, 10-67OrderTwoInt, 9-23OrSyn, 10-68PPack_M, 6-61PackCx_M, 6-62PackFix_M, 6-63PackInt_M, 6-65PAM2Rec, 2-32PAM2Xmit, 2-33PAM4Rec, 2-35PAM4Xmit, 2-36PattMatch, 7-64PCM_BitCoder, 2-38PCM_BitDecoder, 2-39PcwzLinear, 9-25PhaseShift, 2-40PI4DQPSKSyn, 10-70Polynomial, 9-27PSK2Rec, 2-41PSK2Xmit, 2-43PSK8Syn, 10-72QQAM16, 2-45QAM16Decode, 2-46QAM16Slicer, 2-47QAM4, 2-48QAM4Slicer, 2-50QAM64, 2-51QAM64Decode, 2-52QAM64Slicer, 2-53

QPSKSyn, 10-74Quant, 9-28QuantIdx, 9-30Quantizer, 9-32Quantizer2D, 9-34RRaisedCosine, 2-54RaisedCosineCx, 2-57RampFix, 8-37RampFloat, 8-40RampInt, 8-41RamRegSyn, 11-34RamSyn, 10-76ReadFile, 8-42ReadFilePreProc, 8-43Reciprocal, 5-47RecSpread, 2-59Rect, 8-45RectCx, 8-46RectCxDoppler, 8-47RectFix, 8-49RegSyn, 10-78Repeat, 3-91Reverse, 3-92RLattice, 7-66RMSE, 1-41RomRegSyn, 11-37RomSyn, 10-80SSampleMean_M, 6-66SchmittTrig, 9-38Scrambler, 2-60SDC1, 5-49SDC2, 5-50SDC3, 5-51SDC4, 5-52SDCCx1, 5-54SDCCx2, 5-55SDCCx3, 5-56SDCCx4, 5-58SerialFIRSyn, 11-40Sgn, 5-60ShiftRegPPSyn, 10-82ShiftRegPSSyn, 10-84ShiftRegSPSyn, 10-86Sin, 5-61Sinc, 5-62SineCosineSyn, 10-88, 11-43

Index-4

SineGen, 8-51SinkRespSyn, 10-90SinkStimSyn, 10-91SlidWinAvg, 7-69Spread, 2-64Sqrt, 5-63Sub, 5-64Sub_M, 6-67SubCx, 5-65SubCx_M, 6-68SubFix, 5-66SubFix_M, 6-69SubInt, 5-68SubInt_M, 6-71SubMx_M, 6-72SubMxCx_M, 6-74SubMxFix_M, 6-76SubMxInt_M, 6-78SubRegSyn, 11-45SVD_M, 6-80SymFIRSyn, 11-47TTable, 9-40Table_M, 6-82TableCx, 9-42TableCx_M, 6-84TableInt, 9-44TableInt_M, 6-86TelephoneChannel, 2-65Test, 4-36TestEQ, 4-38TestGE, 4-39TestGT, 4-40TestLE, 4-42TestLT, 4-44TestNE, 4-46Toeplitz_M, 6-88ToeplitzCx_M, 6-90ToeplitzFix_M, 6-92ToeplitzInt_M, 6-95Toggle, 9-46Trainer, 3-93Transpose, 3-95Transpose_M, 6-97TransposeCx_M, 6-98TransposeFix_M, 6-99TransposeInt_M, 6-100Trig, 5-69

TrigCx, 5-70UUnPk_M, 6-101UnPkCx_M, 6-102UnPkFix_M, 6-103UnPkInt_M, 6-105Unwrap, 9-48UpSample, 3-96VVariance, 5-71ViterbiDecoder, 1-43WWalshCoder, 2-67WaveForm, 8-52WaveFormCx, 8-54Window, 8-56XXmitSpread, 2-70Xor2Syn, 10-94XorSyn, 10-92ZZeroInterpSyn, 10-95

Index-5

Index-6

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