MSP430 Debugger - · PDF fileMSP430 Debugger 2 ©1989-2017 Lauterbach GmbH SYStem.BdmClock Define JTAG frequency 18 SYStem.CONFIG Configure debugger according to target topology 19

MSP430 Debugger

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TRACE32 Documents ......................................................................................................................

ICD In-Circuit Debugger ................................................................................................................

Processor Architecture Manuals ..............................................................................................

MSP430 .....................................................................................................................................

MSP430 Debugger ................................................................................................................ 1

Brief Overview of Documents for New Users ................................................................. 3

Warning .............................................................................................................................. 4

General Notes/Target Design Requirements/Recommendations 4

General ............................................................................................................................... 5

Target Design Requirements 5

Limitations 5

Contacting Support ........................................................................................................... 6

Quick Start ......................................................................................................................... 7

Troubleshooting ................................................................................................................ 10

Communication between Debugger and Processor can not be established 10

FAQ ..................................................................................................................................... 11

MSP430 Specific Implementations .................................................................................. 13

Breakpoints 13

Software Breakpoints 13

On-chip Breakpoints 13

Breakpoints on Data Addresses and Data Values 14

Breakpoints on Registers 14

Breakpoints on Interrupts 14

Example for Standard Breakpoints 15

Cycle Counter 16

Runtime Measurement 16

Memory Classes 17

State Storage 17

Trigger Sequencer 17

General SYStem Commands ............................................................................................ 18

SYStem.state Display SYStem.state window 18

MSP430 Debugger 1 ©1989-2018 Lauterbach GmbH

SYStem.BdmClock Define JTAG frequency 18

SYStem.CONFIG Configure debugger according to target topology 19

SYStem.CPU Select the used CPU 20

SYStem.CpuAccess Run-time CPU access (intrusive) 20

SYStem.JtagClock Set jtag clock frequency 21

SYStem.LOCK Lock and tristate the debug port 21

SYStem.MemAccess Run-time memory access 22

SYStem.Mode Establish the communication with the target 23

SYStem.Option Configure debugger behavior 24

SYStem.Option IMASKASM Disable interrupts for assembler single steps 24

SYStem.Option IMASKHLL Disable interrupts for HLL single steps 24

SYStem.Option LPMX5 Enable LPMx5 support 24

SYStem.Option TURBO Speed up memory access 25

SYStem.Option TCKTOTEST Configure clock output pins 25

MSP430 Specific TrOnchip Commands .......................................................................... 26

TrOnchip.CONVert Extend the breakpoint range 26

TrOnchip.RESet Set on-chip trigger to default state 26

TrOnchip.state Display on-chip trigger window 26

Low Power Mode debugging ............................................................................................ 27

Avoid loss of device 27

Supported Low Power Modes 27

Debug Connection ............................................................................................................ 29

Support ............................................................................................................................... 30

Available Tools 30

Compilers 41

Target Operating Systems 41

3rd-Party Tool Integrations 42

Products ............................................................................................................................. 43

Product Information 43

Order Information 44


MSP430 Debugger

Version 22-Mar-2018

Brief Overview of Documents for New Users

Architecture-independent information:

• “Debugger Basics - Training” (training_debugger.pdf): Get familiar with the basic features of a TRACE32 debugger.

• “T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger. T32Start is only available for Windows.

• “General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands.

Architecture-specific information:

• “Processor Architecture Manuals”: These manuals describe commands that are specific for the processor architecture supported by your debug cable. To access the manual for your processor architecture, proceed as follows:

- Choose Help menu > Processor Architecture Manual.

• “RTOS Debuggers” (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating system-aware debugging. The appropriate RTOS manual informs you how to enable the OS-aware debugging.


Warning

General Notes/Target Design Requirements/Recommendations

Before starting please be sure to have up to date debugger software by getting an update from the LAUTERBACH website. Note that the downloads on the website are stable releases but not necessarily the latest versions. Therefore in case of problems please contact LAUTERBACH support at [email protected]

NOTE: To prevent debugger and target from damage it is recommended to connect or disconnect the debug cable only while the target power is OFF.

Recommendation for the software start:

1. Disconnect the debug cable from the target while the target power is off.

2. Connect the host system, the TRACE32 hardware and the debug cable.

3. Power ON the TRACE32 hardware.

4. Start the TRACE32 software to load the debugger firmware.

5. Connect the debug cable to the target.

6. Switch the target power ON.

7. Configure your debugger e.g. via a start-up script.

Power down:

1. Switch off the target power.

2. Disconnect the debug cable from the target.

3. Close the TRACE32 software.

4. Power OFF the TRACE32 hardware.


General

• The Lauterbach TRACE32 debugger for MSP430 is a on-chip debugging tool (OCD). It uses the debug function implemented in the target CPU.

• Available debug interfaces are the 4-wire JTAG interface or the Spy-Bi-Wire interface.

• The debugging support does also include CC430 devices.

Target Design Requirements

• Locate the debug connector as close as possible to the processor to minimize the capacitive influence and cross coupling of noise onto the signals.

• Reduce the cable length between CPU and Lauterbach connector to a minimum. Best results will be provided, if a adequate connector will be foreseen directly on the target board.

• The TEST pin of the MSP430 must be connected to the debugger if available. See “Debug Connection” (debugger_msp430.pdf) on page 29 for connection information.

Limitations

• The debugger offers no target power supply.

• Locking the JTAG interface is currently not supported.

• Multicore debugging is currently not supported. Please contact technical support if you intend to debug multicore setups.


Contacting Support

LAUTERBACH GmbHAltlaufstrasse 4085635 Hoehenkirchen-SiegertsbrunnGermany

Be sure to include detailed system information about your TRACE32 configuration.

1. To generate a system information report, choose TRACE32 > Help > Support > Systeminfo.

2. Preferred: click Save to File, and send the system information as an attachment to your e-mail.

3. Click Save to Clipboard, and then paste the system information into your e-mail.

Phone (+49) 8102-9876-555

Fax (+49) 8102-9876-187

Internet http://www.lauterbach.com/tsupport.html or http://www.lauterbach.com/report.html Here you’ll find local and special support addresses.

E-mail [email protected] support address where your request will be answered within a short time if it is a basic support request or redirected to the appropriate address.

NOTE: Please help to speed up processing of your support request. By filling out the system information form completely and with correct data, you minimize the number of additional questions and clarification request e-mails we need to resolve your problem.


http://www.lauterbach.com/tsupport.html

http://www.lauterbach.com/report.html

Quick Start

Starting up the debugger is done by the following steps:

1. Select the device prompt B: for the TRACE32 ICD-Debugger, if the device prompt is not active after starting the TRACE32 software.

The device prompt B:: is normally already selected in the command line. If this is not the case enter B: to set the correct device prompt. A RESet command is useful if you do not start directly after booting the TRACE32 development tool.

2. Select the CPU derivative to load the specific settings.

The default value for SYStem.CPU is “MSP430”, which is a derivative that does not exist. You should always select an appropriate device. Otherwise the debug connection to the target might fail. The default values of all other SYStem options are set in such a way that it should be possible to work without modification. Please consider that this is probably not the best configuration for your target.

3. Enter debug mode.

4. Declare size and type of FLASH memory is recommended doing via script.

Select the adequate PRACTICE script for the connected target. It will set up the flash memory to allow writing and setting of software-breakpoints. A number of demo *.cmm scripts for flash programming is included in your MSP430 installation demo directory.

You can load a program into flash (if this was not already done by the demo script) as follows:

5. Load the program.

This example loads a sieve demo for the MSP430F5438 evaluation board. Data.Load.AUTO detects automatically the correct format. Refer to Supported Compilers” to see if your compiler is supported or not. The option auto is not mandatory an could be left aside. Loading an application to flash memory is only possible if the flash is declared correctly and unlocked. Please refer to the flash demo scripts if you need an example for this.

A detailed description of the Data.LOAD command and all available options is given in the “General Reference Guide”.

b::

SYStem.CPU <cputype>

SYStem.Mode Up

DO ~~/demo/msp430/flash/msp430f*.cmm

Data.LOAD.auto ~~/demo/msp430/hardware/msp_exp430f5438/sieve.d43


A typical start sequence is shown below. This sequence can be written to PRACTICE script file (*.cmm, ASCII file format) and executed with the command DO <filename>.

*) These commands open windows on the screen. The window position can be specified with the WinPOS command.

B:: ; Select the ICD-Debugger device prompt

RESet ; Reset TRACE32 Software (not target!)

WinCLEAR ; Clear all windows

SYStem.CPU MSP430F5438 ; Select the CPU derivative type

SYStem.Up ; Reset the target and enter debug mode

DO ~~/demo/msp430/flash/msp430f5xx.cmm

; Start flash programming and load the; application

Register.Set PC main ; Set the PC to function main

Register.view /SpotLight ; Open register window *)

Data.List ; Open source code window *)

Frame.view /Locals /Caller ; Open the stack frame with ; local variables *)

Var.Watch %Spotlight flags ast ; Open watch window for variables *)

PER.view ; Open a window for the special; function registers and peripherals *); Appropriate cpu must be selected!


Having executed this script your debug session might look like this:

Data.List PER.view

Frame.viewVar.WatchRegister.view

Command line


Troubleshooting

Communication between Debugger and Processor can not be established

Typically the SYStem.Up command is the first command of a debug session where communication with the target is required. If you receive error messages like “debug port fail” or “debug port time out” while executing this command this may have the reasons below. “target processor in reset” is just a follow-up error message. Open the AREA window to view all error messages.

• The target has no power or the debug cable is not connected to the target. This results in the error message “target power fail”.

• The target is in an unrecoverable state. Re-power your target and try again.

• The default debug clock speed is too fast, especially if the target is connected to the debugger by a long cable. Reduce the communication speed with SYStem.JtagClock command and optimize the speed when you got it working.

• The CPU has no clock.

• The CPU is kept in reset.

• Although the debugger takes care of the watchdog you should check if there is a watchdog which needs to be deactivated.

• The target is in low power mode and the JTAG interface is not available.

• The target is protected via JTAG fuse / password. In this case it is not possible to establish a JTAG connection.

• In case you’ve selected Spy-Bi-Wire (SBW) to connect to the target, check if there are capacities connected to the reset line. In SBW mode the MSP430 shares the data line with the reset line. Any capacities/loads might act as low-pass that reduces your possible clock speed.

• The core is in LPMx.5 (Low power mode with JTAG turned off). The core could not be recovered via JTAG. Try to connect to your core using the Spy-Bi-Wire (SBW) interface.


FAQ

Debugging via VPN

The debugger is accessed via Internet/VPN and the performance is very slow. What can be done to improve debug performance?

The main cause for bad debug performance via Internet or VPN are low data throughput and high latency. The ways to improve performance by the debugger are limited:

• in practice scripts, use "SCREEN.OFF" at the beginning of the script and"SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates.Please note that if your program stops (e.g. on error) without executing"SCREEN.OFF", some windows will not be updated.

• "SYStem.POLLING SLOW" will set a lower frequency for target statechecks (e.g. power, reset, jtag state). It will take longer for the debugger torecognize that the core stopped on a breakpoint.

• "SETUP.URATE 1.s" will set the default update frequency ofData.List/Data.dump/Variable windows to 1 second (the slowest possiblesetting).

• prevent unneeded memory accesses using "MAP.UPDATEONCE[address-range]" for RAM and "MAP.CONST [address--range]" forROM/FLASH. Address ranged with "MAP.UPDATEONCE" will read thespecified address range only once after the core stopped at a breakpoint ormanual break. "MAP.CONST" will read the specified address range onlyonce per SYStem.Mode command (e.g. SYStem.Up).


Setting a Software Breakpoint fails

What can be the reasons why setting a software breakpoint fails?

Setting a software breakpoint can fail when the target HW is not able to implement the wanted breakpoint.

Possible reasons:

• The wanted breakpoint needs special features that are only possible torealize by the trigger unit inside the controller.

Example: Read, write and access (Read/Write) breakpoints ("type" in Break.Set window). Breakpoints with checking in real-time for data-values ("Data"). Breakpoints with special features ("action") like TriggerTrace, TraceEnable, TraceOn/TraceOFF.

• TRACE32 can not change the memory.Example: ROM and Flash when no preparation with FLASH.Create, FLASH.TARGET and FLASH.AUTO was made. All type of memory if the memory device is missing the necessary control signals like WriteEnable or settings of registers and SpecialFunctionRegisters (SFR).

• Contrary settings in TRACE32.Like: MAP.BOnchip for this memory range. Break.SELect.<breakpoint-type> Onchip (HARD is only available for ICE and FIRE).

• RTOS and MMU:If the memory can be changed by Data.Set but the breakpoint doesn't work it might be a problem of using an MMU on target when setting the breakpoint to a symbolic address that is different than the writable and intended memory location.


MSP430 Specific Implementations

Breakpoints

Two types of breakpoints are available for MSP430 architecture: Software breakpoints (SW-BP) and on-chip breakpoints (HW-BP).

Software Breakpoints

Software breakpoints are the default breakpoints. To set a software breakpoint, before resuming the CPU, the debugger replaces the instruction at the breakpoint address with a breakpoint code instruction. SW-BPs can be used in RAM areas and in FLASH areas if FLASH.AUTO is set properly.

There is no restriction in the number of software breakpoints. But it must be considered that by setting software breakpoints in flash the flash memory will be changed. Consequently the use of software breakpoints in flash will reduce the number of program/erase cycles that are left for the flash.

Please note that software breakpoints consume one on-chip breakpoint resource if one or more software breakpoints are set. This must be taken into account when combining on-chip and software breakpoints.

On-chip Breakpoints

If on-chip breakpoints are set the debugger will configure the integrated debug hardware of the MSP430 for this purpose. Current available MSP430 devices allow to set 2 to 8 on-chip breakpoints (device dependent). Breakpoints that are set on code in read only memory must be on-chip breakpoints. With the command MAP.BOnchip <range> it is possible to declare memory address ranges for use with on-chip breakpoints to the debugger. The number of onchip breakpoints to be set depends on the complexity of the desired breakpoint. Complex breakpoints consume more hardware resources than simple ones. Onchip breakpoints take effect before execution.

The Lauterbach MSP430 debugger allows to use a powerful variety of breakpoints. Available breakpoint types are also device dependent. It is possible to use the following breakpoints:

• Program/Instruction Breakpoints: Break on instruction fetch, either on single address or address range

• Data Breakpoints: Break on data read and/or write on a single address or address range

• Memory Breakpoints: Break when a certain program part does a read/write access to a certain address range.

• Register Breakpoint: Break when a certain register is written (if available)

• All range breakpoints might be used with the exclude option

You can check your breakpoint setup with the command Break.List.

If no more on-chip breakpoints are available you will get an error message on trying to set a new on-chip breakpoint. Delete other breakpoints to regain debug resources.


Breakpoints on Data Addresses and Data Values

Breakpoints on data addresses are bound to several conditions:

1. The entity doing the data access (read and/or write) must be the CPU. Any other accesses from on-chip or off-chip peripherals (DMA etc.) will not be recognized by the data address breakpoints. If you would like to trigger on other sources, like the DMA, contact technical support.

2. The data being targeted must be qualified by an address in memory. It is not possible to target registers (GPRs), peripherals etc.

3. Per default the break will be done independently of the value (empty DATA field of Break.Set window).

Breakpoints on Registers

Only a break on a register write action is supported by the MSP430 hardware. Register breakpoints are not available for all MSP430. Limitations:

1. Only write actions on registers can be triggered. Other breakpoint options for this type like read or read/write would cause an error.

2. When the pc is changed after an instruction execution this will not trigger a break action.

3. Changes to SR (status register) might not always trigger a break action.

4. A register breakpoint is automatically combined with a range breakpoint since most variables mapped to registers are only valid in a certain address range.

Breakpoints on Interrupts

MSP430 devices do not offer a special mechanism to halt the device on an interrupt event. However, you can set a data read/write breakpoint on the interrupt vector table. Once an interrupt is triggered the cpu will fetch the address of the interrupt handler from the interrupt vector table. This operation will trigger the read/write breakpoint and therefore halt the cpu on an interrupt event.

Please refer to your MSP430 specific device documentation for more information on MSP430 interrupts.


Example for Standard Breakpoints

Assume you have a target (MSP430FG4618) with:

• Code flash memory from 0x3100--0x19fff

• RAM from 0x1100--0x30ff

The following standard breakpoint combinations are possible without activated auto flash mode:

1. Unlimited breakpoints in RAM and up to eight breakpoints in ROM/FLASH

2. Unlimited breakpoints in RAM and up to eight breakpoints (BP) on a read or write access and up to four breakpoints on a read and write access (On single address each). Up to two read/write range breakpoints.

Break.Set 0x11f0 /Program ; Software breakpoint 1 (RAM)

Break.Set 0x1220 /Program ; Software breakpoint 2 (RAM)

Break.Set ram_addr /Program ; Software breakpoint 3 (RAM)

Break.Set 0x4100 /Program ; On-chip breakpoint (flash)

Break.Set 0x11f0 /Program ; Software breakpoint 1 (RAM)

Break.Set 0x1332 /Write ; On-chip breakpoint (RAM)

Break.Set 0x1332--0x135E /Write ; On-chip range BP (RAM)

Break.Set 0x1334 /ReadWrite ; On-chip breakpoint (RAM)

Break.Set 0x1334++0x1C /ReadWrite ; On-chip range BP (RAM)


With activated auto flash mode even in code flash memory unlimited breakpoints (BP) are allowed. Like in RAM complex breakpoints will still need an onchip breakpoint.

3. Unlimited breakpoints in ROM/FLASH

4. Breakpoints on registers: It is assumed that variable “i” is mapped to a register. The variable shall be part of the Lauterbach sieve demo. “sieve\7” is the address where the variable is accessed within the function.

Cycle Counter

The Cycle Counter is used to evaluate the number of cycles certain actions take. This could be for example measuring the number of instruction fetches that occurred.

There is currently no support implemented. Request a software update.

Runtime Measurement

The command RunTime allows run time measurements based on polling the CPU run status by software. Therefore the result will be about few milliseconds higher than the real value.

The measured value depends on the set JtagClock for the debugger polls the cpu. A higher clock means faster communication with the target an thus a more accurate measurement.

FLASH.AUTO 0x4000--0x43FF Allow software breakpoints in specific Flash area

Break.Set 0x4100 /Program ; Software BP 1 (flash)

Break.Set 0x5320 /Program ; Software BP 2 (flash)

Break.Set flash_addr /Program ; Software BP 3 (flash)

Break.Set 0x4200--0x423f /Program ; On-chip BP (flash)

Var.Break.Set sieve\7 /VarWrite \main\sieve\i

; register breakpoint on variable “i” in sieve demo


Memory Classes

Though the MSP430 has a linear memory space, the following specific memory classes are available:

To access a memory class write the class in front of the address. Prepending an E as attribute to the memory class will make memory accesses possible, even when the target CPU is running. Such an access must be allowed: See SYStem.MemAccess and SYStem.CpuAccess for more information. Example:

Note: Since the address space of the MSP430 is linear and non-overlapping memory class D and P are not distinguished memory classes and can be left aside.

Note: The MSP430 does not allow to read/write memory during run time. This means that a memory access using the access class E: is intrusive, i.e. the CPU is continuously stopped and restarted.

State Storage

The State Storage of the MSP430 allows to records the last eight address bus, data bus and status register values, dependant on the trigger that triggers the state storage.


Trigger Sequencer

The trigger sequencer can be used to trigger an action under the condition that a certain programmed sequence happened.


Memory Class Description

P Program Memory

D Data Memory

VM Virtual Memory (memory on the debug system)

E Emulation Memory, Pseudo Dual port Access to Memory.

Data.dump E:0x200 ; View data while CPU is running

Data.dump D:0x200 ; View data memory

Data.dump VM:0x200 ; Virtual memory, no target access


General SYStem Commands

SYStem.state Display SYStem.state window

Opens the SYStem.state window, where you can configure the MSP430 debugger:

SYStem.BdmClock Define JTAG frequency

Obsolete command syntax. It has the same effect as SYStem.JtagClock. Use SYStem.JtagClock instead.

Format: SYStem.state

SYStem.JtagClock

SYStem.CPU

SYStem.Mode

SYStem.Option

SYStem.MemAccess


SYStem.CONFIG Configure debugger according to target topology

The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger of the TAP controller position in the JTAG chain if there is more than one core in the JTAG chain. The information is required before the debugger can be activated, e.g., by a SYStem.Mode.Attach.

TriState has to be used if several debugger are connected to a common JTAG port at the same time. TAPState and TCKLevel define the TAP state and TCK level which is selected when the debugger switches to TriState mode. TCK can have a pull-up or pull-down resistor, other trigger inputs need to be kept in inactive state.

Format: SYStem.CONFIG <parameter>

<parameter>: stateDEBUGPORTTYPEIRPRE <bits>IRPOST<bits>DRPRE <bits>DRPOST <bits>TriState [ON | OFF]Slave [ON | OFF]TAPState <state>TCKLevel <level>

DEBUGPORTTYPE[JTAG | SPY-BI-WIRE]

Select JTAG or Spy-Bi-Wire (SBW) interface. Only available for devices with SBW.

state Not available yet. Contact technical support.

IRPRE Not available yet. Contact technical support.

IRPOST Not available yet. Contact technical support.

DRPRE Not available yet. Contact technical support.

DRPOST Not available yet. Contact technical support.

TriState [ON | OFF] Not available yet. Contact technical support.

Slave [ON | OFF] Not available yet. Contact technical support.

TAPState Not available yet. Contact technical support.

TCKLevel [0 | 1] Not available yet. Contact technical support.


SYStem.CPU Select the used CPU

Select the processor type. See Available Tools for supported processors. (Go to figure.)

SYStem.CpuAccess Run-time CPU access (intrusive)

The run-time memory access has to be activated for each window by using the memory class E: or by using the format option %E .

Format: SYStem.CPU <cpu>

<cpu>: MSP430xxx | CC430xxx

Format: SYStem.CpuAccess <mode>

<mode>: Enable | Denied | Nonstop

Enable In order to perform a memory read or write while the CPU is executing the program the debugger stops the program execution shortly.Each short stop takes 1 … 100 ms depending on the speed of the CPU and debug interface and on the size of the read/write accesses required.

Denied No intrusive memory access is possible while the CPU executes the program.

Nonstop Nonstop ensures that the program execution can not be stopped and that the debugger does not affect the real-time behavior of the CPU.The debugger inhibits the following:• to stop the program execution• all features of the debugger that are intrusive (e.g. spot break-

points, performance analysis via Stop-and-go, conditional break-points etc.)

NOTE: Non-intrusive memory access during runtime is not possible for the MSP430. Use the Enable option to declare if an intrusive memory access can take place while the CPU is executing code.


Example:

Please refer to Memory classes for additional information. (Go to figure.)

SYStem.JtagClock Set jtag clock frequency

Selects the JTAG port frequency (TCK) used by the debugger to communicate with the processor. The frequency affects e.g. the download speed. It could be useful to reduce the JTAG frequency if there are buffers, additional loads or high capacities on the JTAG lines or if VTREF is very low. A very high frequency will not work on all systems and will result in an erroneous data transfer.

The debugger cannot select all frequencies accurately. It chooses the next possible frequency and displays the real value in the SYStem.state window.

A decimal number like “100000.” also short forms like “100kHz” or “15MHz” can be used for <frequency>. The short forms imply a decimal value, although no “.” is used.

SYStem.LOCK Lock and tristate the debug port

Default: OFF.

If the system is locked, no access to the debug port will be performed by the debugger. While locked, the debug connector of the debugger is tristated. The main intention of the lock command is to give debug access to another tool. The command has no effect for the simulator.

Data.dump E:0x200 ; Intrusive Data.dump at specific location

Data.List E: ; Intrusive Data.List at current program counter

Data.List E:0x3100 ; Intrusive Data.List at specific location

Var.View %E first ; Intrusive display of variable first

Format: SYStem.JtagClock <frequency>

Format: SYStem.LOCK [ON | OFF]


SYStem.MemAccess Run-time memory access

Default: Denied. (Go to figure.)

If SYStem.MemAccess is not Denied, it is possible to read from memory, to write to memory and to set software breakpoints while the CPU is executing the program. This is only possible for the instruction set simulator.

If a specific window that displays memory or variables should be updated while the program is running select the memory class E: or the format option %E.

Please refer to Memory classes for additional information.

Format: SYStem.MemAccess <mode>SYStem.ACCESS (deprecated)

<mode>: CPUDenied

CPU A run-time memory access is made without CPU intervention while the program is running (Only Simulator).

Denied No memory access is possible while the CPU is executing the program.

Data.dump E:0x200 ; Non-Intrusive Data.dump at specific location

Data.List E: ; Non-Intrusive Data.List at program counter

Data.List E:0x3100 ; Non-Intrusive Data.List at specific location

Var.View %E first ; Non-Intrusive display of variable first


SYStem.Mode Establish the communication with the target

Select target reset mode. (Go to figure.)

Format: SYStem.Mode <mode>

<mode>: Down | NoDebug | Go | Attach | Up

Down Disables the debugger (default).The state of the CPU remains unchanged. The JTAG/SBW port is tristated.

NoDebug Disables the debugger.The state of the CPU remains unchanged. The JTAG/SBW port is tristated.

Go Resets the target and enables the debugger and start the program execution.Program execution can be stopped by the break command or external trigger.

Up Resets the target and sets the CPU to debug mode.After execution of this command the CPU is stopped and prepared for debugging. All registers are set to the default level.

Attach User program remains running and the debug mode is activated.After this command the user program can be stopped with the break command or if any break condition occurs.

StandBy Not available for MSP430.


SYStem.Option Configure debugger behavior

System options allow to influence the behavior of the debugger.

SYStem.Option IMASKASM Disable interrupts for assembler single steps

Default: OFF

Disable interrupts while single stepping in assembler mode.

SYStem.Option IMASKHLL Disable interrupts for HLL single steps

Default: OFF

Disables interrupts while single stepping in HLL mode. An HLL step might execute several lines of code. Thus a target application might re-enable interrupts again during the step.

SYStem.Option LPMX5 Enable LPMx5 support

Default: OFF

Per default the support of the LPM5 mode is disabled. If enabled, the debugger will check the LPMx.5 state of a device. This takes additional time and will decrease the debug performance.

Format: SYStem.Option IMASKASM <option>

<option>: ON | OFF

Format: SYStem.Option IMASKHLL <option>

<option>: ON | OFF

Format: SYStem.Option LPMX5 <option>

<option>: ON | OFF


Only available for MSP430F5xxx, MSP430F6xxx, MSP30FR5xxx, CC4305xxx, CC430F5xxx devices that support the LPMx.5 mode.

SYStem.Option TURBO Speed up memory access

Default: OFF

If activated, additional error checks are avoided. This increases the read and write access to memory. Write or read errors might not be detected.

Only available for MSP430F5xxx, MSP430F6xxx, MSP30FR5xxx, CC4305xxx, CC430F5xxx devices.

SYStem.Option TCKTOTEST Configure clock output pins

Select output pin for debug clock. This option applies only for a Spy-Bi-Wire connection. It makes no sense to use this with 4-wire JTAG.

Format: SYStem.Option TURBO <option>

<option>: ON | OFF

Format: SYStem.Option TCKTOTEST <option>

<option>: NORMAL | BOTHTCK | BOTHTEST | SWAP

NORMAL Clock is only output on TCK pin

BOTHTCK Clock is output on TCK and TEST pin

BOTHTEST Test is output on TCK and TEST pin

SWAP Clock is only output on TEST pin


MSP430 Specific TrOnchip Commands

The TrOnchip command provides low-level access to the on-chip debug register.

TrOnchip.CONVert Extend the breakpoint range

Default: ON.

The debug unit of some devices does not provide the resources to set an on-chip breakpoint to an address range. Instead only bit masks can be used to mark a memory range with a breakpoint. A mask has a reduced flexibility and cannot handle all ranges. It is therefore required to adapt the address range the user has entered so that it fits to the debug unit capabilities.

If TrOnchip.Convert is set to ON (default) and a breakpoint is set to a range, this range is extended to the next possible bit mask. The result is that in most cases a bigger address range is marked by the specified breakpoint. This can be easily controlled by the Data.View command.

If TrOnchip.Convert is set to OFF, the debugger will only accept breakpoints which exactly fit to the on-chip breakpoint hardware.

This setting affects all on-chip breakpoints.

TrOnchip.RESet Set on-chip trigger to default state

Sets the TrOnchip settings and trigger module to the default settings.

TrOnchip.state Display on-chip trigger window

Opens the TrOnchip.state window.

Format: TrOnchip.CONVert [ON | OFF]

Format: TrOnchip.RESet

Format: TrOnchip.state


Low Power Mode debugging

MSP430 devices offer different low power modes. Low Power modes are designed to save energy. This is done by disabling certain clocks, the CPU itself and the JTAG connection. Which parts are deactivated depends on the Low Power Mode and the device. Details can be found in the device specific data sheet.

Avoid loss of device

Devices that implement the LPMx.5 mode (i.e. LPM3.5 and/or LPM4.5) may disable JTAG in LPMx.5 mode. In this case the debugger has no access to the device until the next wake-up which cannot be done by the debugger. If the JTAG is kept alive during LPMx.5 the debugger may snoop the LPMx.5 state of the device and wake the device into debug mode. Hence the debugger might not be able to recover a device that goes to LPMx.5 shortly after the device went out from reset. This happens when JTAG is powered down to fast. Development recommendation:

• Add a wait time of 5 to 10 seconds in the LPMx.5 application before entering LPMx.5. The debugger has then a chance to bring the device to debug mode before LPMx.5 is entered.

• Check then if device can be recovered from LPMx.5. Remove wait time once the development of the LPMx.5 application has finished or if the device can be recovered by the debugger.

Supported Low Power Modes

The current low power mode of the device is indicated on the at the right bottom of TRACE32:

LPM0 - LPM4 All MSP430 derivatives

LPMx.5 MSP430F5xxx, MSP430FR5xxx, MSP430F6xxx, CC430F5xxx, CC430F6xx. Some of these devices may not support LPMx.5. Refer to device data sheet.


The following state information can be displayed

Please refer to your device specific data sheet for detailed information on supported low power modes.

running Core is active an running. Core power is up. All clocks are active.

running (lpm0)

Core is in lpm0. Core power is up. CPU and some clocks are disabled.

running (lpm1)


running (lpm2)


running (lpm3)


running (lpm4)

Core is in lpm4. Core power is up. CPU and all clocks are disabled.

running (lpmx.5)

Core is in lpm3.5 or lpm4.5. Core power is down, JTAG is not accessible.

running (lpm3.5)

Core is in lpm3.5. Core power is down and JTAG is accessible

running (lpm4.5)

Core is in lpm4.5. Core power is down and JTAG is accessible


Debug Connection

Pinout of the 14-pin Debug Cable:

For details on logical functionality, physical connector, alternative connectors, electrical characteristics, timing behavior and printing circuit design hints, refer to the application note JTAG Interface Specification.

In case of problems contact support at [email protected].

Signal Pin Pin SignalTDO|SBWTDIO RST 1 2 N/C

TDI TCLK 3 4 VTREFTMS 5 6 N/C

TCK|TEST SBWTCK 7 8 TESTGND 9 10 N/CRST 11 12 N/CN/C 13 14 NC


Support

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CC430F5123 YES YESCC430F5125 YES YESCC430F5133 YES YESCC430F5135 YES YESCC430F5137 YES YESCC430F5143 YES YESCC430F5145 YES YESCC430F5147 YES YESCC430F6125 YES YESCC430F6126 YES YESCC430F6127 YES YESCC430F6135 YES YESCC430F6137 YES YESCC430F6143 YES YESCC430F6145 YES YESCC430F6147 YES YESMSP430AFE221 YES YESMSP430AFE222 YES YESMSP430AFE223 YES YESMSP430AFE231 YES YESMSP430AFE232 YES YESMSP430AFE233 YES YESMSP430AFE251 YES YESMSP430AFE252 YES YESMSP430AFE253 YES YESMSP430AFE4110 YES YESMSP430BT5190 YES YESMSP430C091 YES YESMSP430C092 YES YESMSP430C1101 YES YESMSP430C1111 YES YESMSP430C1121 YES YESMSP430C1331 YES YESMSP430C1351 YES YES


MSP430C311 YES YESMSP430C312 YES YESMSP430C313 YES YESMSP430C314 YES YESMSP430C315 YES YESMSP430C323 YES YESMSP430C325 YES YESMSP430C336 YES YESMSP430C337 YES YESMSP430C412 YES YESMSP430C413 YES YESMSP430CG4616 YES YESMSP430CG4617 YES YESMSP430CG4618 YES YESMSP430CG4619 YES YESMSP430F110 YES YESMSP430F1101 YES YESMSP430F1101A YES YESMSP430F1111A YES YESMSP430F112 YES YESMSP430F1121 YES YESMSP430F1121A YES YESMSP430F1122 YES YESMSP430F1132 YES YESMSP430F122 YES YESMSP430F1222 YES YESMSP430F123 YES YESMSP430F1232 YES YESMSP430F133 YES YESMSP430F135 YES YESMSP430F147 YES YESMSP430F1471 YES YESMSP430F148 YES YESMSP430F1481 YES YESMSP430F149 YES YESMSP430F1491 YES YESMSP430F155 YES YESMSP430F156 YES YESMSP430F157 YES YESMSP430F1610 YES YESMSP430F1611 YES YES

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MSP430F1612 YES YESMSP430F167 YES YESMSP430F168 YES YESMSP430F169 YES YESMSP430F2001 YES YESMSP430F2002 YES YESMSP430F2003 YES YESMSP430F2011 YES YESMSP430F2012 YES YESMSP430F2013 YES YESMSP430F2013-EP YES YESMSP430F2101 YES YESMSP430F2111 YES YESMSP430F2112 YES YESMSP430F2121 YES YESMSP430F2122 YES YESMSP430F2131 YES YESMSP430F2132 YES YESMSP430F2232 YES YESMSP430F2234 YES YESMSP430F2252 YES YESMSP430F2254 YES YESMSP430F2272 YES YESMSP430F2274 YES YESMSP430F2274-EP YES YESMSP430F233 YES YESMSP430F2330 YES YESMSP430F235 YES YESMSP430F2350 YES YESMSP430F2370 YES YESMSP430F2410 YES YESMSP430F2416 YES YESMSP430F2417 YES YESMSP430F2418 YES YESMSP430F2419 YES YESMSP430F247 YES YESMSP430F2471 YES YESMSP430F248 YES YESMSP430F2481 YES YESMSP430F249 YES YESMSP430F249-EP YES YES

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MSP430F2491 YES YESMSP430F2616 YES YESMSP430F2617 YES YESMSP430F2618 YES YESMSP430F2618-EP YES YESMSP430F2619 YES YESMSP430F2619-SHT YES YESMSP430F412 YES YESMSP430F413 YES YESMSP430F4132 YES YESMSP430F415 YES YESMSP430F4152 YES YESMSP430F417 YES YESMSP430F423 YES YESMSP430F423A YES YESMSP430F425 YES YESMSP430F4250 YES YESMSP430F425A YES YESMSP430F4260 YES YESMSP430F427 YES YESMSP430F4270 YES YESMSP430F427A YES YESMSP430F435 YES YESMSP430F4351 YES YESMSP430F436 YES YESMSP430F4361 YES YESMSP430F437 YES YESMSP430F4371 YES YESMSP430F438 YES YESMSP430F439 YES YESMSP430F447 YES YESMSP430F448 YES YESMSP430F4481 YES YESMSP430F449 YES YESMSP430F4491 YES YESMSP430F4616 YES YESMSP430F46161 YES YESMSP430F4617 YES YESMSP430F46171 YES YESMSP430F4618 YES YESMSP430F46181 YES YES

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MSP430F4619 YES YESMSP430F46191 YES YESMSP430F47126 YES YESMSP430F47127 YES YESMSP430F47163 YES YESMSP430F47166 YES YESMSP430F47167 YES YESMSP430F47173 YES YESMSP430F47176 YES YESMSP430F47177 YES YESMSP430F47183 YES YESMSP430F47186 YES YESMSP430F47187 YES YESMSP430F47193 YES YESMSP430F47196 YES YESMSP430F47197 YES YESMSP430F477 YES YESMSP430F478 YES YESMSP430F4783 YES YESMSP430F4784 YES YESMSP430F479 YES YESMSP430F4793 YES YESMSP430F4794 YES YESMSP430F5131 YES YESMSP430F5132 YES YESMSP430F5151 YES YESMSP430F5152 YES YESMSP430F5171 YES YESMSP430F5172 YES YESMSP430F5212 YES YESMSP430F5214 YES YESMSP430F5217 YES YESMSP430F5219 YES YESMSP430F5222 YES YESMSP430F5224 YES YESMSP430F5227 YES YESMSP430F5229 YES YESMSP430F5232 YES YESMSP430F5234 YES YESMSP430F5237 YES YESMSP430F5239 YES YES

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MSP430F5242 YES YESMSP430F5244 YES YESMSP430F5247 YES YESMSP430F5249 YES YESMSP430F5252 YES YESMSP430F5253 YES YESMSP430F5254 YES YESMSP430F5255 YES YESMSP430F5256 YES YESMSP430F5257 YES YESMSP430F5258 YES YESMSP430F5259 YES YESMSP430F5304 YES YESMSP430F5308 YES YESMSP430F5309 YES YESMSP430F5310 YES YESMSP430F5324 YES YESMSP430F5325 YES YESMSP430F5326 YES YESMSP430F5327 YES YESMSP430F5328 YES YESMSP430F5329 YES YESMSP430F5333 YES YESMSP430F5335 YES YESMSP430F5336 YES YESMSP430F5338 YES YESMSP430F5340 YES YESMSP430F5341 YES YESMSP430F5342 YES YESMSP430F5358 YES YESMSP430F5359 YES YESMSP430F5418 YES YESMSP430F5418A YES YESMSP430F5419 YES YESMSP430F5419A YES YESMSP430F5435 YES YESMSP430F5435A YES YESMSP430F5436 YES YESMSP430F5436A YES YESMSP430F5437 YES YESMSP430F5437A YES YES

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MSP430F5438 YES YESMSP430F5438A YES YESMSP430F5500 YES YESMSP430F5501 YES YESMSP430F5502 YES YESMSP430F5503 YES YESMSP430F5504 YES YESMSP430F5505 YES YESMSP430F5506 YES YESMSP430F5507 YES YESMSP430F5508 YES YESMSP430F5509 YES YESMSP430F5510 YES YESMSP430F5513 YES YESMSP430F5514 YES YESMSP430F5515 YES YESMSP430F5517 YES YESMSP430F5519 YES YESMSP430F5521 YES YESMSP430F5522 YES YESMSP430F5524 YES YESMSP430F5525 YES YESMSP430F5526 YES YESMSP430F5527 YES YESMSP430F5528 YES YESMSP430F5529 YES YESMSP430F5630 YES YESMSP430F5631 YES YESMSP430F5632 YES YESMSP430F5633 YES YESMSP430F5634 YES YESMSP430F5635 YES YESMSP430F5636 YES YESMSP430F5637 YES YESMSP430F5638 YES YESMSP430F5658 YES YESMSP430F5659 YES YESMSP430F6433 YES YESMSP430F6434 YES YESMSP430F6435 YES YESMSP430F6436 YES YES

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MSP430F6438 YES YESMSP430F6458 YES YESMSP430F6459 YES YESMSP430F6630 YES YESMSP430F6631 YES YESMSP430F6632 YES YESMSP430F6633 YES YESMSP430F6634 YES YESMSP430F6635 YES YESMSP430F6636 YES YESMSP430F6637 YES YESMSP430F6638 YES YESMSP430F6658 YES YESMSP430F6659 YES YESMSP430F6720 YES YESMSP430F6721 YES YESMSP430F6723 YES YESMSP430F6724 YES YESMSP430F6725 YES YESMSP430F6726 YES YESMSP430F6730 YES YESMSP430F6731 YES YESMSP430F6733 YES YESMSP430F6734 YES YESMSP430F6735 YES YESMSP430F6736 YES YESMSP430F6745 YES YESMSP430F67451 YES YESMSP430F6746 YES YESMSP430F67461 YES YESMSP430F6747 YES YESMSP430F67471 YES YESMSP430F6748 YES YESMSP430F67481 YES YESMSP430F6749 YES YESMSP430F67491 YES YESMSP430F6765 YES YESMSP430F67651 YES YESMSP430F6766 YES YESMSP430F67661 YES YESMSP430F6767 YES YES

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MSP430F67671 YES YESMSP430F6768 YES YESMSP430F67681 YES YESMSP430F6769 YES YESMSP430F67691 YES YESMSP430F6775 YES YESMSP430F67751 YES YESMSP430F6776 YES YESMSP430F67761 YES YESMSP430F6777 YES YESMSP430F67771 YES YESMSP430F6778 YES YESMSP430F67781 YES YESMSP430F6779 YES YESMSP430F67791 YES YESMSP430FE423 YES YESMSP430FE4232 YES YESMSP430FE423A YES YESMSP430FE4242 YES YESMSP430FE425 YES YESMSP430FE4252 YES YESMSP430FE425A YES YESMSP430FE427 YES YESMSP430FE4272 YES YESMSP430FE427A YES YESMSP430FG4250 YES YESMSP430FG4260 YES YESMSP430FG4270 YES YESMSP430FG437 YES YESMSP430FG438 YES YESMSP430FG439 YES YESMSP430FG4616 YES YESMSP430FG4617 YES YESMSP430FG4618 YES YESMSP430FG4619 YES YESMSP430FG477 YES YESMSP430FG478 YES YESMSP430FG479 YES YESMSP430FR5720 YES YESMSP430FR5721 YES YESMSP430FR5722 YES YES

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MSP430FR5723 YES YESMSP430FR5724 YES YESMSP430FR5725 YES YESMSP430FR5726 YES YESMSP430FR5727 YES YESMSP430FR5728 YES YESMSP430FR5729 YES YESMSP430FR5730 YES YESMSP430FR5731 YES YESMSP430FR5732 YES YESMSP430FR5733 YES YESMSP430FR5734 YES YESMSP430FR5735 YES YESMSP430FR5736 YES YESMSP430FR5737 YES YESMSP430FR5738 YES YESMSP430FR5739 YES YESMSP430FR5969 YES YESMSP430FW423 YES YESMSP430FW425 YES YESMSP430FW427 YES YESMSP430FW428 YES YESMSP430FW429 YES YESMSP430G2001 YES YESMSP430G2101 YES YESMSP430G2102 YES YESMSP430G2111 YES YESMSP430G2112 YES YESMSP430G2121 YES YESMSP430G2131 YES YESMSP430G2132 YES YESMSP430G2152 YES YESMSP430G2153 YES YESMSP430G2201 YES YESMSP430G2202 YES YESMSP430G2203 YES YESMSP430G2210 YES YESMSP430G2211 YES YESMSP430G2212 YES YESMSP430G2213 YES YESMSP430G2221 YES YES

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MSP430G2230 YES YESMSP430G2230-EP YES YESMSP430G2231 YES YESMSP430G2231-EP YES YESMSP430G2232 YES YESMSP430G2233 YES YESMSP430G2252 YES YESMSP430G2253 YES YESMSP430G2302 YES YESMSP430G2302-EP YES YESMSP430G2303 YES YESMSP430G2312 YES YESMSP430G2313 YES YESMSP430G2332 YES YESMSP430G2332-EP YES YESMSP430G2333 YES YESMSP430G2352 YES YESMSP430G2353 YES YESMSP430G2402 YES YESMSP430G2403 YES YESMSP430G2412 YES YESMSP430G2413 YES YESMSP430G2432 YES YESMSP430G2433 YES YESMSP430G2444 YES YESMSP430G2452 YES YESMSP430G2453 YES YESMSP430G2513 YES YESMSP430G2533 YES YESMSP430G2544 YES YESMSP430G2553 YES YESMSP430G2744 YES YESMSP430G2755 YES YESMSP430G2855 YES YESMSP430G2955 YES YESMSP430L092 YES YES

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Compilers

Target Operating Systems

Language Compiler Company Option Comment

C MSPGCC GNU Compiler Collection

ELF Gnu Compiler for MSP430

C CCS Texas Instruments COFFC/C++ ICC430 IAR Systems AB D43/uBROF


3rd-Party Tool Integrations

CPU Tool Company Host

WINDOWS CE PLATF. BUILDER

- Windows

CODE::BLOCKS - -C++TEST - WindowsADENEO -X-TOOLS / X32 blue river software GmbH WindowsCODEWRIGHT Borland Software

CorporationWindows

CODE CONFIDENCE TOOLS

Code Confidence Ltd Windows

CODE CONFIDENCE TOOLS

Code Confidence Ltd Linux

EASYCODE EASYCODE GmbH WindowsECLIPSE Eclipse Foundation, Inc WindowsCHRONVIEW Inchron GmbH WindowsLDRA TOOL SUITE LDRA Technology, Inc. WindowsUML DEBUGGER LieberLieber Software

GmbHWindows

SIMULINK The MathWorks Inc. WindowsATTOL TOOLS MicroMax Inc. WindowsVISUAL BASIC INTERFACE

Microsoft Corporation Windows

LABVIEW NATIONAL INSTRUMENTS Corporation

Windows

RAPITIME Rapita Systems Ltd. WindowsRHAPSODY IN MICROC IBM Corp. WindowsRHAPSODY IN C++ IBM Corp. WindowsDA-C RistanCASE WindowsTRACEANALYZER Symtavision GmbH WindowsECU-TEST TraceTronic GmbH WindowsUNDODB Undo Software LinuxTA INSPECTOR Vector WindowsVECTORCAST UNIT TESTING

Vector Software Windows

VECTORCAST CODE COVERAGE

Vector Software Windows


Products

Product Information

OrderNo Code Text

LA-3713 JTAG-MSP430

JTAG Debugger for MSP430 (ICD)supports MSP430 via JTAG or Spy-Bi-Wireincludes software for Windows, Linux and MacOSXrequires Power Debug Moduledebug cable with 14 pin connector


Order Information

Order No. Code Text

LA-3713 JTAG-MSP430 JTAG Debugger for MSP430 (ICD)
