MSC8144EC Reference Manual Addendumapplication-notes.digchip.com/314/314-68068.pdf · TDM7_TERR TDM7_RERR TDM6_TERR TDM6_RERR TDM5_TERR TDM5_RERR TDM4_TERR TDM4_RERR Type R/W Reset

Freescale SemiconductorAddendum

MSC8144ECRMADRev. 16, 3/2008

CONTENTS1 About This Book.................................................22 Overview.............................................................23 SC3400 Core Overview......................................34 External Signals ..................................................35 Chip-Level Arbitration and Switching System

(CLASS) .............................................................46 Reset....................................................................57 General Configuration Registers ........................68 Memory Map ....................................................129 MSC8144 SC3400 DSP Subsystem .................1210 Internal Memory Subsystem.............................1311 Interrupt Handling.............................................1412 Serial RapidIO® Controller..............................2213 RapidIO Interface Dedicated DMA Controller 2414 Ethernet Controller ...........................................2415 Debugging, Profiling, and Performance

Monitoring ........................................................27

MSC8144ECReference Manual Addendum

This document provides updates to revision 1 of the MSC8144EC Reference Manual (MSC8144ECRM). The changes are organized by the chapters that are affected.

© Freescale Semiconductor, Inc. 2007, 2008. All rights reserved.

About This Book

1 About This Book

� On page li under “Four DSP Core Subsystems,” change OCE30 to OCE.

� On page lv, for the bullet for Chapter 10, change the last word from (OCE30) to (OCE).

� On page lvi, on the last line of the last bulleted paragraph, change OCE30 to OCE.

� On page vili, in the next to last line of the last bulleted paragraph, change OCE30 to OCE.

2 Overview

� In Table 1-1 on page 1-2, in the StarCore DSP row in the seventh bulleted paragraph for Debug and Profiling Support in the first line of the first sub-bullet, change (OCE30) to (OCE).

� In Figure 1-3 on page 1-10, change OCE30 to OCE.

� In Section 1.4.5 on page 1-15, change all instances of OCE30 to OCE.

MSC8144EC Reference Manual Addendum, Rev. 16

2 Freescale Semiconductor

SC3400 Core Overview

3 SC3400 Core Overview

� Replace Figure 2-1 on page 2-2 with the following:

� In Section 2.1.5 on page 2-7, change all instances of OCE30 to OCE.

4 External Signals

� In Table 3-1 on page 3-1 in the last row, change OCE30 to OCE.


� In Section 3.16 on page 3-58, change all instances of OCE30 to OCE.

Figure 2-1. Block Diagram of the SC3400 Core in the MSC8144ECX

a_D

ATA

Xa_

AD

DR

Instruction Bus

XP

_AD

DR

ProgramSequencer

XP

_DA

TA

Xa_

AD

DR

Xb_

DA

TA

2 AAUs 4 ALUs

Data ALURegister File

6464323232128

128

BMU

Data and Program Memory

Address GeneratorRegister File

OCEModule

SC3400 Core

DALUAGU

TAPController

JTAG Port

PSEQ 2

2

Resource Stall Unit (RSU)

4 42

4Inte

rnal

Bus

BTB


Freescale Semiconductor 3

Chip-Level Arbitration and Switching System (CLASS)

5 Chip-Level Arbitration and Switching System (CLASS)

� Replace Table 4-2 on page 4-10 with the following table:

Table 4-2. CnPGCRx Events Selection

Measurement Mode

Configuration Settings for Each Mode Events Measured

CnWPCR [CE]

CnTPCR [TT]

CnTPCR [PMM]

CnIPCRx [PMM]

CnPGCR0 CnPGCR1 CnPGCR2 CnPGCR3

None selected 0 — 00 00000 — — — —Initiator Priority and Auto-Upgrade

0 — 00 00001 Number of Initiator

requests with

Priority 1

Number of Initiator

requests with

Priority 2

Number of Initiator

requests with

Priority 3

Initiator Auto-

Upgrade

Initiator Access Type

0 — 00 00010 Initiator Pending Request

Number of Initiator Read

Requests

Number of Initiator Write

Requests

Initiator Fast Write

Initiator Stall 0 — 00 00011 Initiator Write After

Read

Initiator Write After Read Stall

Initiator Target Switch

Initiator Target Switch Stall

Initiator Priority Upgrade

0 — 00 00100 Initiator Sample 0 Upgrade

Initiator Sample 1 Upgrade

Initiator Any

Sample Upgrade

—

Initiator Priority Non-Upgrade

0 — 00 00101 Initiator Sample 0

No Upgrade

Initiator Sample 1

No Upgrade

Initiator Any

Sample No

Upgrade

—

Initiator Supervisor

0 — 00 00110 Initiator Pending Request

Initiator Supervisor

Initiator Non-

Supervisor

—

Initiator Bandwidth

0 — 00 00111 Initiator Read Data

Ack.

Initiator Write Data

Ack

— —

Initiator-target Bandwidth

0 — 00 10000 + T Initiator Target T

Read Data Ack

Initiator Target T

Write Data Ack

— —

Arbitration Winner Priority

0 0 01 00000 Target T Win

Priority 0

Target T Win

Priority 1

Target T Win

Priority 2

Target T Win

Priority 3

Target Access Splitting

0 1 01 00000 Target T Initiator Access

Target T Target Access

— —



Reset

� In Section 4.7.20 on page 4-39, replace the next to last sentence in the paragraph before Table 4-23 with the following:

This register is only reset by a hardware reset or by setting the appropriate CnCPCR[PE] bit.

� In Section 4.7.21 on page 4-40, replace the next to last sentence in the paragraph before Table 4-24 with the following:

This register is only reset by a hardware reset or by setting the appropriate CnCPCR[PE] bit.

� In Section 4.7.22 and Section 4.7.23 on page 4-41, change PE to CnCPCR[PE].

6 Reset

� In Section 5.3.3 on page 5-20, replace the register layout with the following:

Arbitration Collision

0 0 10 00000 Number of cycles with more than

one request toward

Target T (Pending Request)

— — —

Target Bandwidth

0 1 10 00000 Target T Read Data

Ack

Target T Write Data

Ack

— —

Target Stall 0 — 11 00000 Target T Write After

Read

Target T Write After Read Stall

— —

Watch Point 1 — 00 00000 Watch Point Event

— — —

RSR Reset Status Register Offset 0x10

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSTSRC — RIO SW1 SW2 SW3 — BSFType R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

— SWSR SWHR — JS — SW4 SW0 SRS HRSType R/WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-2. CnPGCRx Events Selection (Continued)

Measurement Mode

Configuration Settings for Each Mode Events Measured

CnWPCR [CE]

CnTPCR [TT]

CnTPCR [PMM]

CnIPCRx [PMM]

CnPGCR0 CnPGCR1 CnPGCR2 CnPGCR3



General Configuration Registers

� Replace the rows for bits 3 and 2 in Table 5-11 on page 5-21 with the following:

7 General Configuration Registers

� Replace Section 8.2.12 through Section 8.2.15 on page 8-14 through 8-21 with the following

8.2.12 :General Interrupt Register 1 (GIR1)

GIR1 includes the interrupt status of ECC events of M2 and the virtual NMIs. Those bits are sticky and cleared by writing 1. The GIR1 is reset by a hard reset event. All bits are cleared on reset. Write accesses to this register can be performed only in supervisor mode.

SW43

0 Software Watchdog Timer 4Indicates whether software watchdog timer 4 has expired.

0 Software watchdog timer 4 not expired.

1 Software watchdog timer 4 expired.

SW02

0 Software Watchdog Timer 0Indicates whether software watchdog timer 0 has expired.

0 Software watchdog timer 0 not expired.

1 Software watchdog timer 0 expired.

GIR1 General Interrupt Register 1 Offset 0x40

Bit 31 30 29 28 27 26 25 24

—Type R/WReset 0 0 0 0 0 0 0 0

Bit 23 22 21 20 19 18 17 16

—

Type R/WReset 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

— VNMI_3 VNMI_2 VNMI_1 VNMI_0Type R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

— M2_3_ECC M2_2_ECC M2_1_ECC M2_0_ECCType R/WReset 0 0 0 0 0 0 0 0

Table 8-2. GIR1 Bit Descriptions

Name Description Settings

—31–12

Reserved. Write to zero for future compatibility.

VNMI_311

Virtual NMI 3

Asserted when VNMI_3 is activated

0 Interrupt not asserted

1 Interrupt assertedVNMI_2

10Virtual NMI 2



1 Interrupt asserted




8.2.13 General Interrupt Register 1 (GIER1_x)

VNMI_19

Virtual NMI 1




8Virtual NMI 0



1 Interrupt asserted—

7–4Reserved. Write to zero for future compatibility.

M2_3_ECC3

M2 Block 3 ECC Error Interrupt

Asserted when ECC error is reported by M2_3


1 Interrupt assertedM2_2_ECC

2M2 Block 2 ECC Error Interrupt












GIER1_0 ‘General Interrupt Enable Register 1 for Cores 0–3 Offset 0x44 GIER1_1 Offset 0x48 GIER1_2 Offset 0x4C GIER1_3 Offset 0x50

Bit 30 30 29 28 27 26 25 24

—

Type R/WReset 0 0 0 0 0 0 0 0

Bit 23 22 21 20 19 18 17 16

—Type R/W

Reset 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

—Type R/WReset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

— M2_3_ECC_EN M2_2_ECC_EN M2_1_ECC_EN M2_0_ECC_EN

Type R/WReset 0 0 0 0 0 0 0 0

Table 8-2. GIR1 Bit Descriptions (Continued)





GIER1_[0–3] includes interrupt enable bits of ECC events of M2 for cores 0–3. The register is reset by a hard reset event. All bits are cleared by reset. Write accesses to this register can only be performed in supervisor mode.

8.2.14 General Interrupt Register 2 (GIR2)

GIR2 includes interrupt status of some events within MSC8144EC that are rare. Those bits are not sticky but only sample the events. The GIR2 register is reset on a hard reset event. All bits will be deasserted on reset.

Table 8-3. GIER1_n Bit Descriptions


—31–4


M2_3_ECC_EN3

M2 Block 3 ECC Error Enable 0 Interrupt disabled

1 Interrupt enabled

M2_2_ECC_EN2


1 Interrupt enabled

M2_1_ECC_EN1


1 Interrupt enabled

M2_0_ECC_EN0


1 Interrupt enabled


Bit 31 30 29 28 27 26 25 24

— — SWT4 SWT3 SWT2 SWT1 SWT0 OCN_ERRType R/W

Reset 0 0 0 0 0 0 0 0

Bit 23 22 21 20 19 18 17 16

PCI_ERR DDR_ERR DMA_ERR — CE_IECC CE_DECC TDM_P1ECC TDM_P0ECCType R/WReset 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

TDM7_TERR TDM7_RERR TDM6_TERR TDM6_RERR TDM5_TERR TDM5_RERR TDM4_TERR TDM4_RERR

Type R/WReset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

TDM3_TERR TDM3_RERR TDM2_TERR TDM2_RERR TDM1_TERR TDM1_RERR TDM0_TERR TDM0_RERRType R/W

Reset 0 0 0 0 0 0 0 0



—31–30





SWT429

Software Watchdog Timer 4 Interrupt

Reflects SWT 4 interrupt



SWT328





SWT227





SWT126





SWT025

Software Watchdog Timer 0 InterruptReflects SWT 0 interrupt



OCN_ERR24

OCeaN-to-MBus Error Interrupt

Reflects OCeaN error interrupt



PCI_ERR23

PCI Error Interrupt

Reflects PCI error interrupt



DDR_ERR22

DDR Error Interrupt

Reflects DDR error interrupt



DMA_ERR21

DMA Error Interrupt

Reflects DMA error interrupt



—20


QE_IECC19

QUICC Engine IMEM ECC Error Interrupt

Reflects ECC error interrupt of the QUICC Engine IMEM



QE_DECC18

QUICC Engine DRAM ECC Error Interrupt

Reflects ECC error interrupt of the QUICC Engine DRAM



TDM_P1ECC17

TDM[4–7] Parity Error Interrupt

Reflects parity error interrupt of TDM4, TDM5, TDM6 or TDM7



TDM_P0ECC16





TDM7_TERR15

TDM7 Transmit Error Interrupt

Reflects TDM7 Transmit error interrupt



TDM7_RERR14

TDM7 Receive Error Interrupt

Reflects TDM7 Receive error interrupt



TDM6_TERR13





TDM6_RERR12





TDM5_TERR11





TDM5_RERR10





TDM4_TERR9





TDM4_RERR8










8.2.15 General Interrupt Enable Register 2 (GIER2_x)

TDM3_TERR7





TDM3_RERR6





TDM2_TERR5





TDM2_RERR4





TDM1_TERR3





TDM1_RERR2





TDM0_TERR1





TDM0_RERR0





GIER2_0 General Interrupt Enable Register 2 for Cores 0–3 Offset 0x58 GIER2_1 Offset 0x5C GIER2_2 Offset 0x60 GIER2_3 Offset 0x64

Bit 31 30 29 28 27 26 25 24

— — SWT4_EN SWT3_EN SWT2_EN SWT1_EN SWT0_EN OCN_ERR_EN

Type R/W

Reset 0 0 0 0 0 0 0 0

Bit 23 22 21 20 19 18 17 16

PCI_ERR_EN DDR_ERR_EN DMA_ERR_EN — CE_IECC_EN CE_DECC_EN TDM_P1ECC_EN TDM_P0ECC_EN

Type R/WReset 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

TDM7_TERR_EN TDM7_RERR_EN TDM6_TERR_EN TDM6_RERR_EN TDM5_TERR_EN TDM5_RERR_EN TDM4_TERR_EN TDM4_RERR_EN

Type R/WReset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0


Type R/W

Reset 0 0 0 0 0 0 0 0






GIER2_[0–3] include interrupt enable bits for cores 0–3 for some events that rarely occur. The GIER2_[0–3] are reset by a hard reset event. All bits are cleared on reset. Write accesses to this register can only be performed in supervisor mode.

Table 8-5. GIER2_x Bit Descriptions


—31–30


SWT4_EN29

SWT 4 Interrupt Enable 0 Interrupt disabled

1 Interrupt enabled

SWT3_EN28


1 Interrupt enabled

SWT2_EN27


1 Interrupt enabled

SWT1_EN26


1 Interrupt enabled

SWT0_EN25


1 Interrupt enabled

OCN_ERR_EN24

OCeaN Error Interrupt Enable 0 Interrupt disabled

1 Interrupt enabled

PCI_ERR_EN23

PCI Error Interrupt Enable 0 Interrupt disabled

1 Interrupt enabled

DDR_ERR_EN22

DDR Error Interrupt Enable 0 Interrupt disabled

1 Interrupt enabled

DMA_ERR_EN21

DMA Error Interrupt Enable 0 Interrupt disabled

1 Interrupt enabled

—20


CE_IECC_EN19

ECC Error Interrupt of the QUICC Engine IMEM Enable 0 Interrupt disabled

1 Interrupt enabled

CE_DECC_EN18

ECC Error Interrupt of the QUICC Engine DRAM Enable 0 Interrupt disabled

1 Interrupt enabled

TDM_P1ECC_EN17

Parity Error Interrupt of TDM[4–7] Enable 0 Interrupt disabled

1 Interrupt enabled

TDM_P0ECC_EN16


1 Interrupt enabled

TDM7_TERR_EN15

TDM7 Transmit Error Interrupt Enable 0 Interrupt disabled

1 Interrupt enabled

TDM7_RERR_EN14

TDM7 Receive Error Interrupt Enable 0 Interrupt disabled

1 Interrupt enabled

TDM6_TERR_EN13


1 Interrupt enabled

TDM6_RERR_EN12


1 Interrupt enabled

TDM5_TERR_EN11


1 Interrupt enabled

TDM5_RERR_EN10


1 Interrupt enabled



Memory Map

8 Memory Map

� In the second row of Table 9-2 on page 9-2, change OCE30 to OCE.

� In Table 9-9 on pages 9-15 through 9-17, change all instances of OCE30 to OCE.

9 MSC8144 SC3400 DSP Subsystem

� In the fourth bulleted paragraph on page 10-1, change (OCE30) to (OCE).


� In the eleventh line of the first paragraph in Section 10.2 on page 10-3, change OCE30 to OCE.

� In the second line of the first paragraph in Section 10.6 on page 10-6, change OCE30 to OCE.

� Change the last sentence in the notes in Section 10.9.6.7 on page 10-12 and Section 10.9.6.8 and Section 10.9.6.9 on page 10-13 to the following:

Please refer to the Emulation and Debug (OCE) chapter in the SC3400 DSP Core Reference Manual for OCE programming details.

TDM4_TERR_EN9


1 Interrupt enabled

TDM4_RERR_EN8


1 Interrupt enabled

TDM3_TERR_EN7


1 Interrupt enabled

TDM3_RERR_EN6


1 Interrupt enabled

TDM2_TERR_EN5


1 Interrupt enabled

TDM2_RERR_EN4


1 Interrupt enabled

TDM1_TERR_EN3


1 Interrupt enabled

TDM1_RERR_EN2


1 Interrupt enabled

TDM0_TERR_EN1


1 Interrupt enabled

TDM0_RERR_EN0


1 Interrupt enabled





Internal Memory Subsystem

10 Internal Memory Subsystem

� In line 11 of Section 11.1 on page 11-2, change OCE30 to OCE.

� Replace the last paragraph before the note at the end of Section 11.6 on page 11-24 with the following:

The eDRAM memory can fix faulty bits by using both redundancy columns and ECC bits. There are two redundancy columns in each 4 Mb macrocell and the number of columns needing replacement is determined internally. In addition, there are 8 ECC bits per 128 bits in the whole memory. Using its ECC equation, the controller can detect and correct one error in each 128-bit group. The memory is initialized by an initialization sequence performed right after reset deassertion. The initialization sequence lasts up to 0.5 ms. During this period, the MSC8144 can issue accesses to the memory, but the controller keeps the access open and reports the bus as busy.

� Replace Section 11.8.3 on starting on page 11-28 with the following:

11.8.3 L2 ICache Control Register 2 (L2IC_CR2)

Table 11-8 defines the L2IC_CR2 bit fields.

L2IC_CR2 L2 ICache Control Register 2 Offset 0x08

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

—Type R/WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

— BS LB PFS — PROF CDM CGL CE

Type R/WReset 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0

Table 11-8. L2IC_CR2 Bit Descriptions

Name Reset Description Settings

—31–14

0 Reserved. Write to zero for future compatibility.

BS13–11

100 Burst SizeDefines the burst size from L2 ICache toward the system

100 4 VBRs (default).111 1 VBR.all others reserved.

LB10–8

111 Cache Way Boundaries LockThe value of this field defines directly the lower and upper boundaries of the cache that are locked (or open),

000 reserved001 0,1010 2,3011 4,5100 6,7101 0,1,2,3110 4,5,6,7111 0,1,2,3,4,5,6,7

PFS7

1 Prefetch SelectEnables/disables the prefetch operation.

0 Prefetch disabled.

1 Prefetch selected.

—6–4




Interrupt Handling

11 Interrupt Handling

� Replace Table 13-2 on page 13-3 with the following:

PROF3

0 Profiling EnableDetermines whether to generate profiling signals.

0 No profiling signals generated.

1 Generate profiling signals.CDM

20 Cache Debug Mode

Indicates whether cache is in debug mode or not. During debug mode, update mechanisms are disabled and debug registers are accessible. Cache memory is accessible through cache debug registers. An attempt to set this bit while sweep operation is not complete is not allowed.

0 Normal cache mode.

1 Cache debug mode.

CGL1

0 Cache Global LockIndicates whether cache is in global lock mode or not. Assertion of global lock mode is ignored during a cache sweep operation.

0 Cache global lock mode not active.

1 Cache global lock mode active.

CE0

0 Cache Memory EnabledIndicates whether the two L2 cache memory modules are enabled or disabled. At reset deassertion, the two modules are disabled. Once the cache memory is enabled. it may be disabled only by reset. In disable mode the clock inside each memory module is disabled and power is saved.Note: This is a sticky bit.

0 Cache memory disabled.

1 Cache memory enabled.

Table 13-2. General Configuration Block Interrupt SourcesTDM Debug General Watch Dog Timer

TDM 0 Rx error CLASS 0 overrun M2_0 ECC error Watch Dog Timer 0TDM 0 Tx error CLASS 0 watchpoint M2_1 ECC error Watch Dog Timer 1TDM 1 Rx error CLASS 1 overrun M2_2 ECC error Watch Dog Timer 2TDM 1 Tx error CLASS 1 watchpoint M2_3 ECC error Watch Dog Timer 3TDM 2 Rx error CLASS 1 error Watch Dog Timer 4TDM 2 Tx error CLASS 2 overrunTDM 3 Rx error CLASS 2 watchpoint Parity error from TDM[0–3]

TDM 3 Tx errorL2 ICache initiator CLASS overrun

Parity error from TDM[4–7]

TDM 4 Rx errorL2 ICache initiator CLASS watchpoint

QUICC Engine module DRAM ECC error

TDM 4 Tx error L2 ICache target CLASS overrunQUICC Engine module IMEM ECC error

TDM 5 Rx errorL2 ICache target CLASS watchpoint

TDM 5 Tx error Performance Monitor all DMA errorTDM 6 Rx error DDR interruptTDM 6 Tx error PCI allTDM 7 Rx error OCeaN to MBusTDM 7 Tx error

Table 11-8. L2IC_CR2 Bit Descriptions (Continued)

Name Reset Description Settings



Interrupt Handling

� In Table 13-5 on page 13-12, replace the EPIC index 245 row with the following:

� Replace Section 13.5.2.1 through Section 13.5.2.4 on pages 13-15 through 13-22 with the following:

245 Parity error from TDM[0-7] DSP core is reading an address in TDM PRAM with soft error.

Read the failing address and correct the soft error.

QUICC Engine DRAM/IMEM ECC error

DSP core is reading an address in the QUICC Engine subsystem DRAM/IMEM with soft error.

ISR must reset the device.

L2-ICache ECC error DSP core is reading an address in L2 ICache with soft error.

ISR must invalidate the L2 ICache.

DMA error DSP core is reading an address in DMA PRAM (during debug mode) with soft error.

Read the failing address (channel number) and correct the soft error.

DDR single / double ECC error DSP core is reading an address in DDR with soft error

Read the address from the DDR controller and correct the soft error. For single ECC errors, the threshold can be set to more than one error.

DDR access to an address that does not hit any DDR configuration space.

DSP core is reading an address in DDR that does not hit any DDR configuration space (during debug phase).

Read the problematic address from the DDR controller. Use a debug instruction at the end of the ISR.

PCI error DSP core is reading an address in PCI with no response or with parity error.

Use a debug instruction at the end of the ISR.

Performance monitor DSP core is reading an address in L2 ICache and it is a hit, PM counter is set to report a single L2 ICache hit access.

Set the threshold of the counter of the PM that counts hit events in the L2 ICache to 2 or more.



Interrupt Handling

13.5.2.1 :General Interrupt Register 1 (GIR1)

GIR1 includes the interrupt status of ECC events of M2 and the virtual NMIs. Those bits are sticky and cleared by writing 1. The GIR1 is reset by a hard reset event. All bits are cleared on reset. Write accesses to this register can be performed only in supervisor mode.


Bit 31 30 29 28 27 26 25 24

—

Type R/WReset 0 0 0 0 0 0 0 0

Bit 23 22 21 20 19 18 17 16

—Type R/W

Reset 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

— VNMI_3 VNMI_2 VNMI_1 VNMI_0Type R/WReset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

— M2_3_ECC M2_2_ECC M2_1_ECC M2_0_ECC

Type R/WReset 0 0 0 0 0 0 0 0



—31–12


VNMI_311

Virtual NMI 3




10Virtual NMI 2




9Virtual NMI 1




8Virtual NMI 0



1 Interrupt asserted—

7–4Reserved. Write to zero for future compatibility.

M2_3_ECC3

M2 Block 3 ECC Error Interrupt


















Interrupt Handling

13.5.2.2 General Interrupt Register 1 (GIER1_x)

GIER1_[0–3] includes interrupt enable bits of ECC events of M2 for cores 0–3. The register is reset by a hard reset event. All bits are cleared by reset. Write accesses to this register can only be performed in supervisor mode.

GIER1_0 ‘General Interrupt Enable Register 1 for Cores 0–3 Offset 0x44 GIER1_1 Offset 0x48 GIER1_2 Offset 0x4C GIER1_3 Offset 0x50

Bit 30 30 29 28 27 26 25 24

—Type R/WReset 0 0 0 0 0 0 0 0

Bit 23 22 21 20 19 18 17 16

—

Type R/WReset 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

—Type R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

— M2_3_ECC_EN M2_2_ECC_EN M2_1_ECC_EN M2_0_ECC_EN

Type R/WReset 0 0 0 0 0 0 0 0

Table 13-9. GIER1_n Bit Descriptions


—31–4


M2_3_ECC_EN3


1 Interrupt enabled

M2_2_ECC_EN2


1 Interrupt enabled

M2_1_ECC_EN1


1 Interrupt enabled

M2_0_ECC_EN0


1 Interrupt enabled



Interrupt Handling

13.5.2.3 General Interrupt Register 2 (GIR2)

GIR2 includes interrupt status of some events within MSC8144EC that are rare. Those bits are not sticky but only sample the events. The GIR2 register is reset on a hard reset event. All bits will be deasserted on reset.


Bit 31 30 29 28 27 26 25 24

— — SWT4 SWT3 SWT2 SWT1 SWT0 OCN_ERRType R/WReset 0 0 0 0 0 0 0 0

Bit 23 22 21 20 19 18 17 16

PCI_ERR DDR_ERR DMA_ERR — CE_IECC CE_DECC TDM_P1ECC TDM_P0ECC

Type R/WReset 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

TDM7_TERR TDM7_RERR TDM6_TERR TDM6_RERR TDM5_TERR TDM5_RERR TDM4_TERR TDM4_RERRType R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

TDM3_TERR TDM3_RERR TDM2_TERR TDM2_RERR TDM1_TERR TDM1_RERR TDM0_TERR TDM0_RERRType R/WReset 0 0 0 0 0 0 0 0



—31–30


SWT429





SWT328





SWT227





SWT126





SWT025

Software Watchdog Timer 0 InterruptReflects SWT 0 interrupt



OCN_ERR24

OCeaN-to-MBus Error Interrupt

Reflects OCeaN error interrupt



PCI_ERR23

PCI Error Interrupt

Reflects PCI error interrupt



DDR_ERR22

DDR Error Interrupt

Reflects DDR error interrupt



DMA_ERR21

DMA Error Interrupt

Reflects DMA error interrupt





Interrupt Handling

—20


QE_IECC19

QUICC Engine IMEM ECC Error Interrupt

Reflects ECC error interrupt of the QUICC Engine IMEM



QE_DECC18

QUICC Engine DRAM ECC Error Interrupt

Reflects ECC error interrupt of the QUICC Engine DRAM



TDM_P1ECC17





TDM_P0ECC16





TDM7_TERR15





TDM7_RERR14





TDM6_TERR13





TDM6_RERR12





TDM5_TERR11





TDM5_RERR10





TDM4_TERR9





TDM4_RERR8





TDM3_TERR7





TDM3_RERR6





TDM2_TERR5





TDM2_RERR4





TDM1_TERR3





TDM1_RERR2





TDM0_TERR1





TDM0_RERR0









Interrupt Handling

13.5.2.4 General Interrupt Enable Register 2 (GIER2_x)

GIER2_[0–3] include interrupt enable bits for cores 0–3 for some events that rarely occur. The GIER2_[0–3] are reset by a hard reset event. All bits are cleared on reset. Write accesses to this register can only be performed in supervisor mode.

GIER2_0 General Interrupt Enable Register 2 for Cores 0–3 Offset 0x58 GIER2_1 Offset 0x5C GIER2_2 Offset 0x60 GIER2_3 Offset 0x64

Bit 31 30 29 28 27 26 25 24

— — SWT4_EN SWT3_EN SWT2_EN SWT1_EN SWT0_EN OCN_ERR_EN

Type R/WReset 0 0 0 0 0 0 0 0

Bit 23 22 21 20 19 18 17 16

PCI_ERR_EN DDR_ERR_EN DMA_ERR_EN — CE_IECC_EN CE_DECC_EN TDM_P1ECC_EN TDM_P0ECC_EN

Type R/WReset 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8


Type R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0


Type R/WReset 0 0 0 0 0 0 0 0



—31–30


SWT4_EN29


1 Interrupt enabled

SWT3_EN28


1 Interrupt enabled

SWT2_EN27


1 Interrupt enabled

SWT1_EN26


1 Interrupt enabled

SWT0_EN25


1 Interrupt enabled

OCN_ERR_EN24

OCeaN Error Interrupt Enable 0 Interrupt disabled

1 Interrupt enabled

PCI_ERR_EN23

PCI Error Interrupt Enable 0 Interrupt disabled

1 Interrupt enabled



Interrupt Handling

DDR_ERR_EN22

DDR Error Interrupt Enable 0 Interrupt disabled

1 Interrupt enabled

DMA_ERR_EN21

DMA Error Interrupt Enable 0 Interrupt disabled

1 Interrupt enabled

—20


CE_IECC_EN19

ECC Error Interrupt of the QUICC Engine IMEM Enable 0 Interrupt disabled

1 Interrupt enabled

CE_DECC_EN18

ECC Error Interrupt of the QUICC Engine DRAM Enable 0 Interrupt disabled

1 Interrupt enabled

TDM_P1ECC_EN17


1 Interrupt enabled

TDM_P0ECC_EN16


1 Interrupt enabled

TDM7_TERR_EN15


1 Interrupt enabled

TDM7_RERR_EN14


1 Interrupt enabled

TDM6_TERR_EN13


1 Interrupt enabled

TDM6_RERR_EN12


1 Interrupt enabled

TDM5_TERR_EN11


1 Interrupt enabled

TDM5_RERR_EN10


1 Interrupt enabled

TDM4_TERR_EN9


1 Interrupt enabled

TDM4_RERR_EN8


1 Interrupt enabled

TDM3_TERR_EN7


1 Interrupt enabled

TDM3_RERR_EN6


1 Interrupt enabled

TDM2_TERR_EN5


1 Interrupt enabled

TDM2_RERR_EN4


1 Interrupt enabled

TDM1_TERR_EN3


1 Interrupt enabled

TDM1_RERR_EN2


1 Interrupt enabled

TDM0_TERR_EN1


1 Interrupt enabled

TDM0_RERR_EN0


1 Interrupt enabled





Serial RapidIO® Controller

12 Serial RapidIO® Controller

� Replace the register layout in the Section 16.6.5 on page 16-106 with the following:

� Replace the BR row in Table 16-47 on page 16-107 with the following:

� Replace the register layout in the Section 16.6.16 on page 16-120 with the following

� Replace the last row in Table 16-58 on page 16-120 with the following:

� In the register heading in Section 16.6.31 on page 16-137, change the offset value to 0x644.

� In the heading for Section 16.6.38 on page 16-145, change (P0ERISCR) to (P0ERTSCR).

� In the heading for Section 16.6.44 on page 16-151, change (P0AAR) to (P0AACR).

PEFCAR Processing Element Features Capability Register Offset 0x00010

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BR MEM PROC SW — MB DB —TYPE R

RESET 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

— CTLS EF EASTYPE R

RESET 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

BR31

0 BridgeSpecifies whether the MSC8144 can bridge to another interface.

PLTOCCSR Port Link Time-Out Control Command and Status Offset 0x00120 Register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TVTYPE R/W

RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TV —TYPE R/W R

RESET 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

—7–0

0x00 Reserved. Write to zero for future compatibility.



Serial RapidIO® Controller

� In Table 16-97 on page 16-161, replace the RDTYP row with the following:

� Replace Section 16.6.65 on page 16-162 with the following

16.6.65 Port 0 RapidIO Outbound Window Base Address Registers x (P0ROWBARx)

P0ROWBARx selects the base address for the windows that are translated to an alternate target address space. Addresses for outbound transactions are compared with the addresses of these windows. If such a transaction does not fall within one of these spaces, it is forwarded out of the device using the default window. For information on transactions that cross more than one window, see Section 16.2.5.4.2, Window Boundary Crossing Errors, on page 16-22.

� In the heading for Section 16.6.62 on page 16-171, change (DMxDQDPAR) to (OMxDQDPAR).

� In the heading for Section 16.6.66 on page 16-175, change (DMxDCR) to (OMxDCR).

� In the heading for Section 16.6.81 on page 16-192, change (IDxMR) to (IDMR). Change the register layout heading from IDxMR to IDMR.

RDTYP19–16

Read TypeTransaction type to run on the RapidIO interface if the access is a read.

0100 NREAD.

0111 Maintenance Read.

All other values are reserved.

P0ROWBAR[1–8] Port 0 RapidIO Outbound Offset 0x10C08 + x*0x20 Window Base Address Registers 1–8

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

— BEXAD BADDTYPE R R/W

RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BADD

TYPE R/WRESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 16-98. P0ROWBARx Field Descriptions

Bit Reset Description

—31–24


BEXAD23–20

0 Base Extended AddressBits 0–3 of the internal interconnect base address.Note: Bit 0 is the most significant bit.

BADD19–0

0 Base AddressA system address that is the starting-point for the outbound translation window. The window must be aligned on the basis of the size selected in the window size bits. This corresponds to bits 4–23 of the 36-bit internal interconnect base address.Note: Bit 0 is the most significant bit.



RapidIO Interface Dedicated DMA Controller

13 RapidIO Interface Dedicated DMA ControllerIn Table 17-5 on page 17-17, replace the second row with the following:

� In Table 17-13 on page 17-30, replace the DBPATMU row with the following:

� Add the following sentence after the first sentence of the second paragraph in Section 17.3.7 on page 17-27:

ATMU bypass is only supported in small systems (up to 256 devices).

14 Ethernet Controller

� In Section 20.2.15 on page 20-27, replace the second sentence of the second paragraph with the following:

The firmware counters are updated if UPSMR[HSE] is set by the user.

� In Section 20.10.8.2 on page 20-158, replace the first sentence with the following:

The MIB items in the multi-user RAM reside in the address space defined by the TX GLOBAL PRAM TxRMONBasePointer field and the RX GLOBAL PRAM TxRMONBasePointer field.

BA23–0

0 Base AddressHolds the 24 most significant bits of the window base address.Note: For local transactions, the most

significant 4 bits in this field must be 0s.

DBPATMU29

0 Bypass ATMU for this DMA OperationIndicates to use the ATMU outbound windows. Note: The value of this bit only applies to the external

RapidIO interface.

0 Route the transfer through the ATMU outbound windows. DATR[DWRITETTYPE] must specify a local address space transaction type.

1 Bypass ATMU. Never generate an address match. Always use the SATR values to route the transaction to the interface specified by the DTRANSMIT field.



Ethernet Controller

� Replace Table 20-112 and Table 20-113 on pages 20-158 through 20-161 with the following two tables:

Table 20-112. Tx Firmware Counters

AddressTxEtherStatsBase =

TxRMONBasePointerName

Width(Bits)

Description

TxRMONBasePointer+0 SiColTx 32 Single CollisionNumber of frames transmitted OK after a single collision event. Not relevant in Full Duplex mode.

TxRMONBasePointer+4 MulColTx 32 Multiple CollisionNumber of frames in more than one collision and then transmitted successfully.

TxRMONBasePointer+8 LateColTxFr 32 Late CollisionNumber of frames in late collision event during frame transmission (30.3.1.1.10).

TxRMONBasePointer+C FrAbortDueCol 32 Frames Aborted Due to Transmit CollisionNumber of frames aborted due either to repeated collision events or to late collision.

TxRMONBasePointer +10

FrLostInMACTxEr 32 Frames Lost Due to internal MAC Error TransmissionNot counted on any other counter. Number of frames lost due to any other reason, such as OV/UN.


CarrierSenseERTx 32 Carrier Sense Error CounterNumber of times CS was deasserted during frame transmission, including transmission while CS is deasserted.


FrTxOK 32 Number of Frames Transmitted OK

TxRMONBasePointer +1C

TxFrExcessiveDefer 32 Excessive Transmit DeferNumber of frames with deferral time greater than a specified threshold.


TxPkts256 32 Transmit Packets 256Number of packets, including bad packets, transmitted between 256 (Including FCS length==4) and 511 octets.





TxRMONBasePointer +2C

TxPktsjumbo 32 Transmit Packets JumboTotal number of packets, including bad packets, transmitted between 1024 (Including FCS length==4) and MAXLength octets, considering the programmed value MAXLength and the DXE bit defined. When DXE is set and MAXLength =1 518, all untagged packets with length 1518 are counted by the previous counter. For packets 1518 long or smaller, this counter has the lowest priority.



Ethernet Controller

Table 20-113. Rx Firmware Counters

AddressEtherStatsBase =

RxRMONBasePointer Name

Width (Bits)

Description

RxRMONBasePointer +0 FrRxFCSEr 32 Rx Frames With CRC ErrorsNumber of frames received with a CRC error, excluding frames with a too long error, too short error, or alignment error, regardless of their FCS situation.

RxRMONBasePointer +4 FrAlignEr 32 Alignment ErrorsNumber of receive frames with alignment errors.This counter does not update for frames shorter that 64 bytes.

RxRMONBasePointer +8 InRangLenRxER 32 In Range Length ErrorsNumber of receive frames with L/T field in length mode with a data field not equal to the specified length, or with a specified length less than the minimum LLC frame length, regardless of the actual length.

RxRMONBasePointer +C OutRangLenRxER 32 Out of Range Length ErrorNumber of receive frames with a length field greater than the maximum allowed for LLC frames. Frames with L/T = T are not included. The error probably reflects a don’t care value for a jumbo frame.

RxRMONBasePointer +10

FrTooLongRx 32 Receive Frame Too LongNumber of receive frames with a length greater than the programmable MaxLength parameter.


Runt 32 Receive Frame Too ShortNumber of receive frames with a length smaller than MINLength (and considering the DNE bit) that incorporates either an FCS error or an alignment error, but not including frames that are fine otherwise (except for the CRC/ALIGN error).


VeryLongEventRx 32 Very Long Rx EventNumber of receive frames with a length greater than MAXLength and with either an FCS error or an alignment error.

RxRMONBasePointer +1C

SymbolErrorRx 32 Rx Error Symbol from PHYNumber of received frames with a received error symbol reported from the PHY layer device during frame reception.

RxRMONBasePointer + 20

EtherStatsDropRxBsy

32 Rx Not ReadyNumber of events dropped due to resources of type BD not ready in the receive process. This counter is a part of the sum composing EtherStatsDropEvent. It can be extracted by summing FrLostInMACTxEr, FrLossInMACRxEr, and EtherStatsDropRxBsy together with the counters below. However, 2819 does not specify exactly which resources. (2819 p.17) The UC should count all cases of BD not ready on Rx Software should calculate the sum.


— 32 Reserved. Write to zero for future compatibility.


— 32 Reserved. Write to zero for future compatibility.

RxRMONBasePointer + 2C

MisMatchDrop 32 Address Mismatch DropNumber of frames dropped during the MAC filtering process, such as address or type mismatches, that would otherwise be good frames transferred to the upper layers



Debugging, Profiling, and Performance Monitoring

15 Debugging, Profiling, and Performance Monitoring

� Change all instances of OCE30 to OCE.


EtherStatsUnderPkts 32 Rx Frames Under 64 OctetsNumber of receive frames less than 64 octets long but good frames otherwise. That is, they are good frames except for the error of being too short.


EtherStatsPkts256 32 Rx Frames 256Number of receive frames, including bad frames, between 256 (Including FCS length==4) and 511 octets.


EtherStatsPkts512 32 Rx Frames 512Number of receive frames, including bad frames, between 512 (Including FCS length==4) and 1023 octets


EtherStatsPkts1024 32 Rx Frames 1024Number of receive frames, including bad frames, between 1024 (Including FCS length==4) and 1518 octets.


EtherStatsPktsJumbo

32 Rx Frames 1024 and MAXLengthNumber of receive frames, including bad frames, between 1024 (Including FCS length==4) and MAXLength octets, considering the programmed value MAXLength and the DXE bit. When DXE is set and MAXLength = 1518. All untagged frames 1518 long are counted by the previous counter. For frames 1518 or smaller, this counter has the lowest priority.


FrLossInMACRxEr 32 MAC Error Frames LostFrames lost due to an internal MAC error during reception and that are not counted on any other error counter. Counts all frames lost due to any error (such as OV).


PausFrRx 32 Rx Pause FramesNumber of pause frames received by this MAC.


Reserved —


RxRVLANcnt 32 Rx VLAN RemovedNumber of frames with VLAN tag removed.


RxRepVLANcnt 32 Rx VLAN ReplacedNumber of frames with VLAN tag replaced.


RxInVLANcnt 32 Rx VLAN InsertedNumber of frames with VLAN tag was inserted to their header.

Table 20-113. Rx Firmware Counters (Continued)

AddressEtherStatsBase =

RxRMONBasePointer Name

Width (Bits)

Description



MSC8144ECRMADRev. 163/2008

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MSC8144EC Reference Manual Addendum1 About This Book2 Overview3 SC3400 Core Overview4 External Signals5 Chip-Level Arbitration and Switching System (CLASS)6 Reset7 General Configuration Registers8.2.12 :General Interrupt Register 1 (GIR1)8.2.13 General Interrupt Register 1 (GIER1_x)8.2.14 General Interrupt Register 2 (GIR2)8.2.15 General Interrupt Enable Register 2 (GIER2_x)

8 Memory Map9 MSC8144 SC3400 DSP Subsystem10 Internal Memory Subsystem11.8.3 L2 ICache Control Register 2 (L2IC_CR2)

11 Interrupt Handling13.5.2.1 :General Interrupt Register 1 (GIR1)13.5.2.2 General Interrupt Register 1 (GIER1_x)13.5.2.3 General Interrupt Register 2 (GIR2)13.5.2.4 General Interrupt Enable Register 2 (GIER2_x)

12 Serial RapidIO® Controller16.6.65 Port 0 RapidIO Outbound Window Base Address Registers x (P0ROWBARx)

13 RapidIO Interface Dedicated DMA Controller14 Ethernet Controller15 Debugging, Profiling, and Performance Monitoring

Documents

MSC8144EC Reference Manual Addendumapplication-notes.digchip.com/314/314-68068.pdf · TDM7_TERR TDM7_RERR TDM6_TERR TDM6_RERR TDM5_TERR TDM5_RERR TDM4_TERR TDM4_RERR Type R/W Reset