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Data Flow Modeling
M.Mohajjel
2
Continuous AssignmentsContinuously Drive a value onto a netLeft hand side must be netRight hand side
registers nets function calls
Keyword : assing
Digital System Design
module my_and(out, in1, in2);output out;input in1,in2;
assign out = in1 & in2;
endmodule
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Continuous Assignments (cont.)Examples
assign out = i1 & i2;
assign addr[15:0] = addr1_bits[15:0] ^ addr2_bits[15:0];
assign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;
Digital System Design
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Continuous Assignments (cont.)
Implicit Continuous Assignment
wire out = in1 & in2;
//same aswire out;assign out = in1 & in2;
Implicit Net Declaration
wire i1, i2;assign out = i1 & i2;
//same aswire out;assign out = in1 & in2;
Digital System Design
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DelaysRegular Assignment Delay
Syntax : assign #10 out = in1 & in2;
Digital System Design
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Delays (cont.)Implicit Continuous Assignment Delay
wire #10 out = in1 & in2; //same as wire out;
assign #10 out = in1 & in2;
Net Declaration Delaywire # 10 out;
assign out = in1 & in2;//same aswire out;
assign #10 out = in1 & in2;
Digital System Design
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Continuous Assignments (cont.)ExpressionsOperandsOperators
Digital System Design
integer count, final_count;final_count = count + 1;
real a, b, c;c = a - b;
reg [15:0] reg1, reg2;reg [3:0] reg_out;reg_out = reg1[3:0] ^ reg2[3:0]; reg ret_value;ret_value = calculate_parity(A, B);
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Continuous Assignments (cont.)Operato
rs
Digital System Design
Operator category Operators symbol
Arithmetic * / + - % **
Logical ! && ||
Relational > < <= >=
Equality == != === !===
Bitwise ~ & | ^ ^~ ~^
Reduction & ~& | ~| ^ ~^ ^~
Shift >> << >>> <<<
Concatenation { }
Replication { { } }
Conditional ? :
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Arithmetic operatorsA = 4'b0011; B = 4'b0100; D = 6; E = 4; F=2
A * B // 4'b1100D / E // 1A + B // 4'b0111B - A // 4'b0001F = E ** F; // 16
in1 = 4'b101x;in2 = 4'b1010;sum = in1 + in2; // 4'bx
Digital System Design
13 % 3 // 116 % 4 // 0-7 % 2 // -17 % -2 // +1
-10/5 // Evaluates to -2
-'d10/5
//(2's complement of 10)/5=(232-10)/5
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Logical & Relational Operators// Logical operationsA = 3; B = 0;A && B // (logical-1 && logical-0)A || B // (logical-1 || logical-0)!A// not(logical-1)!B// not(logical-0)
A = 2'b0x; B = 2'b10;A && B // (x && logical 1)=x
(a == 2) && (b == 3)
Digital System Design
// Relational Operation
A = 4, B = 3X = 4'b1010 Y = 4'b1101 Z = 4'b1xxx
A <= B // logical 0A > B // logical 1Y >= X // logical 1Y < Z // x
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Equality Operators
// A = 4, B = 3// X = 4'b1010, Y = 4'b1101// Z = 4'b1xxz, M = 4'b1xxz, N = 4'b1xxx
A == B // Results in logical 0X != Y // Results in logical 1X == Z // Results in xZ === M // Results in logical 1 Z === N // Results in logical 0M !== N // Results in logical 1
Digital System Design
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Bitwise & Reduction Operators// X = 4'b1010, Y = 4'b1101// Z = 4'b10x1
~X // 4'b0101X & Y // 4'b1000X | Y // 4'b1111X ^ Y // 4'b0111X ^~ Y // 4'b1000X & Z // 4'b10x0
Digital System Design
// X = 4'b1010, Y = 4'b0000
X | Y // 4'b1010X || Y // 1 || 0. Result is 1.
// X = 4'b1010
&X //1 & 0 & 1 & 0. |X//1 | 0 | 1 | 0. ^X//1 ^ 0 ^ 1 ^ 0.
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Shift Operators
// X = 4'b1100
Y = X >> 1; //4'b0110. Y = X << 1; //Y is 4'b1000. Y = X << 2; //Y is 4'b0000.
integer a, b, c; //Signed data typesa = 0;b = -10; // 111...10110 binaryc = a + (b >>> 3);
Digital System Design
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Concatenation Operator// A = 1'b1, B = 2'b00, C = 2'b10, //D = 3'b110
Y = {B , C} // Result Y is 4'b0010
Y = {A , B , C , D , 3'b001} // Result Y is 11'b10010110001
Y = {A , B[0], C[1]} // Result Y is 3'b101
Digital System Design
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Replication Operatorreg A;reg [1:0] B, C;reg [2:0] D;A = 1'b1; B = 2'b00; C = 2'b10; D = 3'b110;
Y = { 4{A} } // 4'b1111Y = { 4{A} , 2{B} } // 8'b11110000Y = { 4{A} , 2{B} , C } // 8'b1111000010
Digital System Design
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Conditional Operatorcondition_expr ? true_expr : false_expr ;
//model functionality of a tristate bufferassign addr_bus = drive_enable ? addr_out : 36'bz;
//model functionality of a 2-to-1 muxassign out = control ? in1 : in0;
assign out = (A == 3) ? ( control ? x : y ): ( control ? m : n) ;
Digital System Design
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4-to-1 Multiplexermodule mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
assign out = (~s1 & ~s0 & i0)|
(~s1 & s0 & i1) |
(s1 & ~s0 & i2) |
(s1 & s0 & i3);
endmodule
Digital System Design
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4-to-1 Multiplexermodule mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;input i0, i1, i2, i3;input s1, s0;
assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0);
endmodule
Digital System Design
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4-bit Full Addermodule fulladd4(sum, c_out, a, b, c_in);
output [3:0] sum;output c_out;input[3:0] a, b;input c_in;
assign {c_out, sum} = a + b + c_in;
endmoduleDigital System Design
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T flipflopmodule T_FF(q, clk, clear);
// I/O portsoutput q;input clk, clear;
edge_dff ff1(q, ,~q, clk, clear);
endmodule
Digital System Design
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D-flipflopmodule edge_dff(q, qbar, d, clk, clear);
output q,qbar;input d, clk, clear;
wire s, sbar, r, rbar,cbar;
assign cbar = ~clear;
assign sbar = ~(rbar & s), s = ~(sbar & cbar & ~clk), r = ~(rbar & ~clk & s), rbar = ~(r & cbar & d);
assign q = ~(s & qbar), qbar = ~(q & r & cbar);
endmodule
Digital System Design
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Reading AssignmentChapter 6
Digital System Design
