M.Mohajjel. Why? TTM (Time-to-market) Prototyping Reconfigurable and Custom Computing 2Digital System Design

An Introduction to Digital System Design

Programmable Logic DevicesM.MohajjelWhy?TTM (Time-to-market)PrototypingReconfigurable and Custom Computing

2Digital System DesignReprogrammable PLDsUpdating a device or correction of errorsReuse device for a different designIdeal for course laboratories3Digital System DesignProgrammable Read-Only Memory (PROM)Single level of programmabilityFixed AND-arrayProgrammable OR-array

Digital System Design40123...28293031I0

I1

I2

I3

I4A7 A6 A5 A4 A3 A2 A1 A05-to-32decoderFull decoder for its address inputsRarely require more than a few product terms

4Programmable Read-Only Memory (PROM)ExampleDigital System Design5InputsOutputsI4I3I2I1I0A7A6A5A4A3A2A1A00000010110110000010001110100010110001010001110110010......11100000010011110111100010111100100101011111001100110123...28293031I0

I1

I2

I3

I4A7 A6 A5 A4 A3 A2 A1 A05-to-32decoderxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxPROM is well suited to those apps where every possible input combination(AND term) is needed, eg. Code converters, data storage.

Each new i/p needs no. of Memory cells to be doubledAs memory size increases, so do cost, power, delay.5Field-Programmable Logic Array (PLA) Two levels of configurable logicProgrammable AND-arrayProgrammable OR-array

Digital System Design6

Field-Programmable Logic Array (PLA) Example


DrawbacksExpensive to manufacture Poor speed-performance

7Programmable Array Logic (PAL) Single level of programmabilityProgrammable AND-arrayFixed OR-arrayDigital System Design8

flip-flops connected to the OR-gate outputs

PALs simpler to understand and use than PLAs and have performanceadvantages: a fuse array has high capacitance which causes delay.8Programmable Array Logic (PAL) ExampleDigital System Design9

W = A B C + A B C DX = ?Y = ?Z = ?flip-flops connected to the OR-gate outputs

PALs simpler to understand and use than PLAs and have performanceadvantages: a fuse array has high capacitance which causes delay.9Simple PLDs (SPLDs)Digital System Design10FixedAND array(decoder)ProgrammableOR arrayProgrammableconnectionsOutputsInputsProgrammable read-only memory (PROM)ProgrammableAND arrayFixedOR arrayProgrammableconnectionsOutputsInputsProgrammable array logic (PAL) deviceProgrammable logic array (PLA)ProgrammableAND arrayProgrammableOR arrayProgrammableconnectionsOutputsInputsProgrammableconnectionsROM vs. PLA:ROM approach advantageous when(1) design time is short (no need to minimize output functions)(2) most input combinations are needed (e.g., code converters)(3) little sharing of product terms among output functionsROM problem: size doubles for each additional input, can't use don't caresPLA approach advantangeous when(1) design tool like espresso is available(2) there are relatively few unique minterm combinations(3) many minterms are shared among the output functions10Sequential Programmable DevicesDigital System Design11

Complex PLDs (CPLDs)Two levels of programmabilityPLD like blocksGlobal interconnection matrixDigital System Design12

As technology has advanced, it has become possible to produce devices with higher capacitythan SPLDs. The difficulty with increasing capacity of a strict SPLD architecture is that the structureof the programmable logic-planes grow too quickly in size as the number of inputs isincreased. The only feasible way to provide large capacity devices based on SPLD architectures isthen to integrate multiple SPLDs onto a single chip and provide interconnect to programmableconnect the SPLD blocks together. Many commercial FPD products exist on the market todaywith this basic structure, and are collectively referred to as Complex PLDs (CPLDs).

CPLDs provide logic capacity up to the equivalent of about 50 typicalSPLD devices, but it is somewhat difficult to extend these architectures to higher densities. Tobuild FPDs with very high logic capacity, a different approach is needed.

12Field-Programmable Gate Arrays (FPGAs)An array of uncommitted circuit elements, called logic blocks, and interconnect resourcesThree elementsLogic blocksI/O blocksInterconnectionsWiresSwitches


An electronic device or embedded system is said to be field-programmable or in-place programmable if its firmware (stored in non-volatile memory, such as ROM) can be modified "in the field," without disassembling the device or returning it to its manufacturer.


FPGAs vs. CPLDsAre FPGAs and CPLDs the same thing? NoBoth are programmable digital logic chips and are made by the same companies. But they have different characteristics.FPGAs are "fine-grain" devices - that means that they contain a lot (up to 100000) of tiny blocks of logic with flip-flops. CPLDs are "coarse-grain" devices - they contain relatively few (a few 100's max) large blocks of logic with flip-flops.FPGAs are RAM based - they need to be "downloaded" (configured) at each power-up. CPLDs are EEPROM based - they are active at power-up (i.e. as long as they've been programmed at least once...).FPGAs have special routing resources to implement efficiently arithmetic functions (binary counters, adders, comparators...). CPLDs do not.In general, FPGAs can contain large digital designs, while CPLDs can contain small designs only.

13FPGA Logic BlocksLUT-Based (look-up table)Mux-Based (multiplexer)


An electronic device or embedded system is said to be field-programmable or in-place programmable if its firmware (stored in non-volatile memory, such as ROM) can be modified "in the field," without disassembling the device or returning it to its manufacturer.


FPGAs vs. CPLDsAre FPGAs and CPLDs the same thing? NoBoth are programmable digital logic chips and are made by the same companies. But they have different characteristics.FPGAs are "fine-grain" devices - that means that they contain a lot (up to 100000) of tiny blocks of logic with flip-flops. CPLDs are "coarse-grain" devices - they contain relatively few (a few 100's max) large blocks of logic with flip-flops.FPGAs are RAM based - they need to be "downloaded" (configured) at each power-up. CPLDs are EEPROM based - they are active at power-up (i.e. as long as they've been programmed at least once...).FPGAs have special routing resources to implement efficiently arithmetic functions (binary counters, adders, comparators...). CPLDs do not.In general, FPGAs can contain large digital designs, while CPLDs can contain small designs only.

14Digital System Design15



User-Programmable Switch TechnologiesFuseUsed in PLAsFloating gate transistorsUsed in CPLDs


18User-Programmable Switch Technologies (cont.)SRAM-controlled Programmable SwitchesUsed in FPGAsAdvantagesEasily changeableTrack latest SRAM technologyDisadvantagesVolatileHigh Power dissipation



19User-Programmable Switch Technologies (cont.)SRAM-controlled Programmable SwitchesProgrammable connectionsPass-transistorTransmission gateMultiplexer



20User-Programmable Switch Technologies (cont.)Anti-fuseUsed in FPGAsModified CMOS technologyOriginally open-circuits


The figure shows that an antifuseis positioned between two interconnect wires and physically consists of three sandwichedlayers: the top and bottom layers are conductors, and the middle layer is an insulator. Whenunprogrammed, the insulator isolates the top and bottom layers, but when programmed the insulatorchanges to become a low-resistance link. PLICE uses Poly-Si and n+ diffusion as conductorsand ONO (see [Ham88]) as an insulator, but other antifuses rely on metal for conductors, withamorphous silicon as the middle layer [Birk92][Marp94].21User-Programmable Switch Technologies (cont.)Anti-fuseAdvantagesLess expensive than SRAM technologyLow delay Low power dissipation powerDisadvantagesOne-Time Programmable (OTP)

Digital System Design22The figure shows that an antifuseis positioned between two interconnect wires and physically consists of three sandwichedlayers: the top and bottom layers are conductors, and the middle layer is an insulator. Whenunprogrammed, the insulator isolates the top and bottom layers, but when programmed the insulatorchanges to become a low-resistance link. PLICE uses Poly-Si and n+ diffusion as conductorsand ONO (see [Ham88]) as an insulator, but other antifuses rely on metal for conductors, withamorphous silicon as the middle layer [Birk92][Marp94].22User-Programmable Switch Technologies (cont.)Anti-fuseAdvantagesLess expensive than SRAM technologyLow delay Low power dissipation powerDisadvantagesOne-Time Programmable (OTP)

Digital System Design23The figure shows that an antifuseis positioned between two interconnect wires and physically consists of three sandwichedlayers: the top and bottom layers are conductors, and the middle layer is an insulator. Whenunprogrammed, the insulator isolates the top and bottom layers, but when programmed the insulatorchanges to become a low-resistance link. PLICE uses Poly-Si and n+ diffusion as conductorsand ONO (see [Ham88]) as an insulator, but other antifuses rely on metal for conductors, withamorphous silicon as the middle layer [Birk92][Marp94].23Evolution of Programmable Logic DevicesUser-Programmable Switch Technologies (cont.)Digital System Design24

24Designing Logic with FPGAsDigital System Design25

MappingPlacement

RoutingDesigning Logic with FPGAs (cont.)MappingExample : Using 3-LUTsDigital System Design26

Configuring an FPGAMillions of SRAM cells holding LUTs and Interconnect RoutingVolatile Memory Lose configuration when board power is turned off.Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card


ProgrammingBit FileAltera CPLDsMAX 7000Logic Array Blocks (LABs)Programmable Interconnect Array (PIA).


Altera CPLDsMAX 7000LABTwo sets of eight macrocells


where a macrocell comprises a set of programmable product terms(part of an AND-plane) that feeds an OR-gate and a flip-flop. The flip-flops can be configured asD type, JK, T, SR, or can be transparent. As illustrated in Figure 10, the number of inputs to the OR-gate in a macrocell is variable; the OR-gate can be fed from any or all of the five productterms within the macrocell, and in addition can have up to 15 extra product terms from macrocellsin the same LAB. This product term flexibility makes the MAX 7000 series LAB more efficient interms of chip area because typical logic functions do not need more than five product terms, andthe architecture supports wider functions when they are needed. It is interesting to note that variablesized OR-gates of this sort are not available in basic SPLDs (see Figure 1)

29Xilinx XC4000 FPGAConfigurable Logic Block (CLB)Digital System Design30

three separate LUTsUp to 9 input logicThere are two 4-input LUTS that are fed by CLB inputs, and the third LUT can be usedin combination with the other two. This arrangement allows the CLB to implement a wide rangeof logic functions of up to nine inputs, two separate functions of four inputs or other possibilities.Each CLB also contains two flip-flops.

30Xilinx XC4000 FPGA (cont.)Interconnect structureDigital System Design31

Each channel containssome number of short wire segments that span a single CLB (the number of segments in eachchannel depends on the specific part number), longer segments that span two CLBs, and very longsegments that span the entire length or width of the chip.

Thus, speed-performance of an implemented circuitdepends in part on how the wire segments are allocated to individual signals by CAD tools.31Altera FLEX 8000 FPGALogic Element (LE)Digital System Design32

contains a four-input LUT, a flip-flop, and special-purpose carry circuitryfor arithmetic circuits32Altera FLEX 8000 FPGA (cont.)Carry Chain Digital System Design33

contains a four-input LUT, a flip-flop, and special-purpose carry circuitryfor arithmetic circuits33Altera FLEX 8000 FPGA (cont.)Cascade Chain Digital System Design34

contains a four-input LUT, a flip-flop, and special-purpose carry circuitryfor arithmetic circuits34Altera FLEX 8000 FPGA (cont.)Logic Array BlocksLocal interconnect


contains a four-input LUT, a flip-flop, and special-purpose carry circuitry for arithmetic circuits

each LAB contains local interconnect and each local wire can connect any LE to any other LE within the same LAB

35Altera FLEX 8000 FPGA (cont.) FastTrack (global interconnect)


contains a four-input LUT, a flip-flop, and special-purpose carry circuitry for arithmetic circuits

each LAB contains local interconnect and each local wire can connect any LE to any other LE within the same LAB

36Altera FLEX 10000 FPGA (cont.)Embedded Array BlocksDigital System Design37

Each EAB is configurable to serve as an SRAM block with a variable aspect ratio: 256 x 8, 512 x 4, 1K x 2, or 2K x 1. In addition, anEAB can alternatively be configured to implement a complex logic circuit, such as a multiplier,

37Altera FLEX 10000 FPGA (cont.)EAB structureDigital System Design38

Each EAB is configurable to serve as an SRAM block with a variable aspect ratio: 256 x 8, 512 x 4, 1K x 2, or 2K x 1. In addition, anEAB can alternatively be configured to implement a complex logic circuit, such as a multiplier,

38Xilinx Spartan-6 FPGACLBDigital System Design39

Xilinx Spartan-6 FPGASLICEDigital System Design40



Xilinx Spartan-6 FPGALUT6Digital System Design43

Xilinx Spartan-6 FPGALUT6Digital System Design44

Xilinx Spartan-6 FPGAShift register lookup table (SRL)


Xilinx Spartan-6 FPGASLICEM Used as Distributed MemoryDigital System Design46

Xilinx Spartan-6 FPGABlock RAMDigital System Design47

Xilinx Spartan-6 FPGADSP48A1 SliceDigital System Design48

Xilinx Spartan-6 FPGAInterconnect ChannelsDigital System Design49

Computer Aided Design (CAD) Flow for FPDsDigital System Design50

System on a ChipAdd Embedded Micro-Processor Cores in Fabrice.g. RISC PowerPCEthernet Interface

Run Operating System e.g. Linux

Combine Micro-Processor & Massively Parallel Logic

Dual Design FlowsFirmware HDLSoftware CDigital System Design51

Configuration data inConfiguration data out= I/O pin/pad= SRAM cell(a) One embedded core(b) Four embedded coresuPuPuPuPuP

Documents

M.Mohajjel. Why? TTM (Time-to-market) Prototyping Reconfigurable and Custom Computing 2Digital System Design