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MiniProject+ReversePresentations
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Sr. No. Name Mini-Project Reverse Presentation1 nidhi.patel2 karan.shah3 mehul.thakkar4 aman.chanpura5 swati.chavan6 viren.bhalala7 anudeep.j8 megha.brahmbhatt9 shailesh.kavar
10 himanshu.agrawal11 nikunj.naliyapara12 suhas.chaudhari13 gaurang.pandey14 parth.rpatel15 govind.sharma16 priyansh.bhimani17 ajay.chauhan18 sharvil.desai19 sandip.gangani20 shyamal.pampattiwar21 abhay.chavda22 tejas.dalal23 meet.thacker24 rabinkumar.yadav25 mittal.patel26 jayesh.patel27 chirag.rathod28 sureshkumar.kyatham29 nipul.gami30 mercy.christial31 abhishekkumar.sahu32 jaykumar.jasani33 dixita.patel34 chandrasekhar.lanka35 jayesh.prajapati36 gayathri.mohanlal37 ankitkumar.savaliya38 chintan.shah39 moinbaba.shaik40 ravindra.vadi41 vishal.prajapati42 chandrasekhar.naik43 nidhi.padiya44 alay.shah45 rishi.shah
Efficient code writing for FSM in verilog,Parameters and `define
Strength Modeling and Advanced NetDefinitions, Multiple driver resolution
SPI Slave
APB Slave
GPIO Slave
Event Queues in Verilog, Types of VerilogSimulators and their effect on simulation and
simulation timing
Procedural Blocks in Verilog, Blocking vsNon-blocking statements
Timing and Delay Modeling in Verilog, Tasksand Functions
Synthesis vs Simulation, Synthesizable andNon-synthesizable Verilog Constructs
System Tasks and Compiler directives,Races in Verilog
Verilog as a Verification language
Memory Design in Verilog
I2C Slave
APB Master
I2C Master
GPIO Master
SPI Master
JTAG