Microelectronics

Microelectronics Packaging 1

Engr. Enrico Claro R. Delmoro, PECE26 July 2009

Agenda

Evolution and Challenges in Electronics/Semiconductor Industry

- Electronics and Semiconductor Industry in the Philippines

- Microelectronics Revolution

- Semiconductor Devices

Trends in Microelectronics Packaging

- Primary Functions

- Considerations in Package Selection

- Assembly and Test Processes

The Electronics and Semiconductor Industry in the

Philippines

Microelectronics Packaging and

Assembly

Fiber O

ptic

Technolo

gies

Display

Technolog

ies

Microele

ctron

ics

Technologies

Packaging

Technologies

Magnetic/Optical

Storage Technologies

Consumer

Computer

Telecom

Medical

Aerospace

Transportation

USA

Softw

are,

App

licat

ions

Battery Technologies

MPA

At the heart of the communication, information technology, consumer electronics, medical and transportation technologies is microelectronics technology. Microelectronics Packaging is an integral building block of it.

Nokia® Cellular Phone

Inside A Cell Phone

Inside a Cell Phone

Apple iPhone™

Source: http://news.cnet.com/2300-1041_3-6244920-1.html?tag=mncol

Electronics and Semiconductor Industry in the Philippines

(Export Value in Billion Dollars as of 2007)

Sources: National Statistics OfficeBureau of Export Trade Promotion, DTI

7.5510.61

14.98

19.87

27.07 26.64

3129.627.3

24.1723.76

21.6

25.34

4.893.782.97

0

5

10

15

20

25

30

35

1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007

Plastic Products3%

Computer and Peripherals Equipment

7%

Women, Girl and Babies Garments

7%

Other Electrical Equipment

3%

Mens and Boys Garment

3%

Other Industries65%

Semiconductor and Electronics

12%


(Distribution of Employment as of 2007)

Sources: National Statistics OfficeBureau of Export Trade Promotion, DTI


(Total Employment as of 2007)

Sources: Philippine Board of Investments (BOI) & Philippine Economic Zone Authority (PEZA)

74 80 90120

160

220250

280315307

346

402

460

335

376

438

0

50

100

150

200

250

300

350

400

450

500

1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007


ELECTRONIC SUB-ASSEMBLIESHard Disk Drives, Floppy Disks

DVD/CD ROM, Motherboards, LCD PanelsPSU, UPS, Solar Panels

TELECOMMUNICATIONSTelephones, Pagers, VHF,UHF Radios,

Cellular Phones, Scanners, Satellite Receivers

COMPONENTS AND DEVICESCore 2 Duo, DSPs, ASIC, DRAM, SRAM ,Flash

Transistors, Diodes, Resistors, Coils, Capacitors, Transformers, Lead Frames

PC/OFFICE EQUIPMENTPersonal Computers, Photocopy Machines and Parts,

Electronic Calculators

COMMUNICATIONS AND RADARPagers, CCTV, Radar Detectors, Marine and Land Mobile Radios,

CB Transceivers

CONSUMER ELECTRONICSTV Sets, Electronic Games, Radio Cassette

Players, Karaoke Machines, VCD/DVD Players

CONTROL & INSTRUMENTATIONStepper Motor Drivers, PCB Assembly for

Instrumentation Equipment

MEDICAL AND INDUSTRIALSpiro Analyzers, Heart Implants,

Hearing Aids

AUTOMOTIVE ELECTRONICSElectronic Brake Systems, Car RadiosEngine Control Unit, Wiring Harness

Source: Master Plan for Philippine Electronics Industry 1998

Systems Manufacturing

Assembly Manufacturing

Test Manufacturing

Chip Design

Package and Assembly Development

Final Test Development

Systems Development

Software Development

Chip Equipment SME

Software SME

Fab Process Development

Sort Test Development

Sort Manufacturing

Fab Manufacturing

Materials SME

Instrumentation SME

Source : “The Bitter Pill” Building a New Philippine Semiconductor and Electronics Industry Through Technical Competencies Enhancement by Lito Zulaybar


Our activities in the value chain

NUMBER OF FIRMS

860 FIRMS

Sources: Philippine Board of Investments (BOI) & Philippine Economic Zone Authority (PEZA)

Malaysia2%

Others8%

Europe7%

Taiwan4%

Singapore 2% Philippines28%

Korea10%

Japan30%

US9%

NATIONALITY:

72% Foreign28% Filipino

20042004


Too much reliance on Foreign Direct Investment

Among developing nations, China has been the largest recipient of foreign investment, averaging about $40 billion per year during the late 1990s. Membership in the World Trade Organization will result in even higher levels.

U.S. companies are shifting manufacturing from Malaysia, Philippines, Thailand, Indonesia, and even Mexico to China. Toshiba Corp. (TOSBF ) is making its TVs on the mainland, and Sony Corp. (SNE ) is manufacturing its PlayStations there. Taiwan's companies produce half of all their information-technology products in the country.

China's advantages are numerous. Its wage rates are a third of Mexico's and Hungary's, and 5% of those in the U.S. or Japan. China's investments in education and training are attracting research facilities from companies such as IBM (IBM ), Motorola (MOT ), and Microsoft (MSFT ). The critical mass of factories, subcontractors, and specialized vendors has created a manufacturing environment with which few can compete. China is not just an export platform, either; its large and expanding domestic market is another attraction.

“When Everything Is Made in China”, Jeffrey E. Garten, BusinessWeek, June 17, 2002


The problem with the industries too much reliance on Foreign Direct Investment (FDI) is that growth is dependent on how much these Multinational Companies (MNCs) infuse investments into the country.

Competition for FDI comes not only from China, Malaysia, Thailand and India; but Vietnam is emerging as well.

The Microelectronics Revolution

The Microelectronics Revolution

Microelectronics is the cornerstone of:

- The Consumer electronics revolution

- The Computer Revolution

- The Communication Revolution

- Internet

History of the Integrated Circuit

In 1945, Bell Labs established a group to develop a semiconductor replacement for the vacuum tube. The group led by William Shockley, included, John Bardeen, Walter Brattain and others. In 1947 Bardeen and Brattain succeeded in creating an amplifying circuit utilizing a point-contact "transfer resistance" device that later became known as a point contact transistor.

Bardeen and Brattain applied two closely-spaced gold contacts held in place by a plastic wedge to the surface of a small slab of high-purity germanium. The voltage on one contact modulated the current flowing through the other, amplifying the input signal up to 100 times.

Source:http://www.computerhistory.org/semiconductor/timeline/1947-invention.html

In 1948, William Shockley developed the concepts for junction transistor a more practical form of the transistor, the point contact transistor was difficult to produce. By 1951, Gordon Teal grows large single crystals of germanium and works with Morgan Sparks to fabricate the first grown n-p-n junction transistor



The ability to produce low cost transistors that tolerated higher heat levels was an important factor in the transition of computers and other electronic equipment from bulky vacuum-tube systems to more compact, reliable solid-state systems.

On May 10, 1954, TI announced the first commercial availability of grown-junction silicon transistors. These first silicon transistors were constructed by cutting a rectangular bar from a silicon crystal that was grown from a melt containing impurities. The impurities were chosen to produce the desired current-carrying characteristics in the resulting transistor.

Source: http://www.ti.com/corp/docs/company/history/tihistory.shtml


At the Düsseldorf Radio Fair in 1953, the German firm Intermetall unveiled what was probably the world's first transistor radio, more than a year before Texas Instruments claimed that milestone. The radio's amplifier circuit was built around four point-contact transistors made by Intermetall, which Herbert Mataré and businessman Jakob Michael had founded in 1952.

The first commercial transistor radio, the Regency TR-1, was announced on October 18 ,1954 by the Regency Division of Industrial Development Engineering Associates of Indianapolis, Indiana and put on sale in November of 1954. It cost $49.95 (the equivalent of roughly $364 in year-2005 dollars) and sold about 150,000 units. Raytheon and Zenith Electronics transistor radios soon followed.


Source: http://en.wikipedia.org/wiki/Transistor_radio

Jack Kilby designed the first Integrated Circuitover the summer of 1958 at Texas Instruments while most of the company was on vacation, and it was first demonstrated on September 12, and unveiled to the public the following spring.

Kilby succeeded in integrating electronic components, including a transistor and other components, onto a sliver of germanium, which made possible low-cost high volume manufacturing of electronic circuits.


Source: http://www.ti.com/corp/docs/company/history/tihistory.shtml

Kilby's invention had a serious drawback, the individual circuit elements were connected together with gold wires making the circuit difficult to scale up to any complexity. By late 1958 Swiss-born physicist - Jean Hoerni at Fairchild had developed a structure with N and P junctions formed in silicon. Over the junctions a thin layer of silicon dioxide was used as an insulator and holes were etched open in the silicon dioxide to connect to the junctions. Czech-born physicist - Kurt Lehovec of Sprague Electric developed the technique of using PN junctions to electrically isolate components.


In 1959, Robert Noyce also of Fairchild had the idea to create an integrated circuit by combing Hoerni's and Lehovec's processes and evaporating a thin metal layer over the circuits. The metal layer connected down to the junctions through the holes in the silicon dioxide and was then etched into a pattern to interconnect the circuit. The Planar Technology set the stage for complex integrated circuits and is the process used today.


By overcoming the “surface states” that blocked electric fields from penetrating into the semiconductor material. Investigating thermally grown silicon-dioxide layers, they found these states could be markedly reduced at the interface between the silicon and its oxide in a sandwich comprising a layer of metal (M - the gate), a layer of oxide (O - the insulation), and a layer of silicon (S – semiconductor). As their prototype transistor was slow and addressed no pressing needs of the telephone system, it was not pursued further at Bell Labs

In 1959 M. M. (John) Atalla and Dawon Kahng at Bell Labs achieved the first successful insulated-gate field-effect transistor (FET).

In 1960 Karl Zaininger and Charles Meuller fabricated an insulated-gate FET at RCA and C.T. Sah of Fairchild built a surface-potential controlled tetrode. Today both would be called MOS transistors. In an MOS transistor, the conducting region is either p-type (making it a “p-channel” device) or n-type (“n-channel” device) material. The latter devices are faster than p-channel ones but more difficult to manufacture. MOS transistors hit the commercial market in 1964.


Semiconductor devices are enclosed in protective ceramic, metal or plastic packages to prevent damage to the chip and its fragile connecting wires. Despite this important function, packaging is one of the most neglected aspects of semiconductor design. Many programs were delayed because the chip was too large or consumed too much power for the designated package.

In 1965 Don Forbes, Rex Rice, and Bryant ("Buck") Rogers at Fairchild devised a 14-lead ceramic Dual-in-Line Package (DIP) with two rows of pins 100 mils apart that revolutionized computer manufacturing by simplifying layout and allowing automated insertion into printed circuit boards. Low-cost, plastic-molded DIPs dominated production volumes by the early 1970s.



Source: http://www.computerhistory.org/semiconductor/timeline/1965-Moore.html

In 1965, Gordon Moore director of research and development at Fairchild Semiconductor wrote a paper for Electronics entitled “cramming more components onto integrated circuits”. In the paper Moore observed that “the complexity for minimum component cost has increased at a rate of roughly a factor of two per year”. This observation became known as the Moore’s Law

Moore’s Law

Measuring trends in semiconductor manufacturing technology generation

DrainSource

GateGate Insulator

Channel Length is good measure of the development in the semiconductor manufacturing technology

The number of transistors per given area of silicon will double every 2 years

Flash Memory Semiconductor Technology scaling. A tremendous improvement of 1/476 from 1986 to 2004.

The number of transistors per given area of silicon will double every 2 years (Moore’s Law)

Intel 4004:

Nov 1971

10 micron technology

2,300 transistors

108 KHz clock

This 8088 16-bit processor could manage 1 MB of memory using an external 20-bit address bus . The clock frequency chosen by IBM (4.77 MHz) was fairly low, though the processor was running at 10 MHz by the end of its career. The 8088 was packaged in a 40 leads Ceramic DIP



The Pentium 32-bit processor contained 3.3 Million transistors . It has a clock frequency of 66 – 200 MHz and was packaged in a 320 pins Staggered Pin Grid Array (SPGA)


Intel Pentium 4:

June 2002

0.13 micron technology

55 Million transistors

2.40 GHz clock

The Pentium 4 was packaged in 478 pins Flip Chip-Pin Grid Array


Intel Core 2 Duo (Conroe):

June 2006

65 nm technology

~291 Million transistors

3.00 GHz clock

Flip Clip Land Grid Array 775 pins

The Intel® Codre 2 Duo processor has more than 10,000 times as many transistors as the Intel 8088 CPU

Computers become Ubiquitous

Reference: Ray Kurzweil, “The Age of Spiritual Machines”, 1999http://en.wikipedia.org/wiki/Image:PPTExponentialGrowthof_Computing.jpg

Acceleration of Communication

Internet: Pierre Teilhard de Chardin’s Noosphere?Reference: Cyberspace and the Dream of Teilhard de Chardin by John R. Mabry

These striking images are 3D hyperbolic graphs of Internet topology. They are created using the Walrus Visualization tool developed by Young Hyun at the Cooperative Association for Internet Data Analysis (CAIDA).

“Teilhard imagined a stage of evolution characterized by a complex membrane of information enveloping the globe and fueled by human consciousness. It sounds a little off-the-wall, until you think about the Internet, that vast electronic web encircling the Earth, running point to point through a nerve-like constellation of wires. We live in an intertwined world of telephone lines, wireless satellite-based transmissions, and dedicated computer circuits that allow us to travel electronically from Des Moines to Delhi in the blink of an eye.”

Excerpt from : “A Globe, Clothing Itself with a Brain” byJennifer Cobb Kreisberg

Benefits of Continuous Integration

Results into the exponential improvements in:

- System performance

- Cost per function

- Power per function

- System reliability

- Size reduction

The evolution of electronic assembly has reached the 3-D era. (Source: SiliconPipe)Reference: An Alternative Approach to Circuit Design and Assembly for High Speed InterconnectionsSource: http://soccentral.com/results.asp?EntryID=10778

Packaging Technology: Needs to Keep up with Moore’s Law

Packaging Technology: Transition in Semiconductor Package Types

Keys to Microelectronics Revolution

Cheap and abundant

Amazing mechanical, chemical and electronic properties

Probably, the materials best known to humankind


Because of their smaller size and lower power consumption than bipolar devices, over 99.9 percent of the microchips produced today use MOS transistors


Polymers are the most interesting and versatile substances in the world of material science offering an incredibly wide range of physical and chemical properties.

Polymers can be viscous liquids, like silicones, or steel-like solids with high temperature performance.

Although there are natural polymers, such as rubber, most of the thousands of commercial products are synthesized. Our ability to design polymers with specific properties is what makes them so useful.

Polymers are now the most critical ingredients for electronic circuitry and packaging.

Reference: “Thermoplastic Die Attach Adhesive for Today's Packaging Challenges” by K. Gilleo, T. Cinque, S. Corbett, M. Corey, C. Lee & R. Miculich

Microelectronics Packaging

Integrated Circuit Packaging: Primary Functions

Traffic Cop, which routes power, ground and signals going into and/or coming from the die. Interconnects the die to the rest of the system as quickly and with as little added distortion as possible.

Firefighter, which draw performance-sapping and reliability limiting heat away from the die to be absorbed by the surrounding environment; and.

Soldier, which protects the die from mechanical stresses and other environmental effects (moisture, contamination, etc), while creating no stresses of its own.

Reference: “Silicon Contends with Stuffed and Shrinking Packages” by Brian Dipert. June 13, 2002, Electronics Design, Strategy News

Integrated Circuit Packaging: Electrical Functions

Power Distribution

Power Supply

Ground

Signal Distribution

Data ( Transmit and/or Receive)

Address

Clock

Control

Semiconductor Packaging: Introduction

Most ICs are bonded to small IC packages.

IC Packaging Materials

Although it is possible to attach chips directly to boards (The method used extensively in low-cost consumer electronics.) Placing chips in packages enables independent testing of packaged parts, and eases requirements on board pitch and pick and place equipment.

MetalCeramicPlasticLaminates (Fiberglass, Epoxy Resin)

Cap

Base

GlassMetal Stud

Hermetically Sealed Semiconductor Packages.Metal Can

Hermetically Sealed Semiconductor Package.Ceramic

Lidded Ceramic Package

Hermetically Sealed Semiconductor Package.Ceramic

Characteristics of Ceramic packaging material

Consist of several layers of conductors separated by layers of ceramic (Al2O3 “Alumina”)

Chip is placed in a cavity and bonded to the conductors

Metal lid soldered on the package

Hermetically sealed against the environment

Ground layers and direct bypass capacitors possible within a ceramic package

High permittivity of alumina (εr = 10)

Expensive

Cost of Ceramic Packages Versus Plastic Packages

Plastic Packages cost lower compared to Ceramic Packages on similar package configuration and number of pins

Hermetically Sealed Semiconductor Packages.Ceramic

Un-lidded Ceramic Package Ceramic Package with Quartz Bull's-eye

Hermetically Sealed Semiconductor Packages.Ceramic Lidded Chip Carrier (LCC); Hybrid Package

Ceramic Lidded Chip Carrier Hybrid Packages

Hermetically Sealed Semiconductor Packages.Ceramic

IC

Wire (Au-Al)

Base

DevitrifyingGlass

LeadFrame

Cap

PDIP

PLCC

TSOP

Plastic Molded Semiconductor Packages.

DieLeadFrameWire

Mold Compound Die Pad

Characteristics of Plastic packaging material

Die-bonding and wire bonding the chip to a metal lead frame

Encapsulation in injection-molded plastic

Inexpensive but high thermal resistance

Plastic molds are hygroscopic

Absorbs moisture. Storage in low-humidity environmentObservation of factory floor-life

Stored moisture can vaporize during rapid heating. Can leadto hydrostatic pressure during reflow process. Consequencescan be: Delamination within the package, package cracking.Early device failure.


Plastic Molded Semiconductor Packages with Organic Laminate Substrate.

Ball Grid Array (BGA)

Advanced IC package for high density low profile applications

Chip scale package (CSP)

Low lead inductance


Flexible Stacked (Folded Stacked)

Die Stacked Chip Scale Packaging

Interconnect Technology

Package Interconnect

First Level Interconnect connects the silicon die to the package. This maybe a wirebond or a flip chip type interconnect

Second Level Interconnect is the connection between the package and the system board. This may be in the form of leads, pins or balls arrays.

The package serves as a space transformer from the chip interconnection to the board interconnection.

Semiconductor Packaging: First Level Interconnect Technology

Wirebond

Flip Chip

The pads on the IC chip and the adjoining I/O signal, power and ground terminals are connected one by one with Gold (Au) or Aluminum (Al) wires

The invention of the flip chip technology allowed a breakthrough in increasing the number of internal signal interconnect to external package pins.

Semiconductor Packaging: Second Level Interconnect Technology

Pin-Through-Hole (PTH)

Surface Mount Technology (SMT)

Pins are inserted into through-holes in the circuit board and soldered in place from the opposite side of the board

Socket availableManual pick and place possible

SMT packages have leads that are soldered directly to corresponding exposed metal lands on the surface of the circuit board

Elimination of holesEase of manufacturing (high-speed P&P)Components on both sides of the PCBSmaller dimensionsImproved package parasitic componentsIncreased circuit-board wiring density

Semiconductor Packaging: Second Level Interconnect Technology

Trends and Challenges

Packaging Trends

Electrical performance requirements continue to drive increases in pin count and interconnect performance. These requirements include, but are not limited to, increases in bus speed, alternative signaling technologies, feature integration, and low-voltage, high-current power delivery.

Packaging Trends

Reference:Pentium® 4 Processor High-Volume Land-Grid-Array Technology: Challenges and Future Trends Intel Technology Journal, Volume 09Issue 04 November 9, 2005

Packaging Trends

The pad pitch on the IC chip is typically 0.006 inch (6 mils or 152µm). This spacing is alreadymuch larger than the 2 to 8 microns (0.08 to 0.31 mils) pitch of the wiring (metallization) on the ICchip. But PCB wiring requires an even larger pitch, usually between 40 and 100 mils.

Microelectronics Packaging: Interconnect Challenges

The biggest limitation of a modern digital IC: Large reduction in signal count between on chip wires and package pins. Typical IC has:

104 wiring tracks on each of the 4-5 metal layers

103 signals can leave the chip (for cheaper packages: 40…200)

Chips are often “pad limited”. Peripheral-bonded chips. Chip area increases as the square of the number of pads.

Reference: Wire-Loop Shaping in Multi-Tier PackagesURL: http://www.semiconductor.net/article/CA630278.html

Microelectronics Packaging: Interconnect Challenges

Peripheral-bonded chips.

Rent’s Rule

E.F. Rent of IBM published two internal memoranda in 1960 that contained the log plots of "number of pins" versus "number of circuits' in a logic design. These data tend to form a straight line in a log-log plot and yield the relationship:

GPP NKN

Where:NP is the number of pinsNG is the number of logic blocksβ is Rent’s constantKP is a proportionality constant

Rent’s Rule

Packaging Trends

To avoid substantial increases in package size with this increase in pin count, interconnect pitch reduction is required. Pitch reduction imposes package routing, motherboard routing, and socket design constraints that require significant integration to address. From socket design and assembly standpoints, surface-mount capability continues to be desired, imposing additional design considerations. Yield and reliability of large-pin-count and reduced-pitch components are a design challenge due to component warpage and thermal expansion differences between materials.

Ball Pitch

Reference: http://www.semiconductor.net/article/CA6492524.html

Packaging Trends

The rapid progress in chip-level interconnect scaling that is expected between now and 2015 (from 60-20 µm peripheral pitches), relative to the density of interconnects on PCBs (800-500 µm solder ball pitch) is the focus of next-generation flip-chip and substrate technology . With ball grid array (BGA) and micro-BGA approaches, package reliability is dominated by underfill reliability. Smaller diameter bumps put more strain on thinner layers and higher stresses on smaller areas.

Source: http://nepp.nasa.gov/index_nasa.cfm/779/

Packaging Trends

This passive silicon carrier contains a regular grid of through-silicon vias (TSVs). It is designed to serve as a cost-optimized interposer for standard circuit ICs, with matching coefficient of thermal expansion to the chip and carrier.

Assembly and Test Processes

Semiconductor Assembly and Test Process: Introduction

Assembly and test are the processes involved in transforming thefabricated wafers into packaged and functional components.

Semiconductor Assembly and Test Process: Wirebond

Plastic Package Assembly: Die Preparation

Wafer Inventory

Wafer Thinning

Wafer Mount

Wafer Saw

To FOL

Assembly: Front of Line

Die Attach

Plasma Clean

Wirebond

Optical Inspection

Plasma Clean

To EOL

Assembly: End of Line

Encapsulation

Marking

DTF & Lead Finish

To Test Process

Test Processes

Class Test

Bake

Tape and Reel

Dry Pack

FQA

Semiconductor Assembly and Test Process: Flip Chip

A. Die Preparation

AVI BUMP REFLOW

WAFER MOUNT

B. Substrate Preparation

WAFER SAW & WASH APL

C. Assembly Process

CAM DEFLUX EPOXY

CARRIER TRAY LOAD

BURN -IN

POST BURN – IN CHECK

D. Test Process

E. Backend Process

LASER MARK

BALL ATTACH & INSPECT

FVI PACK FQA

Semiconductor Assembly and Test Process: Test Process

PRE BURN –IN CHECK

Semiconductor Assembly: Wafer Level Packaging

[a] wafer encapsulation[b] electrical contacts are routed [c] solder bumps are formed[d] the wafer is singulated[e] the final wafer is one chip short of a WLCSP

Source: Tessera Inc. http://www.semiconductor.net/article/CA6482835.html

The largest contributor to the 13% growth rate for packaging materials in 2007 will be organic substrates, which are required for the rapidly growing ball grid array (BGA) and FCP applications. The organic substrates market, which is the largest segment of the overall packaging materials market, will approach $6.3B this year, compared with $5.1B last year. Without organic substrates in the year-over-year growth rate calculation, the total packaging materials growth rate drops to 7% from 13%.

Source: http://www.semiconductor.net/article/CA6445468.html

Chip-scale packaging (CSP), flip-chip packaging (FCP) and various SiP technologies require organic substrates, new mold compoundformulations, smaller diameter wire and, for some packages, customized underfill materials.

Packaging Material Market Outlook

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