Michael Aquilino Microelectronic Engineering Department Rochester Institute of Technology

Development of a Deep-Submicron CMOS Process for Fabrication of High

Performance 0.25 m Transistors

Michael AquilinoMicroelectronic Engineering DepartmentRochester Institute of TechnologyApril 21, 2005

Motivation

Rochester Institute of TechnologyMicroelectronic EngineeringRochester Institute of TechnologyMicroelectronic Engineering

2

Enable the Microelectronic Engineering department to continue the semiconductor industry trend of fabricating high performance transistors that have faster switching speeds, increased density and functionality, and ultimately a decrease in cost per function.

Push the limits of the SMFL in all areas from design to fabrication to test

Create a baseline process that can be used to integrate strained silicon, metal gates, high-k gate dielectrics, and replacement gate technologies at RIT

Outline


3

RIT/Industry Scaling Trends Gate Control Fundamentals Short Channel Effects Deep-Submicron Scaling Unit Process Development Layout Integration/Fabrication/Test Time Line Questions

Date Processor Family Gate Length

(μm) Frequency Transistors Supply Voltage

(V) November 1971 4004 10 108 KHz 2,300 15

April 1974 8080 6 2 MHz 6,500 12 June 1978 8086 3 10 MHz 29,000 5

February 1982 Intel 80286 1.5 12 MHz 134,000 5 March 1995 Intel Pentium 0.6 120 MHz 3,300,000 3.5 **May 2004 RIT Submicron NMOS 0.5 - - 3.5 August 1999 Intel Pentium 2 & 3 0.25 600 MHz 9,500,000 2.0

**September 2005 RIT Deep-Submicron CMOS 0.25 - - 2.0 September 2001 Intel Pentium 3 & 4 0.18 2.0 GHz 45,000,000 1.7 February 2004 Intel Pentium 4 0.13 3.4 GHz 55,000,000 1.5

June 2004 Intel Pentium 4 0.09 3.6 GHz 125,000,000 1.4

RIT/Industry Scaling Trends


4

o Over last 30 years, transistors have gotten smaller and fastero 110x reduction in gate lengtho 36,000x increase in switching speed

o Integrated circuits have become much more complexo 54,000x increase in number of transistors on an IC

Table 1: RIT/Industry Scaling Trends [3]



(V) November 1971 4004 10 108 KHz 2,300 15







5

o In May of 2004 an NMOS transistor with LPOLY = 0.5 µm was developed

o This is RIT’s smallest transistor with LEFFECTIVE = 0.4 µm

o This is the same technology as the Intel Pentium from 9 years earlier




6

o By September of 2005, this process will yield CMOS transistors with LPOLY = 0.25 µm and LEFFECTIVE = 0.18 µm

o This technology was used in high volume manufacturing of the Intel Pentium III at 600 MHz only 6 years ago

o The gap between industry and RIT is rapidly shrinking




(V) November 1971 4004 10 108 KHz 2,300 15





Outline


7


o NMOS Transistor

o 4 Terminal Device o Gate o Sourceo Drain o Body

To turn transistor on:o Apply positive charge to Gate, QG

o A depletion region in the p-type body is created as positively charged holes are repelled by gate, exposing negatively charged acceptor ions, QB

o As the gate charge is further increased, electrons from the source diffuse into the channel and become inversion charge, QI

o QG = QB + QI

Gate Control Fundamentals


8

Figure 1: Schematic of NMOS Transistor [4]

o The source and body terminals are grounded

o A positive voltage is applied to the drain, VDS

o Inversion charge moves from source to drain and is the current in the device



9


dVVQL

WI nn

VD

VSD )(

o Equation 1 shows the classical derivation for drain current in a transistor by integrating the inversion charge along the channel

(Eq. 1)

o A depletion region from the drain is created by the reverse biased body-drain p-n+ diode

o The positively charged donor ions in drain support some of the negative inversion charge

o This is known as “Charge Sharing” as the gate does not have full control over the inversion channel

o For large gate lengths, the contribution of the drain in controlling the inversion layer is small compared to the gate contribution

o As transistors are scaled smaller in gate length, the drain has a larger percentage contribution in supporting inversion charge in the channel



10


Outline



11

o “Gate Control” is the most important concept in scaling of transistors

o The consequence of the drain taking control away from the gate is short channel effects such as:

o VT Roll-offo Drain Induced Barrier Lowering (DIBL)o Punch-through

Short Channel Effects


Vt Rolloff vs. Leff

0

0.2

0.4

0.6

0.8

1

0.4 0.5 0.6 0.7 0.8 0.9 1

Leff (um)

Th

resh

old

Vo

ltag

e (v

olt

s)

Figure 2 : VT Roll-off Effect [1]

o Threshold voltage decreases as gate length decreases

o For small enough gate lengths the devices will be on at 0 V

12






Figure 3: Drain Induced Barrier Lowering (DIBL) [1]

o Increased off-state leakage with increase in drain voltage

o If gate were in full control, these curves would be one on top of the other

13






Figure 4: Lateral source/drain Punch-through [4]

o At high drain bias, the drain takes control of current through the device

o Excessive heating can occur and cause device failure

14


o The consequence of the drain taking control away from the gate is short channel effects (SCE) such as:


o Transistors with short channel effects are undesirable

o These SCE must be minimized to yield long-channel transistors



15

Outline



16

Deep-Submicron Scaling


o The goal in deep-submicron scaling is to maximize the gate control for switching the device on and off by scaling physical and electrical parameters

ION 600 A/μm Tox 40 - 50 Å IOFF 1 nA/μm XJ (shallow LDD) 50 – 100 nm

Log(ION / IOFF) 5.75 decades ND (LDD) 2 - 5 x1018 cm-3 SS 85 mV/decade RS (LDD) 400 – 850 sq

DIBL < 100 mV/V XJ (contact) 135 – 265 nm VDD 1.8 – 2.5 V ND (contact) 1x1020 cm-3 | VT | 0.5 V XJ (SSRW channel) 50 – 100 nm

Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6]

Figure 5: Physical Scaling Guidelines [7]

17





o Decrease gate oxide thicknesso Gate is closer to the channelo More control in switching device offo Cox since Cox = A/tox or Cox =Q/Vo ID and gm since Cox





18





o Decrease junction depth of source/draino Depletion region from gate dominates depletion region from the draino Trade-off is sheet resistance and ID o ND must which will cause RS





19





o Use sidewall spacer to create deeper source/drain junction called the contacto Typically ~2x as deep as shallow LDDo Doped heavily to reduce RS





20





o Increase doping of channel to decrease the depletion region from the source/draino Use a retrograde profile where doping is low at the surface and higher sub-surfaceo Mobility of carriers o ID and gm since both are mobility





21




o As TOX , gate leakage current

o VDD must to reduce this leakage

o VT must so (VGS-VT) , this is “Gate Overdrive” and is ID

o Want ION since gate delay ION-1

ONI

RC





22




o Want IOFF to be low to reduce standby powero The industry standard metric is 1 nA/µm of off-currento This results in 5.75 decades between ION and IOFF

o There is 500 mV swing between 0 V and VT

o SS of 85 mV/decade is needed to turn the device off

OX

D

C

C

q

KTSS 110ln Theoretical limit ~ 60 mV/decade

@ 300K





23

Outline



24

P-Well N-Well

STIP+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

Aluminum

TiSi2

P-SSRW N-SSRW

N-Substrate

Nitride Spacers

0.25 µm Device Technology


• Shallow Trench Isolation Dual Doped Poly Gates 50 Å gate oxide w/ N2O Low Doped Source/Drain Extensions Titanium Silicide

• Super Steep Retrograde Twin Well Nitride Sidewall Spacers Rapid Thermal Dopant Activation 2 Level Aluminum Metallization Back End CMP

o Unit Processes will be developed to yield cross-section shown in Figure 6

Figure 6: CMOS Cross Section showing NMOS (left) and PMOS (right) Transistors

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Unit Process Development


Shallow Trench Isolation Channel Engineering

Uniformly Doped Twin Well Super Steep Retrograde Well

Ultra Thin Gate Oxide Gate Formation

Lithography Resist Trimming Reactive Ion Etch (RIE) of Gate

Source/Drain/Gate Doping Poly re-ox Low Doped Source/Drain Extensions Sidewall Spacers Source/Drain Contacts Dual Doped Poly

Rapid Thermal Dopant Activation Titanium Salicide Contact Cut Etch 2 Level Aluminum Metallization

P-Well N-Well

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

Aluminum

TiSi2

P-SSRW N-SSRW

N-Substrate

Nitride Spacers

STI

Figure 7: Shallow Trench Isolation

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Shallow Trench Isolation


o Replacement of LOCOS as preferred isolation technology

o LOCOS suffers from “Bird’s Beak” effecto Field oxide encroaches into active region, reducing Wo Reduction in Width leads to reduction in drive currento To recover this loss, transistors must be made wider which takes up more real estateo Small geometries are not possible since Bird’s Beak oxide encroaches from both sides of active area

o With STI, WACTUAL ≈ WDRAWN

o Increased packing densityo Higher drive current for devices with same WDRAWN

o Decreased topography early in the process

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Shallow Trench Isolation


o Grow Pad Oxideo Deposit Nitride by LPCVDo Pattern and Etch Silicon Trench

o Grow liner oxide to repair silicon and round off sharp cornerso Fill with PECVD TEOS Oxide

o CMP trench oxideo Use Nitride as etch stopo Remove Nitride in H3PO4 acid

Figure 8: STI Process after trench etch

Figure 9: STI Process after trench fill

Figure 10: STI Process after CMP

28









29

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

Aluminum

TiSi2

P-SSRW N-SSRW

N-Substrate

Nitride Spacers

STI

P-Well N-Well

Channel Engineering


P-Well N-Well

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

Aluminum

TiSi2

N-Substrate

Nitride Spacers

STI

N-SSRWP-SSRW

Uniformly Doped Twin Wells

o NMOS built in p-wello PMOS built in n-wello Set Field VT to stop parasitic conduction channels from forming between adjacent devices

Super Steep Retrograde Wells

o 2nd step in well formation processo Lower doping at surface which transitions to higher doping sub-surfaceo Control short channel effectso Set active VT

Figure 12: Super Steep Retrograde WellsFigure 11: Uniformly Doped Twin Wells

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o In industry, wells are implanted through the trench oxide with energies of 1 MeV to place the peak 1 µm below the surface

oThe limit of the Varian 350D Ion Implanter is 190 KeV which is not high enough to implant through 3000 Å of trench oxide

o Also, there will be non-uniformities in silicon trench depth and TEOS oxide fill.

o For packing density purposes, multiple active regions are built in the same well with 1 common contact

o It is therefore required for the well doping to be continuous under the trench oxide regions

o For this process, the wells will be implanted before the trench oxide fill in the STI process to ensure the wells are continuous in the field

Uniformly Doped Twin Well


31

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

Aluminum

TiSi2

P-SSRW N-SSRW

N-Substrate

Nitride Spacers

STI

P-Well N-Well

Figure 11: Uniformly Doped Twin Wells

Uniformly Doped Twin Well


Field Region

FOX 3000 Å NSUB 1x1017 cm-3 VTN 13 V VTP -15 V

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

Aluminum

TiSi2

P-SSRW N-SSRW

N-Substrate

Nitride Spacers

STI

P-Well N-Well

o A drive-in thermal step will create uniform wells with:o ND = 1x1017 cm-3

o XJ-WELL = 1 µm

o With a 2.0 V supply, the field-VT is sufficiently large

o The junction depth of the wells must be large enough to prevent vertical punch-through between the reverse-biased drain and complimentary doped starting wafer

o A junction depth of 1 µm will provide more than enough tolerance

Figure 11: Uniformly Doped Twin Wells

Table 3: Field Region VT

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Super Steep Retrograde Well


P-Well N-Well

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

Aluminum

TiSi2

N-Substrate

Nitride Spacers

STI

N-SSRWP-SSRW

o Increased carrier mobility due to lower channel doping at surface

o Increased drive current due to increased mobility

o Suppression of short channel effects (SCE) such as VT roll-off, punch- through, and drain induced barrier lowering (DIBL) due to the higher peek doping sub-surface

o Latch-up is suppressed because the base regions of parasitic BJTs are

doped higher, therefore reducing their gain.

Figure 12: Super Steep Retrograde Wells

33

P-Well N-Well

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

Aluminum

TiSi2

N-Substrate

Nitride Spacers

STI

N-SSRWP-SSRW



o Increased carrier mobility due to lower channel doping at surface

o Increased drive current due to increased mobility

o Suppression of short channel effects (SCE) such as VT roll-off, punch- through, and drain induced barrier lowering (DIBL) due to the higher peek doping sub-surface

o Latch-up is suppressed because the base regions of parasitic BJTs are

doped higher, therefore reducing their gain.

Figure 12: Super Steep Retrograde Wells

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Uniform well for Field VT

Peak channel concentrationLower surface doping concentration

o Implanted after uniformly doped wells go through drive-ino In Industry, heavy ions that are slow diffusers are used:

o Indium (In) is used for p-well of NMOSo Antimony (Sb) or Arsenic (As) are used for n-well of PMOS

oAt RIT, Boron and Phosphorous are available o Boron (B) will be used for p-well of NMOS o Phosphorous (P) will be used for n-well of PMOSo Are more susceptible to transient enhanced diffusion (TED)o Won’t produce profiles as steep as In or Sb but by keeping thermal budget low, can still produce retrograde profiles

Figure 13: Super Steep Retrograde Profile [10]

35









36

50 Å Gate SiO2 with N2O Incorporation


P-Well N-Well

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

Aluminum

TiSi2

P-SSRW N-SSRW

N-Substrate

Nitride Spacers

STI

o NTRS Roadmap suggests 40 – 50 Å, target for this process is 50 Å

o ox = 4 MV/cm, this is at limit of Fowler-Nordheim tunneling

o Nitrogen is incorporated into oxide to block diffusion of boron from p+ poly gate into channel of PMOS transistor

o Surface Charge Analysis can be done to determine density of interface trap states.

Figure 14: Ultra Thin Gate Oxide

37









P-Well N-Well

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

Aluminum

TiSi2

P-SSRW N-SSRW

N-Substrate

Nitride Spacers

STI

N+ Poly P+ Poly

Figure 15: Poly Gate Formation

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Gate Formation - Lithography


o ASML PAS 5500/90 steppero 248 nm KrF excimer lasero Capable of 0.25 µm lines/spaces

o Tool is currently down, laser

o Canon FPA-2000i1 steppero 365 nm i-line sourceo Capable of 0.5 µm lines/spaces

o Standard resist coat/develop track

o Capable of 0.05 µm overlay error

Figure 16: ASML DUV Stepper Figure 17: Canon i-line Stepper

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Gate Formation – Resist Trimming


o Resist trimming can be used to make 0.5 µm line a 0.25 µm line for gate

o Isotropically etch 1250 Å of resist of sides and top of 0.5 µm lineo Resist thickness reduced from 10,000 Å to 8750 Åo This is still sufficiently thick to protect poly during gate plasma etch

o Line width reduced to 0.25 µm target in photoresist

o This technique will be explored if over-exposing/developing is not successful

Figure 18: Resist Trimming Process

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Gate Formation – RIE Poly


o Polysilicon thickness is reduced for smaller gate lengthso 2500 Å target will provide 1:1 aspect ratio for plasma etcho Will block up to 50 keV Phosphorous and 30 keV Boron

o Want high selectivity of poly to oxide since oxide is very thin

o Reactive Ion Etcher will be used since it etches anisotropicallyo Etch rate is higher in the vertical direction compared to horizontal

o If etch was isotropic, enough under-cut would occur due to lateral etching that 0.25 µm would be etched away and remove the photoresist masking layer

After EtchBefore Etch

Figure 19: Under-Cut of Gate Mask 41









42

o After plasma etch of gate there is damage to edges of gate oxide

o A 250 Å oxide will be thermally grown to:o Repair damage to gate oxide from plasma etch of the poly gate

o Create a thicker screening oxide for source/drain extension implant

o Make a thicker etch stop for sidewall spacer etch process

o Form an off-set region for lateral diffusion of shallow s/d extension

o Want to reduce gate overlap of s/d to reduce Miller Capacitanceo This capacitance will reduce the cut-off frequency of the device

o Need 15 – 20 nm overlap or drive current will degrade [11]

Poly Re-Oxidation


Figure 20: Poly Re-Oxidation

43

Poly Re-Oxidation


XJ = 75 nm

52.5 nm 52.5 nm

LPOLY = 250 nm

LEFFECTIVE = 180 nm

o Gate Overlap = 52.5 nm – 25 nm = 27.5 nm ≥ 15 – 20 nm requirement

o Process is designed for LPOLY = 0.25 µm and LEFFECTIVE = 0.18 µm

Figure 21: Gate Overlap and LEFFECTIVE Calculation

44

o Shallow junctions implanted after poly re-ox step

o A portion of VDS is dropped across the LDD so a lower effective voltage is across the channel (Eq. 2)

o The advantage of this is reduced hot carrier effects since carriers see lower horizontal electric field

oThe trade-off is there will be a reduction in drive current & switching speed

Low Doped Source/Drain Extensions


P-Well N-Well

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

N+ Poly P+ Poly

Aluminum

TiSi2

P-SSRW N-SSRW

N-Substrate

Nitride Spacers

STI

LDDLDD

Vchannel = VDS – 2*IDS(Rterminal + Rs/d + RLDD)

Figure 22: Low Doped Source/Drain Extensions

Figure 23:Equivalent Circuit

with Parasitic Resistance

(Eq. 2)

45

Low Doped Source/Drain Extensions


NTRS Guidelines Range Target

XJ(LDD) 0.4*Lpoly +/- 25% 75 nm – 125 nm 75 nm RS (LDD) 400 – 850 sq 400 sq ND(LDD) 5.2x1018 – 2.5 x1018 cm-3 5.2x1018 cm-3

o Low end of range is chosen for XJ and RS so if more diffusion occurs then is anticipated, the devices will still operate properly

o The implant energy must be selected to place the peak of the implant at the Silicon surface. With a 300 Å screening oxide layer:

o B11 of 10 keVo P31 of 25 keV

o The Varian 350D is capable of implant energies as low as 10 keV

o In industry, Silicon (Si) or Germanium (Ge) are implanted before the shallow S/D implants to reduce channeling of dopant ions

Table 4: NTRS Guidelines for LDD Scaling [6]

46

Silicon Nitride Sidewall Spacers


P-Well N-Well

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

Aluminum

TiSi2

P-SSRW N-SSRW

N-Substrate

STI

Nitride Spacers

Re-oxidize Poly GateIon Implant LDD

Deposit LPCVD Nitride RIE Nitrde to form Spacers

o Sidewall spacers are formed after the LDD implants to create an offset region where a deeper source/drain contact region can be implanted.

Figure 24: Nitride Sidewall Spacers Figure 25: SEM Micrograph of Nitride Spacer

Figure 26: Sidewall Spacer Process

47

Silicon Nitride Sidewall Spacers


TOTALSLDD LRWR LDD

LDDSR (/sq)

spacerL

(m) 2 spacerTOTAL LL

(m)

W LDDR ( xm)

W

W

SAT

LDD

R

R

400 0.1 0.2 80 1.9% 400 0.2 0.4 160 3.9% 400 0.25 0.5 200 4.9% 400 0.3 0.6 240 5.8%

o In a perfectly anisotropic etch the Lspacer = tpoly = 0.25 µmo Parasitic LDD resistance is controlled by length of sidewall spacer

TDDsat

oxDDSAT

VVv

tVWR

OX

47.0 = 4108 µm VDD = 2.0 V

|VT| = 0.5 VTox = 50 Å

(Eq. 3)

(Eq. 4)

o NTRS Guidelines require < 10% reduction in drive current due to parasitic source/drain extension resistance

o Source/Drain contact resistance must also be taken into account

Table 5: Sidewall Spacer Length Effect on Drive Current [9]

48

Source/Drain Contact


Ion Implant Deep S/D Contacts

N+/P+ Poly Gates Implanted at same time

o Source/Drain contacts implanted after sidewall spacer formation and are self-aligned to the gate

o Contact is doped higher and junction depth deeper to decrease parasitic source/drain resistance

o Silicide thickness must account for < ½ contact junction depth or increased leakage current will result

Figure 27: Source/Drain Contact and Gate Doping

49

Source/Drain Contact


NTRS Guidelines Range Target XJ(Contact) 0.8*LPOLY +/- 33% 134 nm – 266 nm 150 nm ND(Contact) 1x1020 cm-3 RS(Contact) 50 – 75 /sq

o Midpoint of XJ range chosen so XJ-CONTACT ~ 2*XJ-LDD

o The implant energy must be ~ 2x higher then shallow LDD implants:o B11 of 20 - 30 keVo P31 of 40 - 50 keV

o The sheet resistance of this region must be decreased to decrease the reduction in drive current

o The polysilicon gates are doped n+ for NMOS and p+ for PMOS at the same time the contacts are doped.

Table 6: NTRS Guidelines for Source/Drain Contact Scaling [6]

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Dual Doped Poly Gates


'

42

OX

Bas

FB

C

qNVV BT

i

a

B

n

N

q

KTln

o Retrograde profile will be designed to set appropriate Na for the VT

equation in Eq. 5

ox

ox

MSFB

C

QV

o Dual doped poly is used to create surface channel PMOS transistors by engineering a better matched Metal-Semiconductor work function, MS

(Eq. 5)

(Eq. 6)

(Eq. 7)

51

o Gate depletes body to a depth of WDMAX

o Na transitions from 1x1017 cm-3 at surface to 1x1018 cm-3 at the peek

o The peak of each profile must be set such that the effective Na the gate depletes is what is required for |VT| = 0.5 V

o Na(effective) for NMOS =6.75x1017 cm-3

o Na(effective) for PMOS = 6x1017 cm-3

o Lower surface concentration, higher sub-surface channel doping and proper VT are all benefits of using a super steep retrograde well

Dual Doped Poly Gates


Figure 28: Super Steep Retrograde ProfileWith WDMAX [10]

52









53

Rapid Thermal Dopant Activation


o Need to repair damage to Si lattice caused by ion implant

o Electrically activate dopant atoms

o Transient enhanced diffusion will cause dopants to diffuse at accelerated rate and cause deeper then desired junction depths

o Rapid Thermal Processing is used to rapidly heat the wafer for a short amount of time

o Thermal budget for 0.25 µm device is only 2-3 seconds @ 1000°C

Figure 29: Thermal Budget for p+ Junctions

54









55

Titanium Silicide Formation (TiSi2)


P-Well N-Well

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

Aluminum

P-SSRW N-SSRW

N-Substrate

Nitride Spacers

STI

TiSi2

o Want to reduce sheet resistance of source/drain contact regions from 50 – 75 /sq to 4 /sq

o Want high drive current for fast switching speeds

o Titanium Silicide was widely used at the 0.25 µm node and will be used in this process

Figure 30: Titanium Silicide Formation

56



RC RC

Poly Gate

TiSi2

RCHRS RDRs’ RD’

PARASITICCHANNELTOTAL RRR EXTRINSICEXTENSIONPARASITIC RRR

'' DSEXTENSION RRR CDSEXTRINSIC RRRR 2

spacerS LRWRs LDD '

spacerSD LRWR LDD '

LRWRs SILICIDES

LRWR SILICIDESD

29102, cmL

WR C

C

C

Figure 31: Transistor Cross section with Parasitic Resistances [14]

57



W EXTENSIONR ( x m)

W EXTRINSICR ( x m)

W PARASITICR ( x m)

W SATR ( x m)

W

W

SAT

PARASITIC

R

R

200 7 207 4108 5.1 %

o Require < 10% reduction in drive current due to RPARASITIC

o Sample calculation shown in Table #, assume:

o RS-LDD = 400 /sq LSPACER = 0.25 umo RS-Silcide = 4 /sq LSILICIDE = 0.75 um

o All Resistances are calculated for a nominal 1 µm width

o As width is increased, the total resistance components will decrease but the ratio for drive current reduction will remain the same

o Drive current is only reduced by ~5% by integrating silicide

Table 7: Reduction in Drive Current due to Parasitic Resistance [14]

58



Silicide Thin Film Resistivity (Ω-cm)

Sintering Temp (C)

Stable on Si up to (C)

Reaction with Al at (C)

nm of Si consumed

per nm of metal

nm of resulting silicide per nm of metal

TiSi2 (C54) 13-16 700-900 ~900 450 2.27 2.51 TiSi2 (C49) 60-70 500-700 2.27 2.51

o Table 8 shows properties for Titanium Silicide reactions

o 45 nm of Si is consumed by 20 nm of Ti to produce 50 nm of TiSi2 in C49 phase

o The C49 phase is a higher resistivity phase created after a 500- 700°C rapid thermal step

o The unreacted Ti is removed by wet chemistry and a 2nd thermal step is performed at 700-900°C to form lower resitivity C54 phase

o 50 nm of TiSi2 in the C54 phase should yield an Rs ~ 4 /sq

Table 8: Titanium Silicide Properties [14]

59

o Titanium Silicide suffers from a narrow line width effect where Rs

increases as line width is decreased

o This is why the industry transitioned to CoSi2 for sub-0.25 µm CMOS

o Intel reports an RS of 4 /sq for their 0.25 µm CMOS process, although it is not reported if this is for the source/drain regions only, or gate too

o Test structures will be designed on the test chip to observe this effect



Figure 32: Narrow Line Width Effect [9]

60









61

o In a fully scaled 0.25 µm process, contact cut dimensions are 0.25 µm x 0.25 µm

o Since Canon FPA-2000i1 stepper will be used, the smallest contact cut dimensions will be 0.5 µm x 0.5 µm

o Contact cuts below 2 µm x 2 µm must be dry etched since wet chemistry acid will not go into small holes

o Some devices will be designed with the smallest contact cuts that must be plasma etched, while other devices will be designed with larger contact cuts (2 µm or 5 µm) that can be wet etched

o Loading is a fabrication phenomena where features with small areas will take longer to clear then large areas.

o It is desirable to have all contact cuts for a given design generation to have the same area so that over-etch of smaller contacts will not destroy regions with large areas that clear earlier

Contact Cut Etch


62









63

Aluminum Metallization


P-Well N-Well

P+ WellContact

N+ WellContact

N+ S/D P+ S/D

LDD LDD

N+ Poly P+ Poly

TiSi2

P-SSRW N-SSRW

N-Substrate

Nitride Spacers

STI

Aluminum

o Multi level metal is necessary to build complex logic circuits that require extensive routing while minimizing real estate

o PECVD TEOS will be deposited as inter-level dielectric layero Aluminum will be sputter deposited to a thickness ~ 0.5 µm, then patterned and etched by RIE in Chlorine chemistryo A 2nd PECVD TEOS layer will be deposited to insulate Metal 1 from Metal 2, this layer may undergo CMP to reduce topographyo Vias will be patterned and etched by RIE in Fluorine plasmao Metal 2 will be sputter deposited to thickness ~ 1.0 µm, then patterned and etched similarly to Metal 1

Figure 33: 2 Level Aluminum Metallization

64

Outline



65

Layout of Test Chip


Number Design Layer Number Lithography Level Number Mask Level

1 Active 1 STI 1 STI 2 n-well 2 n-well 2 n-well 3 Poly 3 p-well 3 p-well 4 N+ select 4 n-SSRW - Re-use n-well 5 P+ select 5 p-SSRW - Re-use p-well 6 Contact cut 6 Poly 4 Poly 7 Metal 1 7 n-LDD 5 n-LDD select 8 Via 8 p-LDD 6 p-LDD select 9 Metal 2 9 n+-S/D - Re-use n-LDD select

10 p+-S/D - Re-use p-LDD select 11 Contact cut 7 Contact cut 12 Metal 1 8 Metal 1 13 Via 9 Via 14 Metal 2 10 Metal 2

o A new test chip will be designed and mask set fabricatedo There are 9 design layers which will be used to create 10 photo maskso These 10 photo masks will be used for 14 lithography levelso In addition to transistors, logic circuits will be designed, as well as capacitors for CV analysis, Van-der-pauw test structures for sheet resistance measurements and Cross-Bridge Kelvin Resistor test structures for measurement of contact resistances

Table 9: Test Chip Design Layers

66

Outline



67

Integration/Fabrication/Test


o Unit processes will be integrated into a full CMOS manufacturing flow

o All fabrication will be done in the Semiconductor and Microsystems Fabrication Laboratory (SMFL) at RIT

o When fabrication is completed, the devices will be tested in the Semiconductor Device Characterization lab at RIT

o On and off-state performance will be characterized to qualify this process

o Electrical parameter extraction will be performed to develop SPICE models for this process which can be used in future circuit designs

o The fabrication limits of the SMFL tool set will be pushed so that custom design rules can be created for future layouts

68

Outline



69

Time Line


Spring 2006Spring 2005 Summer 2005 Fall 2005 Winter 2005

Simulation

Process Development

Layout

Fabrication

1

2

3

ID Task Name

5

6

4

Test

Thesis Writing

o This time line constitutes a reasonable plan of study to design, fabricate and test 0.25 µm CMOS transistors

o Ample time is left for thesis writing, review, and defense

Figure 34: Masters Thesis Time Line

70

Outline



71

References


72

[1] M. Aquilino, “Advancing RIT to Submicron Technology: Design and Fabrication of 0.5 μm NMOS Transistors,” RIT Microelectronic Research Journal, 2004. [2] G. E. Moore, “Cramming more components onto integrated circuits”, Electronics, vol. 38, pp. 114-117, 1965. [3] “Microprocessor Quick Reference Guide.” http://www.intel.com/pressroom/kits/quickreffam.htm [4] Y. Tsividis. Operation and Modeling of The MOS Transistor, 2nd Edition. Oxford University Press, 1999. [5] S. E.Thompson, P. A.Packan, and M. T.Bohr, “Linear versus saturated drive current: Tradeoffs in super steep retrograde well engineering,” Symposium on VLSI Technology Digest, pp. 154-155, 1996. [6] L. Wilson, ed., “The National Technology Roadmap for Semiconductors: 1997 Edition”, Semiconductor Industry Association, San Jose, California [7] De, I.; Osburn, C.M., “Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices,” IEEE Trans. Electron Devices, vol. 46, Issue: 8, pp.1711 - 1717, Aug. 1999 [8] R.C. Jaeger. Introduction to Microelectronic Fabrication, 2nd Edition. Prentice Hall, 2002. [9] S. Wolf. Silicon Processing for the VLSI Era. Volume 4-Deep Submicron Process Technology. Lattice Press, 2002 [10] Q. Xu, “The investigation of key technologies for sub-0.1 μm CMOS device fabrication,” IEEE Trans. Electron Devices, vol. 48, pp. 1412-1420, July 2001. [11] S. Thompson, P. Packan, M. Bohr, “MOS Scaling: Transistor Challenges for the 21st Century”, Intel Technology Journal, 1998. [12] A. Brand, A. Haranahalli, N. Hsieh, Y.C. Lin, G. Sery, N. Stenton, B.J. Woo, S. Ahmed, M. Bohr, S. Thompson, S. Yang, “Intel’s 0.25 Micron, 2.0 Volts Logic Process Technology”, Intel Technology Journal, 1998. [13] “MOSIS SCMOS Technology Codes and Layer Maps SCNA and SCNE”, http://www.mosis.org/Technical/Layermaps/lm-scmos_scna.html [14] http://www.stanford.edu/class/ee311/NOTES/Silicides.pdf

Documents

Michael Aquilino Microelectronic Engineering Department Rochester Institute of Technology