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DESIGN AND CONSTRUCTION OF A MICRO-
PROCESSOR CONTROLLED MOVING MESSAGE
DISPLAY SYSTEM
BY
BABALOLA ADEWALE
MATRIC NUMBER: 94616
A PROJECT REPORT SUBMITTED TO THE DEPARTMENT OF ELECTRICAL
AND ELECTRONIC ENGINEERING, FACULTY OF TECHNOLOGY,
UNIVERSITY OF IBADAN, IN PARTIAL FULFILMENT OF THE
REQUIREMENT FOR THE AWARD OF BACHELOR OF SCIENCE DEGREE IN
ELECTRICAL AND ELECTRONIC ENGINEERING OF THE UNIVERSITY OF
IBADAN.
MARCH, 2004
2
CERTIFICATION
This is to certify that the project which this report is based upon was written by
BABALOLA ADEWALE in the department of Electrical and Electronic Engineering,
Faculty of Technology, University of Ibadan, Ibadan, Nigeria.
PROJECT SUPERVISOR: MR. E. O. AKINPELU
Signature with date: ………………………………………………………..
HEAD OF DEPARTMENT: DR. A. OLATUNBOSUN
Signature with date: ……………………………………………………….
3
DEDICATION
This work is dedicated to my parents, for fighting my battles alongside theirs.
4
ACKNOWLEDGEMENT
Mention must be made of those who, by dint of selfless acts, have made my life and study
in the university worth-while. My heartfelt gratitude goes to my parents and siblings, for
the support and love they supplied.
I wish to use this opportunity to appreciate the members of staff of the department of
Electrical and Electronic Engineering, University of Ibadan, particularly my project
supervisor for imparting knowledge of lasting value.
My gratitude also flows to Lekan Faola, Ayo Ajayi, Oshunubi Gbolahan, Wole Falade,
Ego Ogbu, Doyun Adebowale, Shina Kadri, Niyi Awe, Uche Okafor, Yinka Odeneye,
Tunji Oyelakin, Dupe Sanda, Patrick, Akin Akinkunmi, Austin Ogunshakin and Ade
Adenle – I owe you all more than I can possibly pay back.
Ultimately, He who sustains everything by the Word of His Power is worthy of all glory,
honor and praise.
5
ABSTRACT
The design and construction of a programmable microprocessor controlled message
display system is presented. The message display system is interactive such that it is able
to dynamically accept inputs and thereafter display the input until a new input is made.
The inputs consist of alphabets A-Z and numbers 0-9. The microcomputer framework is
used – the system consists of a microprocessor, an input module, an output module and a
memory module.
The microprocessor has complete control over the system as all interrupts are disabled.
The microprocessor maintains an image of the LED matrix display system in the RAM.
Based on manipulation of bit positions in this portion of memory, an output is seen which
gives the effect of alphabets streaming across the LED display system.
Each symbol is represented by a 7x8 array of LED. Bits in this array are either ON or OFF
to achieve the appearance of the desired symbol. The ROM holds the complete bit-
mappings necessary to display any alphabet on the keyboard.
The design, upon implementation, displayed messages scrolling from right to left at a
speed which makes it possible to read the message while allowing more characters to
stream across the matrix display.
6
TABLE OF CONTENTS
PAGE
Title Page i
Certification ii
Dedication iii
Acknowledgement iv
Abstract v
Table of Contents vi
List of Figures viii
List of Tables xi
CHAPTER ONE
1.0 Introduction 11
CHAPTER TWO: SYSTEM DESCRIPTION
2.1 Introduction 15
2.2 Display Unit 15
2.2.1 Light Emitting Diode (LED) 16
2.2.2 Matrix Display 18
2.3 Memory Devices 18
2.3.1 Read Only Memory 20
2.3.2 Random Access Memory 23
2.4 Latch 25
2.5 Decoder 28
7
2.6 Buffer 30
2.7 Input Unit 32
2.7.1 Multiplexer 32
2.8 Microprocessor (Z80) 34
2.8.1 Data Flow within Z80 35
2.8.2 Interfacing Z80 38
CHAPTER THREE: SYSTEM DESIGN
3.1 Introduction 44
3.2 Input module 44
3.2.1 Address Mapping of Buttons 48
3.2.2 Operation 49
3.3 Power Module 50
3.4 Memory Module 51
3.5 Display Module 57
3.6 Integration Of Modules 60
3.6.1 Control, Timing and Addressing 61
3.6.2 Construction 69
8
Page
CHAPTER FOUR: TEST
4 Test, Results And Observations 71
4.1 Problems Encountered 76
CHAPTER FIVE
5.1 Conclusion 77
5.2 Recommendations 78
APPENDICES
Appendix A Program Codes 80
Appendix B System Circuit Layout 82
Appendix C Cost Analysis 83
REFERENCES 85
9
List of Figure
Page
2.1 Circuit symbol of an LED 16
2.2 LED Matrix 19
2.3 Logic symbol of 2732 EPROM 22
2.4 Pin configuration of 74LS374 26
2.5 Functional diagram of 74LS374 27
2.6 Logic Symbol of 74LS 138 29
2.7 Logic Diagram 74LS138 30
2.8 (a) Pin configuration of 74LS244 31
(b) Logic Diagram of LS 244 31
2.9 Connection diagram of a buffer 33
2.10 Internal structure of a Z80 36
2.11 Z80 Pin configuration 41
3.1 Modular Representation of a microprocessor controlled moving
message display system. 45
3.2 Key board outlay 46
3.3 Functional diagram of Keyboard 48
3.4 Power supply scheme 50
3.5 Power supply circuit. 52
3.6 Logic symbol of memory devices 53
10
3.7 Circuit diagram of a row of LEDs in the 48 x7 MED Matrix 58
3.8 Circuit diagram of a column of LEDs in the 48 x7 LED matrix 59
3.9 Program flowchart 63
3.10 Flow of control between subroutines 66
4.1 A snapshot of the main board housing the microprocessor, the memory
module and part of the display module 72
4.2 A snapshot showing the power module and the interface of the input 72
module (a parallel port).
4.3 A snapshot of the LED matrix display (rear view) 73
4.4 A snap shot illustrating the interface between the input module and the
system (note that the input module is detachable) 74
4.5 A snapshot of the 30-key keyboard (the cover was removed to
reveal the circuit). 74
4.6 A snapshot showing the display system being programmed. 75
11
List of Tables
Page
2.1 2732 Operating Mode 23
2.2 HM 6116 Operation mode 24
2.3 74 5374 Operating mode 26
2.4 Functional Representation of 74LS 138 29
2.5 Functional table of Buffer. 32
2.6 Function Table of a multiplexer
3.1 Address mapping of buttons on keyboard. 40
3.2 Memory mapping 54
3.3 Address range of memory devices 54
3.4 Codes of Alphanumeric characters to be display 56
3.5 Matrix display image in memory 57
12
CHAPTER ONE
INTRODUCTION
1.1 Introduction
Originally borne from the need to replace wooden hymn boards in Orthodox Churches
with an appropriate digital equivalent, this project has evolved into a message display
system that can function in other institutions apart from churches.
Message display systems are common sights in high-brow shops, restaurants, air-port
lobbies, and even banks. Employing lighting devices (such as Neon bulbs and Light
Emitting Diodes) arranged in specific patterns, alphanumeric signs and symbols are
illuminated against a dark background. The objective is to convey information. Here are
some other examples of where they are being utilized.
Bi-color LEDs used in programmable message boards
Roadside vehicle speed display
Brake lights on automobiles
City buses, which have brake and tail lights as well as turn signals
Some traffic signals
New railroad crossing flashers
Exit sign
Parking information signs
Construction sign traffic arrows
13
The pattern of arrangement of the lighting device and even the choice of lighting device
employed has changed over the years. Neon and incandescent filaments, arranged to fit
signs and symbols were once display devices of choice. This has obvious draw-backs.
Apart from the fact that the circuit has to be re-arranged in order to change the information
being displayed, the electrical power consumption of this arrangement is rather on the high
side. Devices such as Liquid Crystal Display (LCD) are also used in message display
systems. These devices have an obvious merit – they are low power consuming lighting
devices.
Liquid Crystal Displays (LCD) feature prominently in everyday devices like watches,
clocks, calculator and majority of hand-held devices. However, the visibility of displays
provided by LCDs is dependent on the ambient light; the crystal does not produce any
light itself. This is unlike the Light Emitting Diode (LED) which lights up when a positive
voltage is connected to its anode and the cathode is grounded.
Generally, the pattern of arrangement and the choice of lighting devices are governed by
considerations on producing a message display system which consumes as little power as
possible, is reliable and also affordable.
In addition to the above considerations, this project set out to ensure that the display
system is programmable. This is to ensure that information being displayed can be
changed at will. In the “Design and Construction of a Moving Message System” by Ukoh
Henry (Project Report, 2002), only a single message can be displayed. To change this
message, the Erasable Programmable Read Only Memory (EPROM) used has to be
14
removed from the circuit and reprogrammed. This cumbersome arrangement leaves much
to be desired.
To achieve programmability, a microprocessor forms the core of the design; it moves,
sorts and manipulates data within the system. Although a number of low-ended micro-
processors are available, the choice of Z80 was informed by availability and the ease with
which it can be programmed.
In the chapters that follow the devices employed and the process involved in implementing
a micro-processor controlled device are presented. Chapter two, from a theoretical
perspective, analyzes the various components of the system with a view to laying a proper
foundation for a discussion on how the components were integrated to form the system.
This discussion forms the basis of chapter three. Additionally, chapter three considers the
driver of the system – the program which dictates the operation of the microprocessor. A
trade-off was made between hardware and software, thus the software virtually controls
the system.
Chapter Four presents tests and procedures carried out to ensure that the design and
implementation are fault – free and discusses difficulties encountered in the course of
design and implementation. Chapter Five summarily reviews the project, citing areas for
research and improvement.
15
CHAPTER TWO
SYSTEM DESCRIPTION
2.1 Introduction
As mentioned in Chapter One, the central objective of this project is to design and
construct a moving message display system which
• is reliable and cheap
• consumes as little electrical power as possible
• is programmable such that the information being displayed can be changed at will
To this end, components used in the system were chosen based on affordability,
availability and reliability.
2.2 Display Unit
The display system will function at any time of the day, thus the fonts are required to be
large and properly illuminated. To achieve this, LEDs which are red when conducting are
employed. The LEDS are screened by a dark shield of opaque glass material which, apart
from shielding the LED from adverse environmental factors (like weather conditions and
human factors), also accentuate the effect of the glowing LED, making the display
16
readable from a farther distance. To design a suitable LED matrix, we need to understand
the basic operating principles of the required components.
2.2.1 Light Emitting Diode (LED)
A light emitting diode (LED) is a semiconductor p-n junction that gives off visible light
when it is energized. In any forward biased p-n junction, there is, within the structure and
primarily close to the junction, a recombination of holes and electrons. This recombination
requires that the energy possessed by the unbound free electron be transferred to another
state. Some of this energy is given off as heat, and some as photons.
An LED is optimized to release light of approximately the band gap energy under forward
bias, when electrons fall from the conduction band to the valence band. The electrons and
holes migrate toward the junction where they recombine and release light whose energy
corresponds to the band gap energy. Since the LED is a p-n junction device, it has forward
characteristics similar to diode response curve. Its forward bias voltage ranges between
2.2V – 3.0V with an average forward current of 20mA. Operating and storage temperature
of LEDs range between -55oC -100oC. Figure 2.1 illustrates the circuit symbol of an LED.
Fig 2.1 Circuit symbol of a LED
17
Uses and Capabilities of LEDs
LEDs are currently being used in various ways. One reason to use LEDs is that they last
longer, and they are brighter, and are more efficient than incandescent lights [5]. LEDs are
also extremely tough. This characteristic is a result of having no glass to shatter and no
filament to break. Therefore, the new LED lights are shockproof and more robust than
incandescent lights. Extremely efficient, the LED lamps use as little as ten percent of the
electricity that an incandescent light uses. Consequently, if a light is battery-operated, an
LED design requires far less battery power. Incandescent light bulbs burn out after about
25-100 hours of use, while LEDs have life spans of 100,000 hours; this is over 11 years of
continuous use. The trait of efficiency goes hand in hand with being environmentally
friendly. As a result of the LED’s efficiency, LEDs do not waste as much electricity nor
require large supplies of batteries. They can also be solar-powered.
In addition to these reasons, LEDs are safer and more reliable. LEDs are excellent for use
near explosive gases and liquids, since they can withstand large shocks and vibrations and
operate at a low temperature. Due to their low failure rate, they reduce liability, especially
in areas where a failed light could cause an accident. Many electronic message display
system are used to warn people or to permit people to work at night under safe conditions
thus, light failure can result in substantial cost if it leads to an accident or lost labor.
Therefore, LEDs with characteristics such as low power consumption, long lifetimes,
brightness, and safety are increasingly being used everywhere.
18
2.2.2 Matrix Display
A matrix consists of an array of elements capable of being individually addressed.
Principally, a matrix display finds it use in the fact that the array of LEDs can be
individually addressed. Thus, a combination of LEDs within the matrix can be used to
produce any form of alphanumeric sign and symbol.
The elements of a matrix have a grid structure with an X-Y (2-dimensional pattern)
arrangement. As illustrated in figure 2.2, each LED has one of its two electrode connected
to a row and the other connected to a column. With this arrangement, it is possible to
select any LED by sending energizing a right combination of row and column.
2.3 Memory Devices
In digital systems, memory is a device or an electrical circuit into which information can
be stored, accessed, and retrieved. The unit of memory is the memory cell. A memory cell
could be a flip-flop, a charged capacitor or a spot on a magnetic tape or disk. These cells
store binary logic levels (1s or 0s) in an array structure. The size of each binary word (the
number of bits) depends on the memory device. These binary values are referred to as
data. The location in the memory device where any data value is stored is identified by
another binary number referred to as an address. Thus, each memory location has a unique
address.
19
7 ROWS OF 16 LEDS
16
COLUMNS
OF
7LEDS
20
Figure 2.2 LED Matrix.
All memory devices operate in the same general way. To write data into memory, the
address to be accessed is placed on the address input, the data value to be stored is applied
to the data inputs, and the control signals are manipulated to store the data. To read from
the memory device, the address is applied, the control signals are manipulated and the data
values appear on the output line.
Memories may be classified based on ways of accessing data stored in memory and what
can be done to modify data stored in memory. Such categorization differentiates between
the Read-Only-Memory (ROM) and the Random-Access-Memory (RAM) both of which
are employed in this project.
The ROM is used to store the program which the microprocessor (Z80) executes while the
RAM is used to store data during operation of the display system. Both storage devices are
considered in detail.
2.3.1 Read-Only-Memory (ROM)
ROMs are a broad class of non-volatile semiconductor memories designed for applications
where the ratio of read operations to write operations is very, very high. Technically, a
Rom can be written into (programmed) only once. Thereafter, information can only be
read from the memory. The design of this project makes use of a Read-Mostly-Memory
(RMM), a type of ROM which can be written to more than once but the write operation is
much more complicated than the read operation. The different types of electronic ROM
21
include Programmable ROM (PROM), Erasable Programmable ROM (EPROM) and
Electrically Erasable PROM (EEPROM).
An EPROM can be programmed, erased and reprogrammed as often as desired thus
making it an RMM. Once programmed, the EPROM is non-volatile, that is, it will retain
the stored programmed indefinitely. The process for programming an EPROM involves
the application of special voltage levels (typically between 10V-25V) to the appropriate
chip inputs for the specified amount of time (typically 50ns per address location. The
programming process was carried out by a special circuit that is separate from the circuit
in which EPROM is used.
Once an EPROM cell is programmed, it can be erased by exposing it to ultra-violet (UV)
radiation applied through a window o the chip package. This is very important as mistakes
made while programming can easily be erased and it is really one of the reasons why the
EPROM was chosen as the ROM type to use.
The UV light erases all cells at the same time, thus there is no way for selective erasure.
This erasing process usually requires 10 to 15 minutes of exposure to UV rays.
EPROMS are available in a wide range of capacities and access time; devices with a
capacity of 512k X 8 and an access time of 45ns are common place. The 2732, a 4K X 8
NMOS EPROM that operates from a single +5V power source during normal operation is
used in the display system being considered. The logic symbol for 2732 is illustrated in
figure 2.3.
22
The 2732 allows eleven (12) address line, A0 – A11 and eight (8) data lines D0 – D7. It has
two control inputs CE and OE/Vpp which are both active low. OE/Vpp is a dual purpose
input whose function would depend on the device operating mode. OE is the output enable
and is used to control the device’s buffer so that the device can be connected to the
microprocessor’s data bus without contention. Vpp is the special programming voltage
required during the programming process. CE is chip enable, active low input which is
used to place the device in a standby mode where its power consumption is reduced.
2732
D0
D1
D2
D3
D4
D5
D6
D7
A0
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A1
CE
OE
Figure 2.3 Logic symbol for 2732 EPROM. (Pg 693, TOCCI)
23
The 2732 DIP package has a characteristic window which allows the internal circuitry to
UV light when the complete memory contents are to be erased. A sticker is placed on the
window after erasure and reprogramming to prevent accidental erasure by ambient light.
The 2732 has several operating modes presented in table 2.1
Table 2.1 2732 Operating Modes. INPUTS
Mode CE OE/Vpp Outputs
READ/VERIFY VIL VIL DATAOUT
Output DISABLE VIL VIH High IMPEDANCE
STANDBY VIL X High IMPEDANCE
PROGRAM VIL Vpp DATAIN
Note: VIL = TTL low; VIH = TTL high; X = don’t care; Vpp = nominal 21V
2.3.2 Random-Access Memory (RAM)
RAM is used by micro-processors for temporary storage of programs (instruction codes)
and data. The contents of many RAM locations are read from and also written to as the
microprocessor executes the program. This requires fast read and write cycle times so as
not to slow down the computer. A major characteristic of RAM is that it is volatile and
24
will lose all stored information if power is interrupted or turned off. But for these major
differences, the RAM and ROM are identical.
As with the ROM, the RAM consists of a number of registers each storing a single data
word and each having a unique address. There are a number of RAM types - Static RAM,
Dynamic RAM and so on. Static RAMs can store data as long as power is applied to the
chips. Its memory cells are essentially flip-flops which will stay in a given state (1 or 0)
indefinitely provided power to the circuit is not interrupted.
HM6116 is a 2K X 8 RAM with 11 address lines and 8 data lines. It has four (4) control
pins, CS (Chip select), OE (Output enable), RD (Read), and WR (Write). All these control
lines are active low except RD. The mode of operation of HM6116 is presented in Table
2.2.
Table 2.2 HM6116 Operation Modes
INPUT Operational Mode
OE CS RD/WR
OUTPUT
WRITE VIL VIL VIL DATAIN READ VIL VIL VIH DATAOUT STANDBY VIL VIH X HIGH IMPEDANCE OUTPUT DISABLE
VIH VIL X HIGH IMPEDANCE
25
2.4 LATCH
In designing the display system, it was necessary to delay the transfer of data from the
microprocessor to the display system. To achieve this, an eight bit parallel in/parallel out
register containing eight edge triggered D flip-flops whose output are connected to a
tristate non-inverting buffer are used and this are contained in an IC package 74LS374
These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving
highly-capacitive or relatively low-impedance loads. The high-impedance state and
increased high-logic level drive provide these registers with the capability of being
connected directly to and driving the bus lines in a bus-organized system without need for
interface or pull-up components.
The eight latches of the 74LS374 are transparent D-type latches; this implies that while
the enable (G) is high the Q outputs will follow the data (D) inputs. When the enable is
taken low the output will be latched at the level of the data that was set up. On the positive
transition of the clock, the Q outputs will be set to the logic states that were set up at the D
inputs as shown in Table 2.3. A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state the outputs neither load nor drive the bus lines
significantly. The output control does not affect the internal operation of the latches or
flip-flops. That is, the old data is retained and new data can be entered even while the
outputs are off.
26
This register can be connected to common bus lines along with the outputs from other
similar devices to allow efficient transfer of data over the bus. Figures 2.4 and 2.5
illustrate the pin-out configuration and functional diagram of 74LS374.
Figure 2.4 Pin Configuration of LS374
Table2.3 74LS374 operating modes Output Control Clock D Output L ^ H H L ^ L L L L X QO H X X High Impedance
27
(a)
(b)
Figure 2.5 Functional diagram of LS374
28
2.5 DECODER
A decoder is a logic circuit that accepts a set of inputs that represent a binary number and
activates only the output corresponding to the input number. In other words, a decoder
circuit looks at its inputs, looks at the binary numbers present there and activates the one
output that corresponds to that number [3]. This action may also be described as a De-
multiplexing action. This characteristic of the decoder is employed in the input and output
module of the message display system. Chapter three elaborates on this.
74LS138 is the part number of a 3 line-to-8 line decoder because it has three inputs and
eight output lines. The LS138 is a high speed 1-of-8 Decoder/De-multiplexer fabricated
with the low power Schottky barrier diode process. The logic symbol and diagram are
illustrated in figures 2.4 and 2.5 respectively. The decoder accepts three binary weighted
inputs (A0, A1, A2) and when enabled provides eight mutually exclusive active LOW
Outputs (O0–O7). The relationship between the input, enable and output pins is presented
in Table 2.5. The LS138 features three Enable inputs, two active LOW (E1, E2) and one
active HIGH (E3). All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5
lines to 32 lines) decoder with just four LS138s and one inverter. The LS138 can be used
as an 8-output de-multiplexer by using one of the active LOW Enable inputs as the data
input and the other Enable inputs as strobes. The Enable inputs which are not used are
permanently tied to their appropriate active HIGH or active LOW state.
29
Figure 2.6 74LS138 Logic symbol
Table 2.4 Function table of 74LS138
Inputs Enable Select
Output
G1 G2 (Note1) C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X L H H H H H H H H
H X L L L L L L L L
X X L L L L H H H H
X X L L H H L L H H
X X L H L H L H L H
H H L H H H H H H H
H H H L H H H H H H
H H H H L H H H H H
H H H H H L H H H H
H H H H H H L H H H
H H H H H H H L H H
H H H H H H H H L H
H H H H H H H H H L
30
Figure 2.7 74LS138 Logic Diagram
2.6 BUFFER
A buffer is a logic circuit which is designed to have a greater output current and/or voltage
capability than an ordinary logic circuit. In a microcomputer, a buffer is needed in a
situation that a microprocessor’s bus (either data or address bus) is driving loads (IC
chips) whose overall current demand is higher than what the bus can service.
The LED matrix display is a heavy current load which has a total of seven (7) latches
(74LS374) gated to the data bus. The data bus needs to be buffered to drive this load.
Buffering requirements the data bus requires that
• The buffer is non-inverting
• The buffer produces all the output drive capacity needed by the system.
• The buffer does not have input loading in excess of the drive capacity of the data
bus.
31
Although a data bus buffer is also required to be bi-directional, this property is not
required here because the buffer is needed for the output module alone.
IC package 74LS244 is a high-speed Si-gate TTL device. It is an octal non-inverting
buffer/line driver with 3-state outputs as presented in Table 2.5. The 3-state outputs are
controlled by the output- enable inputs 1OE and 2OE. A HIGH on any of the two OE pins
causes the outputs to assume a high-impedance OFF state. Figure 2.8 illustrates the pin
configuration and logic diagram of the buffer.
(a) (b)
Figure 2.8 (a) Pin Configuration and (b) Logic diagram of 74LS244
32
Table 2.5 Function diagram of a buffer INPUT OUTPUT nOE nAn nYn L L L L H H H X Z Note: H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF state.
2.7INPUT UNIT
The input is essentially an array of keys which map into alphabets A – Z, numbers 0 – 9,
and a few control keys. Since it is an array, each key is uniquely identified by the row and
column on which it belongs. In identifying the individual keys, a multiplexer is used.
Therefore, it is essential to understand the basic operation of a multiplexer.
2.7.1 Multiplexer
Multiplexing is the process of selecting one of several input data sources and transmitting
the selected data to a single output source. Thus, a multiplexer is a logic circuit that,
depending on the status of selected inputs, will channel one of data input to the single
output. Table 2.5 presents the function table while figure 2.9 illustrates the connection
diagram
33
Table 2.6 Function Table of a multiplexer
Inputs Output
E C B A Y W H L L L L L L L L
X L L L L H H H H
X L L H H L L H H
X L H L H L H L H
L D0 D1 D2 D3 D4 D5 D6 D7
H D0 D1 D2 D3 D4 D5 D6 D7
NOTE: H = HIGH Level; L = LOW Level; X = Don't Care; D0, D1...D7 = the level of the respective D input; D0, D1...D7 = inverted D.
Figure 2.9 Connection diagram of a buffer
34
2.8 THE MICRPROCESSOR
In order to ensure that any desired message can be displayed, there is a need to have a
display system capable of accepting input and producing an output based on the input.
Essentially, we need a microcomputer. The functional components of a microcomputer are
an input unit, a storage unit, a microprocessor and an output unit.
The microprocessor is responsible for timing; control and addressing of peripherals;
movement and manipulation of data. The Zilog Z80 is an 8-bit MOS microprocessor.
Sixteen tri-statable output-only address lines, A0-A15, provide access to 65,536 addresses,
each containing one 8-bit byte. Eight tristated, bi-directional data lines D0-D7, provide
paths for 8-bit data into or out of the device. Control functions are provided by eight native
output lines (/M1, /MREQ, /IORQ, /RD, /WR, /RFSH, /HALT, and /BUSAK) and four
native input lines (/WAIT, /INT, /NMI, and /BUSRQ) which can handle dynamic RAM
refresh, interrupts, a Halt mode, and DMA. The device requires one single-phase clock
and a single +5 volt supply. The functional units of the Z80 include two complete sets of
registers similar to the Intel 8085. The "Main Register Set" contains the A, B, C, D, E, H,
L, and a flags register, which exactly match the 8085 in size and use. In addition, an
"Alternate Register Set" is provided, which contains the registers A’, B’, C’, D’, E’, H’,
L’, and F’. The device can switch between the two sets under program control. In addition,
other non-8080 related registers are included, such as two Index registers, IX and IY, an
Interrupt Vector register, I, and a Memory Refresh register, R. Lastly, the Program
Counter (PC) and the Stack Pointer (SP) are retained. The Z80 features three different
interrupt structures, one of which exactly matches the 8085, and two more which are
35
unique to the Z80. The device supports 158 instructions, including the 78 of the 8080/5 as
a subset. Provision is made for DMA via the Bus Request and Bus Acknowledge lines.
The device is available in four speeds: The Z80 at 2.5MHz, the Z80A at 4Mhz, the Z80B
at 6 MHz, and the Z80H at 8MHz. The electrical interfacing is rather similar to that of the
8085 in its approach, although by no means electrically compatible. Zilog manufactures
several peripheral interface devices to ease implementation of a wide variety of designs.
2.8.1 DATA FLOW
An internal data bus interfaces between the ALU, the Data Bus Interface, the Instruction
Register, and a Register Array. The ALU accepts or provides data during math and logical
instructions. The Data Bus Interface communicates with the outside world via a bi-
directional buffer/latch circuit, the instruction register accepts the instruction byte during
M1 to determine what the action to be accomplished is, and the Register Array contains
two sets of eight-bit registers, plus several 16-bit registers. The Data Bus is straight
forward in its use. The Register Array and Instruction Register require further explanation.
The Instruction Register accepts bytes from the internal data bus during the first machine
cycle. It is stored here for the remainder of the instruction execution.
The bit pattern in the Instruction Register is fed to the Instruction Decoder. This decoder
interprets the bits to cause the execution of the instruction under control of the
Timing/Control unit. This unit receives clock pulses from the outside oscillator, and
provides such timing signals as are required to drive the execution of the instructions. It is
interesting to note that the Z80 is a "discrete logic’’ machine. This means that separate
36
circuits have been included inside the device to execute individual types of instructions. If
a specific circuit is used only for a select few instructions or parts of instructions, those
circuits will lie idle until the specific instructions using them are found in a program.
The Register Array communicates with the internal data bus on one side, and with the
Address Logic and Buffers on the other. This addressing circuitry can accept 16-bit groups
from the registers such as PC (Program Counter) and SP (Stack Pointer), and forward
them to the address bus with tristate latches.
8-bit data bus
16-bit address bus
Figure 2.10 Internal structure of the Z80 microprocessor
Accumulator
Temporary register
ALU
Register array
Incrementer/ Decrementer
Address bus buffer
Internal Data Bus
Instruction Decode and CPU timing And Control
Instructi-on Regiter
Data bus Buffers
37
The registers, therefore, act as both creator and storage for addresses required as the
program continues. The Z80 has several ways to generate addresses, including stack
operation and indexing. The Register Array contains the following items:
GENERAL PURPOSE REGISTERS: The Z80 contains two sets of general purpose,
program-accessible, registers. The first set matches those of the 8085, including the A, B,
C, D, E, H, and L registers each eight bits wide. Most of these may be grouped in pairs for
16 bit capabilities; B and C become the BC register pair, D and E become the DE register
pair, and H and L become the HL register pair. Again, the 8085 compatibility is
maintained. An additional register is included which takes the five discrete flip-flops used
to store the 8085’s condition flags and groups them together as a complete byte. This is
called the F register, and is usually treated as a unit with the A register
PC and SP: The Register Array contains both a Program Counter (PC) and a Stack
Pointer (SP), which contain 16-bit addresses for normal and stack operations. The PC’s
contents are applied to the address bus at the start of every machine cycle that needs an
instruction byte, and are automatically incremented by one immediately thereafter. If a
Branch type of OP code is encountered, the incremented contents of the PC are simply
discarded by the new branch-to address. The SP’s contents may be loaded onto the address
bus if a Push, Pop, Call, or Return OP code is encountered. Both the PC and SP in the
Z80 operate identically to those of the 8080/5.
MEMORY REFRESH REGISTER: The Memory Refresh Register provides a built-in
technique for refreshing dynamic RAMs during the time that the Z80 would not need
38
access to the memory system. The refresh must occur every so often, and must be
interleaved with the actions of the processor, or must shut the processor off occasionally to
perform this function. If the microprocessor can indicate when it doesn’t need the RAM,
the RAM subsystem can perform a "hidden refresh", that is, refresh when the
microprocessor is not interested. This register forms a seven bit counter whose contents
are placed on the lower byte of the address bus during the end of the M1 cycle. The Z80
would be analyzing the OP code just received at this time and therefore off the bus.
2.8.2 INTERFACING THE Z80
A brief description of the signals between the Z80 and the outside world follows using
figure 2.10.
ADDRESS LINES A0 - A15: These sixteen tristated lines are outbound-only. They
provide a 16-bit pattern which identifies one unique byte within the processor’s address
space during a read or a write operation to memory. In I/O operations, the lower eight
address lines A0 - A7 identify one of 256 I/O port addresses.
DATA LINES D0 - D7: These eight bi-directional lines accept or transmit one 8-bit data
byte at a time during memory or I/O reads or writes. They may be tristated when the
processor has no immediate data needs.
39
MACHINE CYCLE ONE (/M1): This low-active line indicates that the machine cycle in
progress is dedicated to fetching an instruction part. Certain Z80 instructions require two
bytes to fully specify the Operation Code.
MEMORY REQUEST (/MREQ): This low-active line indicates that the address lines A0-
A15 currently hold a valid memory address for a read or write operation. It is tristated
when any non-memory operation is in progress. This is the main timing signal to activate
transmission to the data bus.
INPUT/OUTPUT REQUEST (I/ORQ): This low-active line indicates that the lower
address byte A0-A7 contains a valid I/O device address for an I/O read or write operation.
It is tristated during any other condition.
READ (/RD): This low-active signal indicates the time at which the processor expects the
memory sub-system or I/O device previously addressed to place the inbound data onto the
data bus. It is tristated otherwise.
WRITE (/WR): This low-active signal indicates that time at which the processor expects
the memory sub-system or I/O device previously addressed to accept the data on the data
bus just placed there by the processor. The data is not considered valid at any other time.
The line is tristated otherwise.
REFRESH (/RFSH): This low-active signal indicates that the lower seven bits of the
address bus (A0-A6) contain a valid refresh address, and that the accompanying /MREQ
should be used to do a RAS-only refresh on all attached dynamic memories.
40
HALT (/HALT): This low-active signal indicates that the processor has executed a Halt
OP Code, and is waiting for an interrupt in order to continue processing. While halted, the
Z80 executes NO-OPs in order to keep the refresh circuits serviced.
WAIT (/WAIT): This low-active input is the means by which slow memory or I/O devices
can stop the processor to allow more response time. The addressed circuit or device pulls
the /Wait line low to add extra T states to the machine cycle.
INTERRUPT REQUEST (/INT): This low-active input signals the processor that an I/O
device wishes an interrupt cycle. The interrupt will be allowed if interrupts are not masked
off inside the MP, and if a Hold sequence is not also being requested. At the end of the
instruction during which the interrupt request occurred, the MP will respond with the M1
and IORQ signals to indicate an Interrupt Acknowledge cycle. Note that there is no
Interrupt Enable output line to show the condition of the Interrupt Enable flip-flop,
although this exists internally.
NON-MASKABLE INTERRUPT (/NMI): This is a negative-edge triggered input which
has a higher priority than any other interrupt and is always acknowledged at the end of the
current instruction.
RESET (/RESET): This low-active input causes the setting to 0 of the Program Counter
and registers I and R, disables the Interrupt Enable flip-flop, and forces the Interrupt Mode
to mode 0. The address and data busses are tristated, and the control lines all go to their
inactive condition.
41
D0
D1
D2
D3
D4
D5
D6
D7
14
15
12
8
7
9
10
13
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
23
25
26
17
16
24
18
28
22
21
20
19
27
CLK
BUSACK
BUSREQ
RESET
NMI
INT
WAIT
HALT
RFSH
WR
RD
IORQ
MEMRQ
M1
Figure 2.11Z80 Pin Configurations.
BUS REQUEST (/BUSRQ): This low-active input allows another direct memory transfer
(DMA) device to request control of the address, data, and control lines so that it may take
over communication with the memory on its own behalf.
42
BUS ACKNOWLEDGE (/BUSAK): This low-active output indicates to the device that
asserted the Bus Request line that the MP has tristated the address, data, and control lines,
and that the requesting device may now assert control of the buses. The MP will remain
off the bus as long as the requesting device keeps the Bus Request line asserted.
CLOCK (0): This is a single-phase, 50%-duty-cycle clock provided by an outside source.
POWER SUPPLIES: The Z80 requires +5 volts and ground.
INPUT/OUTPUT CYCLES
I/O cycles are similar to memory cycles in most respects. However, there are a few
differences between them. First, the function of I/O vs. memory access is defined with the
/IORQ line as opposed to the /MREQ line. Additionally, the /IORQ line is asserted later in
the machine cycle, at the beginning of T2, rather than the middle of T1. The /RD or /WR
lines, to specify the nature of the transaction, are asserted at this same time. Because of the
later occurrence of these signals, a wait cycle Tw is automatically inserted into an I/O
machine cycle. There is insufficient time for most I/O controllers to respond in time for
the data to be captured by the processor during a read. The automatic wait state, therefore,
adds more time for the I/O controller to determine what function is to be performed, and
set up its response accordingly. If a second and additional wait cycles are needed, the I/O
device controller may pull the /WAIT line low during the middle of Tw, causing the MP to
add another Tw behind the first one. Once the wait cycles are released, the processor
43
expects an input data byte to be available during T3, and strobes the data bus at the fall of
f . The MP will then release the /IORQ and /RD lines immediately. If the MP was
performing an I/O write function, the /WR line is asserted during the beginning of T2, at
the same time as /IORQ. The data to be written, however, appears on the data bus at the
middle of T1, to make sure the data bus is stable before the I/O controller, which may use
the falling edge of /WR as a strobe signal actually accepts the data byte.
44
CHAPTER THREE
SYSTEM DESIGN
3.1 INTRODUCTION
It is required to design a microprocessor controlled moving message system. A modular
analysis of the system would enable a thorough analysis of the design and is therefore
employed. Five modules have been identified – Power, Input, Microprocessor,
Storage/Memory and Display; as illustrated in figure 3.1. Essentially, figure 3.1 describes
a basic microcomputer. In the following presentation, each module is discussed separately
and finally, the inter-operation of the modules is explained. The design is such that the
microprocessor is completely in charge of the operation of the system. A thorough
examination of the instructions the microprocessor executes gives a clear picture of how
the system operates.
As should be expected, there is a lot of bit movement and manipulation during system
operation. The RAM was effectively used as both a store-house and a working area.
3.2 INPUT MODULE
Data input into the system is through an 8-bit parallel interface. The keyboard consists of
30 keys, four (4) of which are function keys while twenty six (26) are either alphabets or
45
numbers. The most important key on the keyboard is the PRG ON/OFF key. This key
enables the
Figure 3.1 Modular representation of microprocessor controlled moving message display system.
keyboard. That is, as long as this key is not pressed, the microprocessor does not respond
to any other key on the keyboard. The outlay of the keyboard is illustrated in figure 3.2.
INPUT MODULE o Keyboard with
alphanumeric keys
MICROPROCESSORo Control o Addressing o Data acquisition
and manipulation o Timing
POWER SUPPLY MODULE o AC – DC conversion o Battery power for RAM
DISPLAY MODULE o 48 X 7 LED Matrix
Display
MEMORY MODULE o 4K X 8 ROM
(2732) o 2K X 8 RAM
(HM6116)
46
Figure 3.2 keyboard outlay.
It is required to display alphabets A–Z and numbers 0-9. If each symbol were to have a
key, 36 keys would be used. If this figure is added to the four function keys, we end up
with forty keys. This design is inferior to having a lesser number of keys while still being
able to use the same alphanumeric set. By making adjustments in the program, the number
of keys and thus the size of the keyboard is reduced. This also reduces the complexity of
the circuitry. This sacrifice of hardware for software is used throughout this project. As
will be discovered, the program the microprocessor executes completely controls the
operation of the display system.
Eleven keys on the keyboard are multiplexed-a single key gives two different outputs. The
2nd FNC key is used to achieve this. The multiplexed keys are A/1, B/2, C/3, D/4, E/5,
F/6, G/7, H/8, I/9, J/0, K/., and PRG ON/OFF. Without pressing the 2nd function key,
A/1 B/2 D/4 H/8C/3 G/7 F/6E/5
I/9 J/0 L P K/. O N M
Q R T X S W V U
Y SPACEZ PRGON/OFF
2NDFN DEL
47
the multiplexed keys point to the first entry for example, A in A/1. When the 2nd function
is pressed, the multiplexed keys point to their second entry. The other function keys on the
key pad are:
PRG ON/OFF: this is probably the most important key on the key board. It activates and
de-activates the keyboard. When it is pressed, it signifies that the microprocessor should
start scanning the keyboard to detect any input made. It thus, forces the system into input
mode. On the other hand, when the key is pressed with the 2nd function key, PRG OFF is
activated. This signifies an end to the input mode. The microprocessor ignores the key pad
once again, concentrating on manipulating the data stored in the RAM.
SPACE: if a blank space is viewed as a symbol, then this key is an alphanumeric key.
This approach was utilized.
DEL: as the name implies, the DEL key allows the programmer to remove the last entry.
This key is very useful as it makes allowance for error and correction.
In figure 3.2, we notice that the keys are arranged in an 8x4 array with the last row having
six layers. The eight columns are connected to eight input pins of a 74LS151
(multiplexer), while the four rows are connected to four output pins of a 74LS138
(decoder). This arrangement is illustrated in figure 3.3.
Since all elements on the same row are connected while all elements on the same column
are connected, selecting a row and a column uniquely selects a button on the keypad. The
columns are connected through a current limiting resistor to a +5V source.
48
3.2.1 Address Mapping of Buttons
The key pad is referenced by the IN opcode instruction. Using standard I/O scheme, each
button is identified by address ranging from 00H to 1FH. The address pins A0 – A7 are
used as control inputs in the decoder and multiplexer.
Figure 3.3 keyboard functional diagram
74LS138 DE-CO-DE-ER
74LS151 1x8 Multiplexer
10k Resistors
+5V
49
Specifically, A0 –A2 are data selectors for the multiplexer while A3 – A4 are decoder
inputs. The decoder is permanently enabled. Although 74LS138 is a 3 – to – 8 decoder, 2
inputs are used since number of rows is not more than four. Therefore, it is possible to
expand the keyboard – by increasing the input to the decoder to three. The resulting
address map for the buttons is tabulated in table 3.1.
3.2.2 Operation
The keypad cannot force a response from the microprocessor. The microprocessor
executes a series of instructions which enable it to continuously check the keyboard for
any key pressed. As earlier said, the operation of the keypad is tied to the Z80 instruction
IN opcode.
Let’s assume that the microprocessor wishes to know if the PRG ON/OFF has been
pressed, it executes
IN A, 1EH
This instruction gates 1EH, that is 00011110, on the lower part (A0 – A7) of the address
bus, thus making A0 = 0, A1 = 1, A2 = 1, A3 = 1and A4 = 1.
Decoder inputs A3 and A4 at 1 1 select the fourth row while multiplexer data selectors A0
A1 A2 at 110 select the seventh column. Thus the key PRG ON/OFF is uniquely identified
(4th row, 7th column; refer to figure 3.3).
Pressing the key at this point bridges the 4th row and 7th column. The row has been pulled
low (the output of the decoder is active low) while the column is always high. This
bridging makes the ‘spot’ a ground for the +5V tied to each column. This is transferred or
selected as the output of the multiplexer, resulting in Y = 0 and the inverted output, W = 1.
Thus a high is returned to the LSB of the data line D0 of the microprocessor.
50
Table 3.1 Address mapping of buttons on the key board.
Button I/O Address
Button I/O Address
Button I/O Address
Button I/O Address
A/1 00 J/0 09 S 12 DEL 1C B/2 01 K/. 0A T 13 2ND FNC 1D C/3 02 L 0B U 14 PG
ON/OFF 1E
D/4 03 M 0C V 15 E/5 04 N 0D W 16 F/6 05 O 0E X 17 G/7 06 P 0F Y 19 H/8 07 Q 10 Z 1A I/9 08 R 11 SPACE 1B
3.3 Power Module
The power supply needed to provide the +5V required by all ICs in the project was
designed using a rectifying, filtering and a voltage regulating circuit. The block diagram
below illustrates the power supply system.
Figure 3.4 Power Supply Scheme
The components of the power supply module are:
DC load
Transformer Voltage Regulator
Rectifier Filter
Mains
51
• 240V Center-Tapped (CT) Transformer with two secondary outputs (16V – 0 –
16V)
• a full wave rectifier employing 2 diodes
• a 4.7 µF (25V) capacitor
• two 3-terminal voltage regulator (7805)
The transformer reduces the 240V AC supply from the mains to about 16V. The diodes
rectify this AC voltage to DC voltage which is smoothened by the capacitor. The IC 7805
then regulates the voltage to precisely 5V. Two DC supply outputs are produced, a 5.6V
and 6.2V. This was done because it was necessary to provide the display module with a
separate DC supply because of its high current demand. The power supply circuit is
illustrated in figure 3.5.
Two and three diodes connect the first and second 7805 of to ground. Since each diode has
a forward bias voltage of 0.6V, the output of the first 7805 will read 6.2V while the second
will read 6.8V. These voltages are reduced to 5.6V and 6.1V by the transistors. These
voltages are designed to be higher than the nominal 5V in order to cater for the voltage
drop and loading effect in the circuit such that the operating voltage is maintained at, at
least 5V.
3.4 Memory Module
This project employed a 4K X 8-bit ROM (2732) and a 2K X 8-bit (HM6116) RAM in its
memory module. This section discusses the interfacing of these memory devices with the
Z80 microprocessor and their operations. These memory devices have been discussed in
section 2.2 of this report. The logic symbols of the memory devices are presented in figure
52
3.6.
Center tappedTransformer
Mains
16V-0-16V 4.7 µF
240V
D5
D6
D7
7805
7805
VC2N3055
2N3055
D3
D4
D1
D2
Figure 3.5 Power Supply Circuit
53
A1
Figure 3.6 Logic Symbol of Memory Devices
2732
D0
D1
D2
D3
D4
D5
D6
D7
A0
A2
A3A4A5A6A7A8A9
A10A11
A1
CE
OE
A2
A3
A10
A0
A4A5A6A7A8A9
HM6116
D0
D1
D2
D3
D4
D5
D6
D7
WR
CS
OE
RD
The ROM must start at address 0000H because the main program is stored in the ROM
and initializing should kick-start the operation of the program. Besides, Z80, by default
checks the location 0000H when it initializes. Table 3.2 illustrates the memory mapping.
54
Table 3.2 Memory mapping
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROM
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM
1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
The ROM and the RAM are interfaced with the Z80 such that the following memory map
is realized (Table 3.3):
Table 3.3 Address range of memory devices
Memory Device Starting Address End Address
ROM 0000H 0FFFH
RAM 8000H 87FFH
Address lines A14, A13, and A12 are tied to ground, as they are not used. A0 - A10 are
common to both the RAM and ROM. Partial decoding technique is utilized. A15 is used in
conjunction with MEMRQ to activate the OE (output enable) of the RAM. The two
control lines on the ROM, CS and OE are connected to MEMRQ and RD respectively.
When both lines are low, the Z80 fetches data (instructions) from the ROM.
55
3.4.1 Operation of the Memory Module
Each alphanumeric symbol is stored as bit patterns in the ROM. Eight (8) address
locations in the ROM contain information necessary to display an alphanumeric symbol.
Seven of these eight locations actually contain information on the bit position necessary to
light a 7 x 8 segment of the LED matrix display. The last location contains information on
how many times the alphanumeric symbol in question must be shifted from one end of the
48x7 LED matrix display to the other end. The value of the data held in this location
typically varies from 6 to 8. This is because most alphabets did not occupy the whole 8
bits (width) allocated. Thus, the ROM space may be seen as containing a set of data
necessary to display any alphanumeric symbol.
Two important designations were made in the RAM memory space. The first would be
tagged the instruction cache while the second is the image of the matrix display.
Instruction Cache: RAM location 8700 H to 87FF H (255) locations was set aside as
memory space where the microprocessor checks for the character to display. The alphabets
to be displayed are stored as codes in the RAM location. The are presented in table 3.4
When the microprocessor checks the kneeboard for input, it stores any input made as code
in memory starting from address location 8800, ending at 88FF. thus, not more than 255
characters can be displayed at any one time.
56
Table 3.4 Codes of alphanumeric symbol stored in memory.
Code in RAM
location
Alphabet to display
Code in RAM location
Alphabet to display
Code in RAM location
Alphabet to display
00 SPACE 0D M 1A Z 01 A 0E N 1B 0 02 B 0F O 1C 1 03 C 10 P 1D 2 04 D 11 Q 1E 3 05 E 12 R 1F 4 06 F 13 S 20 5 07 G 14 T 21 6 08 H 15 U 22 7 09 I 16 V 23 8 0A J 17 W 24 9 0B K 18 X 25 . 0C L 19 Y
Matrix Display Image: an image of the matrix system is set aside in the RAM. This
image is not the 48x7 noticed by the outside world. The microprocessor uses a 56x7
display in its memory. The last 8x7 segment is added to make its operations like DEL and
SHIFT realistic
RAM locations 8000 – 8006 address a single row of 54 LEDs, locations 8100 – 8106
address the next row and so on. For each set of 6 horizontal spaces allocated (as in above),
there exists one space allocated for the 7 vertical bits. This information is tabulated in
table 3.5. This memory area is actually where the processor “feels” the display is as all
data manipulation, sorting and shifting is done in this region.
This will be more evident after the instruction codes are analyzed.
57
Table 3.5 Matrix display image in memory
ADDRESS SPACE BIT POSITION 8000 H – 8006 H
8007 H IST ROW COLUMN
8100 H – 8106H 8107 H
2ND ROW COLUMN
8200 H – 8206 H 8207 H
3RD ROW COLUMN
8300 H – 8306 H 8307 H
4TH ROW COLUMN
8400 H – 8406 H 8407 H
5TH ROW COLUMN
8500 H – 8506 H 8507 H
6TH ROW COLUMN
8600 H – 8606 H 8607 H
7TH ROW COLUMN
3.5 Display Module
The display module consists of seven latches (74LS374), one 3-8 decoder (74LS138), a
buffer (74LS244), transistors (BS558 and NC548), and LEDs connected to form a matrix.
The matrix display consists of 48 columns and 7 rows of LED connected in such a way
that the entire LED on a single row have their anodes linked together through the base
terminal of a BN558 which connected to each LED. The co-joined base of the transistor is
connected to a latch pin through a two-stage amplifier. Figure 3.7 illustrates the
connection of LEDs in a single row of the matrix display. For clarity, only four transistors
out of forty-eight (4) in the row are shown.
58
The connection of LED legs on each column is not altogether different. The cathode of the
bottom LED is connected to the emitter of a BC548 (PNP Transistor). All other cathodes
in the column are co-joined. This is illustrated in figure 3.8.
BC558
R
BC558
TO LATCH PIN
D1 D2 D3
Figure 3.7 A row of LEDs in the LED MatrixDisplay
BC558
The LED display is a relatively high current consuming unit, in order to ensure that
59
sufficient current flows to enable the LEDs glow bright, the current level is amplified by
transistors connected as shown in figures 3.7 and 3.8.
+5V
BC548
BC558
D7
D6
BC558
D5
BC558
D4
BC558
D3
BC558
BC558
D2
BC558
D1
+5V
TO LATCH PIN (1 of 48available).
Figure 3.8 Circuit diagram of a column of LEDs in the 48 x7 LED matrix.
60
There are seven latches associated with the display system. Each latch, except the latch
connected to the vertical side of the display, is connected to eight columns in the 48x7
LED matrix. The decoder enables the microprocessor to identify and manipulate each
LED. Because each LED is a bit position in memory as far as the microprocessor is
concerned, as bits are Figure 3.8 Column of LEDs manipulated in memory, the display
follows the pattern of manipulation. The enable pins are connected to the microprocessor
as follows: A – I/OREQ
B – WR
C -- +5V
Thus, an OUT opcode instruction addresses the decoder. Based on the address placed on
the address line, specifically A0 – A2, the decoder selectively activates the latches. For
example OUT 00H will activate the first latch while
OUT 06H will activate the seventh latch.
3.6 INTEGRATION OF MODULES
The modules described in the previous sections depend entirely on the microprocessor.
The microprocessor simply executes instructions stored in the ROM. Thus, the link
between all the modules is the set of instruction executed by the microprocessor.
61
The program follows a general pattern of accepting input from the input module, storing
and manipulating data in the memory and outputting the result in the display system. So
far, little mention has been made of the program. A complete picture of how the display
system works is impossible without discussing the program which the microprocessor
executes.
3.6.1 Control, Timing and Addressing
The flow chart in figure 3.8 illustrates the basic operation of the system. When the
microprocessor is initialized (powered on), it executes instruction which lead it to
scanning RAM locations 8700 H to 87FF H for alphanumeric codes to decode and display.
Almost simultaneously, it keeps checking if the PRG ON/OFF key has been pressed. As
long as this key is not pressed, the microprocessor keeps on manipulating the codes in the
instruction cache. Recall that the RAM is also battery powered (an alternative power
supply) thus it does not lose the data it holds when the message display system is powered
down.
Thus, the display system is capable of holding a message in memory and continuously
displaying the message for as long as the PRG ON key is not activated.
Upon activating the PRG ON key, the micro processor starts scanning the keyboards for
inputs. As data is inputted, it is stored as codes in the instruction cache. As mentioned
62
earlier, a maximum of 255 inputs can be made. Full- stop (.) marks the end of input mode.
When PRG OFF key is activated, the micro processor begins to display the message.
The main program is presented below. Comment lines are placed within the body of the
program to explain the operations of the instructions.
LD D, 00H
MI LD L, D
LD H, 87H
C The 8 – bits content of 8700 is now placed in the accumulator. This is a code
signifying an alphabet to be displayed
LD A, M
C The content of the accumulator is then matched with as known set of codes to
determine which alphanumeric character to be displayed
CALL CHECK
C When the alphabet is determined; the number of times it has to shift through the
memory is also determined by the subroutine SHIFT
PI CALL SHIFT
C The alphanumeric symbol can now be displayed.
CALL OUTPUT
C With this done, a check is carried out on the PRG ON key to find out if it has been
activated.
63
NO
YES
NO
YES
YES
Initialize
CHECK INSTRUCTIONCACHE FOR CODES TO
MANIPULATE
CHECK TO SEE IF PRGON KEY HAS BEEN
ACTIVATED
ACQUIRE DATAAND STORE IN
ROM LOCATION8800H-88FFH
HAS FULL-STOPKEY BEENPRESSED?
HAS 88FF H MEMORYLOCATION BEEN
FILLED?
MANIPULATEAND DISPLAY
DATA
NO
Figure 3.9 Flow-chart
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IN A, 1E
C This returns a value 01H or 00H to the accumulator. The program is only
concerned with the 01 H out put because this signifies that key PRG ON has been
activated.
CP 01H
C If the carry flag is zero, the main program jumps to a sub-routine which allows
input to be made through the keyboard.
JZ INPUT
C Input is a sub-routine which enables the microprocessor acquiring data from the
keyboard.
LD A, B
CP C
C Both instructions relate to the number of shifts the current alphabet being handled
has to run through. If the carry flag is zero, it means the alphanumeric symbol has
been completely shifted. If this is the case, the next RAM location is checked by
incrementing register D. If not, register B is incremented and shift is performed
again.
JZ ALFA
INC B
JMP PI
ALFA INC D
C This instruction allows the microprocessor move on to the next address location
JMP MI
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A number of sub-routines were called in this program segment. They include CHECK,
SHIFT, OUTPUT and INPUT. Other sub-routines not immediately apparent in the main
program are PUT, DELAY, DELETE, BLANK and 2ND FNC.
Before a description of what each sub-routine does is given, it is necessary to illustrate the
flow of control between the sub-routines. This is shown in figure 3.11. Sub-routines
DELETE, BLANK and 2nd FNC are embedded in the INPUT sub-routine. These sub-
routines are invoked by keys on the keyboard. A description of the sub-routines follows:
MAIN PROGRAM
At power on, the microprocessor resets and runs a subroutine called INITIALISE which is
contained in the Main program. The initialization process is where the Z80 specifies the
stack pointer as 8080H, also its predetermined data into the specified memory locations
for the vertical latch’s memory location in the RAM as specified above, and it sets the
address location for the PRG ON/OFF to 00H in readiness for the key to be pressed.,
Also in the MAIN program, after initialization, the HL register pair is loaded with the
address in RAM where instruction to be displayed is loaded, and it calls other subroutine
which will be discussed later. It also scans the keypad to check if the PROG ON/OFF key
is pressed, from which decision is taken to launch a different subroutine.
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MAIN
CHECK
SHIFT
OUTPUT
IN A, 1E INPUT
PUT
SHIFT
YES
NO
Figure 3.10 Flow of control between sub-routines.
CHECK
This is the first subroutine call in the main program, its function is to check if there is valid
data in RAM location by comparing it with the specified location in the ROM where valid
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data are stored, this is done by comparing the content of the Location in the ROM with the
preloaded content of the RAM location, once the zero flag is set, the PUT subroutine is
called if not it keeps on checking until jumps back to the MAIN program.
PUT PROGRAM
This program is a subroutine within the CHECK subroutine program, the function of the
put program is to load the contents of the ROM location that corresponds to the contents
of the RAM into a defined portion of the RAM which we call the “MIRROR” as explained
before, thus the first location in the mirror which is not represented by the display unit is
used to store the first set of data
SHIFT PROGRAM
The SHIFT is a subroutine under the main program that allows the contents of the image
in the RAM location to be shifted through a predetermined number of times which is
determined by the contents of the B register.
OUTPUT PROGRAM
The output program is meant to output the contents of the mirror image in the RAM
location. These are actually sent to the latches whose addresses are specified in the
program as defined above. Thus the addresses are decoded by the decoder which selects
each latches accordingly, this will be explained in the hard ware.
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START PRG
In the main program, chance is given to monitor the PROG ON/OFF key, by checking if
the data defined for it has been changed. This is done by comparing the content of the
accumulator with “00H”, once the zero flag is set control is transferred to START PRG,
which calls BLANK to blank the display, and calls INPUT
INPUT
The input is basically used to scan the input device for any key pressed. Thus the Z80 uses
the address line A2-A0 (To the selector line of the multiplexer at the keypad) and A3-A4
(to the input of the decoder) respectively, , thus if the address is 000002, then the first line
of the multiplexer is selected, and the first output of the decoder is selected. Thus if this
key is depressed, there is a low at the input line of the MUX and since the inverted output
is connected to the D0 line, then we have 0000 00012 (01H) sent to the accumulator, if not
then we have 0000 00002 (00H). This continues in such a way that it scans the 30 push
buttons at a very fast rate.
JUMP
Once the zero flag is set when the CP is made between the content of the accumulator and
the content of the memory which has been preloaded with 01H, control is transferred to
JUMP where the routine of calling PUT, SHIFT and OUT PUT are performed so that the
character in memory which correspond to the address will be loaded to the MIRROR
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image in RAM, shifted and displayed on the display unit, after which control is returned to
the start of the INPUT program.
THE DELAY
This primarily performs a delay routine so as to allow the contents of the mirror image to
be display before another one is displayed. It is an unconditional jump to program.
THE BLANK
The blank is an unconditional jump program. It is called on immediately if we want to
blank our output, thus the blank is predetermine in the ROM 0E30H-0E38H location and it
contains all FFs so that when it has been called, it turns the LEDs off.
3.6.2 Construction
A bus system approach was taken for the data and the address lines to reduce the wiring.
Six (6) Vero boards, each holding a 7x8 LED matrix segment was stringed together, held
in position by metal clips and screwed to two chassis support within the metal housing.
The housing is a cuboid with dimensions 68cmX30cmX20cm. The frontal section is
covered by a dark glass shield (68cm X 30cm). The chassis holding the LED segments are
close to this glass shield to ensure that illumination from each LED is focused and not
dispersed.
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The microprocessor, memory and part of the output module are all on the same circuit
board – a single strip of Vero board. This board is screwed to the metal housing with
insulating material as prop between the housing and the circuit board.
The power module is also encased in the metal housing. The transformer was bolted to the
base of the metal case. The only module external to the system is the input module – the
keyboard. A parallel interface was provided at the rear of the housing for a female DB9
(DB25) connector. A matching male connector connects the keyboard to this interface.
The input unit was detached from other parts of the system to prevent abuse.
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CHAPTER FOUR
TESTS, RESULTS AND OBSERVATION
4.1 TESTS AND RESULTS
The various test carried out on each unit was to ensure that error was minimized and
system reliability established through well known and standard test procedures.
In the input module, a voltmeter was used to check for continuity and also to check for any
short-circuit. The system units test was performed by testing the LEDs with the data
addressed in the ROM, this was done to avoid erroneous programming which was
detected, but it was corrected after debugging.
For the display unit, all the LEDs were powered on at once by applying current to the
anode and the cathode that was tied together, some of these LEDs were not good – they
did not light up. They were subsequently removed and replaced. Additionally, some LEDs
did not light up as brightly as others. To reduce this effect, the LED matrix was moved
close enough to the dark glass shield.
For proper monitoring, the system was left on for a long time, about six hours, to see how
it will function, except for the heat generated, the system was relatively stable.
To check if the back-up battery was operational, the system was powered off and the
message inputted before power down was still being displayed, thus signifying that the
backup battery is working well.
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Figure 4.1 A snapshot of the main board housing the microprocessor, the memory module and part of the display module
Figure 4.2 A snapshot showing the power module and the interface of the input module (a parallel port).
73
Finally, some of the LED columns on the display did not light up, after troubleshooting it
was discovered that the some of the D flip-flop ICs had failed. These ICs were replaced
and the message display system worked quite well. Some pictures of the display system
are presented in figures 4.1 to 4.
Figure 4.3 A snapshot of the LED matrix display (rear view)
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Figure 4.4 A snap shot illustrating the interface between the input module and the system (note that the input module is detachable)
Figure 4.5 A snapshot of the 30-key keyboard (the cover was removed to reveal the circuit).
75
Figure 4.6 A snapshot showing the display system being programmed.
Figure 4.8 A snapshot of the Display system in operation. The message “ ELECTRONIC ENGINEERING” is presently streaming across the display.
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4.2 PROBLEMS ENCOUNTERED
During the construction of this display, the following problems were encountered.
- The LEDs available were of different brightness and this distorts the resulting
display. Transistors were used to amplify the current level at the between the
buffer and the each divided to minimize the effect phenomenon.
- The wring and soldering of the components (especially the 48 x 7 LED Matrix)
was time-consuming and extremely laborious. Quite a number of LEDs were
damaged.
- Programming the ROM involved using a special circuitry which has to be soured.
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CHAPTER FIVE
CONCLUSION AND RECCOMENDATION
5.1 CONCLUSION
The objective of this project was to design and construct a microprocessor controlled
moving message display system. The inclusion of micro-processor in the design and also
the need to make the massage display system programmable contributed immensely to the
design.
LEDs are very day electronic devices but their application in this project father justified
their cost saving and efficient properties. Many other standard electronic devices were
used in designing and construct the moving message display system. Notable among these
are the decades, which were important components in the input module and the display
module; the memory, specifically the RAM, which is the work area of the micro-processor
and lastly the micro -processor itself. The micro -processor was programmed in such a
way that it never yielded control to any module in the system-it was totally in charge.
Control lines associated with DMA and interrupted system were all disabled-these services
were not used. The micro-processor used standard I/0 scheme to address and control the
peripherals (in this case, the keypad and the LED matrix)
The set of instruction executed by the micro-processor is stored in the Rom. As
additionally, bit-mapping necessary to display each alphanumeric character are also; a
back up battery is provided as an alternative power supply. This is to ensure that the
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content of the instruction cache in the RAM are available even after Maxine failure or
power down.
A central part of the system is the input module. It incorporates the basic alphanumeric set
A-Z, 0-9 with function keys which allow a user to interact with the system.
In the design, a modular approach was subscribed to. This ‘divide and rule’ method
essentially segments the whole system to five modules. This aids design, constriction and
fault analysis.
5.2 RECOMMENDATION
The message display system, as it is, could be interfaced with a computer. This would
ensure that the display system can be programmed from within a building, not necessarily
coming near the display system to make changes to the message being displayed.
Since a program would operate on the computer which would control the display, visual
effect such a fading, scrolling and flashing can easily be incorporated. Additionally if the
computer in question is in a network of other computers it is possible to run the program
from a remote computer.
A practical application of this is in the case of banks which continually give an undated of
exchange and interest rates. A single computer at the Head-quarters may be responsible
79
for the information while display systems scattered across branches flash or display the
information.
Secondly, a keyboard with an infra-red interface may be incorporated. This would enable a
wireless input module.
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APPENDIX A
SET OF INSTRUCTIONS FOR THE Z80 MICROPROCESSOR
MAIN PROGRAM INITIALIZE LD SP, 8080 JZ PUT LD H, 80 INC D LD L, B LD L, 70 JUMP LD H, E LD HL, 01 LD A, M LD H, 81 LD C, A LD HL, 02 CHECK INC B LD H, 82 LD B, 00 LD L, B LD HL, 04 LD A, 0F LD A, M LD H, 83 CP 00 (SPACE) LD H, 80 LD HL, 08 JZ PUT LD L, 00 LD H, 84 LD B, 08 LD (HL), A LD HL, 10 CP 01 (A) LD H, E LD H, 85 JZ PUT INC B LD HL, 20 LD B, 10 LD L, B LD H, 86 CP 02 (B) LD A, (HL) LD HL, 40 JZ PUT LD H, 81 LD H,80 LD B,18 LD L ,00 LD L, 0A CPI 03 (C) LD (HL), A LD HL,00 JZ PUT LD H, E LD D,0D LD B, 20 INC B LD HL, 00 CP 04 (D) LD L, B INC HL JZ PUT LD A, (HL) LD HL, 00 LD B, 28 LD H, 82 INC HL CP 05 (E) LD L, 00 LD HL, 00 JZ PUT LD (HL), A CALL BLANK LD B, 30 LD H, E CP 06 (F) JZ PUT LD D, 00 LD B, 38 LD L, D CP 07, (G) LD H, 8F LD B, 40 LD A, (HL) CP 08 (H) CALL CHECK JZ PUT LD B, 00 LD B, 48 INC B CP 09 (I) CALL SHIFT JZ PUT LD E, 0F LD B, 50
81
CALL OUTPUT CP 10 IN PROGON/OFF JZ PUT SHIFT LD H, 80 LD H, 85 CALL SHIFT CALL SHIFT 2 CALL OUT2 LD A, B LD H, 81 LD H, 86 CP C CALL SHIFT 2 CALL OUT 2 JZ NOW LD H, 82 DEC E JP THEN CALL SHIFT 2 LD A, E NOW: LD E, 01 LD H, 83, CP A, 00 CALL OUTPUT CALL SHIFT 2 JP RETURN LD H, 84 CALL SHIFT 2 CALL OUT 2 START PRG LD H, 85 LD A, 00 CALL BLANK LD E, 0F CALL SHIFT 2 OUT 06 LD D, FF LD H, 86 LD L, 01 LD H, 8F CALL SHIFT 2 LD A, (HL) LD L, 00 RETURN 0UT 00 BEGIN: LD A, 00 INC L LD (HL), A SHIFT 2 LD A, (HL) INC L LD L, 00 OUT 01 LD A, FF STC INC L CP L RR (HL) LD A, (HL) JZ INPUT INC L OUT 02 JP BEGIN RR (HL) INC L INC L LD A, (HL) INPUT RR (HL) OUT 03 START: LD B, 08 INC L INC L LD H, 80 RR (HL) LD A, (HL) LD L, 0E INC L OUT 04 LD (HL), 01 RR (HL) INC L DEC L INC L LD A, (HL) LD (HL), 01 RR (HL) OUT 05 IN A, 00 INC L INC L CP (HL) RR (HL) LD A, (HL) JZ JUMP RETURN OUT 06 LD B, 10 CALL DELAY LD (HL), 02 OUTPUT LD A, 00 DEC L LD H, 80 OUT 06 IN 01 CALL OUT 2 RETURN CP (HL) LD H, 81 JZ JUMP CALL OUT 2 BLANK LD B, 18 LD H, 82 LD E, 0E INC L
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CALL OUT 2 LD B, 50 LD (HL), 03 LD H, 83 CALL PUT DEC L CALL OUT LD B, 00 IN 02 LD H, 84, CALL SHIFT CALL OUT 2 THEN: INC B
JUMP LD H,80 LD L,0E LD A, (HL) LD H, 87 INC D MOV L, D LD (HL), A CALL PUT CALL SHIFT LD E, 01 CALL OUTPUT JP START
83
APPENDIX C
COST ANALYSIS
The table below sums up the cost of constructing the Programmable Microcomputer
Display. In the analysis below, such expenditure as money spent on trips and research are
included in miscellaneous expenses.
TABLE A1 Cost Breakdown
Description Part Number Unit Cost(N) Quantity Total
Cost(N)
1-of-8 Decoder SN74LS138 100 4 400
8 Input Multiplexer SN74LS151 100 3 300
Octal Latch SN74LS374 100 14 1400
Hex Inverter SN74LS04 80 4 160
Quad 2- Input NAND Gate SN74LS00 80 2 160
4MHz Crystal T55897 180 2 360
+5V Voltage Regulator 7805 80 4 320
Octal Buffer/Line Driver SN74LS244 100 2 200
Z 80 Microprocessor 800 2 1600
RAM HM6116 700 2 1400
Vero Board 500 8 4000
Diodes IN4007 10 12 240
LED 20 335 3350
Transistors BC548&BC558 20 400 8000
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Description Part Number Unit Cost(N)
Quantity Total Cost(N)
Transistors TC400 60 4 240
Resistors(Fixed) 20 20 400
Capacitors(Fixed) 30 20 600
Link Wires 360 360
Casing 750 2 1500
Transformer 250 2 500
Power Cable 100 2 200
Miscellaneous 14,000
Printer Port Cable 500 2 1000
Total 40,960
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REFERENCES
1. CHARLES W. MCKAY, “Experimenting with MSI, LSI, IO and Modular Memory
systems”, Prentice-Hall Inc.3rd Edition, 1982. Pp 55 – 105.
2. MADDOCK, R.J AND CALCULT, D.M: “Electronics: A course for engineers”
Longman Scientific and Technical, 3rd Edition 1991. Pp 60 – 99.
3. MILNES, A.G, “Semiconductor Devices and Integrated Electronics”, CBS
Publishers and Distributors. 4th Edition, 1987.
4. PAUL HOROWITZ AND WINFIELD HILL: “The art of electronics” University
of Cambridge Press. 3rd Edition 1995.
5. SOL SHERR,”Electronic Display “, Mcgraw-Hill, 5th Edition 1970. Pp 8 – 60.
6. TOCCI, R.J AND WIDMER, N.S:”Digital Systems”, Prentice-Hall Inc 6th Edition
1998. Pp 650 – 693, 45 – 70.